View CY7C374-66AI_3017295.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ultralogic? 128-macrocell flash cpld cy7c374 for new designs see cy7c374i cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03021 rev. ** revised april 1998 features ? 128 macrocells in eight logic blocks 64 i/o pins 6 dedicated inputs including 4 clock pins bus hold capabilities on all i/os and dedicated inputs no hidden delays high speed ?f max = 100 mhz ?t pd = 12 ns ?t s = 6 ns ?t co = 7 ns electrically alterable flash technology available in 84-pin plcc, 84-pin clcc, 100-pin tqfp, and 84-pin pga packages pin compatible with the cy7c373 functional description the cy7c374 is a flash erasable complex programmable logic device (cpld) and is part of the f lash 370 ? family of high-density, high-speed cplds. like all members of the f lash 370 family, the cy7c374 is designed to bring the ease of use and high performance of the 22v10 to high-density cplds. the 128 macrocells in the cy7c374 are divided between eight logic blocks. each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. the logic blocks in the f lash 370 architecture are connected with an extremely fast and predictable routing resource ? the programmable interconnect matrix (pim). the pim brings flex- ibility, routability, speed, and a uniform delay to the intercon- nect. the cy7c374 is a register intensive 128-macrocell cpld. ev- ery two macrocells in the device feature an associated i/o pin, resulting in 64 i/o pins on the cy7c374. in addition, there are two dedicated inputs and four input/clock pins. 7c374 ? 1 pim input macrocells clock inputs inputs logic block logic block 4 4 36 16 16 36 8 i/os 8 i/os logic block logic block 36 16 16 36 8 i/os 8 i/os logic block logic block 36 16 16 36 8 i/os 8 i/os logic block logic 36 16 16 36 8 i/os 8 i/os 32 32 4 2 input/clock macrocells a b c e f g h logic block diagram i/o 0 ? i/o 7 i/o 8 ? i/o 15 i/o 16 ? i/o 23 i/o 24 ? i/o 31 i/o 56 ? i/o 63 i/o 48 ? i/o 55 i/o 40 ? i/o 47 i/o 32 ? i/o 39 logic block d selection guide 7c374-100 7c374-83 7c374-66 7c374l-66 maximum propagation delay t pd (ns) 12 15 20 20 minimum set-up, t s (ns) 6 8 10 10 maximum clock to output, t co (ncs) 7 8 10 10 maximum supply current, i cc (ma) commercial 300 300 300 150 military/industrial 370 370
cy7c374 document #: 38-03021 rev. ** page 2 of 16 pin configurations i/o 63 i/o 14 i/o 15 i/o 48 top view plcc/clcc 98 6 7 5 13 14 12 11 49 48 58 59 60 23 24 26 25 27 15 16 47 46 43 28 33 20 21 19 18 17 22 34 37 36 38 42 41 43 40 66 65 63 64 62 61 67 68 69 74 72 73 71 70 84 81 82 80 21 79 gnd i/o 1 gnd i/o 61 i/o 60 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 gnd i/o 55 i/o 54 i/o 53 i/o 52 i/o 51 gnd i/o 49 clk 3 /i 4 v cc clk 2 /i 3 i/o 45 i/o 44 gnd i/o i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 clk 0 /i 0 v cc clk 1 /i 1 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 53 52 51 50 30 29 31 32 i/o 59 i/o 58 i/o 57 i/o 56 54 55 56 57 i/o 43 i/o 42 i/o 41 i/o 40 77 78 76 75 i/o 21 i/o 22 i/o 23 gnd i/o 2 i/o 50 i/o 47 i/o 46 gnd 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v cc v cc i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 gnd i 2 v cc i/o 0 v cc i 5 i/o 62 gnd i/o 5 i/o 6 i/o 4 i/o 3 i/o 2 i/o 0 v cc gnd i/o 62 i/o 54 i/o 52 i/o 51 i/o 50 i/o 48 clk3 /i 4 i/o 45 gnd i/o 46 i/o 47 i/o 43 i/o 44 i/o 40 i/o 42 i/o 41 gnd i/o 37 i/o 38 i/o 36 i/o 35 i/o 34 i/o 32 i 2 i/o 33 i/o 30 i/o 31 i/o 27 i/o 28 i/o 24 i/o 26 i/o 25 i/o 21 i/o 22 i/o 20 i/o 19 i/o 18 i/o 16 clk1 / i1 clk0 /i 0 i/o 17 i/o 14 i/o 15 i/o 11 i/o 12 i/o 8 i/o 10 i/o 9 gnd pga bottom view v cc i/o 63 i/o 60 i/o 58 i/o 57 i/o 59 i/o 56 gnd i/o 53 l k j h g f e d c b a 123456 78910 11 i/o 23 i/o 39 i/o 55 i/o 7 i/o 1 v cc i 5 gnd v cc i/o 29 i/o 49 v cc clk2 /i 3 gnd v cc i/o 13 i/o 61 7c374 ? 2 7c374 ? 3 top view tqfp 100 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc v cc i/o 55 i/o 54 i/o 53 i/o 52 clk 3 /i 4 i/o 50 i/o 48 gnd nc i / o 47 i/o 46 i/o 49 gnd nc nc gnd i/o 8 i/o 9 i/o 10 i/o 11 i/o 15 v cc gnd clk 1 /i 1 i/o 16 i/o 17 clk 0 /i 0 90 91 i/o 51 v cc clk 2 /i 3 i/o 14 n/c i/o 12 i/o 13 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 gnd nc gnd nc i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 v cc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 48 49 50 7c374 ? 4 gnd i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 v cc v cc i/o 32 i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i 2 nc v cc nc i/o 63 i/o 1 gnd i/o 61 i/o 60 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 59 i/o 58 i/o 57 i/o 56 i/o 2 vcc i/o 0 vcc i 5 i/o 62 nc v cc 83 10 39 35 44 45 37 47 99
cy7c374 document #: 38-03021 rev. ** page 3 of 16 functional description (continued) finally, the cy7c374 features a very simple timing model. un- like other high-density cpld architectures, there are no hid- den speed delays such as fanout effects, interconnect delays, or expander delays. regardless of the number of resources used or the type of application, the timing parameters on the cy7c374 remain the same. logic block the number and configuration of logic blocks distinguishes the members of the f lash 370 family. the cy7c374 includes eight logic blocks. each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. product term array the product term array in the f lash 370 logic block receives 36 inputs from the pim and outputs 86 product terms to the product term allocator. the 36 inputs from the pim are avail- able in both positive and negative polarity, making the overall array size 72 x 86. this large array in each logic block allows very complex functions to be implemented in a single pass through the device. product term allocator the product term allocator is a dynamic, configurable resource that shifts product terms to macrocells that require them. any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). furthermore, product terms can be shared among multiple macrocells. this means that product terms that are common to more than one output can be imple- mented in a single product term. product term steering and product term sharing help to increase the effective density of the f lash 370 cplds. note that product term allocation is han- dled by software and is invisible to the user. i/o macrocell half of the macrocells on the cy7c374 have i/o pins associ- ated with them. the input to the macrocell is the sum of be- tween 0 and 16 product terms from the product term allocator. the i/o macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and two global clocks to trigger the register. the macrocell also fea- tures a separate feedback path to the pim so that the register can be buried if the i/o pin is to be used as an input. buried macrocell the buried macrocell is very similar to the i/o macrocell. again, it includes a register that can be configured as combi- natorial, as a d flip-flop, a t flip-flop, or a latch. the clock for this register has the same options as described for the i/o macrocell. one difference on the buried macrocell is the addi- tion of input register capability. the user can program the bur- ied macrocell to act as an input register (d-type or latch) whose input comes from the i/o pin associated with the neigh- boring macrocell. the output of all buried macrocells is sent directly to the pim regardless of its configuration. programmable interconnect matrix the programmable interconnect matrix (pim) connects the eight logic blocks on the cy7c374 to the inputs and to each other. all inputs (including feedbacks) travel through the pim. there is no speed penalty incurred by signals traversing the pim. bus hold capabilities on all i/os and dedicated inputs a feature called bus-hold has been added to all f lash 370 i/os and dedicated input pins. bus-hold, which is an improved ver- sion of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device ? s per- formance. as a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-in- terface applications. bus-hold additionally allows unused de- vice pins to remain unconnected on the board, which is partic- ularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. development tools development software for the cy7c374 is available from cy- press ? s warp ? software packages. both of these products are based on ieee standard 1076/1164 vhdl. cypress cplds are also supports by a number of third-party vendors such as abel ? cupl ? , and log/ic ? . please refer to third-party tool support data sheets for further information.
cy7c374 document #: 38-03021 rev. ** page 4 of 16 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential .................? 0.5v to +7.0v dc voltage applied to outputs in high z state .....................................................? 0.5v to +7.0v dc input voltage .................................................? 0.5v to +7.0v dc program voltage .....................................................12.5v output current into outputs ........................................ 16 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma notes: 1. t a is the ? instant on ? case temperature. 2. see the last page of this specification for group a subgroup testing infor- mation. 3. these are absolute values with respect to device ground. all overshoots due to system or tester noise are included. 4. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by tester ground degradation. 5. tested initially and after any design or process changes that may affect these parameters. 6. measured with 16-bit counter programmed into each logic block. 7. c i/o for the clcc and cpga packages is 15 pf max. 8. c i/o for i 5 is 15 pf max operating range range ambient temperature v cc commercial 0 c to +70 c 5v 5% industrial ? 40 c to +85 c 5v 5% military [1] ? 55 c to +125 c 5v 10% electrical characteristics over the operating range [2] parameter description test conditions min. max. unit v oh output high voltage v cc = min. i oh = ? 3.2 ma (com ? l/ind) 2.4 v i oh = ? 2.0 ma (mil) v v ol output low voltage v cc = min. i ol = 16 ma (com ? l/ind) 0.5 v i ol = 12 ma (mil) v v ih input high voltage guaranteed input logical high voltage for all inputs [3] 2.0 7.0 v v il input low voltage guaranteed input logical low voltage for all inputs [3] ? 0.5 0.8 v i ix input load current v i = internal gnd, v i = v cc ? 10 +10 a i oz output leakage current v o = internal gnd, v o = v cc ? 50 +50 a i os output short circuit current [4, 5] v cc = max., v out = 0.5v ? 30 ? 160 ma i cc power supply current [6] v cc = max., i out = 0 ma f = 1 mhz, v in = gnd, v cc com ? l 300 ma com ? l ? l ? ? 66 150 ma mil./ind. 370 ma shaded area contains preliminary information. capacitance [5] parameter description test conditions max. unit c i/o [7, 8] input capacitance v in = 5.0v at f=1 mhz 10 pf endurance characteristics [5] parameter description test conditions min. max. unit n minimum reprogramming cycles normal programming conditions 100 cycles
cy7c374 document #: 38-03021 rev. ** page 5 of 16 ac test loads and waveforms 7c374 ? 5 7c374 ? 6 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 35 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) 2ns 2 n output 238 ? (com ? l) 319 ? (mil) 170 ? (com ? l) 236 ? (mil) 99 ? (com ? l) 136 ? (mil) equivalent to: th venin equivalent 2.08v (com'l) 2.13v (mil) 238 ? (com'l) 319 ? (mil) 170 ? (com'l) 236 ? (mil) parameter [9] v x output waveform measurement level t er( ? ) 1.5v t er(+) 2.6v t ea(+) 1.5v t ea( ? ) v thc note: 9. t er is measured with 5-pf ac test load and t ea is measured with 35-pf ac test load. v oh ? 0.5v v x v oh ? 0.5v v x v x ? 0.5v v oh ? 0.5v v oh v x
cy7c374 document #: 38-03021 rev. ** page 6 of 16 switching characteristics over the operating range [10] parameter description 7c374-100 7c374-83 7c374-66 7c374l-66 unit min. max. min. max. min. max. combinatorial mode parameters t pd input to combinatorial output 12 15 20 ns t pdl input to output through transparent input or output latch 15 18 22 ns t pdll input to output through transparent input and output latches 16 19 24 ns t ea input to output enable 16 19 24 ns t er input to output disable 16 19 24 ns input registered/latched mode parameters t wl clock or latch enable input low time [5] 3 4 5 ns t wh clock or latch enable input high time [5] 3 4 5 ns t is input register or latch set-up time 2 3 4 ns t ih input register or latch hold time 2 3 4 ns t ico input register clock or latch enable to combinatorial output 16 19 24 ns t icol input register clock or latch enable to output through trans- parent output latch 18 21 26 ns output registered/latched mode parameters t co clock or latch enable to output 7 8 10 ns t s set-up time from input to clock or latch enable 6 8 10 ns t h register or latch data hold time 0 0 0 ns t co2 output clock or latch enable to output delay (through memory array) 16 19 24 ns t scs output clock or latch enable to output clock or latch enable (through memory array) 10 12 15 ns t sl set-up time from input through transparent latch to output register clock or latch enable 12 15 20 ns t hl hold time for input through transparent latch from output reg- ister clock or latch enable 0 0 0 ns f max1 maximum frequency with internal feedback (least of 1/t scs , 1/(t s + t h ), or 1/t co ) [5] 100 83 66 mhz f max2 maximum frequency data path in output registered/latched mode (lesser of 1/(t wl + t wh ), 1/(t s + t h ), or 1/t co ) 143 125 100 mhz f max3 maximum frequency with external feedback (lesser of 1/(t co + t s ) and 1/(t wl + t wh )) 76.9 67.5 50 mhz t oh -t ih 37x output data stable from output clock minus input register hold time for 7c37x [5, 11] 0 0 0 ns pipelined mode parameters t ics input register clock to output register clock 10 12 15 ns f max4 maximum frequency in pipelined mode (least of 1/(t co + t is ), 1/t ics , 1/(t wl + t wh ), 1/(t is + t ih ), or 1/t scs ) 100 83.3 66.6 mhz
cy7c374 document #: 38-03021 rev. ** page 7 of 16 reset/preset parameters t rw asynchronous reset width [5] 12 15 20 ns t rr asynchronous reset recovery time [5] 14 17 22 ns t ro asynchronous reset to output 18 21 26 ns t pw asynchronous preset width [5] 12 15 20 ns t pr asynchronous preset recovery time [5] 14 17 22 ns t po asynchronous preset to output 18 21 26 ns notes: 10. all ac parameters are measured with 16 outputs switching and 35-pf ac test load. 11. this specification is intended to guarantee interface compatibility of the other members of the cy7c370 family with the cy7c 374. this specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. switching characteristics over the operating range [10] (continued) parameter description 7c374-100 7c374-83 7c374-66 7c374l-66 unit min. max. min. max. min. max.
cy7c374 document #: 38-03021 rev. ** page 8 of 16 switching waveforms combinatorial output t pd 7c374 ? 7 input combinatorial output registered input t is 7c374 ? 8 registered input input register clock t ico combinatorial output t ih clock t wl t wh registered output t s 7c374 ? 9 input clock t co registered output t h clock t wl t wh
cy7c374 document #: 38-03021 rev. ** page 9 of 16 switching waveforms (continued) latched output t s 7c374 ? 10 input latch enable t co latched output t h t pdl latched input and output t ics latched input output latch enable latched output t pdll t icol input latch enable t sl t hl clock to clock 7c374 ? 12 registered input input register clock t ics utput register clock t scs
cy7c374 document #: 38-03021 rev. ** page 10 of 16 switching waveforms (continued) latched input t is 7c374 ? 13 latched input latch enable t ico combinatorial output t ih t pdl latch enable t wl t wh asynchronous reset 7c374 ? 14 input t ro registered output clock t rr t rw asynchronous preset 7c374 ? 15 input t po registered output clock t pr t pw
cy7c374 document #: 38-03021 rev. ** page 11 of 16 switching waveforms (continued) output enable/disable 7c374 ? 17 input t er outputs t ea ordering information speed (mhz) ordering code package name package type operating range 100 cy7c374-100ac a100 100-pin thin quad flat pack commercial cy7c374-100gc g84 84-pin grid array (cavity up) cy7c374-100jc j83 84-lead plastic leaded chip carrier 83 cy7c374-83ac a100 100-pin thin quad flat pack commercial cy7c374-83gc g84 84-pin grid array (cavity up) cy7c374-83jc j83 84-lead plastic leaded chip carrier cy7c374-83ai a100 100-pin thin quad flat pack industrial cy7c374-83ji j83 84-lead plastic leaded chip carrier cy7c374-83gmb g84 84-pin grid array (cavity up) military cy7c374-83ymb y84 84-pin ceramic leaded chip carrier 66 cy7c374-66ac a100 100-pin thin quad flat pack commercial cy7c374-66gc g84 84-pin grid array (cavity up) cy7c374-66jc j83 84-lead plastic leaded chip carrier CY7C374-66AI a100 100-pin thin quad flat pack industrial cy7c374-66ji j83 84-lead plastic leaded chip carrier cy7c374-66gmb g84 84-pin grid array (cavity up) military cy7c374-66ymb y84 84-pin ceramic leaded chip carrier cy7c374l-66ac a100 100-pin thin quad flat pack commercial cy7c374l-66jc j83 84-lead plastic leaded chip carrier
cy7c374 document #: 38-03021 rev. ** page 12 of 16 military specifications group a subgroup testing ultralogic and f lash 370 are trademarks of cypress semiconductor corporation. warp2 and warp3 are registered trademarks of cypress semiconductor corporation. abel is a trademark of data i/o corporation. cupl is a trademark of logical devices incorporated. log/ic is a trademark of isdata corporation. dc characteristics parameter subgroups v oh 1, 2, 3 v ol 1, 2, 3 v ih 1, 2, 3 v il 1, 2, 3 i ix 1, 2, 3 i oz 1, 2, 3 i cc1 1, 2, 3 switching characteristics parameter subgroups t pd 9, 10, 11 t pdl 9, 10, 11 t pdll 9, 10, 11 t co 9, 10, 11 t ico 9, 10, 11 t icol 9, 10, 11 t s 9, 10, 11 t sl 9, 10, 11 t h 9, 10, 11 t hl 9, 10, 11 t is 9, 10, 11 t ih 9, 10, 11 t ics 9, 10, 11 t ea 9, 10, 11 t er 9, 10, 11
cy7c374 document #: 38-03021 rev. ** page 13 of 16 package diagrams 100-pin thin quad flat pack a100
cy7c374 document #: 38-03021 rev. ** page 14 of 16 package diagrams (continued) 84-p in grid array (cavity up) g84 51-80015-a 84-lead plastic leaded chip carrier j83
cy7c374 document #: 38-03021 rev. ** page 15 of 16 ? cypress semiconductor corporation, 1998. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagrams (continued) 84-pin ceramic leaded chip carrier y84
cy7c374 document #: 38-03021 rev. ** page 16 of 16 document title: cy7c374 ultralogic ? 128-macrocell flash cpld document number: 38-03021 rev. ecn no. issue date orig. of change description of change ** 106324 05/08/01 szv transferred from spec number: 38-00214 to 38-03021.

▲Up To Search▲

Price & Availability of CY7C374-66AI

	To Download CY7C374-66AI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .