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tm data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7677 features ? 600 vdc drive for 270 vdc motors 215 amps @85c operates with brushless, brush, and induction motors input to output ground isolation with floating output stage short circuit protection trapezoidal or sinusoidal compatible dsp/microprocessor compatible pw-83225m6 - half-bridge drive pw-84225m6 - half-bridge drive with current sense pw-85225m6 - half-bridge drive with regenerative clamp description the pw-83225m6, pw-84225m6 and pw-85225m6 are half-bridge drive modules containing isolated switch drivers, an upper and lower solid-state switch, and an isolated power supply. in addition, the pw- 84225m6 contains isolated current sensing feedback circuitry and the pw-85225m6 contains a regenerative clamp protection circuit. the three modules can be used in any combination to create drives for brush, brushless dc, or ac induction motors. the current sense output signal and logic inputs are compatible with dsp/ microproces- sors and/or fpga/asic circuits used to control the motor drives. these modular drives are capable of operating from either a 135vdc or 270vdc power source that is electrically isolated from the logic input signals. the modules are fault tolerant from output shorts, loss of any or all power supplies, and power supply sequencing. applications the high reliability and flexibility of these drives make them suitable for military and aerospace applications. among the many applications are: actuator systems for primary and secondary flight controls on air- craft, fan and compressor motor drives for environment conditioning, pump motors for fuel and hydraulic fluid, antenna and radar position- ing, and thrust vector position control of missiles, drones, and rpv's. ? 2001 data device corporation pw-8x225m6 225a, 600v magnum motor drive make sure the next card you purchase has... this preliminary data sheet provides detailed functional capabilities for product currently in prototype production. these specifications are being provided to allow for electrical design, layout and operation.
2 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 figure 1a. pw-83225m6 figure 1b. pw-84225m6 figure 1c. pw-85225m6 power supply v cc v cc-rtn sleep_mode gate drive and fault control upper sc fault lower disable/reset power supply high drive low drive v bus + output v bus - auto reset i s o l a t i o n b a r r i e r power supply sleep_mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive v bus + output v bus - ov amp regen_status regen_clamp auto reset ov_adj v cc v cc-rtn 5k ? ov_adj_low ov_adj_high 0v adj ref. power supply sleep_mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive v bus + output v bus - current amp current amp r sense oc fault v iref v irsense_abs r sense + r sense - v cc v cc-rtn v dd v dd rtn v irsense auto reset
3 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 table 1. pw-8x225m6 absolute maximum ratings tc = 25c units value symbol parameter drive supply voltage v bus + to v bus - 600 vdc logic power-in supply voltage v cc 5.5 vdc input logic voltage upper, lower, disable /reset , sleep_mode, a ut o reset 5.5 vdc reference input voltage v iref v dd + 0.5 vdc vdc continuous output current i o 225 a peak output current (<10ms) i peak 400 a storage temperature range t cs -65 to +125 c intermittent case operating temperature t ci -55 to +125 c continuous case operating temperature t c -55 to +100 c junction temperature, power devices tj +150 c junction temperature, other components tj +125 c isolation voltage (note 2) v iso 2500 vdc table 2. pw-8x225m6 specifications v cc = v dd = 5v unless otherwise noted, t c = -55c to 100c for min. and max values, t c = 25c for typ values (see note 1). typ min max units symbol test conditions parameter note 1: in all tables t c refers to the temperature of the magnum heat sink surface. note 2: from v cc-rtn to v bus +, v bus -, output, regen_clamp, r sense +, r sense -. v bus + to v bus - i o i o i o e on e off i peak i sc v ce(sat) unipolar/bipolar t c = 25c, non switching dc t c = 85c, non switching dc t c = +25 to +85c, 3 phase drive, 50% duty cycle, 20 khz switching v ce = 270v, i = 50a tj = +125c v ce = 270v, i = 50a tj = +125c tc = +25c, 15 ms <5 s i o = 145a 600 270 1.8 14.4 900 2.2 600 215 150 215 360 1200 2.6 vdc a a a mj mj a a vdc output stage drive supply voltage (motor) output switch transistors (each) output current continuous drive (dc) output current commutating drive turn-on energy per pulse turn-off energy per pulse peak current short circuit trip current (note 2) output voltage drop (igbt) v f trr irr ir ir i o = 145a i o = 145a di/dt = 480a/s, if = 150 a (90c) v bus = 480vdc v bus = 480vdc 1.45 180 60 1.65 80 1100 6.0 vdc ns a a ma flyback voltage forward voltage reverse recovery time @ t j = +125 c reverse recovery peak current reverse leakage current @ t j = +25 c reverse leakage current @t j = +125 c td (on) td (off) tsd tr tf t sleep f pwm vbus = 350vdc, resistive load vbus = 350vdc, resistive load 390 740 50 100 0.7 0 100 25 1000 1200 200 200 1.5 ns ns s ns ns ms khz output switching characteristics (see figure 5) turn-on propagation delay turn-off propagation delay disable propagation delay turn-on rise time turn-off fall time sleep_mode delay output switching frequency note 1: in all tables t c refers to the temperature of the magnum heat sink surface. note 2: v bus+ to v bus- must be 10v (during short circuit) for short circuit protection to operate.
4 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 table 2. pw-8x225m6 specifications (cont.) v cc = v dd = 5v unless otherwise noted, t c = -55c to 100c for min. and max values, t c = 25c for typ values (see note 1). typ min max units symbol test conditions parameter v ih v il v hyst i ih i il i ih i il i ih i il v ih v il i ih i il t dead tdoff.auto tdon.auto tpw.reset tcycle.auto v cc = 4.5v v cc = 4.5v vin = v cc vin = 0v vin = v cc vin = 0v vin = v cc vin = 0v v cc = 4.5v v cc = 4.5v vin = v cc vin = 0v a ut o reset tied to sc f a ul t 1.55 0.9 0.4 0 2.4 0.6 300 40 2.5 1.6 0.9 0 1.5 20 0.1 3 0.1 23 1 202 3 100 3.15 2.45 2.1 1.5 21 100 1.5 0.8 vdc vdc vdc a ma a na a a vdc vdc a a s ms ms ns ms control inputs a ut o reset high level input voltage low level input voltage hysteresis voltage high level input current low level input current upper, lower high level input current low level input current disable /reset high level input current low level input current sleep_mode high level input voltage low level input voltage high level input current low level input current upper-lower deadtime a ut o reset delay to output off a ut o reset delay to output enabled reset pulsewidth to clear sc f a ul t cycle time between a ut o reset retries table 3. pw-83225m6 specifications v cc = v dd = 5v unless otherwise noted, t c = -55c to 100c for min. and max values, t c = 25c for typ values (see note 1). typ min max units symbol test conditions parameter v cc , v dd i cc i cc sleep_mode fpwm = 25khz 4.5 5 260 5.5 50 350 vdc ma ma power and logic supply voltage logic supply current (see note 2) i scflth i scfltl vo = v cc vo = 0.4v -80 5 6 a ma control outputs sc fault high level output current low level output current jc jc tj tc tcs each upper or lower -55 -55 -65 0.13 0.36 0.2 0.75 150 100 125 c/w c/w c c c in-lbs in-lbs in-lbs oz (gm) thermal maximum thermal resistance - igbt maximum thermal resistance - diode junction temperature range case operating temperature case storage temperature 10 34 5 17 (482) 12 42 65 mechanical mounting torque hold down power terminals d-connector screws weight note 1: in all tables t c refers to the temperature of the magnum heat sink surface. note 2: v bus + to v bus - must be 10v (during short circuit) for short circuit protection to operate. note 1: in all tables t c refers to the temperature of the magnum heat sink surface. note 2: during initial power-on @ vcc~3.5vdc, a transient current pulse up to 100 ma above icc may be observed.
5 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 table 4. pw-84225m6 specifications, v cc = v dd = 5v unless otherwise noted, t c = -55c to 100c for min. and max values, t c = 25c for typ values (see note 1). typ min max units symbol test conditions parameter v cc , v dd i cc i cc i dd sleep_mode fpwm = 25khz 4.5 15 150 5 25 260 10 5.5 50 350 20 vdc ma ma ma power and logic supply voltage logic supply current (see note 2) current amplifier supply current table 5. pw-85225m6 specifications, v cc = v dd = 5v unless otherwise noted, t c = -55c to 100c for min. and max values, t c = 25c for typ values (see note 1). typ min max units symbol test conditions parameter v cc i cc i cc sleep_mode fpwm = 25khz 4.5 5 25 260 5.5 50 350 vdc ma ma power and logic supply voltage current (see note 2) io io i peak v ce (sat) ir ir t c = +25c t c = +85c t c = +85c, 15 ms 50a 480 vdc 480 vdc 2.5 75 50 100 3 200 1.0 a a a vdc a ma overvoltage transistor (regen_clamp) continuous current drive peak current output voltage drop (igbt) reverse leakage @ t j = +25c reverse leakage @ t j = +125c ir ir v trip v hyst 480 vdc 480 vdc without external adjustment 358 35 400 40 750 20 440 45 a ma vdc vdc overvoltage flyback diode reverse leakage @ tc = +25c reverse leakage @ tc = +125c overvoltage trip trip level hysteresis v oh status v ol status rstatus tdon.status tdoff.status no load no load 11.4 4.5 12 0.2 4.75 36 48 12.6 0.4 5 vdc vdc k ? s s regen status (ref. to vbus-) high level output voltage low level output voltage output resistance vtrip rise to status on delay vtrip fall status off delay 0.5 0.75 c/w thermal maximum thermal resistance g vout % g vout e vout v os %v iref v os t cvos % t cvos g vout % g vabs e vabs v osabs % v iref v osabs tc vosabs % tc vosabs t delay f bw irange i oc t ioc i viref v iref 0a = v iref /2 v iref = 5.0v 0a = v iref /2 0a = v iref /2 v iref = 5.0v 0a = v iref /2 v iref = 5.0v 0a = 0v 0a = 0v v iref = 5.0v v iref = 5.0v 50a to 215a step -3 db v iref = 5.0v 50a to 215a step, viref = 5.0v -7 -0.64 -32 -18 -90 -9 -2.66 -133 -18 -90 20 246.2 4 0.185 9.27 0.372 18.6 9 30 215 274 3 0.26 7 0.64 32 22 130 9 2.66 133 22 110 20 299.7 6 1 v dd %v iref /a mv/a % %v iref mv ppm of v iref /c v/c %v iref /a mv/a % %v iref mv ppm of v iref /c v/c s khz a a s ma vdc current amplifier v irsense gain % v irsense gain v irsense gain error v irsense offset % v irsense offset v irsense offset % drift v irsense offset drift v irsense_abs gain % v irsense_abs gain v irsense_abs gain error v irsense_abs offset % v irsense_abs offset v irsense_abs offset % drift v irsense_abs offset drift delay time bandwidth linear range oc f a ul t trip level trip delay time reference voltage current input reference voltage input i ocflth i ocfltl v o = v dd v o = 0.8v max 0.2 15 4 a ma oc f a ul t (-55 to 100c) high level output current low level output current note 1: in all tables t c refers to the temperature of the magnum heat sink surface. note 2: during initial power-on @ vcc~3.5vdc, a transient current pulse up to 100 ma above icc may be observed. note 1: in all tables t c refers to the temperature of the magnum heat sink surface. note 2: during initial power-on @ vcc~3.5vdc, a transient current pulse up to 100 ma above icc may be observed.
6 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 introduction the pw-8x225m6 magnum family is a series of universal mod- ular half-bridge motor drives intended for use with brush, brush- less, dc and ac induction motors in aerospace applications. the pw-8x225m6 contains an isolation barrier between the power and control stages, that attenuates ground noise generat- ed from the high speed, high power switching. all signals from the control to the power sections are isolated from power and ground of the other section. this eliminates false triggering of the input signals and the need for creative grounding schemes. the isolation barrier also allows the user to operate the output stage from either unipolar or bipolar power supplies without level shift- ing the input signals. a built in power supply located in the con- trol stage provides power to all electronics in the power stage. this eliminates the need for refresh cycles or external power supplies for the gate drive circuitry and allows switching duty cycles from 0 - 100%. (reference figures 1a, 1b, and 1c) the output power transistors on all modules are protected from a short circuit applied to the output pin. when a short circuit condition is detected, the output transistors are shut down and a flag sc f a ul t is made active [logic low (l)] indicating a short has occurred. the pw-84225m6 contains additional current sensing circuitry that can monitor either motor current or dc bus current. the output voltage of the current sensing circuit can be used as a feedback signal in a servo drive to create a torque loop. (reference figure 1b) all output power transistors can be protected from regenerative bus overvoltage when utilizing dynamic braking with the addition of one pw-85225m6 module. this module contains an overvolt- age switch that is enabled when an overvoltage condition is detected. this switch is normally wired to an external (user sup- plied, application specific) load dump resistor to provide a load across the high voltage bus when overvoltage is detected. during an overvoltage condition, the status flag regen_sta- tus is active (logic high (h)) indicating an overvoltage condition is occurring. (reference figure 1c) module and i/o operation upper, lower (inputs) upper and lower are active high cmos schmitt-trigger inputs that control the gate drives of the output transistors. (ttl compatibility requires external 10k ? pull-up resistors) each input is electrically isolated from the output. a dead band, as shown in figure 2, between upper and lower inputs is necessary to prevent output cross conduction. sc f a ul t (output) sc f a ul t is an active low open collector output signal that indi- cates when the output of the module has experienced a short circuit condition. sc f a ul t will remain active until disable /reset is made active (l). the signal is inactive at a logic high (h) during normal operation. see short circuit protection for more detail. disable/reset (input) disable /reset is an active low cmos schmitt-trigger input. when disable /reset is held active it does two things: 1.) resets the sc f a ul t (if it was active), and 2.) disables the output (makes the output high impedance) if this line is used solely to clear sc f a ul t then it only needs to be pulsed active. the width of the active pulse must be at least the width of the trip reset pulse (100ns) to ensure that sc f a ul t is cleared properly. when this line is inactive, the output is allowed to respond to the other control lines of the module (upper, lower, sleep_mode). note: ttl compatibility requires an external pull-up resistor. a ut o reset (input) a ut o reset is an active low (l) input. when a ut o reset is tied to sc f a ul t the protection circuit will reset automatically after the short circuit fault has occurred. this automatic reset enables the output to respond to the input commands. see short circuit protection for more detail. short circuit protection the pw-8x225m6 modules have provisions for complete short circuit protection from either a hard or soft short to the v bus + or v bus - lines. each output transistor on all pw-8x225m6 modules is protected from a hard (direct, low impedance) short to the v bus + or v bus - figure 2. pw-8x225m6 dead band requirement tdead = 1.0 ? min. 50% upper lower 50% 50% 1.0 ? min. 50%
7 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 lines by circuitry that detects the de-saturation voltage for that transistor during a short condition. once a hard short circuit con- dition is detected, the active output transistors are shut down and sc f a ul t output is set active [logic low (l)]. the sc f a ul t sig- nal can be used by a controller as a signal to initiate a fault rou- tine to reset or shut down the system. the disable /reset input can be used to shut down the gate drivers if a short per- sists. if the a ut o reset is tied to sc f a ul t , the circuit will automatically reset when a fault occurs. this inactivates sc f a ul t and reactivates the output transistor within 40 to 100ms. if the short is still present, the circuit will repeat the shut down and automatically reset until the short is clear. protecting against a soft short requires the addition of pw- 84225m6 modules for current sensing and external circuitry. when a soft short occurs, the external circuit can set disable /reset low (l) to shut down the gate drivers. sleep_mode (input) sleep_mode is an active high input that turns the internal power supply off. a logic low (l) enables the power supply and allows the motor drive to operate normally. a logic high (h) on the sleep_mode input disables the internal power supply, disabling the motor drive output. no damage will occur to the motor drive during turn on or turn off of the power supply. additionally, no special power up sequence is required. the upper and lower logic gate driver inputs should not be active while transitioning in and out of sleep mode. if the upper and lower logic inputs must be active while entering sleep mode then disable /reset must be held active while coming out of sleep mode. note: sleep_mode has an internal pull-up resistor. if the input is not connected, it will default to logic high, turning the power supply and the motor drive off. v cc , v cc-rtn (inputs) the v cc and v cc-rtn are power connections that supply input power to the internal power supply, the gate drive and fault control circuits. v bus+ , v bus- (inputs) v bus+ and v bus- are the high voltage power connections to the output stage. the high voltage can be either unipolar (+v and ground) or bipolar (+/- v). care must be taken to ensure that the transient bus voltage v bus at the module terminals never exceeds the absolute maximum supply ratings during switching excursions. external capacitor filtering will be required (see ddc applications note an/h-7). output (output) output is the power switch output that is connected to one input of the motor and applies v bus+ , v bus- , or high impedance to the motor based on the state of the control inputs. figure 3 illus- trates the timing relationship between the output and the upper/lower inputs. the output is capable of sourcing or sinking up to 215 amps, and can withstand a short circuit to v bus+ or v bus- without any damage by automatically turning itself off (zstate). v dd , v dd- rtn (applies to the pw-84225m6 only) v dd and v dd-rtn supplies input power to the current amplifier. v irsense (output) (applies to pw-84225m6 only) v irsense is an output that provides a voltage proportional to the current passing through r sense . the voltage is scaled by a ref- erence voltage v ref and is equal to v ref /2 to represent zero current. a voltage greater than viref/2 indicates a positive cur- rent flow (positive voltage from r sense + to r sense -) through r sense . see figure 1b. this v irsense voltage is scaled by the input voltage at v iref , where v irsense = (v iref /2) + (v iref /540) * (i rsense ) note: i rsense is current through r sense = 108m ? . zero amps in r sense is indicated when v irsense = v iref /2. a voltage greater (less) than v iref /2 indicates a positive (negative) current flow through r sense with a value defined by the v irsense equation. v irsense is electrically isolated from the output stage. a positive (negative) current flow from r sense + to r sense - produces a positive (negative) voltage measurement (see figure 1b). when the power supply is shut down (sleep_mode input high), the voltage at v irsense will indicate 0v. v iref (input) (applies to pw-84225m6 only) a precision voltage reference from an external source is con- nected to the v iref pin to set the output voltage scale for v irsense and v irsense_abs . note: the accuracy of the v irsense and v irsense_abs outputs are subject to the accuracy and tem- upper/lower 50% t f t r output current 90% 10% 50% t d (on) t d (off) figure 3. pw-8x225m6 input/output timing relationship
8 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 perature coefficient of v iref . these must be taken into account in calculating the overall accuracy of v irsense . r sense+ , r sense- (inputs) (applies to pw-84225m6 only) the r sense+ and r sense- pins are connected to an internal shunt resistor and monitoring circuitry. these pins can be con- nected anywhere within the isolation restrictions on the pins (600v to power pins, 2500v to logic pins). these pins are typi- cally connected in series with the output, v bus+ or v bus- , to measure motor drive current. v irsense_abs (output) (applies to pw-84225m6 only) v irsense_abs output voltage is the absolute value of the v irsense voltage signal. v irsense_abs is zero volts when there is no current flowing through the r sense resistor. it will increase towards the value of v iref as the current in r sense approaches either -274 or +274 amps (measurement limits of v irsense ). v irsense_abs is an open source output and is "wire-or-able". when two or more v irsense_abs outputs are "wire-or-ed", the highest voltage will appear on the common signal. a typical use for combining these outputs is for determining when an overload condition has occurred. the v irsense_abs voltage is scaled by the input voltage v irsense where: v irsense_abs = 2 x [v irsense- v iref /2] oc f a ul t (output) (applies to pw-84225m6 only) oc f a ul t is an active low open drain output that goes active when the current flowing through r sense has exceeded the oc f a ul t trip level. this signal is not latched like sc f a ul t , and goes inactive as soon as the over current condition stops. regen_status (output) (applies to pw-85225m6 only) the regen_status pin is referenced to v bus- . it indicates the state of the regen clamp switch (h = on, l = off). an external opto-isolator input can be connected between regen_status and v bus- to translate this status to logic circuits if desired. the regen_status output is connected to the 0v amp through a 5k resistor. when the regen clamp switch is active (inactive), the 0v amp sources +15v (0v) through the 5k resistor. (see fig- ure 1c) regen_clamp (output) (applies to pw-85225m6 only) (ref. r20 on figures 13 and 14) an external load dump resistor is connected between regen_clamp and v bus+ . when v bus+ reaches the overvolt- age trip level set by the ov_adj, the internal clamp circuit will apply the load dump resistor from v bus+ to the v bus- , thereby dissipating the regenerative energy in the external resistor. table 6. pw-8x225 truth table disable /reset upper lower test a* test b* test c* a ut o reset output sc f a ul t sleep_mode 1 1 0 1 0 0 1 v bus + 1 0 1 0 1 1 0 0 1 v bus - 1 0 1 1 0 0 1 0 1 v bus + 1 0 1 0 1 0 1 0 1 v bus - 1 0 1 1 0 0 0 1 1 v bus + 1 0 1 0 1 0 0 1 1 v bus - 1 0 1 1 0 1 1 1 1 v bus + 1 0 1 0 1 1 1 1 1 v bus - 1 0 1 0 0 1 1 1 1 z 0 0 1 1 0 1 1 1 1 z 0 0 1 0 1 1 1 1 1 z 0 0 1 x x 0 0 0 x z x 0 0 x x x x x x z x 0 x x x = indicates this input is irrelevant z = high impedance state (off) z (v bus x) = sc fault will not inhibit a gate drive that did not generate the fault. the opposite gate drive may still activate the outp ut (vbusx state). only the gate drive (upper or lower) that faulted is inhibited and the output stays high impedance (zstate) when faulted driver is commanded active. * optional feature of pw-8x225m6-600 only. x x x x x z 1 1
9 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 ov_adj (input) (applies to pw-85225m6 only) the pw-85225m6 is internally set for a trip voltage of 400v. the trip point can be adjusted to a higher or lower voltage by connecting an external overvoltage adjust resistor r ov_adj (ref. r21 on figures 13 and 14). to set the ov trip point to a voltage above 400 volts connect r ov_adj between the ov_adj and ov_adj_high pins. to set the ov trip point to a voltage above 400 volts connect r ov_adj between the ov_adj and ov_adj_low pins. the value of r ov_adj for voltages above (below) 400 volts should be selected based upon figures 4 and 5. test a, test b, test c (pw-8x225m6-600 only) these logic inputs are used to test individual pairs (upper and lower) of output transistors within the module per table 6. the intent is to provide the user with the capability to detect an open transistor within the parallel combination of output devices. note: when test a, test b, test c are exercised individually, the device is not capable of delivering the rated current. 1,000 10,000 100,000 1,000,000 10,000,000 360 370 380 390 400 410 420 430 440 450 460 470 480 490 500 510 520 530 540 550 560 570 580 590 600 trip voltage radj (ohms) turn on turn off figure 4. pw-8x225m6 overvoltage trip voltage vs. resistance of external resistor connected between ov_adj and ov_adj_high 10 100 1,000 10,000 100,000 40 90 140 190 240 290 340 390 trip voltage radj (ohms) turn on turn off figure 5. pw-8x225m6 typical overvoltage trip voltage vs. resistance (in ohms) of external resistor rov_adj connected between ov_adj and ov_adj_low
10 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 power dissipation (see figures 6 and 7) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. consider the following operating conditions: tcase = 85 c vbus = +270v i o = 40a ton = 50 s ; t = 100? ( period ) v ce(sat) = 2.2v (see table 2 and figures 6 and 7) t r = 200ns ) t f = 200ns f pwm = 10khz (switching frequency) v f is the diode forward voltage, (table 2), i o = 50a, t c = +25 c v f (avg) = 1.35v t j max = 150 c (table 2, t j ) jc = 0.55 c / w (table 2) 1. conduction losses (p c ) p c = i o x v ce(sat) x (ton / t) p c = 40a x 2.2v x (50? / 100?) p c = 44w 2. switching losses (p s-total ) p s-total = (p s-on + p s-off ) x fpwm p s-on = ( e on x (vbus / 270) x ( i o /50a) ) p s-on = ( 4.0 x (270 / 270) x (40 / 50)) p s-on = 3.2 mj p s-off = (e off x (v bus /270) x (i o /50)) p s-off = (2.4 mj x (270/270) x (40/50)) p s-off = 1.92 mj p s-total = 10000 x (.0032 + .00192) p s-total = 51.2w 3. flyback diode losses (pdf) pdf = i o x v f (avg) x (1- (ton / t)) pdf = 40a x 1.35v x [1 - (50? / 100?)] pdf = 33.8w 4. transistor power dissipation (p t ) p t = p c + p s = 95.2w 5. maximum module power dissipation (p max ) to calculate the maximum power dissipation of the output tran- sistor / diode pair as a function of the case temperature, use the following equation: p max = ((t j max - t case ) / jc ) 118w = ((150 c - 85 c) / 0.55 c/w) figure 6. output characteristics figure 7. pw-8x2255 average motor current vs. motor drive power dissipation 10% 90% t d (off) 10% 90% 5% v bus o i d (on) t r f t t upper / lower on ps- t on off ps- 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 0 66.67 133.33 200 266.67 333.33 400 466.67 533.33 600 666.67 733.33 800 5khz 10khz 15khz 20khz 25khz average motor current (amps) m o to r d rive p o w e r d issipa tio n (w a tts) 5khz 10khz 15khz 20khz 25khz
11 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 figure 8. - saturation voltage characteristics figure 9. - temperature dependence of vce(sat) 0 30 60 90 120 150 180 210 240 270 300 330 0.511.522.533.5 vce (volts) ic (amps) 0.4 0.6 0.8 1 1.2 1.4 1.6 25 50 75 100 125 150 tj - degrees c vce(sat) - normalized ic = 300a ic = 150a ic = 75a applications the pw-8x225 3-module set can be easily used in a variety of applications, including motor position, velocity or torque control (see figure 10). examples of these applications are described below. position or velocity control using dsp figure 13 shows an example of position and/or velocity control hook-up with inner torque loop using the digital signal processor (dsp) for motor control. using software, the dsp can be imple- mented with one of several motor control algorithms such as foc (field oriented control) with svm (space vector modula- tion). torque hook-up using uc-2625 motor con- troller figure 14 shows an example of torque control loop with regen- erative clamp protection using uc-2625, two pw-84225m6, and one pw-85225m6. two pw-84225m6 ( ? bridge with current sense) sense the current in motor phase b and c. v irsense_abs pins on each of the pw-84225m6 can be tied together to gener- ate a single composite analog output which is compared to the torque commanded input to produce an error signal. uc2625 uses this error signal to regulate the output current (or torque) by controlling the duty cycle of the output transistors. for the case when a resolver is available instead of hall-effect devices, the circuit shown in figure 15 converts the resolver (sin and cos) signals to hall signals which can be used to com- mutate the output transistors. hall signal commutation the hall signals hab, hbc, hca are logic signals from the motor hall-effect sensors. the uc-2625 uses a phasing convention referred to as 120 degree spacing; that is, the output of hab is in phase with motor back emf voltage vab, the output of hbc is in phase with motor back emf voltage vbc, and the output of hca is in phase with motor back emf voltage vca. logic "1" (or high ) is defined by an input greater than 2.4vdc or an open cir- cuit to the controller; logic "0"(or low) is defined as any hall voltage input less than 0.8vdc. the uc-2625 will operate with hall phasing of 60 or 120 elec- trical spacing. if 60 commutation is used, then the output of hca must be inverted as shown in figures 11 and 12. in fig- ure 11 the hall sensor outputs are shown with the correspon- ding back emf voltage they are in phase with.
12 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 position command position error velocity command velocity error torque command torque error current error amp pwm pw-8x075p6 3-module set 3-phase motor torque loop velocity loop position loop + - + - + - motor angle / position information (hall / resolver / encoder) velocity error amp position error amp figure 10. typical position, velocity and torque control loop figure 11. hall phasing figure 12. hall sensor spacing hall-effect sensor phasing vs. motor back emf for cw rotation (120 commutations) 300 0 60 120 180 240 300 360 /0 60 v ab v bc v ca back emf of motor rotating cw cw hab hbc hca hca in phase with v ab in phase with v bc in phase with v ca in phase with v ac (60?) s hca hab 120 n hbc 120 n hca 120 remote position sensor (hall) spacing for 120 degree commutation 60 60 remote position sensor (hall) spacing for 60 degree commutation s hab hbc hca
13 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn motor sleep_mode v cc upper lower sc fault disable/reset v cc-rtn regen_status v bus + output v bus - regen - clamp+ upper lower sc fault oc fault virsense v ref upper lower sc fault i_vout v ref v bus + output v bus - r sense + r sense - v bus + output v bus - r sense + r sense - pw-85225m6 pw-84225m6 pw-84225m6 sleep_mode sleep_mode disable/reset disable/reset oc fault v cc v cc-rtn v cc v cc-rtn v dd v dd-rtn v dd v dd-rtn (4) auto reset auto reset auto reset regen- clamp- vref a / d ch. 1 ua la ub lb uc lc a / d ch. 2 interrupt dsp motor controller position or velocity command resolver r/d converter rd-19230 vcc vdd vdd rtn i / o i / o i / o i / o i / o r22 c12 c13 r23 ov_adj ov_adj_high ov_adj_low r21 (4) figure 13. pw- 8x225m6 position or velocity hook- up using dsp motor controller notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/ h- 7, magnum motor drive power supply capacitor selection. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/ h- 7, magnum motor drive power supply cap acitor selection. 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 (load dump resistor), and r21 (ov adjust resistor) is application specific. (see ov_adj and regen_ clamp descriptions for details)
14 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 +15v +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn r19 10k (8) r18 5k 0.01f c7 r17 10k 10m cr4 3.3v 1n746 cd4050 cd4049 c6 0.1f r15 10k r14 10k r13 10k +5v 19 11 18 14 hca hab hall supply +5v motor lm741 r11 1m r6 1k +5v command signal input 3.3v 1n746 cr5 10k (8) 10k 10k (8) 100 ? lm741 r10 r12 r22 r9 10k (8) r23 cd4049 1/6 1/6 1/6 1/6 q1(9) sleep_mode v cc upper lower sc fault disable/reset v cc-rtn regen_status ov adj v bus + output v bus - regen_ clamp+ upper lower sc fault oc fault v irsense v iref upper lower sc fault v iref v bus + output v bus - r sense + r sense - v bus + output v bus - r sense + r sense - pw-85225m6 pw-84225m6 pw-84225m6 hall rtn 10k v- v- 10k v- 10k uc-2625 sleep_mode sleep_mode disable/reset disable/reset oc fault (10) (10) (10) (11) (11) (11) (11) (11) (11) (11) (11) v cc v cc-rtn v cc v cc-rtn v dd v dd_rtn v dd v dd_rtn (4) auto reset auto reset auto reset regen_ clamp- v irsense_abs v irsense_abs v irsense v irsense_c v irsense_b icomp hca hab hbc v iref v iref v iref current decommutation circuit (see fig. 16) -15v +5v r21 (4) ov_adj_high ov_adj_low a b c +15v hbc hall sensor inputs r1 1k r2 1k c1 2000pf c2 2000pf c3 2000pf r3 1k hca hab hbc 9 8 10 h1 h2 h3 vcc pwr-vc pua pda pub pdb puc pdc isense a isense b gnd quad-se rc-osc pwm-in e/a out e/a in- dir e/a in+ isense s-start rc-brake tach-out ov-coast speed-in r4 10k r5 2k lm111 r7 20k c5 0.001f 7 23 20 21 24 3 1 6 28 27 2 22 25 26 c4 0.01f r16 15 5 4 12 16 17 13 figure 14. pw- 8x225m6 torque hook- up using uc- 2625 motor controller notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/ h- 7, magnum motor drive power supply capacitor selection. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/ h- 7, magnum motor drive power supply cap acitor selection. 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 and r21 is application specific. 5. all resistors have a tolerance of 10%, unless otherwise specified. 6. the cd4050 converts the +15v logic output of the uc- 2625 to +5v logic signals. 7. the cd4049 (or equivalent) inverts the upper signal from the uc- 2625. 8. 1% or better, depending on required accuracy. 9. q 1 can be either irml2402 or irmu014 or irld014. 10. these high impedance inputs and summing junctions of the operational amplifiers are highly sensitive to noise. 11. these grounds should be closely tied together to reduce ground noise effect. 12. connect hall sensor inputs to motor shaft position sensors that are 120 electrical degrees apart. motors with 60 electrical d egree position sensor coding can be used if one or two of the position sensor signals are inverted.
15 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 -vco vel -vsum cos -c +c bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 cb sin -s +s agnd +ref u3 -ref gnd a b bit/ inh/ el/ em/ c26 0.1f c27 22f c28 0.1f c29 22f 15 40 +5v r27 120k c25 560pf r28 2.8 m c24 56pf 9 8 7 6 5 10 11 13 14 12 19 20 4 r24 20k r25 20k r26 20k 1 2 r35 10k r29 0.1k r30 0.1k rs rc r31 10k r32 1k 2n2907 +15v 21 cr7 39 18 3 +5v vpp pgm oe ce a0 26 24 33 31 37 35 25 23 29 27 10 9 6 5 8 7 25 24 4 3 a1 a2 a3 a4 a5 a6 a7 a8 a9 20 22 c30 0.1f +5v 27 1 a10 a11 a12 21 23 2 00 01 02 03 04 05 06 07 26 24 33 31 37 35 27c64 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 74hct374 clk d7 +5v 1 11 r33 10k hc hb ha +15 -15 gnd gnd sense sin c22 0.1f +15v c23 0.1f -15v 13 8 10 11 2 1 c20 0.1f c21 0.1f +15v +15v 16 2 3 20 19 1 4 1 2 3 4 5 6 u6 el2009 16 17 -5v 22 ddc rdc-19220 hall outputs digital position & velocity information which can be used by the dsp (figure 8a) to close the position and/or velocity loops resolver inputs figure 15. resolver to hall signal conversion circuit
16 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 logic equations: /** inputs **/ ha /* phase a hall input, active high */ hb /* phase b hall input, active high */ hc /* phase c hall input, active high */ /** outputs **/ sw_gcomp /* positive gain compensation switch control, active low*/ sw_nb /* switch control for negative b curre nt, active low */ sw_nc /* switch control for negative c curre nt, active low */ sw_pb /* switch control for positive b curre nt, active low */ sw_pc /* switch control for positive c curre nt, active low */ /** equations **/ /** operator definition => = and, + = or **/ sw_gcomp = ( ha) sw_nb = (ha hb hc) sw_nc =( ha hc) sw_pb = (ha hb hc) sw_pc = (ha hc) table [ha,hb,hc] => [sw_gcomp,sw_nb,sw_nc, sw_pb,sw_pc] ia_n ic_p ia_p ic_n zero i_b_bipolar2 i_c_b ipolar2 vref ic ib i_comp 0 0 0 0 0 0 0 0 0 u4b lf 147 5 6 4 11 7 + - v+ v- out u3 dg201 1 3 2 16 14 15 9 11 10 8 6 7 12 13 5 4 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 vl vdd gnd vss { rp } u4a lf 147 3 2 4 11 1 + - v+ v- out r6 4k { rn } u6 dg 201 1 3 2 16 14 15 9 11 10 8 6 7 12 13 5 4 in1 s1 d1 in2 s2 d2 in3 s3 d3 in4 s4 d4 vl vdd gnd vss r8 4k r9 4k u4c lf147 10 9 4 11 8 + - v+ v- out { rp } r10 4k r11 4k { rf } r12 4k { rs } r7 4k c4 1000p { rn } { rf } c3 1000p comp { rs } { rs }, { rp }, { rn } and vref relationships: hca hcb hcc +5v (common to all) +15v +15v +15v +5v +15v -15v +5v -15v -15v -15v -15v +15v 74ls14 54ls00 54ls00 54ls00 54ls00 54ls00 nb pc pb nc b 000 => b 01111; b 001 => b 11011; b 010 => b 10111; b 011 => b 11011; b 100 => b 01110; b 101 => b 01101; b 110 => b 01110; b 111 => b 11111; figure 16. pw-8x225m6 current decommutation circuit
17 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 table 7. pin assignments pin # control pins power pins 1 pw-83225m6 pw-84225m6 pw-85225m6 sleep_mode sleep_mode sleep_mode 2 test b * test b * test b * 3 test a * test a * test a * 4 v cc v cc v cc 5 v cc-rtn v cc-rtn v cc-rtn 6 n/c n/c n/c 7 sc f a ul t sc f a ul t sc f a ul t 8 n/c n/c n/c 9 n/c n/c regen_status 10 n/c n/c 0v_adj_high 11 n/c n/c 0v_adj 12 n/c n/c 0v_adj_low 13 n/c v iref n/c 14 test c * test c * test c * 15 a ut o reset a ut o reset a ut o reset 16 v cc v cc v cc 17 v cc-rtn v cc-rtn v cc-rtn 18 disable/reset disable/reset disable /reset 19 lower lower lower 20 upper upper upper 21 n/c v cc-rtn n/c 22 n/c v dd n/c 23 n/c v irsense n/c 24 n/c v irsense_abs n/c 25 n/c oc f a ul t n/c 4 n/a r sense+ n/a 1 v bus+ v bus+ v bus+ 2 output output output 3 v bus- v bus- v bus- 5 * optional feature of pw-8x255m6-600 only n/a r sense- regen_clamp
18 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 j1 (usa ) b a figure 17. pw-8x225m6 mechanical outline
19 data device corporation www.ddc-web.com pw-8x225 preliminary a-8/30/02-0 ordering information pw - 8x225m6 - x x 0 process requirements 0 = standard ddc procedures no burn-in 2 = high reliability processing with burn-in temperature grade/data requirements 1 = -55 c to +125 c 3 = -0 c to +70 c 4 = -55 c to +125 c with variables test data 8 = 0 c to +70 c with variables test data 9 = -55 c to 85 c voltage rating 6 = 600v current rating 225 = 225a features 3 = standard ? bridge 4 = standard ? bridge w/ current sense 5 = standard ? bridge w/ regenerative voltage clamp pw-8x225m6-600 high reliability version (-55 to +125 degrees c) with individual transistor testability.
20 preliminary a-3/1/02-0 printed in the u.s.a. the information in this preliminary data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7677 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u

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