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motorola motorola six sigma 6 s microprocessor & memory technologies group m68360quads-040 users manual issue 1.0 - draft thi d t t d ith f m k 4 0 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 - user? manual draft 1.0 table of contents 1 - general information 7 1.1 introduction 7 1.2 related documentation 7 1.3 abbreviations used in the document 7 1.4 specifications 7 1.5 cooling requirements 8 1.6 features 9 1.7 hardware block diagram 10 2 - hardware preparation and installation 11 2.1 introduction 11 2.2 unpacking instructions 11 2.3 hardware preparation 11 2.3.1 adi port address selection 13 2.3.2 caches enable / disable 14 2.3.3 mmu enable / disable 14 2.3.4 parity error interrupt generation 14 2.3.5 arbitration configuration 14 2.3.6 eest configuration 14 2.3.7 user selectable options 14 2.4 installation instructions 14 2.4.1 +5v power supply connection 15 2.4.2 p7: +12v power supply connection 15 2.4.3 adi installation 15 2.4.4 host computer to m68360quads-040 connection 15 2.4.5 terminal to m68360quads-040 rs-232 connection 16 3 - operating instructions 17 3.1 introduction 17 3.2 controls and indicators 17 3.2.1 soft reset switch sw1 17 3.2.2 abort switch sw2 17 3.2.3 hard reset - switches sw1 & sw2 17 3.2.4 eest configuration jumpers j1 to j6 17 3.2.4.1 tpen jumper - j1 17 3.2.4.2 aport jumper - j2 17 3.2.4.3 tpapce jumper - j3 17 3.2.4.4 tpsqel jumper - j4 17 3.2.4.5 tpfuldl jumper - j5 18 3.2.4.6 loop - diagnostic loopback jumper - j6 18 3.2.5 hardware breakpoint usage jumper - j7 18 3.2.6 parity error interrupt jumper - j8 18 3.2.7 bus request jumper - j9 18 3.2.8 bus grant jumper - j10 18 3.2.9 halt indicator - ld10 18 3.2.10 040run indicator - ld8 18 3.2.11 dmarun indicator - ld9 19 3.2.12 ethernet tx indicator - ld3 19 3.2.13 ethernet rx indicator - ld2 19 3.2.14 ethernet clsn indicator ld4 19 3.2.15 ethernet lil indicator - ld5 19 3.2.16 ethernet plr indicator - ld6 19 3.2.17 ethernet jabb indicator - ld1 19 3.2.18 power indicator - ld7 19 3.3 memory map 19 3.3.1 main memory map 20 thi d t t d ith f m k 4 0 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 - user? manual draft 1.0 table of contents 3.4 programming the slave quicc 21 3.4.1 module base address register 21 3.4.2 module configuration register 21 3.4.3 clko control register 21 3.4.4 pll control register 21 3.4.5 port e pin assignment register 21 3.4.6 system protection control 21 3.4.7 global memory register 22 3.4.8 base register 0 and option register 0 22 3.4.9 base register 1 and option register 1 22 3.4.10 base register 2 and option register 2 23 3.4.11 base register 3 and option register 3 23 3.4.12 base register 4 and option register 4 23 3.4.13 base register 5 and option register 5 24 3.4.14 base register 6 and option register 6 24 3.4.15 base register 7 and option register 7 24 3.4.16 port a open drain register 24 3.4.17 port a data register 24 3.4.18 port a data direction register 24 3.4.19 port a pin assignment register 24 3.4.20 port b open drain register 24 3.4.21 port b data register 24 3.4.22 port b data direction register 25 3.4.23 port b pin assignment register 25 3.4.24 port c data register 25 3.4.25 port c data direction register 25 3.4.26 port c pin assignment register 25 3.4.27 port c special options register 25 4 - functional description 26 4.1 introduction 26 4.2 master mc68ec040 26 4.2.1 reset for the 68ec040 & the quicc 26 4.2.2 utilizing the mc68ec040 data cache 27 4.3 interrupts on the m68360quads-040 27 4.3.1 abort push-button 27 4.3.2 host - nmi 28 4.3.3 hardware-breakpoint interrupt 28 4.3.4 parity error interrupt 28 4.3.5 host request / acknowledge interrupt 28 4.4 bus arbitration 28 4.5 system utilities 29 4.5.1 breakpoints generator 29 4.5.2 bus monitor 29 4.5.3 spurious interrupt monitor 30 4.5.4 software watch-dog 30 4.5.5 periodic interval timer - pit 30 4.6 clock generator 30 4.7 flash prom 30 4.8 bursting sram 30 4.9 eeprom 31 4.10 dram 31 4.11 slave quicc 31 4.11.1 dram controller 32 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 - user? manual draft 1.0 table of contents 4.11.2 chip select ta~ and dsack~ generator 32 4.11.3 adi port 32 4.11.3.1 adi port signal description 33 4.11.4 rs-232 serial port 34 4.11.4.1 rs-232 port signal description 35 4.11.5 m68360quads-040 status register 35 4.11.5.1 status register bits description 35 4.11.6 ethernet controller 36 4.11.6.1 ethernet aui ports signal description 36 4.11.6.2 ethernet twisted-pair port signal description 37 4.11.7 serial eeprom 37 4.11.8 slave quicc general purpose i/o pins 37 4.11.8.1 slave quicc port a 37 4.11.8.2 slave quicc port b 38 4.11.8.3 slave quicc port c 39 4.11.8.4 slave quicc port e 40 5 - support information 41 5.1 introduction 41 5.2 interconnect signals 41 5.2.1 connector p1 interconnect signals 41 5.2.2 connector p2 interconnect signals 42 5.2.3 connector p3 interconnect signals 42 5.2.4 connector p4 interconnect signals 43 5.2.5 connector p5 interconnect signals 43 5.2.6 connector p6 interconnect signals 44 5.2.7 connector p7 interconnect signals 44 5.2.8 connector p8 interconnect signals 44 5.2.9 connector p9 interconnect signals 45 5.2.10 connector p10 interconnect signals 47 5.2.11 connector p11 interconnect signals 47 5.3 m68360quads-040 parts list 47 a.1 introduction 51 a.2 ibm-pc/xt/at to m68360quads-040 interface 51 a.2.1 adi installation in ibm-pc/xt/at 51 a.3 sun-4 to m68360quads-040 interface 52 a.3.1 adi installation in the sun-4 53 appendix b - adi port handshake description 55 b.1 introduction 55 b.2 adi port concept and operation description 55 b.3 handshake description 55 b.3.1 write cycle from host to m68360quads-040 56 b.3.2 write cycle from m68360quads-040 to host 57 b.3.3 m68360quads-040 interrupt to the host 58 b.3.4 host interrupt to the m68360quads-040 59 b.3.5 host reset to the m68360quads-040 59 b.3.6 addressing all m68360quads-040 59 appendix c - pals?equations 60 c.1 u10 - indicators logic 60 c.2 u11 - reset & abort generator 61 c.3 u12 - adi controller 64 c.4 u23 - core disable logic 65 c.5 u32 - bursting sram controller 68 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 - user? manual draft 1.0 list of figures figure 2-1 m68360quads location diagram 12 figure 2-2 configuration dip-switch - dsw1 13 figure 2-3 p6: +5v power connector 15 figure 2-4 p6: +12v power connector 15 figure 2-5 p1 - adi port connector 16 figure 2-6 p2 - rs-232 serial port connector 16 figure 4-1 arbitration scheme: 29 figure 4-2 adi port connector 33 figure 4-3 rs-232 serial port connector 35 figure 4-4 status register 35 figure 4-5 ethernet aui port connector 36 figure 4-6 ethernet twisted-pair port connector 37 figure a-1 physical location of jumper jg1 and jg2 52 figure a-2 jg1 configuration options 52 figure a-3 adi board for sbus 53 figure b-1 host computer (adi) to m68360quads-040 connection 56 figure b-2 host write to m68360quads-040 57 figure b-3 m68360quads-040 write cycle to host 58 figure b-4 m68360quads-040 interrupt to host 59 thi d t t d ith f m k 4 0 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 user? manual draft 1.0 list of tables table 1-1. m68360quads-040 specifications 1 table 3-1. ec040 cycle types and responding devices 13 table 3-2 m68360quads-040 main memory map 14 table 4-1. dram simm types 27 table 4-2 port a pins description 34 table 4-3 port b pins description 35 table 4-4 port c pins description 36 table 5-1 connector p1 interconnect signals 37 table 5-2 connector p2 interconnect signals 38 table 5-3 connector p3 interconnect signals 38 table 5-4 connector p8 interconnect signals 39 table 5-5 connector p5 interconnect signals 39 table 5-6 connector p6 interconnect signals 40 table 5-7 connector p7 interconnect signals 40 table 5-8 connector p8 interconnect signals 40 table 5-9 connector p9 interconnect signals 41 table 5-10 parts list 43 thi d t t d ith f m k 4 0 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual general information 7 1 - general information 1.1 introduction this document describes the evaluation board for the mc68ec040 - mc68360 combination called the m68360quads-040. this board is constructed with an mc68ec040 as the master processor and a mc68360 (quicc) as a slave in mc68ec040 companion mode. the purpose of this board is to evaluate the performance of the above combination, rather than serve as a development system. . 1.2 related documentation mc68360 user? manual. mc68ec040 user? manual. mc68lc040 user? manual. adi board specification. 1.3 abbreviations used in the document quads - application development system for the quicc device. adi - application development interface. uart - universal asynchronous receiver/transmitter. simm - single in-line memory module. aui - attachment unit interface. spi - serial peripheral interface nmi - non maskable interrupt eest - enhanced ethernet serial transceiver the mc68160 sia - serial interface adapter, the am7992 tp - twisted pair nsec - nano second 1.4 specifications the m68360quads-040 specifications are given in table 1-1. paragraph 1.5 details the cooling requirements. table 1-1. m68360quads-040 specifications characteristics specifications power requirements (no other boards attached) +5vdc @ 3.5 a (typical), 5 a (maximum) +12vdc - determined by the ethernet network a microprocessor xc68ec/lc040fe33 b @ 25 mhz thi d t t d ith f m k 4 0 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual general information 8 1.5 cooling requirements the m68360quads-040 is specified, designed, and tested to operate reliably with an ambient air temperature range from 0 o c to 30 o c. this, due to the overheating problems of the xc68ec040 as the 68ec040 must have a heat-sink attached to it for proper operation at room 1 temperature. therefore, the ambient temperature of operation for the m68360quads-040 should never exceed 30 o c . a. the 12v supply is not used on the board, it is connected only to the ethernet aui connectors p3 & p5 to be supplied to the network. therefore, the power consumption of that supply is independent of the m68360quads-040. b. 33 mhz components are used to get better s.u. timing between the quicc & the ec040. c. since a28 to a31 of the slave quicc are used as write-enable signals, the on-board addressing space is reduced to 256 mbytes. 1. if no heat sink is attached to the 68ec040, maximum ambient temperature allowed @ 25 mhz is -4 o c !!! addressing total address range: on-board - off-board - flash memory dynamic ram eeprom 256 mbytes c 4 gigabytes 512 kbyte, 32 bits wide expandable to 2 mbytes 1 mbyte, 36 bits wide simm (32 bit data, 4 bit parity) option to use higher density simm, up to 8 mbyte 256 byte, serial eeprom operating temperature 0 o c - 30 o c storage temperature -25 o c to 85 o c relative humidity 5% to 90% (non-condensing) dimensions: height depth thickness 9.173 inches (233 mm) 6.3 inches (160 mm) 0.063 inches (1.6 mm) table 1-1. m68360quads-040 specifications characteristics specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual general information 9 1.6 features following are the main features of the m68360quads-040: o master mc68ec040fe33 with 32-bit address bus, 32 bit data bus, instruction and data caches. o supports also mc68lc040. o 1 mbyte dynamic ram, 60 nsec access time, 36 bits wide (data and parity) simm, accessed with 3,2,2,2 clock cycles. support for dram simms upto 8 mbyte with automatic size and speed detection. o 512 kbyte flash prom, on-board (5v) programmable, individual sector protection, 32 bits wide, 120 nsec access time, support is given up to 2 mbyte. o 128k byte synchronous bursting sram, 36 bits wide, 12 nsec access time. accessed with 3,1,1,1 clock cycles. option for additional 128k byte identical bank. o 256 byte serial eeprom, accessed by the spi port. o application development interface (adi) port via 37 pin d-type connector. o serial rs-232 port for terminal or host computer connection via 9 pin dtype connector. o two ethernet ports: 1. the first using motorola? mc68160 (eest) with both aui and tp connectors. 2. the second using amd? am7992 (sia) with aui connector. o scc2 (connected to the second ethernet port) may be used for other purpose, by removing the sia from its socket. o expansion and logic analyzer connectors for both slave quicc and mc68ec040. o slave quicc (core disabled in 68ec040 companion mode) providing the following functions: 1. dram controller 2. chip select, ta~ and dsack~ generator. 3. parallel port (adi) controller. 4. uart for terminal or host computer connection. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual general information 10 5. dual-port ethernet controller. o vmebus double-height board dimensions o soft-reset, hard-reset and abort switches. o status leds for power, ec040 run, dma run, halt and ethernet signals. o single +5vdc power supply. 1.7 hardware block diagram 1 mbyte dram 256 byte eeprom adi port rs-232 port expansion connectors logic analyzer connectors mc68ec/lc040 (master) quicc (slave) ethernet port eest mc68160 512 kbyte flash-prom aui connector ethernet port t.p rj-45 connector (32 bits wide) (serial) (36 bits wide simm) with parity 256 k byte burst sram (36 bit wide) staus register sia am7992 ethernet port aui connector reset, interrupt & indications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual hardware preparation and installation 11 2 - hardware preparation and installation 2.1 introduction this chapter provides unpacking instructions, hardware preparation, and installation instructions for the m68360quads-040. 2.2 unpacking instructions note if the shipping carton is damaged upon receipt, request carrier? agent be present during unpacking and inspection of equipment. unpack equipment from shipping carton. refer to packing list and verify that all items are present. save packing material for storing and reshipping of equipment. caution avoid touching areas of integrated circuitry; static discharge can damage circuits. 2.3 hardware preparation to select the desired configuration and ensure proper operation of the m68360quads-040 board, changes of the dip-switch settings may be required before installation. the location of the switches, leds, dip-switches, and connectors is illustrated in figure 2-1. the board has been factory tested and is shipped with dip-switch settings as described in the following paragraphs. parameters can be changed for the following conditions: adi port address enable/disable mc68ec040? caches (both instruction and data) eanble / disable mc68lc040? memory management unit 1 hardware breakpoint logic operation parity error interrupt generation arbitration configuration eest twisted pair interface configuration user selectable options 1. if a mc68 lc 040 device is installed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual hardware preparation and installation 12 figure 2-1 m68360quads location diagram p11 p10 p9 p1 adi port rs-232 port p6 p7 +5v +12v f1 5a dram simm u22 u33 u34 u35 u36 dip-switch sw1 sw2 abort soft reset mc68ec040 u24 u25 slave quicc mc68360 p2 p5 p4 ethernet aui (sia) ethernet tp p3 ethernet aui (eest) dsw1 1 flash memory u18 u19 u20 u21 u27 u28 u29 u30 bursting sram p8 j7 j8 j9 j10 1 a 1 1 1 1 j1 j2 j3 j4 j5 j6 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual hardware preparation and installation 13 2.3.1 adi port address selection the m68360quads-040 can have eight possible slave addresses set for its adi port, enabling up to eight m68360quads-040 boards to be connected to the same adi board in the host computer. the selection of the slave address is done by setting switches 6, 7 & 8 in the dip-switch. switch 6 stands for the most- significant bit of the address and switch 8 stands for the least-significant bit. if the switch is in the ?n?state, it stands for logical ?? in figure 2-2 dsw1 is shown to be configured to address ?? figure 2-2 configuration dip-switch - dsw1 table 2-1 describes the switch settings for each slave address: table 2-1 adi address selection address switch 6 switch 7 switch 8 0 off off off 1 off off on 2 off on off 3 off on on 4 on off off 5 on off on 6 on on off 7ononon dsw1 on 5 6 7 8 1 2 3 4 sel2: on - ?? off ? sel1: on - ?? off ? sel0: on - ?? off ? opt2: on - ?? off ? opt1: on - ?? off ? opt0: on - ?? off ? cdis~: on - disabled mdis~: on - disabled f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual hardware preparation and installation 14 2.3.2 caches enable / disable switch #1 on dsw1 enables / disables the mc68ec040 caches. when it is in ?ff?position (factory setup) both caches may be enabled by software. when it is in ?n?position, both instruction and data caches can not be enabled by software. 2.3.3 mmu enable / disable switch #2 on dsw1 enables / disables the memory management unit, which exists only on a mc68lc040 processor. when a mc68ec040 is installed, this switch has no effect. when switch #2 is in ?ff?position the mmu (if exists) is enabled, when in ?n?position - the mmu (if exists) is disabled. hardware break point logic configuration the hardware breakpoint out signal (bkpto~) of the quicc may be used for 2 purposes: 1. generating level 7 interrupt (nmi) to the ec040, serving its original purpose. 2. a caching shield logic, to avoid redundant caching of data into the data cache the selection between the above is done via jumper j7. when pins 1 and 2 of j7 are connected, the breakpoint logic functions in its original goal. when pins 2 and 3 of j7 are connected, the breakpoint logic serves a data caching shield. j7 is configured at factory to position 1-2. 2.3.4 parity error interrupt generation when the quicc? parity logic is operating, i.e., parity is generated and checked by the memory controller, it is possible to generate level 5 interrupt to the ec040 when parity error is encountered. when jumper j8 is connected, the quicc? parity error line (perr~) is connected to the quicc? level 5 interrupt request line - irq5~ to generate level 5 interrupt upon parity error occurrence. when j8 is disconnected, no parity error interrupt is generated. j8 is disconnected at factory. 2.3.5 arbitration configuration to allow for external master to be connected off-board, the arbitration scheme must be changed. jumper j9 connects between the ec040 bus request output (br040~) and quicc? bus request input (brq~), while j10 connects between the quicc? bus grant output (bgq~) and the ec040? bus grant input (bg040~). when both j9 and j10 are connected, arbitration is done by the quicc? arbiter. when both j9 and j10 are disconnected, an external arbiter may be introduced via the expansion connectors. both j9 & j10 are connected at factory. 2.3.6 eest configuration the configuration of the mc68160 - eest is determined by the position of jumpers j1 to j6. for the concise description of the role of each jumper see section 3.2.4 on page 17. the eest is factory set to aui interface, i.e., jumpers j1, j2 & j6 connected and j2 - j5 disconnected. 2.3.7 user selectable options since the state of switches #3 to #5 is readable to software via the board status-register, it is possible to use them for software configuration, modes?selection, etc. for further information on that subject see 4.11.5 on page 35. 2.4 installation instructions when the m68360quads-040 has been configured as desired by the user, it can be installed according to the required working environment as follows: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual hardware preparation and installation 15 2.4.1 +5v power supply connection the m68360quads-040 requires +5 vdc @ 5 a max, power supply for operation. connect the +5v power supply to connector p11 as shown below: figure 2-3 p6: +5v power connector p5 is a 3 terminal block power connector with power plug. the plug is designed to accept 14 to 22 awg wires. it is recommended to use 14 to 18 awg wires. to provide solid ground, two gnd terminals are supplied. it is recommended to connect both gnd wires to the common of the power supply, while vcc is connected with a single wire. note since hardware applications can be connected to the m68360quads-040 using the expansion connectors p8 and p10, the additional power consumption should be taken into consideration when a power supply is connected to the m68360quads-040. 2.4.2 p7: +12v power supply connection the m68360quads-040 requires +12 vdc @ 1 a max, power supply for the ethernet aui port. the m68360quads-040 can work properly without the +12v power supply, if the aui port is not in use or if the aui port is used with an aui hub that does not require 12 v to be provided by the network termination equipment. connect the +12v power supply to connector p6 as shown below: figure 2-4 p6: +12v power connector p6 is a 2 terminal block power connector with power plug. the plug is designed to accept 14 to 22 awg wires. it is recommended to use 14 to 18 awg wires. 2.4.3 adi installation for adi installation on various host computers, refer to appendix a - on page 51. 2.4.4 host computer to m68360quads-040 connection the m68360quads-040 adi interface connector, p1, is a 37 pin, male, d type connector. the connection between the m68360quads-040 and the host computer is by a 37 line flat cable, supplied with the adi board. figure 2-5 below shows the pin configuration of the connector. vcc gnd gnd 1 2 3 vpp gnd 1 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual hardware preparation and installation 16 figure 2-5 p1 - adi port connector note: pin 26 on the adi is connected to +12 v power supply, but it is not used in the m68360quads-040. 2.4.5 terminal to m68360quads-040 rs-232 connection in the stand-alone operation mode, a vt100 compatible terminal should be connected to the rs-232 connector p2. the rs-232 connector is a 9 pin, female, d-type connector as shown in figure 2-6. figure 2-6 p2 - rs-232 serial port connector note: the rts line (pin 7) is not connected in the m68360quads-040. gnd 20 int_ack 1 2 gnd 21 gnd 22 gnd 23 gnd 24 gnd 25 (+ 12 v) n.c. 26 hst_ack 3 ads_all 4 host_vcc ads_reset ads_sel2 ads_sel1 ads_sel0 5 6 7 8 27 host_vcc host_vcc gnd gnd host_enable~ host_req ads_req ads_ack ads_int host_brk~ ads_brk 9 10 11 12 13 14 28 29 30 31 32 gnd 33 pd0 34 pd2 pd4 pd6 n.c. pd1 pd3 pd5 pd7 15 16 17 18 19 35 36 37 n.c. 1 tx 2 rx 3 rts 4 cts 5 dsr 6 gnd 7 cd 8 9 n.c. dtr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 17 3 - operating instructions 3.1 introduction this chapter provides necessary information to use the m68360quads-040 in host-controlled and stand- alone configurations. this includes controls and indicators, memory map details, and software initialization of the board. 3.2 controls and indicators the m68360quads-040 has the following switches and indicators. 3.2.1 soft reset switch sw1 the soft reset switch, sw1, resets all m68360quads-040 devices, and resets the ec040, and performs soft reset to the quicc internal modules, maintaining quicc? configuration (clocks & chip- selects) . the switch signal is debounced, and it is not possible to disable it by software. 3.2.2 abort switch sw2 the abort switch is normally used to abort program execution by issuing a level 7 interrupt to the ec040 to return control to the quicc040bug. the abort switch signal is debounced and can not be disabled by software. 3.2.3 hard reset - switches sw1 & sw2 when both switches - sw1 and sw2 are depressed simultaneously, hard reset is generated to both the ec040 and quicc. when the quicc is hard reset, all its configuration is lost and has to be re- initialized. 3.2.4 eest configuration jumpers j1 to j6 the following jumpers j1 to j6 are used to determine the eest operation modes according to the description below: 3.2.4.1 tpen jumper - j1 the tpen (twisted pair enable) jumper, determines the interface type of the eest ethernet port. when in position along with j2, the eest port uses the aui interface. when removed and j2 in position, the interface type is twisted pair. warning whenever j2 is to be removed, j1 must be removed prior to the removal of j2. failure in doing so, might result in permanent damage to eest device (u7). 3.2.4.2 aport jumper - j2 when the aport (automatic port selection enable) jumper - j2 is in position, the interface type of the eest device is selected manually via j1. when j2 is removed, the selection is done automatically according to the presence of link beats on the twisted pair receive input. 3.2.4.3 tpapce jumper - j3 when the tpapce (twisted pair automatic polarity correction enable) jumper - j3 is removed, the eest device corrects internally polarity faults and indicates them via the tpplr led - ld6. when j3 is in position, automatic polarity correction is disabled. 3.2.4.4 tpsqel jumper - j4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 18 when the tpsqel (twisted pair signal quality error test enable) jumper - j4 is in position, the collision detect circuitry test is enabled, i.e., simulated collision is generated to the eest collision detect circuitry. the generated collision does not have any effect over the tp media. when j4 is removed, the above test is disabled. 3.2.4.5 tpfuldl jumper - j5 when the tpfuldl (twisted pair full duplex mode select) jumper - j5 is in position, simultaneous receive and transmit are enabled for the tp port without collision indication. when j5 is removed, the above is disabled. 3.2.4.6 loop - diagnostic loopback jumper - j6 when the loop jumper - j6 is removed, diagnostic loop-back mode is enabled for the eest regardless of the interface type selected. in this mode, data is transmitted back into the receiver but not to the medium. when j6 is in position, the diagnostic loop-back mode is disabled. 3.2.5 hardware breakpoint usage jumper - j7 when j7 is connected between pins 1- 2, the hardware breakpoint out (bkpto~) signal of the quicc is connected to the interrupt logic. when breakpoint is reached, level 7 interrupt is generated to the ec040. when j7 is connected between pins 2 - 3, bkpto~ is connected to the transfer cache inhibit (tci~) signal of the ec040. that way desired memory areas may be ?hielded?and prevented from being cached. this allows for better utilization of the ec040 data cache, keeping one-time accessed data out of the data cache. 3.2.6 parity error interrupt jumper - j8 when j8 is positioned in place and parity is enabled, occurrence of parity error, causes a level 5 interrupt to the ec040 via the quicc? interrupt controller. when j8 is removed, parity error interrupts are disabled. 3.2.7 bus request jumper - j9 when j9 is in position, the bus request (br~) output of the ec040 is connected to the bus request input of the quicc. this is the normal operating mode. when j9 is removed, the bus request output of the ec040 is disconnected from the bus request input of the quicc, allowing for an external (off-board) arbiter to be located between them. 3.2.8 bus grant jumper - j10 when j10 is in position the bus grant (bg~) output of the quicc is connected to the bus grant input of the ec040. this is the normal operating mode. when j10 is removed, the bus grant output of the quicc is disconnected from the bus grant input of the ec040, allowing for an external (off-board) arbiter to be located between them. note for proper operation of the m68360quads-040, both j9 and j10 must be in position, unless an external arbiter is connected via the expansion connectors. 3.2.9 halt indicator - ld10 the red led halt indicator ld1 is lit whenever the ec040 enters the halt state. for example, when the ec040 can not recover from an error, it frees the bus and enters the halt state. 3.2.10 040run indicator - ld8 the green led 040run indicator is connected to the transfer in progress (tip*) signal. it is lit if the tip* signal is low (asserted) and it indicates the activity on the bus. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 19 3.2.11 dmarun indicator - ld9 the yellow dmarun indicator is connected to as* signal of the slave quicc, this to indicate bus activity of one of the quicc? dma channels. 3.2.12 ethernet tx indicator - ld3 the green led ethernet transmit indicator blinks whenever the eest is transmitting data through one of the ethernet ports p3 or p4. 3.2.13 ethernet rx indicator - ld2 the green led ethernet receive indicator blinks whenever the eest is receiving data from one of the ethernet ports p3 or p4. 3.2.14 ethernet clsn indicator ld4 the red led ethernet collision indicator clsn, blinks whenever a collision is detected in the aui p3 port or the tp p4 port, or a jabber condition is detected in tp mode. 3.2.15 ethernet lil indicator - ld5 the yellow led ethernet twisted pair link integrity indicator - lil, lights to indicate good link integrity on the tp p4 port. the led is off when the link integrity fails, or when the aui port is selected. 3.2.16 ethernet plr indicator - ld6 the red led ethernet tp polarity indicator - plr, lights if the wires connected to the receiver input of tp p4 port are reversed. the led is lit by the eest, and remains on when the eest has automatically corrected for the reversed wires. 3.2.17 ethernet jabb indicator - ld1 the red led ethernet tp jabber indicator - jabb, lights whenever a jabber condition is detected on the tp p4 port. 3.2.18 power indicator - ld7 the yellow power indicator, indicates the presence of the +5v supply at p5. 3.3 memory map at the beginning of each cycle, the chip-select generator of the slave quicc determines the kind of memory cycle and which device is selected. cycle types and address spaces are determined for ec040 cycles by the transfer modifier lines tm0 - tm2 and the transfer type lines tt0 - tt1 and by function codes fc0 - fc3 for quicc? dma cycles. the cycle types and the devices that respond are described in table 3-1. table 3-1. ec040 cycle types and responding devices tm(2:0) tt(1:0) address space responding devices 000 00 data cache push all 001 0x user data all 010 00 user program all 011 00 mmu table search a data all f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 20 3.3.1 main memory map the memory map of devices that respond to user data, user program, supervisory data, supervisory program, and dma access is shown in table 3-2. notes: 1. refer to the mc68360 quicc user? manual for complete description of the quicc internal memory. 2. the device appears repeatedly in multiples of its size. for example, the status register appears at memory locations 01230002, 01230006, 012300a etc... 3. the dram simm installed in the m68360quads-040 is mcm36256 256kx36 bit. the user may replace the dram module with a higher density simm and increase the dram space up to 8 mbytes. a. for 68lc040 only, reserved otherwise b. for 68lc040 only, reserved otherwise a. not populated - optional. b. connected to d0 - d15 100 00 mmu table search b code all 101 0x supervisor data all 110 00 supervisor program all 111 00 supervisor cpu quiccs mbar register 111 11 supervisor cpu quicc during interrupt acknowledge cycle. table 3-2 m68360quads-040 main memory map addess range accessed device data size notes 00000000 - 001fffff flash prom 32 2 00200000 - 003bffff empty space 003c0000 - 003cffff bursting sram - bank 1 a 32 + parity 003e0000 - 003effff bursting sram - bank 2 32 + parity 00400000 - 004fffff 00400000 - 005fffff 00400000 - 007fffff 00400000 - 00bfffff dram simm mcm36256 dram simm mcm36512 dram simm mcm36100 dram simm mcm36200 32 + parity 3 01210000 - 01211fff slave quicc internal memory 32 1 01230000 - 01231fff m68360quads-040 status register 16 b 2 table 3-1. ec040 cycle types and responding devices tm(2:0) tt(1:0) address space responding devices f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 21 3.4 programming the slave quicc the slave quicc (core disabled) provides the following functions on the m68360quads-040: 1. dram controller 2. chip select and dsack~ generator. 3. parallel port (adi). 4. uart for terminal or host computer connection. 5. dual ethernet controller. 6. interrupter 7. serial eeprom interface. 8. general purpose i/o signals. the slave quicc internal registers must be programmed after hardware reset as described in the following paragraphs. the addresses and programming values are in hexadecimal base. please refer to the mc68360 quicc user? manual for more information. 3.4.1 module base address register the slave quicc? module base address register (mbar) controls the location of its internal memory and registers and their access space. the slave quicc mbar resides at a fixed location in ?003ff00?in the cpu space. the mbar must be initialized to ?0122001?to obtain the memory map as described in table 3-2 3.4.2 module configuration register the module configuration register (mcr) controls the sim60 configuration in the slave quicc. the mcr is initialized to 60018c3f after reset. 3.4.3 clko control register the clko control register (clkocr) controls the operation of the clko(1:2) pins. this register must be initialized to ?3?after reset to enable clko2 and disable clko1. 3.4.4 pll control register the pll control register (pllcr) controls the operation of the pll. there is no need to program the pllcr after hard reset, because the configuration of the modck(0:1) pins on the quads determines its value. it is recommended to set the pllwr bit to prevent accidental writing. 3.4.5 port e pin assignment register port e pins can be programmed by the port e pin assignment register (pepar). the pepar must be initialized to ?7c0? to configure port e of the slave quicc as follows: the output of the slave quicc interrupt request is on iout(0:2)~ pins. ras1~ and ras2~ double drive function is used to drive the dram. the a(31:28) pins of the slave quicc are configured as write enables. the oe~/amux pin is configured as amux to drive the external multiplexers of the dram. the cas(0:3)~ output function is used for the dram. cs7~ output function is enabled. aveco~ function is chosen. 3.4.6 system protection control the system protection register (sypcr) controls the system monitors, the software watchdog, and the bus monitor timing. this register must be initialized to ?4?to disable the software watchdog, disable the double f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 22 bus fault monitor and to enable the bus monitor function to respond after 1 k clock cycles in the slave quicc. 3.4.7 global memory register the global memory register (gmr) contains selections for the memory controller of the slave quicc. the gmr must be initialized according to the size and the access time of the dram simm installed on the m68360quads as follows: for 60, 70, 80 & 100 nsec dram type mcm36256 or mcm36100, the gmr must be initialized to ?8a40000? for 60, 70, 80 & 100 nsec dram type mcm36512 or mcm36200, the gmr must be initialized to ?ca40000? the gmr defines the following parameters: the dram refresh period is 15.36 m sec. the dram refresh cycle length 4 clocks long. the dram module port size is 32 bits. no extra wait between 040 dram accesses (4 phase precharge time) no extra wait between quicc dram accesses (4 phase precharge time) same length quicc dram reads / writes same length 040 sram reads / writes parity is disabled. the cs~/ras~ lines of the slave quicc will not assert when accessing the cpu space. internal address multiplexing for the dram is disabled. 3.4.8 base register 0 and option register 0 base register 0 (br0) and option register 0 (or0) control the operation of cs0~ pin of the slave quicc, which serves as the flash prom chip-select. br0 is initialized to 00000001 to determine the following: base address - 0. no burst support for ec040 access parity disabled 3.4.9 base register 1 and option register 1 base register 1 (br1) and option register 1 (or1) control the operation of ras1~ pin of the slave quicc. this pin is connected to the ras signal of the first bank in the dram module. br1 must be initialized to ?0400021? regardless of the type and the access time of the dram to establish the following: base address 400000. burst support for ec040 access parity disabled or1 must be initialized according to the type of the dram simm installed on the m68360quads-040 as follows: f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 23 for mcm36256 or mcm36512 types: for 100 nsec access time - 3ff00001 for 80 nsec or 70 nsec access time - 2ff00001 for 60 nsec access time 1ff00001 for mcm36100 or mcm36200 types: for 100 nsec access time - 3fc00001 for 80 nsec or 70 nsec access time - 2fc00001 for 60 nsec access time 1fc00001 note to ensure proper operation of the dram, its ras signal should be asserted and negated 8 times after power-up. therefore after power-up, each dram bank should be read 8 times to comply with the requirement above. 3.4.10 base register 2 and option register 2 base register 2 (br2) and option register 2 (or2) control the operation of ras2~ pin of the slave quicc. this pin is connected to the second 1 bank of the dram module. br2 must be initialized according to the type of dram simm installed on the m68360quads-040 as follows: for mcm36256 or mcm36100 types, br2 is not initialized leaving ras2 inactive. for mcm36512 type, br2 must be initialized to 500021 for mcm36200 type, br2 must be initialized to 800021 or2 initialization depends also of the dram simm type installed on the m68360quads-040 as to the following: for mcm36256 or mcm36512 types: for 100 nsec access time - 3ff00001 for 80 nsec or 70 nsec access time - 2ff00001 for 60 nsec access time 1ff00001 for mcm36100 or mcm36200 types: for 100 nsec access time - 3fc00021 for 80 nsec or 70 nsec access time - 2fc00001 for 60 nsec access time 1fc00001 3.4.11 base register 3 and option register 3 base register 3 (br3) and option register 3 (or3) control the operation of cs3~ pin of the slave quicc, which controls the first bank of the bursting sram. br3 must be initialized to ?03c0021? and or3 must be initialized to ?ffe0000?to obtain the memory map as described in table 3-2. 3.4.12 base register 4 and option register 4 base register 4 (br4) and option register 4 (or4) control the operation of cs4~ pin of the slave quicc, which controls the second bank of the bursting sram. br4 must be initialized to ?03e0021? and or4 must be initialized to ?ffe0000?to obtain the memory map as described in table 3-2. 1. if available f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 24 3.4.13 base register 5 and option register 5 base register 5 (br5) and option register 5 (or5) control the operation of cs5~ pin of the slave quicc, which is connected to the status register and to the level -7 interrupt logic. when cs5~ is asserted (for read-only) both the status register is read and all existing level - 7 status bits are cleared. br5 must be initialized to ?1230003? and or5 must be initialized to ?ffff800?to obtain the memory map as described in table 3-2. 3.4.14 base register 6 and option register 6 since cs6~ is not being used on the m68360quads-040, br6 and or6 are not initialized by the debugger. cs6~ is available for user? applications via the expansion connector - p11. 3.4.15 base register 7 and option register 7 since cs7~ is not being used on the m68360quads-040, br7 and or7 are not initialized by the debugger. cs7~ is available for user? applications via the expansion connector - p11. 3.4.16 port a open drain register port a of the slave quicc is 16 pins port, and each pin may be configured as general purpose i/o pin or as dedicated peripheral interface pin. the port a open drain register (paodr) configures the drivers of port a pins as open-drain or as active drivers. the paodr must be initialized to ?000?to select the active drivers configuration. 3.4.17 port a data register the port a data register (padat) can be read to check the data at the pin. if a port pin is configured as general purpose output pin, the value in the padat for that pin is driven onto the pin. on the m68360quads-040, port a is used for serial channels as well as for adi parallel port. padat must be initialized to ?f00?before configuring the other port registers. 3.4.18 port a data direction register the port a data direction register (padir) has different functions according to the configuration of the port pins. if a pin is a general purpose i/o pin, the value in the padir for that pin defines the direction of the pin. if a pin is a dedicated peripheral interface pin, the value in the padir for that pin may select one of two dedicated functions of the pin. padir must be initialized to ?000? 3.4.19 port a pin assignment register the port a pin assignment register (papar) configures the function of the port pins. if the value in the papar for a pin is ?? the pin is general purpose i/o, otherwise the pin is a dedicated peripheral interface pin. the papar must be initialized to ?f3f? 3.4.20 port b open drain register port b of the slave quicc is a 18 bit port, and each pin may be configured as general purpose i/o pin or as dedicated peripheral interface pin. the port b open drain register (pbodr) configures the drivers of port b pins as open-drain or as active drivers. the pbodr must be initialized to ?000?to select the active drivers configuration. 3.4.21 port b data register port b data register (pbdat) can be read to check the data at the pin. if a port pin is configured as general purpose output pin, the value in the pbdat for that pin is driven onto the pin. it is recommended to initialize pbdat to ?ffff?before configuring the other port registers. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual operating instructions 25 3.4.22 port b data direction register the port b data direction register (pbdir) has different functions according to the configuration of the port pins. if a pin is general purpose i/o pin, the value in the pbdir for that pin defines the direction of the pin. if a pin is dedicated peripheral interface pin, the value in the pbdir for that pin may select one of two dedicated functions of the pin. the pbdir must be initialized to ?000f? pins 10 to 17 are connected to the adi port data bus, therefore their direction must be changed by software according to the data flow. 3.4.23 port b pin assignment register the port b pin assignment register (pbpar) configures the function of the port pins. if the value in the pbpar for a pin is ?? the pin is general purpose i/o, otherwise the pin is a dedicated peripheral interface pin. the pbpar must be initialized to ?000f? 3.4.24 port c data register port c of the slave quicc is a 12 bit port, and each pin may be configured as general purpose i/o pin or as dedicated peripheral interface pin, with interrupt capability. the port c data register (pcdat) can be read to check the data at the pin. if a port pin is configured as general purpose output pin, the value in the pcdat for that pin is driven onto the pin. it is recommended to initialize pcdat to ?00?before configuring the other port registers. 3.4.25 port c data direction register the port c data direction register (pcdir) has different functions according to the configuration of the port pins. if a pin is general purpose i/o pin, the value in the pcdir for that pin defines the direction of the pin. if a pin is dedicated peripheral interface pin, the value in the pcdir for that pin may select one of three dedicated functions of the pin. the pcdir must be initialized to ?00? 3.4.26 port c pin assignment register the port c pin assignment register (pcpar) configures the function of the port pins, along with pcdir and pcso. the pcpar must be initialized to ?00? 3.4.27 port c special options register the port c special options register (pcso) configures the cdx and ctsx pins. port c can detect changes on the cts and cd lines and assert the corresponding interrupt while the scc simultaneously uses those lines. the pcso must be initialized to ?30? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 26 4 - functional description 4.1 introduction this chapter details the hardware design of the m68360quads-040, and describes each module in order to simplify the design. 4.2 master mc68ec040 the cpu on the m68360quads-040 is a 33 mhz mc68ec040, running at 25 mhz, which uses the slave quicc? ?8ec040 companion mode?as the memory controller, the interrupt controller, bus arbiter and other system functions usually provided by dedicated logic or peripherals. due to this ?ompanion?mode support, the mc68ec040 interfaces gluelessly to the quicc, while some of the quicc pins change their function to match these of the 68ec040. the mc68ec040 is unbuffered from the slave quicc and the other peripherals (except for the externally multiplexed dram address lines). in order to demonstrate the ?lueless?concept under practical test and evaluation. address lines a(28:31) of the slave quicc are used in their alternate function as we(0:3)~ to avoid having to generate them externally. as a result only 256 mbyte of memory may be accessed by both the 68ec040 and the quicc with chip-select support. all the pins of the mc68ec040 device are available unbuffered to the user through the logic analyzer connectors. the user can monitor the 040 activity during its development stage. 4.2.1 reset for the 68ec040 & the quicc there are four basic types of reset, regarding their source and consequence, available on the m68360quads-040 board: 1. quicc generated reset - these types of reset are generated internally by the quicc and include: power-up & software watch-dog. double-bus-fault reset is not supported when the quicc is in ec040 companion mode. 2. soft reset - may be caused by either depressing the soft-reset push-button or when the adi-port? soft-reset signal is asserted by the remote host. when either happens, the 040 is reset while the quicc is soft-reset, i.e., the configuration of the quicc is unchanged, preserving the contents of the dram. 3. hard-reset - may be generated by either depressing soft-reset in conjunction with the abort push-button or when the adi-port? hard-reset signal is asserted by the remote host. when either happens, the 040 is reset and the quicc is hard-reset, i.e., all the quicc? sub-modules are reset, including configuration and clock logic. 4. reset instruction - when the reset instruction is executed by the mc68ec040, resets* line is asserted to the quicc, which in turn, asserts this line to complete 512 clock cycles. execution of reset instruction does not cause the reset of the mc68ec040 itself, therefore not interrupting the software flow. 1 1. it was observed that the ec040 may start the next bus cycle faster than the quicc can recover from the reset; there- fore, it is recommended that the reset instruction is loaded to an even cache-line address and executed from the cache. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 27 4.2.2 utilizing the mc68ec040 data cache in order to achieve best performance out of the mc68ec040, both caches, instruction and data, are used. since the bus interface of the ec040 and the quicc? dma are different, snooping is not supported on the m68360quads-040. therefore, when the data cache is enabled and used, two basic problems arise: 1. when registers or buffer descriptors are changed values by hardware or dma are to be polled, they should not be cached, otherwise they will be polled indefinitely from the data cache, while their value may change outside, unnoticed by application software. 2. transmit or receive buffers should not be cached, since they are being used only once, therefore, not only caching them will not contribute to better performance, but rather will harm it, since it will keep the replacement mechanism busier. to answer the above problems, the following measures were taken on the m68360quads-040: 1. the quicc internal memory map area, including the registers and buffer-descriptors spaces, was moved to the second 16 mbyte block 1 , where it is marked as non-cashable in the dttr1 register of the 68ec040. 2. to allow for memory areas containing transmit or receive buffers to avoid being cached, the hardware breakpoint mechanism may be utilized as a caching shield. the bkpto* signal of the quicc is connected via a jumper - j7, to the tci* signal of the ec040, which when asserted at the beginning of a data-cache line read cycle, avoids the caching of that line in the data-cache. as the bkar and bkcr are programmed to match the address, size, and attributes of the desired memory space 2 to be shielded, bkpto* will be asserted on the relevant access to that space and avoid redundant caching. 4.3 interrupts on the m68360quads-040 in slave mode (including 68ec040 companion) the quicc serves as an interrupt encoder for the master processor. it integrates all internal and external interrupt sources and encodes them to iout(0:2)~ to be connected to standard 68000 ipl~ lines. since the parity lines are used on the m68360quads-040, iout(0:2)~ are used on the expense of irq1~, irq4~ and irq6~ of the slave quicc. there are 5 external 3 interrupt sources on the m68360quads-040: 1. abort push-button - non-maskable, level 7. 2. host nmi via adi port - non-maskable, level 7. 3. hardware-breakpoint - non-maskable, optional, level 7. 4. parity error, generated by the slave quicc? parity logic - maskable, level 5. 5. host request / acknowledge from adi port - maskable, level 2. all the level - 7 interrupt source are registered and two of them are available in the status register, this to allow software to detect the source of the of the interrupt. the interrupts on levels 5 and 2 are most likely to use the autovector mechanism of the quicc. 4.3.1 abort push-button when the abort push button - sw2 is depressed, a non-maskable, level-7 interrupt is generated to the ec040 by the quicc. when the abort push-button is depressed in conjunction with the soft-reset 1. there is no mmu on the mc68ec040, therefore use must be done with one of the two dttrs - data transparent translation registers, of the ec040. these registers can address memory blocks no smaller than 16 mbytes. since the first 16 mbyte block on board, holds memories that are to be data-cached, the quicc was moved to the second block. 2. not bigger than 32k bytes. 3. off quicc. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 28 push-button - sw1, hard - reset is generated to board. indication for the occurrence of that interrupt is concluded from the absence of both host nmi and hardware-breakpoint indications in the status register. 4.3.2 host - nmi when a host is connected to the m68360quads-040 via the adi port, it is possible for the host to generate a level - 7 interrupt via the adi port, allowing for full 1 remote control over the board. to generate that interrupt, the host computer needs to assert and deassert the ads_brk signal of the adi port. that interrupt is indicated via the h_nmi~ bit in the status register. 4.3.3 hardware-breakpoint interrupt 2 to support hardware-breakpoint, the bkpto~ signal of the quicc may be connected via jumper - j7 (1- 2) to the level - 7 interrupt generation logic. when a hardware breakpoint is reached and j7 pins 2-3 are connected, a level - 7 interrupt is generated,and the indication is shown by the bkint~ bit in the status register. 4.3.4 parity 3 error interrupt it is possible to generate a level - 5, maskable interrupt to the ec040 in case a parity error occurs during dram or bursting sram read. the quicc? perr~ (parity error) signal is connected to irq5~ signal of the quicc. 4.3.5 host request / acknowledge interrupt 4 to support interrup based handshaking with the host computer via the adi port, it is possible for the assertion (by the host computer) of either host_req or host_ack signals, when the board is selected, to generate a level 2, maskable interrupt to the ec040. 4.4 bus arbitration when a quicc is configured in 68ec040 companion mode, its arbiter lines do not change function and the quicc remainsbus arbiter (rather than a requester as in other slave modes). the 68ec040 arbitration lines are connected gluelessly to those of the quicc. the lock~ signal of the 68ec040 is connected also to support indivisible bus cycles. when the quicc doesn? need the bus, it asserts bg~ constantly for the 040 to reduce arbitration overhead time for the 040, and therefore improving its performance. to support external master connection via the expansion connectors, the br* bg* pairs are connected to each other via jumpers and appear also at the expansion connector, thus enabling an external arbiter to be located off-board. the arbitration logic scheme is demonstrated in figure 4-1 on page 29. 1. in conjunction with remote soft & hard resets capability. 2. it is important to remember that the hardware-breakpoint and the memory caching shield operation is mutualy exclusive, that is, when the data-caching shield is operating (j7 2-3) the hardware - breakpoint use is not available and vice-versa. 3. parity in not enabled during normal operation. it is up to the users to enable the parity logic to their desire. 4. during normal operation these interrupts are masked and a polling handshake takes place between the board and the host computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 29 figure 4-1 arbitration scheme: since the level of priority associated with the br~ input is lower (8) than the sdma?, no use is done with the bclro~ signal of the quicc is not used. in sake of simplicity, no use is done with the ipend~ is not used as a bcli~ for the quicc. 4.5 system utilities the slave quicc provides the m68360quads-040 with the following system utilities, usually provided by external logic: 1. breakpoint generation 2. bus monitor (also known as hardware watch-dog) 3. spurious interrupt monitor 4. software watch-dog 5. periodic interval timer (also known as real-time-clock or tic-timer) 4.5.1 breakpoints generator the quicc may be used as a hardware breakpoint generator for the 68ec040. when the 68ec040 initiates a bus cycle by asserting ts~, the breakpoint logic compares the cycle? address to the address in the bkar and to the access attributes in the bkcr. if there is a match, the bkpto* signal is asserted by the quicc. since ts~ is asserted only at the beginning of the cycle, no address comparison is done for the rest of the access (burst access). the bkpto* of the slave quicc is wired via a jumper to generate a non-maskable interrupt on level 7. if the ec040 performs a breakpoint instruction, the quicc will not respond, letting the bus monitor terminate the cycle with tea~. 4.5.2 bus monitor the quicc monitors for unterminated bus cycles, performed either by the 68ec040 or by the quicc? internal masters. if a bus cycle fails to terminate with ta~ or tea~ (dsack~ or berr) during a programmable period of time, the bus monitor terminates the cycle, by asserting tea~ for the ec040 (or berr~ for an internal master). upon reset, the bus monitor is initialized to expire after 1k system clocks (clko1 clocks). quicc ec040 br bg br bg expansion connector j10 j9 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 30 4.5.3 spurious interrupt monitor in ec040 mode, the quicc monitors for spurious interrupt cycles performed by the ec040. this support is limited to those levels supported internally by the quicc interrupter, i.e., only on those levels used by the cpm and the sim60. if such a condition occurs, the quicc terminates the cycle with tea~. 4.5.4 software watch-dog the software watch-dog on the m68360quads-040 may be programmed to generate a system reset when an application software is stuck in an endless loop. the software watch dog is disabled after reset and it may be enabled if the users want it enabled. 4.5.5 periodic interval timer - pit if desired, the quicc? pit may be used to generate periodic interrupt in favor of real-time kernel. the pit is disabled after reset. 4.6 clock generator there are two main clocks available on the m68360quads-040: 1. 25mhz system clock, which supplies bclk for the ec040 and extal clock input for the quicc. this clock is supplied via four buffers to the different board area. 2. 50mhz clock, which supplies the pclk for the ec040 and is generated using the quicc? pll via clko2. during reset, clko2 reflects the state of the extal input and becomes 2 x extal after the quicc? pll is locked. the 25mhz clock is generated by an external crystal oscillator (u37) which is divided by 2 to yield a 50% duty cycle (u39) which is buffered (u38) and distributed to all board consumers. 4.7 flash prom the flash prom on the m68360quads-040 is constructed of four am29f010-12 devices providing a total of 512 kbytes. the am29f010 is a 5 v programmable, with 8 - sectors?protection capability, 120 nsec access time, 128 kbyte device, accessed with 3 wait-states @ 25 mhz system clock. an option is made to use bigger flash proms up to the am29f040. the flash prom is used to store the resident debugger and other necessary drivers, which reside in 4 protected sectors. the rest of the sectors are available for on-board user programming. the flash prom is selected using the global cs (cs0) of the slave quicc. to program the flash prom, the program (and / or data) should be downloaded to the dram (or bsram) and then programmed into the flash prom by a dedicated debugger command. if a dedicated programming routine is to be used it is important to remember that the flash prom can not be accessed normally during the programming process. therefore, the programming routine should reside in another memory. 4.8 bursting sram the bursting sram on the m68360quads-040 is constructed of two 1 banks, each containing 4 mcm62940afn12 32k x 9sram chips. this ram provides fast access times for the ec040: 3,1,1,1 clock cycles for burst access and 3 clock cycles for normal access. if desired, the volume of the bsram may be doubled, this, by soldering identical memory components to the empty locations designated by u27, u28, u29 & u30. 1. one populated and the other optional f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 31 warnning additional bsram components should be soldered with care. otherwise permanent damage may be inflicted to the m68360quads-040. the bursting sram may be accessed by both the ec040 and the dma, however access by the quicc must be even word aligned. 4.9 eeprom the eeprom used in the m68360quads-040 is motorola mcm2814, 256 byte serial eeprom (u14). the slave quicc provides 4 signals to control accesses to the eeprom. the mcm2814 has internal hardware protection against inadvertent writes to the eeprom that might happen at power up or power down time. 4.10 dram the m68360quads-040 is supplied with 1 mbyte of dynamic ram, which is implemented by the mcm36256s-60 dram module. the module is a 72 lead simm, 60 nsec access time, organized as 256k x 36 bit for data and parity signals, and is accessed with 3,2,2,2 clock cycles during burst cycles and 3 clocks during normal read / write access. it is possible to replace the supplied dram simm with a higher density module in order to increase the dram memory space up to 8 mbyte. the higher density modules may require using ras1 and ras2 signals of the slave quicc if they are organized as two memory banks. after hard / power-up reset, the status register is read to detect the kind of dram simm inserted, in order to initialize the cs registers with the correct data regarding the dram? size and delay. the dram is controlled by the slave quicc device, using its dram controller function for normal accesses, burst mode accesses, and refresh accesses. the dram can be accessed by the master 68ec040 and the slave quicc? dma channels. note: due to problems of implementation, the quicc? support for 68ec040? burst mode inhibits the support for internal page mode. therefore, the i/sdmas access the dram using normal access pattern only. 4.11 slave quicc during normal operation, the cpu of the slave quicc is disabled, and the device is used to implement the following functions on the ads: 1. dram controller 2. chip select ta~ and dsack~ generator. 3. parallel port (adi) controller. 4. uart for terminal or host computer connection. 5. ethernet controller. the address of the mbar register is configured to $0033ff00. the quicc? peripherals (such as the idma and sdma) can request the bus and become bus master, even though the cpu is disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 32 4.11.1 dram controller the slave quicc device provides the necessary control signals for the dram module. the debugger on the m68360quads-040 reads the presence detect pins (simm1 - simm4) of the simm found in the status register and sets the dram controller parameters according to the dram module? size and access time. the available combinations of the presence detect pins are described in table 4-1. the hardware connection of the slave quicc to the dram module is straight-forward. since the slave quicc doesn? support address multiplexing for external masters, external address multiplexers are used to drive the dram address lines. 4.11.2 chip select ta~ and dsack~ generator the slave quicc device provides the chip select signals for the dram, eprom, bursting eprom, and bursting sram on the ads. it also generates the ta~ signal for the 68ec040 during master accesses and dsack~ signals for the quicc during internal accesses, this, according to the access time of the devices and the working frequency of the board. no external logic is required for the connection of the slave quicc to the devices. 4.11.3 adi port the adi parallel port supplies the parallel link from the m68360quads-040 to various host computers. this port is connected via a 37 line cable to a special board called adi (application development interface) installed in the host computer. two versions of the adi board are available to support connection to ibm- pc/xt/at and sun-4 sparc stations. it is possible to connect the m68360quads-040 board to these computers provided that the appropriate software drivers are installed on them. each m68360quads-040 can have 8 possible slave addresses set for its adi port, enabling up to 8 m68360quads-040 boards to be connected to the same adi board. table 4-1. dram simm types simm(4:1) simm type simm organization access time (nsec) control signals 0000 mcm36100s10 1m x 36 100 ras1 0001 mcm36512s10 512k x 36 100 ras1, ras2 0010 mcm36256s10 256k x 36 100 ras1 0011 mcm36200s10 2m x 36 100 ras1, ras2 0100 mcm36100s80 1m x 36 80 ras1 0101 mcm36512s80 512k x 36 80 ras1, ras2 0110 mcm36256s80 256k x 36 80 ras1 0111 mcm36200s80 2m x 36 80 ras1, ras2 1000 mcm36100s70 1m x 36 70 ras1 1001 mcm36512s70 512k x 36 70 ras1, ras2 1010 mcm36256s70 256k x 36 70 ras1 1011 mcm36200s70 2m x 36 70 ras1, ras2 1100 mcm36b100asg60 1m x 36 60 ras1 1101 mcm36b512asg60 512k x 36 60 ras1, ras2 1110 mcm36b256asg60 256k x 36 60 ras1 1111 mcm36b200asg60 2m x 36 60 ras1, ras2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 33 the adi port connector is a 37 pin, male, d type connector. the connection between the m68360quads- 040 and the host computer is by a 37 line flat cable, supplied with the adi board. figure 4-2 below shows the pin configuration of the connector. figure 4-2 adi port connector note: pin 26 on the adi is connected to +12 v power supply, but it is not used in the m68360quads-040. 4.11.3.1 adi port signal description the adi port on the quads-040 was slightly modified to generate either hard reset or soft reset. this feature was added to comply with the quicc? reset mechanism. the host software written for the quads-040 should be able to work properly with existing ads boards, such as the m68302ads. in the list below, the directions ?? ?? and ?/o?are relative to the m68360quads-040 board. (i.e. ??means input to the m68360quads-040) note: since the adi was originated for the dsp56001ads, some of its signals throughout the boards it was used with, were designated with the prefix ?ds? this convention is kept with this design also. gnd 20 int_ack 1 2 gnd 21 gnd 22 gnd 23 gnd 24 gnd 25 (+ 12 v) n.c. 26 hst_ack 3 ads_all 4 host_vcc ads_reset ads_sel2 ads_sel1 ads_sel0 5 6 7 8 27 host_vcc host_vcc gnd gnd host_enable~ host_req ads_req ads_ack ads_int host_brk~ ads_brk 9 10 11 12 13 14 28 29 30 31 32 gnd 33 pd0 34 pd2 pd4 pd6 n.c. pd1 pd3 pd5 pd7 15 16 17 18 19 35 36 37 n.c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 34 ads_sel(0:2) - ?? these three input lines determine the slave address of the m68360quads-040 being accessed by the host computer. up to 8 boards can be addressed by one adi board. ads_all - ? this input line is used to reset or abort program execution on all m68360quads-040 development boards that are connected to the same adi board. host_enable~ - ? this line is always driven low by the adi board. the m68360quads-040 software uses this line to determine if a host is connected to the adi port. ads_brk - ? when a host is connected, this line is used in conjunction with the addressing lines or with the ads_all line to generate a non-maskable interrupt (interrupt level 7) to the quicc. ads_reset - ? when a host is connected, this line is used in conjunction with the addressing lines or with the ads_all line to generate a reset (hard or soft) to the m68360quads-040 board. host_req -? this signal initiates a host to m68360quads-040 write cycle. ads_ack - ? this signal is the m68360quads-040 response to the host_req signal, indicating that the board has detected the assertion of host_req. ads_req - ? this signal initiates an m68360quads-040 to host write cycle. hst_ack - ? this signal serves as the host? response to the ads_req signal. host_brk~ - ? this open-collector signal generates an interrupt to the host. this signal is common to all m68360quads-040 boards that are connected to the same adi. ads_int - ? this line is polled by the host computer during its interrupt acknowledge cycle to determine which m68360quads-040 board has generated the interrupt. int_ack - ? this line is asserted by the host at the end of its interrupt acknowledge cycle. this signal is used by the m68360quads-040 hardware to negate the host_brk~ signal. the software in the m68360quads-040 must negate the ads_int signal upon detecting the assertion of int_ack to support the daisy-chain interrupt structure. in addition, this signal selects between the type of reset applied to the selected board(s). when ??is driven, soft reset is applied and when ??- hard reset is applied. host_vcc - ?? (three lines) these lines are power lines from the host computer. in the m68360quads-040, these lines are used by the software to determine if the host computer is powered on. pd(0:7) - ?/o? these eight i/o lines are the parallel data bus. this bus is used to transmit and receive data from the host computer. 4.11.4 rs-232 serial port the serial port is provided by one of the slave quicc serial channels. the m68360quads-040 can be connected to a vt100 compatible terminal or to a host computer through the serial port. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 35 the rs-232 serial port connector is a 9 pin, male, d-type connector as shown in figure 2-6. figure 4-3 rs-232 serial port connector 4.11.4.1 rs-232 port signal description in the list below, the directions ?? ?? and ?/o?are relative to the m68360quads-040 board. (i.e. ??means input to the m68360quads-040) cd ( o ) - data carrier detect. this line is always asserted by the ads. tx ( o ) - transmit data. rx ( i ) - receive data. dtr ( i ) - data terminal ready. this signal is used by the software in the ads to detect if a terminal is connected to the ads board. dsr ( o ) - data set ready. this line is always asserted by the ads. rts ( i ) - request to send. this line is not connected in the ads. cts ( o ) - clear to send. this line is always asserted by the ads. 4.11.5 m68360quads-040 status register the status register is a 16 bit wide read only register used to hold board status, level 7 interrupt source identification and an input register for adi interface signals. figure 4-4 status register 4.11.5.1 status register bits description dtr* - when active ?? indicates that a terminal is connected to the serial port. h_nmi* - when active ?? indicates that the last level 7 interrupt (nmi) was generated from the host via the adi port. inack - when active ?? indicates that a host interrupt acknowledge cycle is in progress. adssel - when active ?? indicates that the board is selected by the adi port. hsreq* - when active ?? indicates that the host request to write a data byte to the board via the adi port. hsack* - when active ?? indicates that the host has successfully read a byte of data written to it by the board via the adi port. hsten - when active ?? indicates that the board is connected to an adi port. hsvcc* - when active ?? indicates that the host computer is alive (not turned off). 1 rx 2 tx 3 rts 4 cts 5 dsr 6 gnd 7 dcd 8 9 n.c. dtr 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 dtr* h_nmi* inack* adssel hsreq* hsack* hsten hsvcc* simm4 simm3 simm2 simm1 bkint* opt0* opt1* opt2* f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 36 simm4 to simm1 - these four bits, encode the data identifying the dram simm connected to the m68360quads-040. for the various dram types supported, refer to table 4-1. bkint* - when active ?? indicates that the last level 7 interrupt (nmi) was generated by the hardware breakpoint logic. opt0* - when active ?? indicates that switch #5 in dsw1 is in on position opt1* - when active ?? indicates that switch #4 in dsw1 is in on position opt2* - when active ?? indicates that switch #3 in dsw1 is in on position 4.11.6 ethernet controller there are two ethernet ports on the m68360quads-040 implemented via scc1 and scc2 of the quicc. the first ethernet port is implemented by connecting scc1 to motorola? mc68160 eest device. the mc68160 provides two ethernet interfaces: aui (p3) and twisted-pair (p4). the connection between the mc68160 and the quicc is straight forward, and does not require external glue logic. the second ethernet port is implemented by connecting scc2 to amd? sia (am7992) device. in this case however, only aui port is implemented via p5. to support other uses of scc2, it? signals are available also at the expansion connectors and the sia (u4) is mounted on a socket. that way the sia can be removed freeing scc2 signals for other use via the expansion connector - p11. 4.11.6.1 ethernet aui ports signal description the aui port connectors p3 and p5 are 15 pin, female, d-type connectors as shown in figure 2-6. figure 4-5 ethernet aui port connector the list below describes the port signals. the directions ?? ?? and ?/o?are relative to the m68360quads- 040 board. (i.e. ??means input to the m68360quads-040) acx+ ( i ) - collision input (positive). atx+ ( o ) - transmit data (positive). arx+ ( i ) - receive data (positive). acx- ( i ) - collision input (negative). atx- ( o ) - transmit data (negative). arx- ( i ) - receive data (negative). 1 atx+ 2 arx+ 3 4 5 6 gnd 7 8 9 n.c. 10 11 12 13 14 15 gnd gnd gnd gnd gnd atx- acx+ acx- +12v arx- n.c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 37 +12v ( o ) - +12v power supply from the m68360quads-040. 4.11.6.2 ethernet twisted-pair port signal description the twisted-pair port connector p4 is a 8 pin, rj-45 connector as shown in figure 2-6. figure 4-6 ethernet twisted-pair port connector the list below describes the port signals. the directions ?? ?? and ?/o?are relative to the m68360quads- 040 board. (i.e. ??means input to the m68360quads-040) tptx+ ( o ) - transmit data (positive). tptx- ( o ) - transmit data (negative). tprx+ ( i ) - receive data (positive). tprx- ( i ) - receive data (negative). 4.11.7 serial eeprom the mcm2814 serial eeprom (u14) is a 256 bytes eeprom with spi interface. it is controlled by the spi port of the slave quicc (pins 1,2 and 3 of port b), and by a general purpose output pin (pin 0 of port b). the spi port operates in master mode. the serial eeprom serves as non-volatile memory on the m68360quads-040 and may be used to store software parameters to be protected from power-downs. 4.11.8 slave quicc general purpose i/o pins the slave quicc has three ports, a, b, and c, whose pins can be individually configured by software to be general purpose i/o pin or dedicated peripheral function. the quicc also has another port, e, whose pins are not general purpose i/o, but they can be configured to operate in one of two possible modes. the following subsections describe the slave quicc ports. refer to 3.4 on page 21 for the required programming information. 4.11.8.1 slave quicc port a 1 2 3 4 5 6 7 8 tptx+ tprx+ n.c. tptx- tprx- n.c. n.c. n.c. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 38 port a is 16 pins port. table 4-2 describes the configuration of port a. 4.11.8.2 slave quicc port b table 4-2 port a pins description pin pin name description 0 eest rx this pin is connected to the receive data output of the eest. it is con?ured as the receive data of scc1 in the slave quicc. 1 eest tx this pin is connected to the transmit data input of the eest. it is con?ured as the transmit data of scc1 in the slave quicc. 2 sia rx this pin is connected to the receive data output of the sia. it is con?ured as the receive data of scc2 in the slave quicc. 3 sia tx this pin is connected to the transmit data input of the sia. it is con?ured as the transmit data of scc2 in the slave quicc. 4 rs-232 rx this pin is connected to the receive data output of the rs-232 transceiver u23. it is con?ured as the receive data of scc3 in the slave quicc. 5 rs-232 tx this pin is connected to the transmit data input of the rs-232 transceiver u23. it is con?ured as the transmit data of scc3 in the slave quicc. 6 pa6 this pin is connected to the expansion connector (p11) and may be utilized for users applications. 7 pa7 this pin is connected to the expansion connector (p11) and may be utilized for users applications. 8 eest tclk this pin is connected to the transmit clock output of the eest. it is con?ured as the transmit clock of scc1 in the slave quicc. 9 eest rclk this pin is connected to the receive clock output of the eest. it is con?ured as the receive clock of scc1 in the slave quicc. 10 sia tclk this pin is connected to the transmit clock output of the sia. it is con?ured as the transmit clock of scc2 in the slave quicc. 11 sia rclk this pin is connected to the receive clock output of the sia. it is con?ured as the receive clock of scc2 in the slave quicc. 12 ads ack~ this pin is connected to the adi port signal ads_ack through the buffer u1. it is con?ured as output pin in the slave quicc. 13 ads req~ this pin is connected to the adi port signal ads_req through the buffer u1. it is con?ured as output pin in the slave quicc. 14 ads g~ this pin is connected to the adi port logic. it is con?ured as output pin in the slave quicc, and it is used by the adi logic to control the adi data transceiver. 15 ads int~ this pin is connected to the adi port signal ads_int through the buffer u1. it is con?ured as output pin in the slave quicc, and it is also used by the adi logic to interrupt the host computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 39 port b is 18 pins port. table 4-2 describes the configuration of port b. 4.11.8.3 slave quicc port c table 4-3 port b pins description pin pin name description 0 eeprom select this pin is connected to the select input of the eeprom, and it is con?ured as output pin in the slave quicc. 1 eeprom clk this pin is connected to the clock input of the eeprom, and it is con?ured as the spi clock of the slave quicc. 2 eeprom serial in this pin is connected to the serial data input of the eeprom, and it is con?ured as the spi mosi of the slave quicc. 3 eeprom serial out this pin is connected to the serial data output of the eeprom, and it is con?ured as the spi miso of the slave quicc. 4 - 9 pb4 - pb9 these pins are connected to the expansion connector p11 and may be used by users applications. 10 adi data 0 this pin is connected to the adi port signal pd0 through the data bus transceiver u13, and it is con?ured as i/o pin. 11 adi data 1 this pin is connected to the adi port signal pd1 through the data bus transceiver u13, and it is con?ured as i/o pin. 12 adi data 2 this pin is connected to the adi port signal pd2 through the data bus transceiver u13, and it is con?ured as i/o pin. 13 adi data 3 this pin is connected to the adi port signal pd3 through the data bus transceiver u13, and it is con?ured as i/o pin. 14 adi data 4 this pin is connected to the adi port signal pd4 through the data bus transceiver u13, and it is con?ured as i/o pin. 15 adi data 5 this pin is connected to the adi port signal pd5 through the data bus transceiver u13, and it is con?ured as i/o pin. 16 adi data 6 this pin is connected to the adi port signal pd6 through the data bus transceiver u13, and it is con?ured as i/o pin. 17 adi data 7 this pin is connected to the adi port signal pd7 through the data bus transceiver u13, and it is con?ured as i/o pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual functional description 40 port c is 12 pins port. table 4-2 describes the configuration of port c. 4.11.8.4 slave quicc port e port e pins can be configured to operate in one of two dedicated peripheral functions. the pepar register configures the operation mode, as described in section 3.4.5 on page 21. table 4-4 port c pins description pin pin name description 0 eest tena this pin is connected to the tena input of the eest. it is con?ured as the rts signal of scc1 in the slave quicc. 1 sia tena this pin is connected to the tena input of the sia. it is con?ured as the rts signal of scc2 in the slave quicc. 2 - 3 pc2 - pc3 these pins are connected to the expansion connector p11 and may be used by users applications. 4 eest clsn this pin is connected to the clsn output of the eest. it is con?ured as the cts signal of scc1 in the slave quicc. 5 eest rena this pin is connected to the rena output of the eest. it is con?ured as the cd signal of scc1 in the slave quicc. 6 sia clsn this pin is connected to the clsn output of the eest. it is con?ured as the cts signal of scc2 in the slave quicc. 7 sia rena this pin is connected to the rena output of the eest. it is con?ured as the cd signal of scc2 in the slave quicc. 8 - 11 pc8 - pc11 these pins are connected to the expansion connector p11 and may be used by users applications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 41 5 - support information 5.1 introduction this chapter provides the interconnection signals, parts list, and schematic diagrams of the m68360quads-040 board. 5.2 interconnect signals the m68360quads-040 board interconnects with external devices through the following connectors: p1 is 37 pin, male d type connector, for the adi port. p2 is 9 pin, female d type connector, for the rs-232 port. p3 is 15 pin, female d type connector, for aui connection to the eest ethernet port. p4 is 8 pin, rj-45 connector, for twisted-pair connection to the eest ethernet port. p5 is 15 pin, female d type connector, for aui connection to the (amd?) sia ethernet port. p6 is 3 pin connector for 5v power supply input: gnd (x2) and +5v p7 is 2 pin connector for 12v power supply input: gnd and +12v p8 and p9 are 96 pin din connectors for logic analyzer connection. p10 1 & p11 2 are 96 pin din connectors for off-board hardware expansions. 5.2.1 connector p1 interconnect signals connector p4 is a 37 pin, male d-type connector. it is the adi port of the m68360quads-040. table 5- 1 describes the p1 connector signals. 1. connector p10 has identical pinout to p8 2. connector p11 has identical pinout to p9 table 5-1 connector p1 interconnect signals pin no. signal name description 1 int_ack interrupt acknowledge input signal from the host 2 - not connected 3 hst_ack host acknowledge input signal from the host 4 ads_all quads-040 all input signal from the host 5 ads_reset quads-040 reset input signal from the host 6 ads_sel2 quads-040 select 2 input signal from the host 7 ads_sel1 quads-040 select 1 input signal from the host 8 ads_sel0 quads-040 select 0 input signal from the host 9 host_req host request input signal from the host 10 ads_req quads-040 request output signal from the m68360quads-040 to the host 11 ads_ack quads-040 acknowledge output signal from the m68360quads-040 to the host 12 ads_int quads-040 interrupt output signal from the m68360quads-040 to the host 13 host_brk~ host break open collector output signal from the m68360quads-040 to the host 14 ads_brk quads-040 break input signal from the host f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 42 5.2.2 connector p2 interconnect signals connector p2 is a 9 pin, female d type connector. it is the rs-232 serial port of the m68360quads-040. table 5-1 describes the p5 connector signals. 5.2.3 connector p3 interconnect signals connector p3 is 15 pin, female d type connector. it is the eest aui ethernet port of the m68360quads- 040 board. table 5-1 describes the p3 connector signals. 15 - not connected 16 pd1 bit 1 of the adi port data bus 17 pd3 bit 3 of the adi port data bus 18 pd5 bit 5 of the adi port data bus 19 pd7 bit 7 of the adi port data bus 20 - 25 gnd ground signal of the m68360quads-040 26 - not connected. the host supplies +12v on this pin, but it is not connected on the m68360quads-040 27 - 29 host_vcc host vcc input from the host. the m68360quads-040 does not use these inputs for power supply. 30 host_enable~ host enable input signal from the host. 31 - 33 gnd ground signal of the m68360quads-040 34 pd0 bit 0 of the adi port data bus 35 pd2 bit 2 of the adi port data bus 36 pd4 bit 4 of the adi port data bus 37 pd6 bit 6 of the adi port data bus table 5-2 connector p2 interconnect signals pin no. signal name description 1 cd carrier detect output from the m68360quads-040. 2 tx transmit data output from the m68360quads-040. 3 rx receive data input to the m68360quads-040. 4 dtr data terminal ready input to the m68360quads-040. 5 gnd ground signal of the m68360quads-040. 6 dsr data set ready output from the m68360quads-040. 7 rts (n.c.) request to send. this line is not connected in the m68360quads-040. 8 cts clear to send output from the m68360quads-040. 9 - not connected table 5-3 connector p3 interconnect signals pin no. signal name description 1 gnd ground signal of the m68360quads-040. table 5-1 connector p1 interconnect signals pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 43 5.2.4 connector p4 interconnect signals connector p4 is 8 pin, rj-45 connector. it is the twisted-pair ethernet port of the m68360quads-040 board. table 5-1 describes the p8 connector signals. 5.2.5 connector p5 interconnect signals connector p5 is 15 pin, female d type connector. it is the sia aui ethernet port of the m68360quads- 040 board. table 5-1 describes the p3 connector signals. 2 acx+ collision detect positive input to the m68360quads-040. 3 atx+ transmit data positive output from the m68360quads-040. 4 gnd ground signal of the m68360quads-040. 5 arx+ receive data positive input to the m68360quads-040. 6 gnd ground signal of the m68360quads-040. 7 - not connected 8 gnd ground signal of the m68360quads-040. 9 acx- collision detect negative input to the m68360quads-040. 10 atx- transmit data negative output from the m68360quads-040. 11 gnd ground signal of the m68360quads-040. 12 arx- receive data negative input to the m68360quads-040. 13 vpp +12v power supply from the m68360quads-040. 14 gnd ground signal of the m68360quads-040. 15 - not connected table 5-4 connector p8 interconnect signals pin no. signal name description 1 tptx+ twisted-pair transmit data positive output from the m68360quads-040. 2 tptx- twisted-pair transmit data negative output from the m68360quads-040. 3 tprx+ twisted-pair receive data positive input to the m68360quads-040. 4 - not connected 5 - not connected 6 tprx- twisted-pair receive data negative input to the m68360quads-040. 7 - not connected 8 - not connected table 5-5 connector p5 interconnect signals pin no. signal name description 1 gnd ground signal of the m68360quads-040. 2 acx+ collision detect positive input to the m68360quads-040. 3 atx+ transmit data positive output from the m68360quads-040. 4 gnd ground signal of the m68360quads-040. table 5-3 connector p3 interconnect signals pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 44 5.2.6 connector p6 interconnect signals connector p6 is 3 pin connector for 5v power supply. the connector is supplied with 3 pin plug for convenient connection to the power supply. table 5-1 describes the p6 connector signals. 5.2.7 connector p7 interconnect signals connector p7 is a 2 pin connector for 12v power supply. the connector is supplied with 2 pin plug for convenient connection to the power supply. table 5-1 describes the p7 connector signals. 5.2.8 connector p8 interconnect signals connector p8 is a triple-row, 96 pin, male din connector. p8 and p9 logic-analyzer connectors provide most of the signals of the slave quicc and the mc68ec040?. table 5-1 describes the p8 connector signals. 5 arx+ receive data positive input to the m68360quads-040. 6 gnd ground signal of the m68360quads-040. 7 - not connected 8 gnd ground signal of the m68360quads-040. 9 acx- collision detect negative input to the m68360quads-040. 10 atx- transmit data negative output from the m68360quads-040. 11 gnd ground signal of the m68360quads-040. 12 arx- receive data negative input to the m68360quads-040. 13 vpp +12v power supply from the m68360quads-040. 14 gnd ground signal of the m68360quads-040. 15 - not connected table 5-6 connector p6 interconnect signals pin no. signal name description 1 vcc +5v connection to the power supply. 2 gnd ground connection to the power supply. 3 gnd ground connection to the power supply. table 5-7 connector p7 interconnect signals pin no. signal name description 1 vpp +12v connection to the power supply. 2 gnd ground connection to the power supply. table 5-8 connector p8 interconnect signals pin no. signal name description a1 - a32 a0 - a31 address lines 0 to 31 of the ec040 and slave quicc a b1 - b32 d0 - d31 data lines 0 to 31 of the ec040 and slave quicc c1 - c3 tm0 - tm2 transfer modi?r lines 0 to 2 of the ec040 table 5-5 connector p5 interconnect signals pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 45 5.2.9 connector p9 interconnect signals connector p9 is a triple-row, 96 pin, male din connector. p8 and p9 logic-analyzer connectors provide most of the signals of the slave quicc and the mc68ec040?. table 5-1 describes the p9 connector signals. a. quicc? a28 - a31 are used as write enables, therefore not connected to ec040? corresponding signals c4 tt0 transfer type signal 0 pin of the ec040 c5 gnd m68360quads-040 board ground. c6 - c7 siz0 - siz1 ec040s access size indicators 0 to 1 c8 brq~ quiccs bus request c9 bgq~ quiccs bus grant c10 bb~ bus busy c11 as~ quiccs address strobe c12 gnd board ground c13 tt1 ec040s transfer type 1 c14 r/w~ read / write c15 gnd board ground c16 lock~ ec040 locked (rmw) cycle indicator c17 dd2~ quiccs ras double drive 2 c18 tbi~ ec040s transfer burst inhibit c19 ta~ ec040s transfer acknowledge c20 tea~ ec040s transfer error acknowledge c21 vcc boards vcc plane c22 rsth~ hard reset pin of the quicc c23 rsts~ soft reset pin of the quicc c24 perr~ parity error pin of the quicc c25 vcc boards vcc plane c26 ts~ ec040? transfer start c27 we0~ quiccs write enable 0 c28 we1~ quiccs write enable 1 c29 gnd boards ground c30 we2~ quiccs write enable 2 c31 gnd boards ground c32 we3~ quiccs write enable 3 table 5-9 connector p9 interconnect signals pin no. signal name description a1 clk4 buffered system clock a2 gnd boards ground a3 sia_rx sia receive data. also scc2s receive data table 5-8 connector p8 interconnect signals pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 46 a4 sia_tx sia transmit data. also scc2s transmit data a5 - a6 gnd boards gnd a7 - a8 pa6 - pa7 port a 6 - 7 parallel i/o lines a9 gnd boards ground a10 clko1 quiccs clock out 1 a11 gnd boards ground a12 - a14 vcc boards vcc plane a15 siatck sias transmit clock. also quiccs clk3. a16 siarck sias receive clock. also quiccs clk4. a17 vcc boards vcc plane a18 - a21 prty0 - prty3 quiccs parity lines a22 - a24 gnd boards ground a25 - a26 irq2~ irq3~ quiccs interrupt requests 2 - 3 a27 vcc boards vcc plane a28 irq5~ quiccs interrupt request 5 a29 - a31 vcc boards vcc plane a32 gnd boards ground b1 - b2 tln0 - tln1 ec040s transfer line indicators b3 - b4 upa0 - upa1 ec040s users programmable attributes. b5 - b10 pb4 - pb9 quiccs port bs parallel i/o lines 4 - 9 b11 tip~ ec040s transfer in progress b12 br040~ ec040s bus request b13 bg040~ ec040s bus grant b14 - b17 pst0 - pst3 ec040s processor status 0 - 3 b18 - b19 sc0 - sc1 ec040s snoop control 0 - 1 b20 gnd boards ground b21 s_tena sias transmit enable input b22 - b23 pc2 - pc3 quiccs port c parallel i/o lines 2 - 3 b24 - b25 gnd boards ground b26 s_clsn sias collision indicator b27 s_rena sias receive enable output b28 - b31 pc8 - pc11 quiccs port c parallel i/o lines 8 - 11 b32 gnd boards ground c1 - c4 cas0~ - cas3~ quiccs column address strobe outputs 0 -3 c5 - c10 vcc boards vcc plane c11 gnd boards ground c12 - c13 cs6~ - cs7~ quicc chip-select outputs 6 - 7 c14 gnd boards ground c15 locke~ ec040 lock end output c16 tci~ ec040s transfer cache inhibit input table 5-9 connector p9 interconnect signals pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 47 5.2.10 connector p10 interconnect signals connector p10 is a 96 pin, female, 90 0 , din connector, serving as an expansion connector for off-board hardware applications. it is identical in pin out to p8. for interconnect signal reference, see table 5-1 on page 41. 5.2.11 connector p11 interconnect signals connector p11 is a 96 pin, female, 90 0 , din connector, serving as an expansion connector for off-board hardware applications. it is identical in pin out to p9. for interconnect signal reference, see table 5-1 on page 41. 5.3 m68360quads-040 parts list the components of the m68360quads-040 and their reference designation are listed in table 5-10. a. applicable only if mc68 lc 040 processor is installed. c17 mi~ ec040s memory inhibit output c18 ciout~ ec040 cache inhibit out c19 ipend~ ec040 interrupt pending output c20 cdis~ ec040s cache disable input c21 bkpto~ quiccs breakpoint output c22 rsth~ quiccs hard reset signal c23 rsts~ quiccs soft reset signal c24 badd3 quiccs burst address line 3 c25 mdis~ a lc040s memory management unit disable input. c26 badd2 quiccs burst address line 2 c27 dd1~ quiccs ras double drive output 1 c28 - c32 gnd boards ground table 5-10 parts list reference designation part description notes c1 capacitor 100 m f electrolytic t.h. c2, c3, c8 - c10, c12, c13, c18, c19, c21 - c28, c30, c31, c34 - c49, c51 - c109 capacitor 0.1 m f smd c4 - c7 capacitor 10 m f electrolytic smd c11 capacitor 4700 pf smd c14 capacitor 680 pf smd c15 capacitor 20 pf smd table 5-9 connector p9 interconnect signals pin no. signal name description f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 48 c16, c17 capacitor 100 pf smd c20 capacitor 0.039 m f smd c29 capacitor 3900 pf smd c32, c33 capacitor 68 pf smd c50 capacitor 390 pf smd d1 mbrd620ct smd d2 1smc5.0at3 (zener) smd dsw1 dip-switch, spst 8 smd f1 fuse block, with 5a fuse 5v power supply j1 - j6, j8 - j10 jumper header, 2 pole, with fabricated jumper j7 jumper header, 3 pole, with fabricated jumper ld1, ld4, ld6, ld10 led red smd ld2, ld3, ld8 led green smd ld5, ld7, ld9 led yellow smd p1 connector 37 pin d type male p2 connector 9 pin d type female p3, p5 connector 15 pin d type female p4 connector 8 pin rj-45 p6 power connector, 3 pin with plug 5v power supply p7 power connector, 2 pin with plug 12v power supply p8, p9 connector 96 pin din male straight logic analyzer p10, p11 connector 96 pin din female 90 0 . compatible wire-wrap connectors are supplied with the m68360quads-040. expansion r1 - r3, r12 - r14, r18 - r21 resistor 39.1 w smd r4, r11, r17, r23, r29 - r37 resistor 4.7 k w smd r5 resistor 240 w smd r6 - r10 resistor 330 w smd r15 resistor 3 k w smd r16 resistor 510 w smd r22 resistor 290 w smd table 5-10 parts list reference designation part description notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 49 a. only u33 - u36 are factory populated. u27 - u30 are user optional. r24 resistor 100 w smd r25 - r28 resistor 150 w smd rn1 rn2 resistor network 16 pin, 8 resistors 22 w smd rn3 - rn10 resistor network 14 pin, 13 resistors 4.7 k w smd sw1, sw2 s.p.d.t. push button t1, t3 i.c. pe64503 dip t2 i.c. pe65263 dip t4 i.c. pe65260 dip u1- u2 i.c. 74ls240 smd u3 i.c. mc145407 smd u4 i.c. am7992 cdip socket mounted u5 laf10t-7b ethernet ?ter sil u6 laf10t-3b ethernet ?ter sil u7 i.c. mc68160 (eest) pqfp u8 - u9 i.c. 74ls373 smd u10 - u11 i.c. pal20ra10-20 dip socket mounted u12 i.c. pal22v10-25 dip socket mounted u13 i.c. 74ls245 smd u14 i.c. mcm2814 dip u15 i.c. 74ls85 smd u16, u38 i.c. 74act86 smd u17, u26, u31 i.c. 74f157 smd u18 - u21 i.c. am29f010-12 smd socket mounted u22 i.c. mcm36256 dram simm simm socket mounted u23 i.c. pal22v10-15 dip socket mounted u24 mc68ec040fe33 cqfp u25 mc68360 quicc pga socket mounted u27 - u30, u33 - u36 a mcm62940afn smd u32 i.c. pal16r4-7 dip socket mounted u37 i.c. clock generator 50 mhz, cmos / ttl levels dip socket mounted u39 i.c. 74act74 smd y1, y2 crystal resonator 20mhz smd table 5-10 parts list reference designation part description notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 50 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 51 appendix a - adi board installation a.1 introduction this appendix describes the hardware installation of the adi board into various host computers. the installation instructions cover the following host computers: 1. ibm-pc/xt/at 2. sun - 4 (sbus interface) a.2 ibm-pc/xt/at to m68360quads-040 interface the adi board should be installed in one of the ibm-pc/xt/at motherboard system expansion slots. a single adi can control up to eight m68360quads-040 boards. the adi address in the computer is configured to be at i/o memory addresses 100-102 (hex), but it may be reconfigured for an alternate address space. caution before removing or installing any equipment in the ibm-pc/xt/at computer, turn the power off and remove the power cord. a.2.1 adi installation in ibm-pc/xt/at refer to the appropriate installation and setup manual of the ibm-pc/xt/at computer for instructions on removing the computer cover. the adi board address block should be configured at a free i/o address space in the computer. the address must be unique and it must not fall within the address range of another card installed in the computer. the adi board address block can be configured to start at one of the three following addresses: $100 - this address is unassigned in the ibm-pc $200 - this address is usually used for the game port $300 - this address is defined as a prototype port the adi board is factory configured for address decoding at 100-102 hex in the ibm-pc/xt/at i/o address map. these are undefined peripheral addresses. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 52 figure a-1 physical location of jumper jg1 and jg2 note: jumper jg2 should be left unconnected. the following figure shows the required jumper connection for each address configuration. address 0 hex is not recommended, and its usage might cause problems. figure a-2 jg1 configuration options to properly install the adi board, position its front bottom corner in the plastic card guide channel at the front of the ibm-pc/xt/at chassis. keeping the top of the adi board level and any ribbon cables out of the way, lower the board until its connectors are aligned with the computer expansion slot connectors. using evenly distributed pressure, press the adi board straight down until it seats in the expansion slot. secure the adi board to the computer chassis using the bracket retaining screw. refer to the computer installation and setup manual for instructions on reinstalling the computer cover. a.3 sun-4 to m68360quads-040 interface the adi board should be installed in one of the sbus expansion slots in the sun-4 sparcstation computer. a single adi can control up to eight m68360quads-040 boards. jg1 jg2 0 hex 100 hex 200 hex 300 hex f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 53 caution before removing or installing any equipment in the sun-4 computer, turn the power off and remove the power cord. a.3.1 adi installation in the sun-4 there are no jumper options on the adi board for the sun-4 computer. the adi board can be inserted into any available sbus expansion slot on the motherboard. refer to the appropriate installation and setup manual for the sun-4 computer for instructions on removing the computer cover and installing the board in an expansion slot. figure a-3 adi board for sbus following is a summary of the instructions in the sun manual: 1. turn off power to the system, but keep the power cord plugged in. be sure to save all open files and then the following steps should shut down your system: hostname% /bin/su password: mypasswd hostname# /usr/etc/halt wait for the following messages. syncing file systems... done halted program terminated type b(boot), c(continue), n(new command mode) when these messages appear, you can safely turn off the power to the system unit. 2. open the system unit. be sure to attach a grounding strap to your wrist and to the metal casing of the power supply. follow the instructions supplied with your system to gain access to the sbus slots. 3. remove the sbus slot filler panel for the desired slot from the inner surface of the back panel of the system unit. note that the adi board is a slave only board and thus will function in any available sbus slot. 4. slide the adi board at an angle into the back panel of the system unit. make sure that the mounting plate on the adi board hooks into the holes on the back panel of the system unit. adi sbus connector connector f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 54 5. push the adi board against the back panel and align the connector with its mate and gently press the corners of the board to seat the connector firmly. 6. close the system unit. 7. connect the 37 pin interface flat cable to the adi board and secure. 8. turn power on to the system unit and check for proper operation. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 55 appendix b - adi port handshake description b.1 introduction in this appendix, the adi port signals and the handshake procedure are explained. the m68360quads- 040 adi port can be connected to an adi board mounted in a host computer. there are adi boards for the following host computers: 1. ibm-pc/xt/at 2. sun - 4 (sbus interface) b.2 adi port concept and operation description each adi board can be connected to up to 8 m68360quads-040 boards. each m68360quads-040 has its own address which is fixed by setting dip-switch dsw1 on the board. refer to section 2.3.1 on page 13. the following operations can be performed using the adi port : the host computer can write a byte to the m68360quads-040 the m68360quads-040 can write a byte to the host computer the m68360quads-040 can interrupt the host computer the host computer can interrupt the m68360quads-040 (interrupt level 7) the host computer can reset (soft or hard) the m68360quads-040 if more than one m68360quads-040 is connected to the same adi board, the host computer can perform the following operations simultaneously on all m68360quads-040 boards : abort all boards (interrupt level 7) reset all boards b.3 handshake description every action between the m68360quads-040 and the host is asynchronous and is implemented by asserting and negating handshake signals by software. all signals have ttl levels. a control signal is asserted if it is driven to logic ??ttl level, and it is negated if it is driven to logic ??level. the connection between the host computer and the m68360quads-040 is shown in figure b-1 below. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 56 figure b-1 host computer (adi) to m68360quads-040 connection b.3.1 write cycle from host to m68360quads-040 the application software in the host uses the handshake signals to coordinate data transfer across the parallel link. the quicc040bug software in the m68360quads-040 is responsible for accepting the data and responding to the handshake signals. the signals are shown in figure b-2. the sequence of events during a byte write to the m68360quads-040 is as follows: 1. the host selects the m68360quads-040 board by putting the board? address on the ads_sel(0:2) signals. 2. the host places a data byte in the data bus latch (buffer is in high-impedance state). 3. the host asserts the host_req signal (the data buffer is enabled, data appears on the bus). 4. the m68360quads-040 detects the host_req signal and reads the data byte. 5. the m68360quads-040 asserts the ads_ack signal. host_req ads_ack ads_req hst_ack ads_brk host_brk~ ads_int int_ack ads_reset ads_all ads_sel(0:2) pd(0:7) host_enable~ host_vcc m68360quads-040 adi board host computer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 57 6. the host detects the ads_ack signal and negates the host_req signal (data buffer is disabled). 7. the m68360quads-040 detects the negation of host_req signal and negates ads_ack to end the cycle. figure b-2 host write to m68360quads -040 b.3.2 write cycle from m68360quads-040 to host the signal handshake during an m68360quads-040 to host write cycle is shown in figure b-3. the sequence of events is as follows: 1. the m68360quads-040 places a data byte on the parallel port data bus (buffer disabled) and asserts the ads_req signal (the ads_req signal will not appear on the port until the board is selected by the host). 2. the host polls each m68360quads-040 address and detects the ads_req signal from the requesting board. the host asserts the hst_ack signal in response, which enables the data buffer in the m68360quads-040. 3. the m68360quads-040 negates the ads_req signal. the data appears on the bus as long as the hst_ack signal is asserted. 4. the host reads the data. 5. the host negates the hst_ack signal to end the cycle. the m68360quads-040 ends the cycle. ads_sel(0:2) host_req ads_ack pd(0:7) address valid 1 2 3 4 5 6 7 data valid f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 58 figure b-3 m68360quads-040 write cycle to host b.3.3 m68360quads-040 interrupt to the host the m68360quads-040 can generate an interrupt to the host. the interrupt request and acknowledge sequence is shown in figure b-4. the sequence is as follows: 1. the m68360quads-040 places a service request code on the parallel port data bus (buffer disabled) and asserts the ads_int and the host_brk~ signals. the host_brk~ signal is an open-collector signal, asserted low, common to all m68360quads-040 boards which will appear immediately on the port. the ads_int signal will not appear on the port until the board is selected by the host. 2. the host detects the host_brk~ signal and polls each m68360quads-040 address to determine the interrupting board. 3. the host asserts the hst_ack signal, enabling the data buffer in the m68360quads- 040. 4. the host reads the service request code on the data bus. 5. the host negates the hst_ack signal. 6. the host asserts the int_ack signal, which resets the host_brk latch in the m68360quads-040 and negates the host_brk~ signal. the host_brk~ signal can still be low (asserted) if another m68360quads-040 board is driving it low. 7. the selected m68360quads-040 detects the int_ack signal and negates the ads_int signal. 8. the host negates the int_ack signal and ends the cycle. ads_sel(0:2) hst_ack pd(0:7) address valid 1 2 3 4 5 data valid ads_req f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 59 figure b-4 m68360quads-040 interrupt to host b.3.4 host interrupt to the m68360quads-040 the host can interrupt the m68360quads-040 (interrupt level 7) to abort the execution of programs running on the board. this is done by selecting the address of the required m68360quads-040 and momentarily asserting the ads_brk signal, which sets a latch in the m68360quads-040. the output of the latch interrupts the ec040 on the m68360quads-040. the latch is cleared by the interrupt handling software on the m68360quads-040. b.3.5 host reset to the m68360quads-040 the host can perform either hard reset or soft reset on the m68360quads-040. soft reset is done by selecting the address of the required board and asserting the ads_reset signal for more than 26 microseconds. hard reset is done by selecting the address of the required board, asserting int_ack signal, and asserting the ads_reset signal for more than 26 microseconds. b.3.6 addressing all m68360quads-040 the host can reset or interrupt all m68360quads-040 boards that are connected to the same adi. the host should assert the ads_all signal in conjunction with either ads_reset or ads_brk. the contents of the ads_sel(0:2) lines have no affect. ads_sel(0:2) hst_ack pd(0:7) address valid 1 2 3 4 5 data valid ads_int host_brk~ int_ack 6 7 8 hardware software f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 60 appendix c - pals?equations c.1 u10 - indicators logic title indicatr pattern indicatr.pds revision pilot.0 date 8,8,93 ;******************************************************** chip indic pal20ra10 ;*************************** pl pst0 pst1 pst2 pst3 tip as adsnt bkclr ck_nmi cs5 gnd ; 1 2 3 4 5 6 7 8 9 10 11 12 oe nc nc nc nc h_brk h_brk_ h_nmi hlt rundm run040 vcc ; 13 14 15 16 17 18 19 20 21 22 23 24 ;******************************************************************** ; this pal serves as indicators logic, adi interrupts logic ; and future support for mc68040 buffers configuration (via ipl). ; run040 drives the run040 led when tip is active (low). ; rundm drives the rundma led when as is active (low). ; hlt drives the halt led according to the state of pst(0:3). ; h_nmi serves as a ff for the host generated level 7 interrupt. ; h_brk_ is a simulated o.c. output for the adi's host break, oe ; of which is driven by h_brk. ;******************************************************************** equations ;************** /run040 = vcc run040.trst = /tip run040.rstf = vcc ; bypass run040.setf = vcc /rundm = vcc rundm.trst = /as rundm.rstf = vcc ; bypass rundm.setf = vcc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 61 /hlt = vcc hlt.trst = /pst3 * pst2 * /pst1 * pst0 ; halted state hlt.rstf = vcc; bypass hlt.setf = vcc h_nmi.clkf = ck_nmi ; rising edge of ck_nmi /h_nmi := vcc h_nmi.trst = vcc h_nmi.rstf = /cs5 h_nmi.setf = gnd h_brk_ = gnd h_brk_.trst = h_brk h_brk_.rstf = vcc ; bypass h_brk_.setf = vcc h_brk.clkf = /adsnt ; rising edge of adsnt~ h_brk := vcc h_brk.trst = vcc h_brk.rstf = gnd h_brk.setf = /bkclr c.2 u11 - reset & abort generator title rstabr pattern rstabr.pds revision pilot.0 date 8,8,93 ;******************************************************** chip rstabr pal20ra10 ;*************************** ; this pal is used as a reset and abort generator for the quicc040evb. ; deb1 serves as a debouncer for the reset push-button and deb2 serves ; a debouncer for the abort p.b. ; irq7 which is the logical sum of all events causing level 7 interrupt, ; i.e., abort push button, breakpoint and host nmi, (drives the oe of ; irq7 to simulate open collector. - abort was removed since its pin was ; needed for rsti, therefore, irq7* at the connector should never be ; driven from outside) ; abrt serves a ff holding the request for the abort push button f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 62 ; bkint serves as a ff holding the request from the breakpoint logic. ; rsts_ is a simulated o.c. driving the soft reset line of the quicc, while ; its oe is driven by rsts ; rsth_ is a simulated o.c. driving the hard reset line of the quicc, while ; its oe is driven by rsth ; rsts logically sums the conditions for soft reset: push-button, host ; soft reset and reset instruction (rsto). ; rsti logically sums the conditions for 040 reset: hard reset ; (both push-buttons are depressed), p.b. soft reset, host hard and soft ; reset, p.u. reset and software watch-dog reset. ; rsti is separated from rsth_ in order of supporting soft reset as well. ;************************************************************************* pl rst1 rst2 abr1 abr2 h_rsth h_rsts rsto cs5 h_nmi bkpto gnd ; 1 2 3 4 5 6 7 8 9 10 11 12 oe rsti deb2 deb1 abrt rsts rsth bkint irq7 rsts_ rsth_ vcc ; 13 14 15 16 17 18 19 20 21 22 23 24 ;************************************************************************ equations ;************** /irq7 = /abrt ; abort p.b. ff + /h_nmi; host nmi + /bkint; breakpoint logic irq7.trst = vcc irq7.rstf = vcc; bypass irq7.setf = vcc deb1.trst = vcc deb1.rstf = /rst2 deb1.setf = /rst1 ;reset debouncer deb2.trst = vcc deb2.rstf = /abr2 deb2.setf = /abr1 ;abort debouncer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 63 abrt.clkf = deb2 ; rising edge of abort debouncer. /abrt := vcc ; active low. abrt.trst = vcc abrt.rstf = /cs5 ; reset the ff ('1') abrt.setf = gnd rsts = h_rsts ; host generated soft reset + deb1 * /deb2 ; soft reset push button depressed + /rsto ; reset instruction rsts.trst = vcc rsts.rstf = vcc ; bypass rsts.setf = vcc rsth = h_rsth ; host generated hard reset + deb1 * deb2 ; both push buttons depressed rsth.trst = vcc rsth.rstf = vcc ; bypass rsth.setf = vcc bkint.clkf = /bkpto ; falling edge of bkpto. /bkint := vcc ; active low. bkint.trst = vcc bkint.rstf = /cs5 ; reset the ff ('1') bkint.setf = gnd /rsti = /rsth_ ; quicc generated resets + host hard reset + deb1 ; p.b. hard + soft reset + h_rsts ; host soft reset rsti.trst = vcc rsti.rstf = vcc ; bypass rsti.setf = vcc /rsts_ = vcc ; active low rsts_.trst = rsts rsts_.rstf = vcc ; bypass rsts_.setf = vcc /rsth_ = vcc ; active low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 64 rsth_.trst = rsth rsth_.rstf = vcc ; bypass rsth_.setf = vcc c.3 u12 - adi controller ; reference designation - u3 title parallel_cont pattern parcont.pds revision a.0 date 23,12,92 ;******************************************************** chip parcont pal22v10 ;*************************** ads_g rsts hsvcc adrst adall adbrk hsten hsack hsreq inack nc gnd ; 1 2 3 4 5 6 7 8 9 10 11 12 adssel adi_rd ck_nmi bkclr nc nc adiac h_rsth h_rsts adi_g adidir ; 13 14 15 16 17 18 19 20 21 22 23 vcc global ; 24 the 25'th pin ;*************************************************************** ; this pal serves as an adi controller for the m68360quads-040. ; h_rsts generates soft reset for the evb ; h_rsth generates hard reset for the evb ; ck_nmi generates the level 7 interrupt ; bkclr resets the host break ff ; adi_rd open the strobes buffer towards the adi ; adi_g enables the data buffer ; adi_ac generates interrupt upon host request or acknowledge. ; adidir controls the direction of the data buffer: 0 - outside. ;**************************************************************** equations ;************** h_rsts = hsten * /hsvcc * /adrst * adssel + hsten * /hsvcc * /adrst * /adall f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 65 h_rsth = hsten * /hsvcc * /adrst * adssel * /inack + hsten * /hsvcc * /adrst * /adall * /inack ck_nmi = hsten * /hsvcc * /adbrk * adssel + hsten * /hsvcc * /adbrk * /adall /bkclr = /rsts + /inack * hsten * /hsvcc * adssel /adi_rd = hsten * adssel * /hsvcc /adi_g = hsten * /hsvcc * adssel * /hsack; host reads + hsten * /hsvcc * adssel * /ads_g; local read + hsten * /hsvcc * /adall * /ads_g; local read /adiac = hsten * /hsvcc * /hsreq * /adall + hsten * /hsvcc * /hsreq * adssel + hsten * /hsvcc * /hsack * adssel /adidir = hsten * ads_g * /hsvcc * adssel * /hsack; host read only c.4 u23 - core disable logic title discpu pattern dis_bug.pds revision pilot.0 date 9,8,93 ;************************************************************************* ; this pal is meant to fix the core-disable problem in the quicc. ; it contains a 6 bit synchronous counter, which starts counting after ; reseth_ is asserted. ; during the first 64 clocks since reseth_ is asserted, conf2 is held at ; '1' to allow reset of the core. on the next clock conf2 is driven low ; until reseth_ is negated. after that conf2 is tri-stated and held down ; by an external pull-down resistor. ; f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 66 ; s_rst: synchronized reseth ; ds_rst: double synchronized reseth ; d_rst: detect reseth asserted. ; conf2: quicc config2 pin, which determines core disable. ; q0 - q5: counter stages ; reseth: quiccs hard reset i/o pin - active low. ; cin: active high count enable. ;************************************************************************* chip dis_bug pal22v10 ;********************** clk nc nc nc nc nc nc nc cin nc reseth gnd ; i1 i2 i3 i4 i5 i6 i7 i8 i9 i10 i11 12 nc q5 q4 q3 q2 q1 q0 conf2 d_rst ds_rst s_rst vcc ; i13 o14 o15 o16 o17 o18 o19 o20 o21 o22 o23 24 global equations ;************* s_rst := reseth; sync reseth s_rst.trst = vcc ds_rst := s_rst; double sync reseth ds_rst.trst = vcc /d_rst = /s_rst * ds_rst ; identifying reseth falling edge to ; synchronously reset the counter q0 := /q0 * d_rst * cin ; counter lsb + q0 * d_rst * /cin q0.trst = vcc q1 := /q1 * q0 * d_rst * cin + q1 * /q0 * d_rst * cin + q1 * d_rst * /cin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 67 q1.trst = vcc q2 := q2 * /q1 * d_rst * cin + q2 * /q0 * d_rst * cin + /q2 * q1 * q0 * d_rst * cin + q2 * d_rst * /cin q2.trst = vcc q3 := q3 * /q2 * d_rst * cin + q3 * /q1 * d_rst * cin + q3 * /q0 * d_rst * cin + /q3 * q2 * q1 * q0 * d_rst * cin + q3 * d_rst * /cin q3.trst = vcc q4 := q4 * /q3 * d_rst * cin + q4 * /q2 * d_rst * cin + q4 * /q1 * d_rst * cin + q4 * /q0 * d_rst * cin + /q4 * q3 * q2 * q1 * q0 * d_rst * cin + q4 * d_rst * /cin q4.trst = vcc q5 := q5 * /q4 * d_rst * cin ; counter msb + q5 * /q3 * d_rst * cin + q5 * /q2 * d_rst * cin + q5 * /q1 * d_rst * cin + q5 * /q0 * d_rst * cin + /q5 * q4 * q3 * q2 * q1* q0 * d_rst * cin + q5 * d_rst * /cin q5.trst = vcc /conf2 = q1 * q2 * q3 * q4 * q5 ; end of count conf2.trst = /reseth ; tristated after reseth rising edge f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 68 global.setf = gnd global.rstf = gnd c.5 u32 - bursting sram controller title sramcont pattern sramcnt.pds revision pilot.0 date 15,8,93 ;******************************************************** chip sramcnt pal16r4 ;******************************************************************* ; this pal serves as a bursting sram controller, for the quicc040evb. ; srmg(1:2) are active-low g (oe) for the sram banks. ; tsc is a delayed ts~ ; baa(1:2) are active-low burst address advance for the srams. ; baa should be driven to the srams only during burst access and in ; burst write cycle one clock later than in burst read. ; sas is a one clock delayed as. ;******************************************************************* clk cs3 ts tip as siz0 siz1 ta r_w gnd ; 1 2 3 4 5 6 7 8 9 10 oe cs4 nc sas baa2 tsc baa1 srmg2 srmg1 vcc ; 11 12 13 14 15 16 17 18 19 20 ;******************************************************** equations ;************** /srmg1 = /cs3 * r_w srmg1.trst = vcc /srmg2 = /cs4 * r_w srmg2.trst = vcc /tsc := /ts + /as * sas f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
m68360quads-040 hardware user? manual support information 69 /baa1 := siz1 * siz0 * /tsc * /cs3 * r_w * ta * /tip ; burst read + siz1 * siz0 * tsc * /cs3 * /r_w * /ta * /tip ; burst write baa~ should be asserted ; one clock later + /baa1 * /cs3 /baa2 := siz1 * siz0 * /tsc * /cs4 * r_w * ta * /tip ; burst read + siz1 * siz0 * tsc * /cs4 * /r_w * /ta * /tip ; burst write baa~ should be asserted ; one clock later + /baa2 * /cs4 /sas := /as cs4.trst = gnd; input f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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