View ADSP-21MOD870_3044696.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADSP-21MOD870 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 internet gateway processor functional block diagram serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 16k 3 24 pm 8k 3 24 overlay 1 8k 3 24 overlay 2 timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode 16k 3 16 dm 8k 3 16 overlay 1 8k 3 16 overlay 2 features performance complete single-chip internet gateway processor (no external memory required) implements v.34/v.90 data/fax modem including controller and datapump 19 ns instruction cycle time @ 3.3 v, 52 mips sustained performance open architecture platform extensible to voice over ip and other applications low power dissipation, 80 mw (typical) for digital modem power-down mode featuring low cmos standby power dissipation integration adsp-2100 family code compatible, with instruction set extensions 160k bytes of on-chip ram, configured as 32k words on-chip program memory ram and 32k words on- chip data memory ram dual purpose program memory for both instruction and data storage independent alu, multiplier/accumulator and barrel shifter computational units two independent data address generators powerful program sequencer provides zero overhead looping conditional instruction execution programmable 16-bit interval timer with prescaler 100-lead lqfp with 0.4 square inch (256 mm 2 ) footprint system interface 16-bit internal dma port for high speed access to on- chip memory (mode selectable) two double-buffered serial ports with companding hardware and automatic data buffering programmable multichannel serial port supports 24/32 channels automatic booting of on-chip program memory through internal dma port six external interrupts 13 programmable flag pins provide flexible system signaling ice-port? emulator interface supports debugging in final systems general description the ADSP-21MOD870 is a single-chip internet gateway pro- cessor optimized for implementation of a complete v.34/56k modem. all data pump and controller functi ons can be imple- mented on a single chip, offering the lowest power consumption and highest possible modem port density. the ADSP-21MOD870, shown in the functional block dia- gram, combines the adsp-2100 family base architecture (three computational units, data address generators and a program sequencer) with two serial ports, a 16-bit internal dma port, a byte dma port, a programmable timer, flag i/o, extensive interrupt capabilities and on-chip program and data memory. the ADSP-21MOD870 integrates 160k bytes of on-chip memory configured as 32k words (24-bit) of program ram, and 32k words (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery operated portable equipment. the ADSP-21MOD870 is available in 100-lead lqfp package. fabricated in a high speed, low power, cmos process, the ADSP-21MOD870 operates with a 19 ns instruction cycle time. every instruction can execute in a single processor cycle. the ADSP-21MOD870s flexible architecture and comprehen- sive instruction set allow the processor to perform multiple operations in parallel. in one processor cycle the ADSP-21MOD870 can: ? generate the next program address ? fetch the next instruction ? perform one or two data moves ? update one or two data address pointers ? perform a computational operation ice-port is a trademark of analog devices, inc. all other trademarks are the property of their respective holders .
ADSP-21MOD870 C2C rev. 0 this takes place while the processor continues to: ? receive and transmit data through the two serial ports ? receive and/or transmit data through the internal dma port ? receive and/or transmit data through the byte dma port ? decrement timer modem software the modem software executes general modem control, com- mand sets, error correction and data compression, data modula- tions (for example, v.90 and v.34), and host interface functi ons. the host interface allows system access to modem statistics such as call progress, connect speed, retrain count, symbol rate and other modulation parameters. the modem data pump and controller software reside in on- chip sram and do not require external memory. you can configure the ADSP-21MOD870 dynamically by downloading software from the host through the 16-bit dma interface. this sram-based architecture provides a software upgrade path to future standards and applications, such as voice over ip. the modem software is available as object code. development system the adsp-2100 family development software, a complete set of tools for software and hardware system development, sup- ports the ADSP-21MOD870. the system builder provides a high level method for defining the architecture of systems under development. the assembler has an algebraic syntax that is easy to program and debug. the linker combines object files into an executable file. the simulator provides an interactive instruction-level simulation with a reconfigurable user interface to display different portions of the hardware environment. a prom splitter generates prom programmer compatible files. the c compiler, based on the free software founda tions gnu c compiler, generates ADSP-21MOD870 assembly source code. the source code debugger allows programs to be cor- rected in the c environment. the runtime library includes over 100 ansi-standard mathematical and dsp-specific functions. the adsp-218x ez-ice ? emulator aids in the hardware de- bugging of an ADSP-21MOD870 system. the emulator consists of hardware, host computer resident software, and the target board connector. the ADSP-21MOD870 integrates on-chip emulation support with a 14-pin ice-port interface. this interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other adsp-2100 family ez-ices. the ADSP-21MOD870 device need not be removed from the target system when using the ez- ice, nor are any adapters needed. due to the small footprint of the ez-ice connector, emulation can be supported in final board designs. the ez-ice performs a full range of functions, including: ? in-target operation ? up to 20 breakpoints ? single-step or full speed operation ? registers and memory values can be examined and altered ? pc upload and download functions ? instruction-level emulation of program booting and execution ? complete assembly and disassembly of instructions ? c source-level debugging see designing an ez-ice-compatible target system in the adsp-2100 family ez-tools manual (adsp-2181 sections) as well as the designing an ez-ice compatible system section of this data sheet for the exact specifications of the ez-ice target board connector. ADSP-21MOD870 reference design/evaluation kit the ADSP-21MOD870-ev1 is a reference design/evaluation kit that includes an isa bus pc card that has an adsp-21061l sharc ? processor as a host, four ADSP-21MOD870 internet gateway processors and a t1 interface. the board is shipped with an evaluation copy of the modem software and software that runs on the pc. the pc software provides a user interface that lets you run a modem session right out of the box. when you run the modem in keyboard mode, characters typed on the keyboard are transmitted to the other modem and characters sent by the other modem are displayed on the screen. data can also be streamed through the com port of the pc to send and receive files and perform automated testing. the modem system contains four ADSP-21MOD870s connected to an adsp-21061 sharc host processor. this design is ex- tensible to 32 ADSP-21MOD870s. the ADSP-21MOD870s are connected to a t1 interface. this accommodates testing with a digital line. a diagram of the system is shown below in figure 1. the sharc processor communicates to the pc through the isa bus. the sharc acts as the modem system host and con- trols the ADSP-21MOD870-based modems connected to a dma bus. the code, written in c, runs on the sharc and provides an example of how the host loads code i nto the adsp- 21mod870s, ez-ice and sharc are registered trademarks of analog devices, inc. adsp-21061 sharc flash host modem pool line i/f t1/isdn adsp-2183 digital telco adsp- 21mod870 adsp- 21mod870 adsp- 21mod870 adsp- 21mod870 isa bus sport mem i/f idma port sport0 idma port idma port idma port sport0 sport0 sport0 figure 1. evaluation/reference design board
ADSP-21MOD870 C3C rev. 0 how data is passed, and how commands and status information are communicated. you can port this c code to whatever host processor you are using in your system. the s harc also controls an adsp-2181 connected to the dma bus. the adsp-2181 controls the t1 interface. the pcm serial stream from the t1 interface is connected to the serial ports of the ADSP-21MOD870s. a debugger is provided that lets you download code and data to the sharc and examine register and memory contents. moni- tor software is also included so you can run a modem session immediately out of the box without writing extra layers of software or adding to the configuration. additional information this data sheet provides a general overview of ADSP-21MOD870 functionality. for additional information on the architecture and instruction set of the processor, refer to the adsp-2100 family users manual, third edition . for more information about the development tools, refer to the adsp-2100 family development tools data sheet. for more information about the modem software refer to ADSP-21MOD870-100 modem software data sheet. architecture overview the ADSP-21MOD870 instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. every instruction can be executed in a single pro- cessor cycle. the ADSP-21MOD870 assembly language uses an algebraic syntax for ease of coding and readability. a compre- hensive set of development tools supports program development. serial ports sport 1 sport 0 memory programmable i/o and flags byte dma controller 16k 3 24 pm 8k 3 24 overlay 1 8k 3 24 overlay 2 timer adsp-2100 base architecture shifter mac alu arithmetic units power-down control program sequencer dag 2 dag 1 data address generators program memory address data memory address program memory data data memory data external data bus external address bus internal dma port external data bus or full memory mode host mode 16k 3 16 dm 8k 3 16 overlay 1 8k 3 16 overlay 2 figure 2. functional block diagram figure 2 is an overall block diagram of the ADSP-21MOD870. the processor contains three independent computational units: the alu, the multiplier/accumulator (mac) and the shifter. the computational units process 16-bit data directly and have provisions to support multiprecision computations. the alu performs a standard set of arithmetic and logic operations; division primitives are also supported. the mac performs single-cycle multiply, multiply/add and multiply/subtract opera- tions with 40 bits of accumulation. the shifter performs logical and arithmetic shifts, normalization, denormalization and de- rive exponent operations. the shifter can be used to efficiently implement numeric format control including multiword and block floating-point representations. the internal result (r) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. a powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these compu- tational units. the sequencer supports conditional jumps, sub- routine calls and returns in a single cycle. with internal loop counters and loop stacks, the ADSP-21MOD870 executes looped code with zero overhead; no explicit jump instructions are re- quired to maintain loops. two data address generators (dags) provide addresses for simultaneous dual operand fetches (from data memory and program memory). each dag maintains and updates four ad- dress pointers. whenever the pointer is used to access data (indi- rect addressing), it is post-modified by the value of one of four possible modify registers. a length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. efficient data transfer is achieved with the use of five internal buses: ? program memory address (pma) bus ? program memory data (pmd) bus ? data memory address (dma) bus ? data memory data (dmd) bus ? result (r) bus the two address buses (pma and dma) share a single external address bus, allowing memory to be expanded off-chip, and the two data buses (pmd and dmd) share a single external data bus. byte and i/o memory space also share the external buses. program memory can store both instructions and data, permit- ting the ADSP-21MOD870 to fetch two operands in a single cycle, one from program memory and one from data memory. the ADSP-21MOD870 can fetch an operand from program memory and the next instruction in the same cycle. in lieu of the address and data bus for external memory connec- tion, the ADSP-21MOD870 may be configured for 16-bit inter- nal dma port (idma port) connection to external systems. the idma port is made up of 16 data/address pins and five control pins. the idma port provides transparent, direct ac- cess to the dsps on-chip program and data ram. an interface to low cost byte-wide memory is provided by the byte dma port (bdma port). the bdma port is bidirectional and can directly address up to four megabytes of external ram or rom for off-chip storage of program overlays or data tables. the byte memory and i/o memory space interface supports slow memories and i/o memory-mapped peripherals with pro- grammable wait state generation. external devices can gain control of external buses with bus request/grant signals ( br , bgh , and bg ). one execution mode (go mode) allows the ADSP-21MOD870 to continue running from on-chip memory. normal execution mode requires the processor to halt while buses are granted. the ADSP-21MOD870 can respond to eleven interrupts. there can be up to six external interrupts (one edge-sensitive, two level-sensitive, and three configurable) and seven internal inter- rupts generated by the timer, the serial ports (sports), the byte dma port, and the power-down circuitry. there is also a master reset signal. the two serial ports provide a complete
ADSP-21MOD870 C4C rev. 0 synchronous serial interface with optional companding in hard- ware and a wide variety of framed or frameless data transmit and receive modes of operation. each port can generate an internal programmable serial clock or accept an external serial clock. the ADSP-21MOD870 provides up to 13 general-purpose flag pins. the data input and output pins on sport1 can be alter- natively configured as an input flag and an output flag. in addi- tion, there are eight flags that are programmable as inputs or outputs, and three flags that are always outputs. a programmable interval timer generates periodic interrupts. a 16-bit count register (tcount) decrements every n processor cycles, where n is a scaling value stored in an 8-bit register (tscale). when the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (tperiod). serial ports the ADSP-21MOD870 incorporates two complete synchronous serial ports (sport0 and sport1) for serial communications and multiprocessor communication. here is a brief list of the capabilities of the ADSP-21MOD870 sports. for additional information on serial ports, refer to the adsp-2100 family users manual, third edition . ? sports are bidirectional and have a separate, double- buffered transmit and receive section. ? sports can use an external serial clock or generate their own serial clock internally. ? sports have independent framing for the receive and trans- mit sections. sections run in a frameless mode or with frame synchronization signals internally or externally generated. frame sync signals are active high or inverted, with either of two pulsewidths and timings. ? sports support serial data word lengths from 3 to 16 bits and provide optional a-law and m -law companding according to ccitt recommendation g.711. ? sport receive and transmit sections can generate unique interrupts on completing a data word transfer. ? sports can receive and transmit an entire circular buffer of data with one overhead cycle per data word. an interrupt is generated after a data buffer transfer. ? sport0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. ? sport1 can be configured to have two external interrupts ( irq0 and irq1 ) and the flag in and flag out signals. the internally generated serial clock may still be used in this configuration. pin descriptions the ADSP-21MOD870 is available in a 100-lead lqfp package. to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt, and external bus pins have dual, multiplexed functionality. the external bus pins are configured during reset, while serial port pins are software configurable during program execution. flag and interrupt functionality is retained concurrently on multiplexed pins. the following table shows the common-mode pins. when pin functionality is configurable, the default state is shown in plain text, alternate functionality is in italics. common-mode pins # input/ pin of out- name(s) pins put function reset 1 i processor reset input br 1 i bus request input bg 1 o bus grant output bgh 1 o bus grant hung output dms 1 o data memory select output pms 1 o program memory select output ioms 1 o memory select output bms 1 o byte memory select output cms 1 o combined memory select output rd 1 o memory read enable output wr 1 o memory write enable output irq2/ 1 i edge- or level-sensitive interrupt request 1 pf7 i/o programmable i/o pin irql1/ 1 i level-sensitive interrupt requests 1 pf6 i/o programmable i/o pin irql0/ 1 i level-sensitive interrupt requests 1 pf5 i/o programmable i/o pin irqe/ 1 i edge-sensitive interrupt requests 1 pf4 i/o programmable i/o pin mode d/ 1 i mode select inputchecked only during reset pf3 i/o programmable i/o pin during normal operation mode c/ 1 i mode select inputchecked only during reset pf2 i/o programmable i/o pin during normal operation mode b/ 1 i mode select inputchecked only during reset pf1 i/o programmable i/o pin during normal operation mode a/ 1 i mode select inputchecked only during reset pf0 i/o programmable i/o pin during normal operation clkin, xtal 2 i clock or quartz crystal input clkout 1 o processor clock output sport0 5 i/o serial port 0 pins ( tfs0 , rfs0 , dt0 , dr0 , sclk0 ) sport1 2 5 i/o serial port 1 pins ( tfs1 , rfs1 , dt1 , dr1 , sclk1 ) or interrupts and flags: irq0 ( rfs1 ) 1 i external interrupt request #0 irq1 ( tfs1 ) 1 i external interrupt request #1 fi ( dr1 ) 1 i flag input pin fo ( dt1 ) 1 o flag output pin pwd 1 i power-down control input pwdack 1 o power-down control output fl0, fl1, fl2 3 o output flags v dd and gnd 16 i power and ground ez-port 9 i/o for emulation use notes 1 interrupt/flag pins retain both functions concurrently. if imask is set to enable the corresponding interrupts, the dsp will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2 sport configuration determined by the dsp system control register. software configurable.
ADSP-21MOD870 C5C rev. 0 memory interface pins the ADSP-21MOD870 processor can be used in one of two modes: full memory mode, which allows bdma operation with full external overlay memory and i/o capability, or host mode, which allows idma operation with limited external addressing capabilities. the operating mode is determined by the state of the mode c pin during reset and cannot be changed while the processor is running. full memory mode pins (mode c = 0) # of input/ pin name pins output function a13:0 14 o address output pins for pro- gram, data, byte and i/o spaces d23:0 24 i/o data i/o pins for program, data, byte and i/o spaces (8 msbs are also used as byte memory addresses) host mode pins (mode c = 1) # of input/ pin name pins output function iad15:0 16 i/o idma port address/data bus a0 1 o address pin for external i/o, program, data, or byte access d23:8 16 i/o data i/o pins for program, data byte and i/o spaces iwr 1 i idma write enable ird 1 i idma read enable ial 1 i idma address latch pin is 1 i idma select iack 1 o idma port acknowledge configurable in mode d; open drain in host mode, external peripheral addresses can be decoded using the a0, cms , pms , dms and ioms signals. terminating unused pin the following table shows the recommendations for terminating unused pins. pin terminations i/o hi-z* pin 3-state reset caused unused name (z) state by configuration xtal i i float clkout o o float a13:1 or o (z) hi-z br , ebr float iad12:0 i/o (z) hi-z is float a0 o (z) hi-z br , ebr float d23:8 i/o (z) hi-z br , ebr float d7 or i/o (z) hi-z br , ebr float iwr i i high (inactive) d6 or i/o (z) hi-z br , ebr float ird ii br , ebr high (inactive) d5 or i/o (z) hi-z br , ebr float ial i i low (inactive) d4 or i/o (z) hi-z br , ebr float is i i high (inactive) d3 or i/o (z) hi-z br , ebr float iack ** ** float d2:0 or i/o (z) hi-z br , ebr float iad15:13 i/o (z) hi-z is float pms o (z) o br , ebr float dms o (z) o br , ebr float bms o (z) o br , ebr float ioms o (z) o br , ebr float cms o (z) o br , ebr float rd o (z) o br , ebr float wr o (z) o br , ebr float br i i high (inactive) bg o (z) o ee float bgh o (z) o ee float irq2 /pf7 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql1 /pf6 i/o (z) i input = high (inactive) or program as output, set to 1, let float irql0 /pf5 i/o (z) i input = high (inactive) or program as output, set to 1, let float irqe /pf4 i/o (z) i input = high (inactive) or program as output, set to 1, let float sclk0 i/o i input = high or low, output = float rfs0 i/o i high or low dr0 i i high or low tfs0 i/o o high or low dt0 o o float sclk1 i/o i input = high or low, output = float rfs1/ irq0 i/o i high or low dr1/ fi i i high or low tfs1/ irq1 i/o o high or low dt1/ fo o o float ee i i ebr ii ebg oo ereset ii ems oo eint ii eclk i i elin i i elout o o notes * *hi-z = high impedance. **determined by mode d pin: mode d = 0 and in host mode: iack is an active, driven signal and cannot be wire ored. mode d = 1 and in host mode: iack is an open source and requires an external pull-down, but multiple iack pins can be wire ored together. 1. if the clkout pin is not used, turn it off. 2. if the interrupt/programmable flag pins are not used, there are two options: option 1: when these pins are configured as inputs at reset and function as interrupts and input flag pins, pull the pins high (inactive). option 2: program the unused pins as outputs, set them to 1, and let them float. 3. all bidirectional pins have three-stated outputs. when the pins is configured as an output, the output is hi-z (high impedance). 4. clkin, reset, and pf3:0 are not included in the table because these pins must be used.
ADSP-21MOD870 C6C rev. 0 interrupts the interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. the ADSP-21MOD870 provides four dedicated external inter- rupt input pins, irq2 , irql0 , irql1 , and irqe (shared with the pf7:4 pins). in addition, sport1 may be reconfigured for irq0 , irq1 , flag_in and flag_out, for a total of six external interrupts. the ADSP-21MOD870 also supports internal interrupts from the timer, the byte dma port, the two serial ports, software and the power-down control circuit. the inter- rupt levels are internally prioritized and individually maskable (except power down and reset). the irq2 , irq0 and irq1 input pins can be programmed to be either level- or edge- sensitive. irql0 and irql1 are level-sensitive and irqe is edge-sensitive. the priorities and vector addresses of all inter- rupts are shown in table i. table i. interrupt priority and interrupt vector addresses source of interrupt interrupt vector address (hex) reset (or power-up with pucr = 1) 0000 (highest priority) power-down (nonmaskable) 002c irq2 0004 irql1 0008 irql0 000c sport0 transmit 0010 sport0 receive 0014 irqe 0018 bdma interrupt 001c sport1 transmit or irq1 0020 sport1 receive or irq0 0024 timer 0028 (lowest priority) interrupt routines can either be nested with higher priority inter- rupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the power-down interrupt is nonmaskable. the ADSP-21MOD870 masks all interrupts for one instruction cycle following the execution of an instruction that modifies the imask register. this does not affect serial port autobuffering or dma transfers. the interrupt control register, icntl, controls interrupt nesting and defines the irq0 , irq1 and irq2 external interrupts to be either edge- or level-sensitive. the irqe pin is an external edge sensitive interrupt and can be forced and cleared. the irql0 and irql1 pins are external level-sensitive interrupts. the ifc register is a write-only register used to force and clear interrupts. on-chip stacks preserve the processor status and are automatically maintained during interrupt handling. the stacks are twelve levels deep to allow interrupt, loop, and subroutine nesting. the following instructions allow global enable or disable servicing of the interrupts (including power down), regardless of the state of imask. disabling the interrupts does not affect serial port autobuffering or dma. ena ints; dis ints; when the processor is reset, interrupt servicing is enabled. low power operation the ADSP-21MOD870 has three low power modes that signifi- cantly reduce the power dissipation when the device operates under standby conditions. these modes are: ? power-down ? idle ? slow idle the clkout pin may also be disabled to reduce external power dissipation. power-down the ADSP-21MOD870 internet gateway processor has a low power feature that lets the processor enter a very low power dormant state through hardware or software control. here is a brief list of power-down features. refer to the adsp-2100 fam- ily users manual, third edition , system interface chapter, for detailed information about the power-down feature. ? quick recovery from power-down. the processor begins executing instructions in as few as 400 clkin cycles. ? support for an externally generated ttl or cmos processor clock. the external clock can continue running during power- down without affecting the lowest power rating and 400 clkin cycle recovery. ? support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approxi- mately 4096 clkin cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 400 clkin cycle startup. ? power-down is initiated by either the power-down pin (pwd) or the software power-down force bit. interrupt support al- lows an unlimited number of instructions to be executed before optionally powering down. the power-down interrupt also can be used as a nonmaskable, edge-sensitive interrupt. ? context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. ? the reset pin also can be used to terminate power-down. ? power-down acknowledge pin indicates when the processor has entered power-down. idle when the ADSP-21MOD870 is in the idle mode, the processor waits indefinitely in a low power state until an interrupt occurs. when an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the idle instruc- tion. in idle mode idma, bdma and autobuffer cycle steals still occur. slow idle the idle instruction is enhanced on the ADSP-21MOD870 to let the processors internal clock signal be slowed, further reduc- ing power consumption. the reduced clock frequency, a pro- grammable fraction of the normal clock rate, is specified by a selectable divisor given in the idle instruction. the format of the instruction is idle ( n ); where n = 16, 32, 64 or 128. this instruction keeps the processor fully functional, but operating at the slower clock rate. while it is in this state, the processors other internal clock signals, such as sclk, clkout and timer clock, are reduced by the same
ADSP-21MOD870 C7C rev. 0 ratio. the default form of the instruction, when no clock divisor is given, is the standard idle instruction. when the idle ( n ) instruction is used, it effectively slows down the processors internal clock and thus its response time to in- coming interrupts. the one-cycle response time of the standard idle state is increased by n, the clock divisor. when an enabled interrupt is received, the ADSP-21MOD870 will remain in the idle state for up to a maximum of n processor cycles ( n = 16, 32, 64, or 128) before resuming normal operation. when the idle ( n ) instruction is used in systems that have an externally generated serial clock (sclk), the serial clock rate may be faster than the processors reduced internal clock rate. under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). system interface figure 3 shows a typical multichannel modem configuration with the ADSP-21MOD870. a line interface can be used to connect the multichannel subscriber or client data stream to the multichannel serial port of the ADSP-21MOD870. the adsp- 21mod870 can support 24 or 32 channels. the idma port of the ADSP-21MOD870 is used to give a host processor full access to the internal memory of the ADSP-21MOD870. this lets the host dynamically configure the ADSP-21MOD870 by loading code and data into its internal memory. this configuration also lets the host access server data directly from the ADSP-21MOD870s internal memory. in this configuration, the ADSP-21MOD870 should be put into host memory mode where mode c = 1, mode b = 0 and mode a = 1 (see table ii). clock signals the ADSP-21MOD870 can be clocked by either a crystal or a ttl-compatible clock signal. the clkin input cannot be halted, changed during operation, or operated below the specified frequency during normal opera- tion. the only exception is while the processor is in the power- down state. for additional information, refer to chapter 9, adsp-2100 family users manual, third edition, for detailed information on this power-down feature. if an external clock is used, it should be a ttl-compatible signal running at half the instruction rate. the signal is con- nected to the processors clkin input. when an external clock is used, the xtal input must be left unconnected. the ADSP-21MOD870 uses an input clock with a frequency equal to half the instruction rate; a 26 mhz input clock yields a 19 ns processor cycle (which is equivalent to 52 mhz). nor- mally, instructions are executed in a single processor cycle. all device timing is relative to the internal instruction clock rate, which is indicated by the clkout signal when enabled. because the ADSP-21MOD870 includes an on-chip oscillator circuit, an external crystal may be used. the crystal should be connected across the clkin and xtal pins, with two capaci- tors connected as shown in figure 4. capacitor values are de- pendent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fundamental frequency, microprocessor-grade crystal should be used. a clock output (clkout) signal is generated by the processor at the processors cycle rate. this is enabled and disabled by the clkodis bit in the sport0 autobuffer control register. adsp- 21mod870 sp0 idma adsp- 21mod870 idma sp0 adsp- 21mod870 sp0 idma adsp- 21mod870 idma sp0 adsp- 21mod870 sp0 idma adsp- 21mod870 idma sp0 adsp- 21mod870 sp0 idma adsp- 21mod870 idma sp0 line interface call control t1, e1, pri, xdsl, atm host bus host (2183) lan or internet ADSP-21MOD870 functions host functions ? multi-dsp control and overlay management ? service 32 dsps/host ? data packetizing ? v.34/56k modem ? v.17 fax ? v.42, v.42bis, mnp2-5 dtmf dialing hdlc protocol caller id figure 3. network access system clkin clkout xtal dsp figure 4. external crystal connections
ADSP-21MOD870 C8C rev. 0 reset the reset signal initiates a master reset of the adsp- 21mod870. the reset signal must be asserted during the power-up sequence to assure proper initialization. reset during initial power-up must be held long enough to allow the internal clock to stabilize. if reset is activated any time after power-up, the clock continues to run and does not require stabilization time. the power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid v dd is ap- plied to the processor, and for the internal phase-locked loop (pll) to lock onto the specific crystal frequency. a minimum of 2000 clkin cycles ensures that the pll has locked but does not include the crystal oscillator start-up time. during this pow er-up sequence the reset signal should be held low. on any subsequent resets, the reset signal must meet the minimum pulsewidth specification, t rsp . the reset input contains some hysteresis; however, if you use an rc circuit to generate your reset signal, the use of an external schmidt trigger is recommended. the master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the mstat register. when reset is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is p erformed. the first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. table ii. modes of operation 1 mode d 2 mode c 3 mode b 4 mode a 5 booting method x 0 0 0 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in full memory mode. 6 x010no automatic boot operations occur. program execution starts at external memory location 0. chip is configured in full memory mode. bdma can still be used but the processor does not automatically use or wait for these operations. 0100 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode. iack has active pull-down. (requires additional hardware). 0101i dma feature is used to load any internal memory as desired. program ex- ecution is held off until internal program memory location 0 is written to. chip is configured in host mode. 6 iack has active pull-down. 1100 bdma feature is used to load the first 32 program memory words from the byte memory space. program execution is held off until all 32 words have been loaded. chip is configured in host mode; iack requires external pull- down. (requires additional hardware). 1101i dma feature is used to load any internal memory as desired. program ex- ecution is held off until internal program memory location 0 is written to. chip is configured in host mode. iack requires external pull-down. 6 notes 1 all mode pins are recognized while reset is active (low). 2 when mode d = 0 and in host mode, iack is an active, driven signal and cannot be wire ored. when mode d = 1 and in host mode, iack is an open source and requires an external pull-down, multiple iack pins can be wire ored together. 3 when mode c = 0, full memory mode enabled. when mode c = 1, host memory mode enabled. 4 when mode b = 0, auto booting enabled. when mode b = 1, no auto booting. 5 when mode a = 0, bdma enabled. when mode a = 1, idma enabled. 6 considered standard operating settings. using these configurations allows for easier design and better memory management. modes of operation table ii summarizes the ADSP-21MOD870 memory modes. setting memory mode the ADSP-21MOD870 uses the mode c pin to make a memory mode selection during chip reset. this pin is multiplexed with the processors pf2 pin, so exercise care when selecting a mode. the two methods for selecting the value of mode c are active and passive. passive configuration uses a pull-up or pull-down resistor connected to the mode c pin. to minimize power consump- tion, or if the pf2 pin is used as an output in the dsp applica- tion, use a weak pull-up or pull-down, on the order of 100 k w . this value should be sufficient to pull the pin to the desired level and still let the pin operate as a programmable flag output without undue strain on the processors output driver. for mini- mum power consumption during power-down, reconfigure pf2 as an input, as the pull-up or pull-down will hold the pin in a known state, and will not switch. active configuration uses a three-statable external driver con- nected to the mode c pin. a drivers output enable should be connected to the processors reset signal so it only drives the pf2 pin when reset is active (low). when reset is de-as- serted, the driver should three-state, allowing the pf2 pin to be an input or output. to minimize power consumption during power-down, configure the programmable flag as an output when connected to a three-stated buffer. this ensures that the pin is
ADSP-21MOD870 C9C rev. 0 program memory (full memory mode) is a 24-bit space for storing both instruction op codes and data. the ADSP-21MOD870 has 32k words of program memory ram on chip, and the capability of accessing up to two 8k external memory overlay spaces using the external data bus. table iii. pmovlay bits pmovlay memory a13 a12:0 0, 4, 5 internal not applicable not applicable 1 external 0 13 lsbs of address overlay 1 between 0x2000 and 0x3fff 2 external 1 13 lsbs of address overlay 2 1 between 0x2000 and 0x3fff data memory the data memory map is shown in figure 6. held at a constant level and will not oscillate if the three-state drivers level hovers around the logic switching point. memory architecture the ADSP-21MOD870 provides a variety of memory and pe- ripheral interface options. the key functional groups are pro- gram memory, data memory, byte memory and i/o. refer to the following figures and tables for pm and dm memory alloca- tions in the ADSP-21MOD870. program memory the program memory map is shown in figure 5. accessible when pmovlay = 2 accessible when pmovlay = 1 accessible when pmovlay = 5 8k internal pmovlay = 0 8k external program memory mode b = 1 address 0x3fff 0x2000 0x1fff 0x0000 8k internal pmovlay = 0, 4, 5 or 8k external pmovlay = 1, 2 0x3fff 0x2000 0x1fff 8k internal 0x0000 program memory mode b = 0 address always accessible at address 0x0000 C 0x1fff accessible when pmovlay = 0 accessible when pmovlay = 4 internal memory external memory 0x2000C 0x3fff 0x2000C 0x3fff 0x2000C 0x3fff 0x2000C 0x3fff 2 0x2000C 0x3fff 2 pm mode b=0 accessible when pmovlay = 1 reserved reserved internal memory external memory 0x2000C 0x3fff 0x0000C 0x1fff 2 pm (mode b=1) 1 reserved 1 when mode = 1, pmovlay must be set to 0 2 see table iii for pmovlay bits accessible when pmovlay = 0 reserved figure 5. program memory accessible when dmovlay = 2 accessible when dmovlay = 1 accessible when dmovlay = 5 32 memory mapped registers 0x3fff 0x2000 0x1fff internal 8160 words 0x0000 data memory address 8k internal dmovlay = 0, 4, 5 or external 8k dmovlay = 1, 2 0 x3fe0 0x3fdf always accessible at address 0x2000 C 0x3fff accessible when dmovlay = 0 accessible when dmovlay = 4 internal memory external memory 0 x2000C 0x1fff 0x0000C 0x1fff 0x0000C 0x1fff 0x0000C 0x1fff 0x0000C 0x1fff data memory figure 6. data memory map program memory (host mode) allows access to all internal memory. external overlay access is limited by a single external address line (a0). external program execution is not available in host mode due to a restricted data bus that is 16 bits wide only. the pmovlay bits are defined in table iii.
ADSP-21MOD870 C10C rev. 0 data memory (full memory mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. the ADSP-21MOD870 has 32k words on data memory ram on chip, consisting of 16,352 user-acces sible locations and 32 memory-mapped registers. support also exists for up to two 8k external memory overlay spaces through the external data bus. all internal accesses complete in one cycle. accesses to external memory are timed using the wait states specified by the dwait register. data memory (host mode) allows access to all internal memory. e xternal overlay access is limited by a single external address line (a0). the dmovlay bits are defined in table iv. table iv. dmovlay bits dmovlay memory a13 a12:0 0, 4, 5 internal not applicable not applicable 1 external 13 lsbs of address overlay 1 0 between 0x2000 and 0x3fff 2 external 13 lsbs of address overlay 2 1 between 0x2000 and 0x3fff i/o space (full memory mode) the ADSP-21MOD870 supports an additional external memory space called i/o space. this space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface asic data registers. i/o space supports 2048 locations of 16-bit-wide data. the lower eleven bits of the external address bus are used; the upper 3 bits are undefined. two instructions were added to the core adsp- 2100 family instruction set to read from and write to i/o memory space. the i/o space also has four dedicated three-bit wait state registers, iowait0-3, which specify up to seven wait states to be automatically generated for each of four regions. the wait states act on address ranges as shown in table v. table v. wait states address range wait state register 0x000C0x1ff iowait0 0x200C0x3ff iowait1 0x400C0x5ff iowait2 0x600C0x7ff iowait3 composite memory select ( cms ) the ADSP-21MOD870 has a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. the cms signal is generated to have the same timing as each of the individual memory select signals ( pms , dms , bms , ioms ) but can com- bine their functionality. each bit in the cmssel register, when set, causes the cms signal to be asserted when the selected memory select is as- serted. for example, to use a 32k word memory to act as both program and data memory, set the pms and dms bits in the cmssel register and use the cms pin to drive the chip select of the memory, and use either dms or pms as the additional address bit. the cms pin functions like the other memory select signals with the same timing and bus request logic. a 1 in the enable bit causes the assertion of the cms signal at the same time as the selected memory select signal. all enable bits default to 1 at reset, except bms . boot memory select ( bms ) disable the ADSP-21MOD870 lets you boot the processor from one external memory space while using a different external memory space for bdma transfers during normal operation. you can use the cms to select the first external memory space for bdma transfers and bms to select the second external space for booting. the bms signal can be disabled by setting bit 3 of the system control register to 1. the system control register is illustrated in figure 7. 00 0 0 01 00 00 0 00 1 1 1 15 14 13 12 11 10 987654321 0 dm (0x3fff) system control register sport0 enable 1 = enabled, 0 = disabled sport1 enable 1 = enabled, 0 = disabled sport1 configure 1 = serial port 0 = fi , fo , irq0 , irq1 , sclk pwait program memory wait states bms enable 0 = enabled, 1 = disabled figure 7. system control register byte memory the byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. byte memory is accessed using the bdma feature. the byte memory space consists of 256 pages, each of which is 16k 8. the byte memory space on the ADSP-21MOD870 supports read and write operations as well as four different data formats. the byte memory uses data bits 15:8 for data. the byte memory uses data bits 23:16 and address bits 13:0 to create a 22-bit address. this allows up to a 4 meg 8 (32 megabit) rom or ram to be used without glue logic. all byte memory accesses are timed by the bmwait register. byte memory dma (bdma, full memory mode) the byte memory dma controller allows loading and storing of program instructions and data using the byte memory space. the bdma circuit is able to access the byte memory space while the processor is operating normally and steals only one processor cycle per 8-, 16- or 24-bit word transferred. bdma control bmpage bdma overlay bits btype bdir 0 = load from bm 1 = store to bm bcr 0 = run during bdma 1 = halt during bdma 0000000000001000 1514131211109876543210 dm (0x3fe3) figure 8. bdma control register the bdma circuit supports four different data formats which are selected by the btype register field. the appropriate num- ber of 8-bit accesses are done from the byte memory space to build the word size selected. table vi shows the data formats supported by the bdma circuit.
ADSP-21MOD870 C11C rev. 0 unused bits in the 8-bit data memory formats are filled with 0s. the biad register field is used to specify the starting address for the on-chip memory involved with the transfer. the 14-bit bead register specifies the starting address for the external byte memory space. the 8-bit bmpage register specifies the start- ing page for the external byte memory space. the bdir register field selects the direction of the transfer. finally the, 14-bit bwcount register specifies the number of dsp words to transfer and initiates the bdma circuit transfers. table vi. data formats internal btype memory space word size alignment 00 program memory 24 full word 01 data memory 16 full word 10 data memory 8 msbs 11 data memory 8 lsbs bdma accesses can cross page boundaries during sequential addressing. a bdma interrupt is generated on the completion of the number of transfers specified by the bwcount register. the bwcount register is updated after each transfer so it can be used to check the status of the transfers. when it reaches zero, the transfers have finished and a bdma interrupt is generated. the bmpage and bead registers must not be accessed by the processor during bdma operations. the source or destination of a bdma transfer will always be on-chip program or data memory. when the bwcount register is written with a nonzero value, the bdma circuit starts executing byte memory accesses with wait states set by bmwait. these accesses continue until the count reaches zero. when enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. the transfer takes one processor cycle. processor accesses to external memory have priority over bdma byte memory accesses. the bdma context reset bit (bcr) controls whether the processor is held off while the bdma accesses are occurring. setting the bcr bit to 0 allows the processor to continue opera- tions. setting the bcr bit to 1 causes the processor to stop execution while the bdma accesses are occurring, to clear the context of the processor, and start execution at address 0 when the bdma accesses have completed. the bdma overlay bits specify the ovlay memory blocks to be accessed for internal memory. internal memory dma port (idma port; host memory mode) the idma port provides an efficient means of communication between a host system and the ADSP-21MOD870. the port is used to access the on-chip program memory and data memory of the processor with only one processor cycle per word over- head. the idma port cannot be used, however, to write to the processors memory-mapped control registers. a typical idma transfer process is described as follows: 1. host starts idma transfer. 2. host checks iack control line to see if the processor is busy. 3 . host uses is and ial control lines to latch either the dma starting address (idmaa) or the pm/dm ovlay selection into the processors idma control registers. if iad[15] = 1, the value of iad[7:0] represents the idma overlay: bits 14:8 must be set to 0. if iad[15] = 0, the value of iad[13:0] represents the start- ing address of internal memory to be accessed and iad[14] reflects pm or dm for access. 4 . host uses is and ird (or iwr ) to read (or write) processor internal memory (pm or dm). 5 . host checks iack line to see if the processor has completed the previous idma operation. 6. host ends idma transfer. the idma port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. the idma port is com- pletely asynchronous and can be written to while the adsp- 21mod870 is operating at full speed. the processor memory address is latched and is then automati- cally incremented after each idma transaction. an external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. this increases throughput as the address does not have to be sent for each memory access. idma port access occurs in two phases. the first is the idma address latch cycle. when the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. the address specifies an on-chip memory location; the destination type specifies whether it is a dm or pm access. the falling edge of the address latch signal latches this value into the idmaa register. once the address is stored, data can then be either read from, or written to, the ADSP-21MOD870s on-chip memory. asserting the select line ( is ) and the appropriate read or write line ( ird and iwr respectively) signals the ADSP-21MOD870 that a par- ticular transaction is required. in either case, there is a one- processor-cycle delay for synchronization. the memory access consumes one additional processor cycle. once an access has occurred, the latched address is automati- cally incremented, and another access can occur. through the idmaa register, the processor can also specify the starting address and data format for dma operation. asserting the idma port select ( is ) and address latch enable (ial) directs the ADSP-21MOD870 to write the address onto the iad[14:0] bus into the idma control register. if iad[15] is set to 0, idma latches the address. if iad[15] is set to 1, idma latches o vlay memory. this register, shown below, is memory mapped at address dm (0x3fe0). note that the latched address (idmaa) cannot be read back by the host.
ADSP-21MOD870 C12C rev. 0 figure 9 shows the idma control and ovlay registers, fig- ure 10 shows the bus usage during idma transfers, and figure 11 shows the dma memory maps. idma control (u = undefined at reset) dm(0x3fe0) idmaa address idmad destination memory type: 0 = pm 1 = dm idma overlay dm(0x3fe7) reserved set to 0 id dmovlay id pmovlay 000000000000000 1514131211109876543210 uuuuuuuuuuuuuuu 1514131211109876543210 figure 9. idma control/ovlay registers (iad 15C0) 0 = pm 1 = dm 1 0000000 dm page pm page 1514131211109876543210 page latch 0 address address latch page and address latch (iad 15C0) data lower byte 1514131211109876543210 dm 16-bit idma data write/input data upper byte data middle byte pm 24-bit data upper byte data lower byte ignored 1st transfer 2nd transfer (iad 15C0) data lower byte 1514131211109876543210 dm 16-bit idma data read/output data upper byte data middle byte pm 24-bit data upper byte data lower byte 0 0000000 1st transfer 2nd transfer figure 10. bus usage during idma transfers accessible when pmovlay = 5 always accessible at address 0x0000 C 0x 1fff accessible when pmovlay = 0 accessible when pmovlay = 4 0x2000C 0x3fff 0x2000C 0x3fff 0x2000C 0x3fff dma program memory ovlay note: idma and bdma have separate dma control registers accessible when dmovlay = 5 always accessible at address 0x2000 C 0x 3fff accessible when dmovlay = 0 accessible when dmovlay = 4 0x0000C 0x1fff 0x0000C 0x1fff 0x0000C 0x1fff dma data memory ovlay figure 11. direct memory access-pm and dm memory maps bootstrap loading (booting) the ADSP-21MOD870 has two mechanisms to allow automatic loading of the internal program memory after reset. the method for booting is controlled by the mode a, b and c configuration bits. when the mode pins specify bdma booting, the adsp- 21mod870 initiates a bdma boot sequence when reset is released. the bdma interface is set up during reset to the following defaults when bdma booting is specified: the bdir, bmp age, biad and bead registers are set to 0, the btype register is set to 0 to specify program memory 24-bit words, and the bwcount register is set to 32. this causes 32 words of on- chip program memory to be loaded from byte memory. these 32 words are used to set up the bdma to load in the remaining program code. the bcr bit is also set to 1, which causes pro- gram execution to be held off until all 32 words are loaded into on-chip program memory. execution then begins at address 0. the adsp-2100 family development software (revision 5.02 and later) fully supports the bdma booting feature and can generate boot code compatible with byte memory space. the idle instruction can also be used to allow the processor to hold off execution while booting continues through the bdma interface. for bdma accesses while in host mode, the ad- dresses to boot memory must be constructed externally to the ADSP-21MOD870. the only memory address bit provided by the processor is a0. idma port booting the ADSP-21MOD870 can also boot programs through its in- ternal dma port. if mode c = 1, mode b = 0, and mode a = 1, the ADSP-21MOD870 boots from the idma port. idma feature can load as much on-chip memory as desired. program execution is held off until data is written to on-chip program memory location 0. bus request and bus grant the ADSP-21MOD870 can relinquish control of the data and address buses to an external device. when the external device requires access to memory, it asserts the bus request ( br ) signal. if the ADSP-21MOD870 is not performing an external memory access, it responds to the active br input in the follow- ing processor cycle by: ? three-stating the data and address buses and the pms , dms , bms , cms , ioms , rd , wr output drivers, ? asserting the bus grant ( bg ) signal and ? halting program execution. if go mode is enabled, the ADSP-21MOD870 will not halt pro- gram execution until it encounters an instruction that requires an external memory access. if the ADSP-21MOD870 is performing an external memory access when the external device asserts the br signal, it will not three- state the memory interfaces or assert the bg signal until the processor cycle after the access completes. the instruction does not need to be completed when the bus is granted. if a single instruction requires two external memory accesses, the bus will be granted between the two accesses.
ADSP-21MOD870 C13C rev. 0 when the br signal is released, the processor releases the bg signal, reenables the output drivers and continues program execution from the point at which it stopped. the bus request feature operates at all times, including when the processor is booting and when reset is active. the bgh pin is asserted when the ADSP-21MOD870 is ready to execute an instruction but is stopped because the external bus is already granted to another device. the other device can release the bus by deasserting bus request. once the bus is released, the ADSP-21MOD870 deasserts bg and bgh and executes the external memory access. flag i/o pins the ADSP-21MOD870 has eight general purpose programmable input/output flag pins. they are controlled by two memory map- ped registers. the pftype register determines the direction, 1 = output and 0 = input. the pfdata register is used to read and write the values on the pins. data being read from a pin configured as an input is synchronized to the ADSP-21MOD870s clock. bits that are programmed as outputs will read the value being output. the pf pins default to input during reset. in addition to the programmable flags, the ADSP-21MOD870 has five fixed-mode flags, flag_in, flag_out, fl0, fl1, and fl2. fl0-fl2 are dedicated output flags. flag_in and flag_out are available as an alternate configuration of sport1. note: pins pf0, pf1, pf2 and pf3 are also used for device configuration during reset. instruction set description the ADSP-21MOD870 assembly language instruction set has an algebraic syntax that was designed for ease of coding and read- ability. the assembly language, which takes full advantage of the processors unique architecture, offers the following ben- efits: ? the algebraic syntax eliminates the need to remember cryptic assembler mnemonics. for example, a typical arithmetic add instruction, such as ar = ax0 + ay0, resembles a simple equation. ? every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. ? the syntax is a superset adsp-2100 family assembly lan- guage and is completely source and object code compatible with other family members. programs may need to be relo- cated to utilize on-chip memory and conform to the adsp- 21mod870s interrupt vector and reset vector map. ? sixteen condition codes are available. for conditional jump, call, return or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. ? multifunction instructions allow parallel execution of an arithmetic instruction with up to two fetches or one write to processor memory space during a single instruction cycle. designing an ez-ice-compatible system the ADSP-21MOD870 has on-chip emulation support and an ice-port, a special set of pins that interface to the ez-ice. these features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the ez-ice. target systems must have a 14-pin connector to accept the ez-ices in-circuit probe, a 14- pin plug. see the adsp-2100 family ez-tools data sheet for complete information on ice products. issuing the chip reset command during emulation causes the dsp processor to perform a full chip reset, including a reset of its memory mode. therefore, it is vital that the mode pins are set correctly prior to issuing a chip reset command from the emu- lator user interface. as the mode pins share functionality with pf0:2 (and pf3 on the ADSP-21MOD870), it may be necessary to reset the target hardware separately to insure the proper mode selection state on emulator chip reset. if you are using a passive method of maintaining mode informa- tion (as discussed in the setting memory modes section), it does not matter that mode information is latched by an emula- tor reset. however, if you are using the reset pin as a method of setting the value of the mode pins, then you must consider the effects of an emulator reset. one method of ensuring that the values located on the mode pins is correct is to construct a circuit like the one shown below. this circuit will force the value located on the mode a pin to zero, regardless of whether it latched via the reset or ereset pin. ereset reset mode a/pfo programmable i/o 1k v figure 12. reset , ereset circuit see the adsp-2100 family ez-tools data sheet for complete information on ice products. the ice-port interface consists of the following ADSP-21MOD870 pins: ebr ems elin ebg eint elout ereset eclk ee these ADSP-21MOD870 pins must be connected only to the ez- ice connector in the target system. these pins have no function except during emulation, and do not require pull-up or pull- down resistors. the traces for these signals between the adsp- 21mod870 and the connector must be kept as short as possible, no longer that three inches. the following pins are also used by the ez-ice: br reset bg gnd the ez-ice uses the ee (emulator enable) signal to take control of the ADSP-21MOD870 in the target system. this causes the processor to use its ereset , ebr and ebg pins instead of the reset , br and bg pins. the bg output is three-stated. these signals do not need to be jumper-isolated in your system.
ADSP-21MOD870 C14C rev. 0 the ez-ice connects to your target system via a ribbon cable and a 14-pin female plug. the ribbon cable is ten inches long with one end fixed to the ez-ice. the female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. target board connector for ez-ice probe the ez-ice connector (a standard pin strip header) is shown in figure 13. you must add this connector to your target board design if you intend to use the ez-ice. be sure to allow enough room in your system to fit the ez-ice probe onto the 14-pin connector. the 14-pin, 2-row pin strip header is keyed at the pin 7 loca- tionyou must remove pin 7 from the header. the pins must be 0.025 inch square and at least 0.20 inch in length. pin spacing should be 0.1 0.1 inches. the pin strip header must have at least 0.15 inch clearance on all sides to accept the ez-ice probe plug. pin strip headers are available from vendors such as 3m, mckenzie and samtec. target memory interface for your target system to be compatible with the ez-ice emu- lator, it must comply with the memory interface guidelines listed below. 12 34 56 78 910 11 12 13 14 gnd key (no pin) reset br bg top view ebg ebr elout ee eint elin eclk ems ereset figure 13. target board connector for ez-ice pm, dm, bm, iom and cm design your program memory (pm), data memory (dm), byte memory (bm), i/o memory (iom), and composite memory (cm) external interfaces to comply with worst case device tim- ing requirements and switching characteristics as specified in this data sheet. the performance of the ez-ice may approach published worst case specification for some memory access timing requirements and switching characteristics. note: if your target does not meet the worst case chip specifica- tion for memory access parameters, you may not be able to emulate your circuitry at the desired clkin frequency. de- pending on the severity of the specification violation, you may have trouble manufacturing your system as processor compo- nents statistically vary in switching characteristic and timing requirements within published limits. restriction: all memory strobe signals on the ADSP-21MOD870 (rd , wr , pms , dms , bms , cms and ioms ) used in your target system must have 10 k w pull-up resistors connected when the ez-ice is being used. the pull-up resistors are necessary because there are no internal pull-ups to guarantee their state during prolonged three-state conditions resulting from typical ez-ice debugging sessions. these resistors may be removed at your option when the ez-ice is not being used. target system interface signals when the ez-ice board is installed, the performance on some system signals changes. design your system to be compatible with the following system interface signal changes introduced by the ez-ice board: ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the reset signal. ? ez-ice emulation introduces an 8 ns propagation delay between your target circuitry and the processor on the br signal. ? ez-ice emulation ignores reset and br when single- stepping. ? ez-ice emulation ignores reset and br when in emulator space (processor halted). ? ez-ice emulation ignores the state of target br in certain modes. as a result, the target system may take control of the processors external memory bus only if bus grant ( bg ) is asserted by the ez-ice boards processor.
C15C rev. 0 ADSP-21MOD870 recommended operating conditions k grade parameter min max unit v dd 3.15 3.45 v t amb 0 +70 c electrical characteristics k/b grades parameter test conditions min typ max unit v ih hi-level input voltage 1, 2 @ v dd = max 2.0 v v ih hi-level clkin voltage @ v dd = max 2.2 v v il lo-level input voltage 1, 3 @ v dd = min 0.8 v v oh hi-level output voltage 1, 4, 5 @ v dd = min i oh = C0.5 ma 2.4 v @ v dd = min i oh = C100 m a 6 v dd C 0.3 v v ol lo-level output voltage 1, 4, 5 @ v dd = min i ol = 2 ma 0.4 m a i ih hi-level input current 3 @ v dd = max v in = v dd max 10 m a i il lo-level input current 3 @ v dd = max v in = 0 v 10 m a i ozh three-state leakage current 7 @ v dd = max v in = v dd max 8 10 m a i ozl three-state leakage current 7 @ v dd = max v in = 0 v 8 , t ck = 25 ns 10 m a i dd supply current (idle) 9 @ v dd = 3.3 t ck = 19 ns 10 10 ma t ck = 25 ns 10 8ma t ck = 30 ns 10 7ma i dd supply current (dynamic) 11 @ v dd = 3.3 t amb = +25 c t ck = 19 ns 10 51 ma t ck = 25 ns 10 41 ma t ck = 30 ns 10 34 ma c i input pin capacitance 3, 6, 12 @ v in = 2.5 v, f in = 1.0 mhz, 8 pf t amb = +25 c c o output pin capacitance 6, 7, 12, 13 @ v in = 2.5 v, f in = 1.0 mhz, t amb = +25 c8pf notes 1 bidirectional pins: d0-d23, rfs0, rfs1, sclk0, sclk1, tfs0, tfs1, a1Ca13, pf0Cpf7. 2 input only pins: reset , br , dr0, dr1, pwd . 3 input only pins: clkin, reset , br , dr0, dr1, pwd . 4 output pins: bg , pms , dms , bms , ioms , cms , rd , wr , pwdack, a0, dt0, dt1, clkout, fl2-0, bgh . 5 although specified for ttl outputs, all ADSP-21MOD870 outputs are cmos-compatible and will drive to v dd and gnd, assuming no dc loads. 6 guaranteed but not tested. 7 three-statable pins: a0Ca13, d0Cd23, pms , dms , bms , ioms , cms , rd , wr , dt0, dt1, sclk0, sclk1, tfs0, tfs1, rfs0, rsf1, pf0Cpf7. 8 0 v on br . 9 idle refers to ADSP-21MOD870 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 10 v in = 0 v and 3 v. for typical figures for supply currents, refer to power dissipation section. 11 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 12 applies to lqfp package type. 13 output pin capacitance is the capacitive load for any three-stated output pin. specifications subject to change without notice. specifications
ADSP-21MOD870 C16C rev. 0 warning! esd sensitive device esd sensitivity the ADSP-21MOD870 is an esd (electrostatic discharge) sensitive device. electrostatic charges readily accumulate on the human body and equipment and can discharge without detection. permanent damage may occur to devices subjected to high energy electrostatic discharges. the ADSP-21MOD870 features proprietary esd protection circuitry to dissipate high energy discharges (human body model) per method 3015 of mil-std-883. proper esd precautions are recommended to avoid performance degradation or loss of functionality. unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination before devices are removed. absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +4.6 v input voltage . . . . . . . . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v output voltage swing . . . . . . . . . . . . . C0.5 v to v dd + 0.5 v operating temperature range (ambient) . . C40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (5 sec) lqfp . . . . . . . . . . . . . . . . +280 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. these are stress ratings only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. timing parameters general notes use the exact timing information given. do not attempt to derive parameters from the addition or subtraction of others. while addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. consequently, you cannot meaningfully add up parameters to derive longer times. timing notes switching characteristics specify how the processor changes its signals. you have no control over this timingcircuitry external to the processor must be designed for compatibility with these signal characteristics. switching characteristics tell you what the processor will do in a given circumstance. you can also use switching characteristics to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. timing requirements guarantee that the proces- sor operates correctly with other devices. memory timing specifications the table below shows common memory device specifications and the corresponding ADSP-21MOD870 timing parameter. adsp- memory 21mod870 timing device timing parameter specification parameter definition address setup to t asw a0Ca13, xms setup write start before wr low address setup to t aw a0Ca13, xms setup write end before wr deasserted address hold time t wra a0Ca13, xms hold before wr low data setup time t dw data setup before wr high data hold time t dh data hold after wr high oe to data valid t rdd rd low to data valid address access time t aa a0Ca13, xms to data valid note: xms = pms , dms , bms , cms , ioms . frequency dependency for timing specifications t ck is defined as 0.5 t cki . the ADSP-21MOD870 uses an input clock with a frequency equal to half the instruction rate: a 26 mhz input clock (which is equivalent to 38 ns) yields a 19 ns processor cycle (equivalent to 52 mhz). t ck values within the range of 0.5 t cki period should be substituted for all relevant tim- ing param eters to obtain the specification value. example: t ckh = 0.5 t ck C 7 ns = 0.5 (19 ns) C 7 ns = 2.5 ns environmental conditions ambient temperature rating: t amb =t case C (pd q ca ) t case = case temperature in c pd = power dissipation in w q ca = thermal resistance (case-to-ambient) q ja = thermal resistance (junction-to-ambient) q jc = thermal resistance (junction-to-case) package u ja u jc u ca lqfp 50 c/w 2 c/w 48 c/w
ADSP-21MOD870 C17C rev. 0 output drive currents figure 14 shows typical i-v characteristics for the output driv- ers of the adsp -21mod870. the curves represent the current drive ca pability of the output drivers as a function of output voltage. source voltage C v 80 C40 0 4.0 source current C ma 0.5 1.0 1.5 2.0 3.0 3.5 60 C20 C60 C80 40 0 20 3.0v, +85 c 3.3v, +25 c 3.6v, C40 c 3.0v, +85 c 3.3v, +25 c 3.6v, C40 c 2.5 figure 14. typical drive currents power dissipation to determine total power dissipation in a specific application, the following equation should be applied for each output: c v dd 2 f c = load capacitance, f = output switching frequency. example in an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: assumptions ? external data memory is accessed every cycle with 50% of the address pins switching. ? external data memory writes occur every other cycle with 50% of the data pins switching. ? each address and data pin has a 10 pf total load at the pin. ? the application operates at v dd = 3.3 v and t ck = 30 ns. total power dissipation = p int + ( c v dd 2 f ) p int = internal power dissipation from power vs. frequency graph (figure 15). ( c v dd 2 f ) is calculated for each output: # of pins 3 c 3 v dd 2 3 f address, dms 8 10 pf 3.3 2 v 33.3 2 mhz = 29.0 mw data output, wr 9 10 pf 3.3 2 v 16.67 mhz = 16.3 mw rd 1 10 pf 3.3 2 v 16.67 mhz = 1.8 mw clkout 1 10 pf 3.3 2 v 33.3 mhz = 3.6 mw 50.7 mw total power dissipation for this example is p int + 50.7 mw. 1/t ck C mhz 250 150 33.3 52 100 200 50 0 21mod870 power, internal 1, 3, 4 v dd = 3.6v v dd = 3.3v v dd = 3.0v 216mw 168.3mw 132mw 144mw 112.2mw 87mw 1/f ck C mhz 45 25 10 33.3 52 40 20 15 35 30 5 0 power, idle 1, 2, 3 v dd = 3.6v v dd = 3.3v v dd = 3.0v 35mw 30mw 25mw 23mw 21mw 1/f ck C mhz 45 15 33.3 25 20 35 30 10 5 0 power, idle n modes 3 52 idle idle (16) idle (128) 13mw 12mw 23mw 10mw 9mw valid for all temperature grades. 1 power reflects device operating with no output loads. 2 idle refers to ADSP-21MOD870 state of operation during execution of idle instruction. deasserted pins are driven to either v dd or gnd. 3 typical power dissipation at 3.3v v dd and +25 8 c, except where specified. 4 i dd measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions. 40 32mw 32mw figure 15. power vs. frequency
ADSP-21MOD870 C18C rev. 0 capacitive loading figures 16 and 17 show the capacitive loading characteristics of the ADSP-21MOD870. c l C pf rise time (0.4v C 2.4v) C ns 0 0 200 50 100 150 18 16 12 8 4 t = +85 c v dd = 30v 250 14 10 6 2 figure 16. typical output rise time vs. load capacitance, c l (at maximum ambient operating temperature) c l C pf 10 1 0 20.0 20 80 120 160 9 6 4 2 nominal 8 7 5 3 C1 C2 valid output delay or hold C ns C3 C4 40 60 100 140 180 figure 17. typical output valid delay or hold vs. load capacitance, c l (at maximum ambient operating temperature) 1.5v input or output 1.5v figure 18. voltage reference levels for ac measure- ments (except output enable/disable) test conditions output disable time output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. the out- put disable time (t dis ) is the difference of t measured and t decay . the time is the interval from when a reference signal reaches a high or low voltage level to w hen the output voltages have changed by 0.5 v from the measured output high or low voltage, see figure 19. the decay time, t decay , is dependent on the capacitive load, c l , and the current load, i l , on the output pin. it can be approxi- mated by the following equation: t decay = c l 0.5 v i l from which t dis = t measured C t decay is calculated. if multiple pins (such as the data bus) are dis- abled, the measurement value is that of the last pin to stop driving. output enable time output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. the output enable time (t ena ) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, see figure 19. if multiple pins (such as the data bus) are enabled, the mea- surement value is that of the first pin to start driving. figure 20 shows the equivalent device loading for ac measurements. 2.0v 1.0v t ena reference signal output t decay v oh (measured) output stops driving output starts driving t dis t measured v ol (measured) v oh (measured) C 0.5v v ol (measured) +0.5v high-impedance state. test conditions cause this voltage level to be approximately 1.5v. v oh (measured) v ol (measured) figure 19. output enable/disable to output pin 50pf +1.5v i oh i ol figure 20. equivalent device loading for ac measure- ments (including all fixtures)
ADSP-21MOD870 C19C rev. 0 timing parameters parameter min max unit clock signals and reset timing requirements : t cki clkin period 38 100 ns t ckil clkin width low 15 ns t ckih clkin width high 15 ns switching characteristics: t ckl clkout width low 0.5 t ck C 7 ns t ckh clkout width high 0.5 t ck C 7 ns t ckoh clkin high to clkout high 0 20 ns control signals timing requirements : t rsp reset width low 5 t ck 1 ns t ms mode setup before reset high 2 ns t mh mode setup after reset high 5 ns note 1 applies after power-up sequence is complete. internal phase lock loop requires no more than 2000 clkin cycles assuming stable c lkin (not including crystal oscillator start-up time). t ckoh t cki t ckih t ckil t ckh t ckl t mh t ms clkin clkout pf(3:0) * reset * pf3 is mode d , pf2 is mode c, pf1 is mode b, pf0 is mode a t rsp figure 21. clock signals
ADSP-21MOD870 C20C rev. 0 timing parameters parameter min max unit interrupts and flags timing requirements : t ifs irqx , fi, or pfx setup before clkout low 1, 2, 3, 4 0.25 t ck + 15 ns t ifh irqx , fi, or pfx hold after clkout high 1, 2, 3, 4 0.25 t ck ns switching characteristics : t foh flag output hold after clkout low 5 0.25 t ck C 7 ns t fod flag output delay from clkout low 5 0.5 t ck + 6 ns notes 1 if irqx and fi inputs meet t ifs and t ifh setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on t he following cycle. (refer to interrupt controller operation in the program control chapter of the adsp-2100 family users manual, third edition, for further information on interrupt servicing.) 2 edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 irqx = irq0 , irq1 , irq2 , irql0 , irql1 , irqe . 4 pfx = pf0, pf1, pf2, pf3, pf4, pf5, pf6, pf7. 5 flag outputs = pfx, fl0, fl1, fl2, flag_out. t fod t foh t ifs clkout flag outputs irq x fi pfx t ifh figure 22. interrupts and flags
ADSP-21MOD870 C21C rev. 0 parameter min max unit bus requestCbus grant timing requirements : t bh br hold after clkout high 1 0.25 t ck + 2 ns t bs br setup before clkout low 1 0.25 t ck + 17 ns switching characteristics : t sd clkout high to xms , rd , wr disable 0.25 t ck + 10 ns t sdb xms , rd , wr disable to bg low 0 ns t se bg high to xms , rd , wr enable 0 ns t sec xms , rd , wr enable to clkout high 0.25 t ck C 4 ns t sdbh xms , rd , wr disable to bgh low 2 0ns t seh bgh high to xms , rd , wr enable 2 0ns notes xms = pms , dms , cms , ioms , bms . 1 br is an asynchronous signal. if br meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recogniz ed on the following cycle. refer to the adsp-2100 family users manual, third edition, for br / bg cycle relationships. 2 bgh is asserted when the bus is granted and the processor requires control of the bus to continue. clkout t sd t sdb t se t sec t sdbh t seh t bs br t bh clkout pms , dms bms , rd wr bg bgh figure 23. bus requestCbus grant
ADSP-21MOD870 C22C rev. 0 timing parameters parameter min max unit memory read timing requirements : t rdd rd low to data valid 0.5 t ck C 9 + w ns t aa a0Ca13, xms to data valid 0.75 t ck C 12.5 + w ns t rdh data hold from rd high 0 ns switching characteristics : t rp rd pulsewidth 0.5 t ck C 5 + w ns t crd clkout high to rd low 0.25 t ck C 5 0.25 t ck + 7 ns t asr a0Ca13, xms setup before rd low 0.25 t ck C 6 ns t rda a0Ca13, xms hold after rd deasserted 0.25 t ck C 3 ns t rwr rd high to rd or wr low 0.5 t ck C 5 ns w = wait states t ck . xms = pms , dms , cms , ioms , bms . clkout a0 C a13 d t rda t rwr t rp t asr t crd t rdd t aa t rdh dms , pms , bms , ioms , cms rd wr figure 24. memory read
ADSP-21MOD870 C23C rev. 0 parameter min max unit memory write switching characteristics : t dw data setup before wr high 0.5 t ck C 7 + w ns t dh data hold after wr high 0.25 t ck C 2 ns t wp wr pulsewidth 0.5 t ck C 5 + w ns t wde wr low to data enabled 0 ns t asw a0Ca13, xms setup before wr low 0.25 t ck C 6 ns t ddr data disable before wr or rd low 0.25 t ck C 7 ns t cwr clkout high to wr low 0.25 t ck C 5 0.25 t ck + 7 ns t aw a0Ca13, xms , setup before wr deasserted 0.75 t ck C 9 + w ns t wra a0Ca13, xms hold after wr deasserted 0.25 t ck C 3 ns t wwr wr high to rd or wr low 0.5 t ck C 5 ns w = wait states t ck . xms = pms , dms , cms , ioms , bms . clkout a0Ca13 d t wp t aw t cwr t dh t wde t dw t asw t wwr t wra t ddr dms , pms , bms , cms , ioms rd wr figure 25. memory write
ADSP-21MOD870 C24C rev. 0 timing parameters parameter min max unit serial ports timing requirements : t sck sclk period 38 ns t scs dr/tfs/rfs setup before sclk low 4 ns t sch dr/tfs/rfs hold after sclk low 7 ns t scp sclk in width 15 ns switching characteristics : t cc clkout high to sclk out 0.25 t ck 0.25 t ck + 10 ns t scde sclk high to dt enable 0 ns t scdv sclk high to dt valid 15 ns t rh tfs/rfs out hold after sclk high 0 ns t rd tfs/rfs out delay from sclk high 15 ns t scdh dt hold after sclk high 0 ns t tde tfs (alt) to dt enable 0 ns t tdv tfs (alt) to dt valid 14 ns t scdd sclk high to dt disable 15 ns t rdv rfs (multichannel, frame delay zero) to dt valid 15 ns clkout sclk tfs out rfs out dt alternate frame mode t cc t cc t scs t sch t rh t scde t scdh t scdd t tde t rdv multichannel mode, frame delay 0 (mfd = 0) dr tfs in rfs in rfs out tfs out t tdv t scdv t rd t scp t sck t scp tfs in rfs in alternate frame mode t rdv multichannel mode, frame delay 0 (mfd = 0) t tdv t tde figure 26. serial ports
ADSP-21MOD870 C25C rev. 0 parameter min max unit idma address latch timing requirements : t ialp duration of address latch 1, 2 10 ns t iasu iad15C0 address setup before address latch end 2 5ns t iah iad15C0 address hold after address latch end 2 2ns t ika iack low before start of address latch 2, 3 0ns t ials start of write or read after address latch end 1, 2 3ns t iald address latch start after address latch end 1, 2 2ns notes 1 start of address latch = is low and ial high. 2 end of address latch = is high or ial low. 3 start of write or read = is low and iwr low or ird low. iack ial is iad15C0 ird or iwr t ika t ialp t iald t iasu t iah t iasu t ials t iah t ialp figure 27. idma address latch
ADSP-21MOD870 C26C rev. 0 timing parameters parameter min max unit idma write, short write cycle timing requirements : t ikw iack low before start of write 1 0ns t iwp duration of write 1, 2 15 ns t idsu iad15C0 data setup before end of write 2, 3, 4 5ns t idh iad15C0 data hold after end of write 2, 3, 4 2ns switching characteristics : t ikhw start of write to iack high 4 15 ns notes 1 start of write = is low and iwr low. 2 end of write = is high or iwr high. 3 if write pulse ends before iack low, use specifications t idsu , t idh . 4 if write pulse ends after iack low, use specifications t iksu , t ikh . iad15C0 data t ikhw t ikw t idsu iack t iwp t idh is iwr figure 28. idma write, short write cycle
ADSP-21MOD870 C27C rev. 0 parameter min max unit idma write, long write cycle timing requirements : t ikw iack low before start of write 1 0ns t iksu iad15C0 data setup before iack low 2, 3, 4 0.5 t ck + 10 ns t ikh iad15C0 data hold after iack low 2, 3, 4 2ns switching characteristics : t iklw start of write to iack low 4 1.5 t ck ns t ikhw start of write to iack high 4 15 ns notes 1 start of write = is low and iwr low. 2 if write pulse ends before iack low, use specifications t idsu , t idh . 3 if write pulse ends after iack low, use specifications t iksu , t ikh . 4 this is the earliest time for iack low from start of write. for idma write cycle relationships, please refer to the adsp-2100 family users manual, third edition . iad15C0 data t ikhw t ikw iack is iwr t iklw t ikh t iksu figure 29. idma write, long write cycle
ADSP-21MOD870 C28C rev. 0 parameter min max unit idma read, short read cycle timing requirements : t ikr iack low before start of read 1 0ns t irp duration of read 15 ns switching characteristics : t ikhr iack high after start of read 1 415ns t ikdh iad15C0 data hold after end of read 2 0ns t ikdd iad15C0 data disabled after end of read 2 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 10 ns notes 1 start of read = is low and ird low. 2 end of read = is high or ird high. t irp t ikr previous data t ikhr t irdv t ikdd t irde t ikdh iad15C0 iack is ird figure 30. idma read, short read cycle
ADSP-21MOD870 C29C rev. 0 timing parameters parameter min max unit idma read, long read cycle timing requirements : t ikr iack low before start of read 1 0ns t irk end of read after iack low 2 2ns switching characteristics : t ikhr iack high after start of read 1 415ns t ikds iad15C0 data setup before iack low 0.5 t ck C 7 ns t ikdh iad15C0 data hold after end of read 3 0ns t ikdd iad15C0 data disabled after end of read 3 10 ns t irde iad15C0 previous data enabled after start of read 0 ns t irdv iad15C0 previous data valid after start of read 10 ns t irdh1 iad15C0 previous data hold after start of read (dm/pm1) 2 2 t ck C 5 ns t irdh2 iad15C0 previous data hold after start of read (pm2) 4 t ck C 5 ns notes 1 start of read = is low and ird low. 2 dm read or first half of pm read. 3 end of read = is high or ird high. 4 second half of pm read. t ikr previous data read data t ikhr t ikds t irdv t irdh t ikdd t irde t ikdh iad15C0 iack is ird t irk figure 31. idma read, long read cycle
ADSP-21MOD870 C30C rev. 0 100-lead lqfp package pinout 5 4 3 2 7 6 9 8 1 56 71 72 73 74 69 70 67 68 65 66 60 61 62 63 58 59 57 54 55 64 52 53 51 75 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 identifier top view (not to scale) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 d19 d18 d17 d16 irqe +pf4 irql0 +pf5 gnd irql1 +pf6 dt0 tfs0 sclk0 v dd dt1/fo tfs1/irq1 rfs1/irq0 dr1/fi gnd sclk1 ereset reset d15 d14 d13 d12 gnd d11 d10 d9 v dd gnd d8 d7/ iwr d6/ ird d5/ial d4/ is gnd v dd d3/ iack d2/iad15 d1/iad14 d0/iad13 bg ebg br ebr a4/iad3 a5/iad4 gnd a6/iad5 a7/iad6 a8/iad7 a9/iad8 a10/iad9 a11/iad10 a12/iad11 a13/iad12 gnd clkin xtal v dd clkout gnd v dd wr rd bms dms pms ioms cms ADSP-21MOD870 irq2 +pf7 rfs0 dr0 ems ee elout eclk elin eint a3/iad2 a2/iad1 a1/iad0 a0 pwdack bgh fl0 fl1 fl2 d23 d22 d21 d20 gnd pf1 [mode b] gnd pwd v dd pf0 [mode a] pf2 [mode c] pf3 [mode d]
ADSP-21MOD870 C31C rev. 0 lqfp pin configurations lqfp pin lqfp pin lqfp pin lqfp pin number name number name number name number name 1 a4/ iad3 26 irqe + pf4 51 ebr 76 d16 2 a5/ iad4 27 irql0 + pf5 52 br 77 d17 3 gnd 28 gnd 53 ebg 78 d18 4 a6/ iad5 29 irql1 + pf6 54 bg 79 d19 5 a7/ iad6 30 irq2 + pf7 55 d0/ iad13 80 gnd 6 a8/ iad7 31 dt0 56 d1/ iad14 81 d20 7 a9/ iad8 32 tfs0 57 d2/ iad15 82 d21 8 a10/ iad9 33 rfs0 58 d3/ iack 83 d22 9 a11/ iad10 34 dr0 59 v dd 84 d23 10 a12/ iad11 35 sclk0 60 gnd 85 fl2 11 a13/ iad12 36 v dd 61 d4/ is 86 fl1 12 gnd 37 dt1/fo 62 d5/ ial 87 fl0 13 clkin 38 tfs1/irq1 63 d6/ ird 88 pf3 [mode d] 14 xtal 39 rfs1/ irq0 64 d7/ iwr 89 pf2 [mode c] 15 v dd 40 dr1/fi 65 d8 90 v dd 16 clkout 41 gnd 66 gnd 91 pwd 17 gnd 42 sclk1 67 v dd 92 gnd 18 v dd 43 ereset 68 d9 93 pf1 [mode b] 19 wr 44 reset 69 d10 94 pf0 [mode a] 20 rd 45 ems 70 d11 95 bgh 21 bms 46 ee 71 gnd 96 pwdack 22 dms 47 eclk 72 d12 97 a0 23 pms 48 elout 73 d13 98 a1/ iad0 24 ioms 49 elin 74 d14 99 a2/ iad1 25 cms 50 eint 75 d15 100 a3/ iad2 the ADSP-21MOD870 package pinout is shown in the table below. pin names in bold text replace the plain text named functions when mode c = 1. a + sign separates two functions when either function can be active for either major i/o mode. signals enclose d in brackets [ ] are state bits latched from the value of the pin at the deassertion of reset .
ADSP-21MOD870 C32C rev. 0 c3340C2C2/99 printed in u.s.a. ordering guide ambient instruction temperature rate package package part number range (mhz) description option ADSP-21MOD870-000 0 c to +70 c 52.0 plastic thin quad flatpack (lqfp) st-100 outline dimensions dimensions shown in inches and (mm). 100-lead metric thin plastic quad flatpack (lqfp) (st-100) seating plane 0.030 (0.75) 0.024 (0.60) typ 0.020 (0.50) 0.063 (1.60) max 12 typ 0.007 (0.177) 0.005 (0.127) typ 0.003 (0.077) 6 8 4 8 0 8 C 7 8 0.004 (0.102) max lead coplanarity top view (pins down) 1 25 26 51 50 75 100 76 0.011 (0.27) 0.009 (0.22) typ 0.007 (0.17) 0.640 (16.25) 0.630 (16.00) 0.620 (15.75) typ sq 0.020 (0.50) bsc lead pitch 0.555 (14.10) 0.551 (14.00) 0.547 (13.90) typ sq lead width note: the actual position of each lead is within 0.0032 (0.08) from its ideal position when measured in the lateral direction. center figures are typical unless otherwise noted.

▲Up To Search▲

Price & Availability of ADSP-21MOD870

	To Download ADSP-21MOD870 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .