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asynchronous sram 64k x 16 x 2 sram +3.3v supply, two chip enables revolutionary pinout gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , inc. galvantech, inc. reserves the right to chang e products or specifications without notice . rev. 1/9 9 galvantech, inc. 3080 oakmead village drive, santa clara, ca 9505 1 tel (408) 566-0688 fax (408) 566-069 9 web site: http://www.galvantech.co m feature s ? fast access times: 10, 12, and 15n s ? fast oe# access times: 5, 6, and 7n s ? single +3.3v + 0.3v power suppl y ? fully static -- no clock or timing strobes necessar y ? all inputs and outputs are ttl-compatibl e ? three state output s ? center power and ground pins for greater noise immunit y ? easy memory expansion with ce# and oe# option s ? automatic ce# power dow n ? high-performance, low-power consumption, cmos triple-poly, double-metal proces s ? packaged in 44-pin, 400-mil tsop and 44-pin tqf p option s markin g ? timin g 10ns access -10 12ns access -12 15ns access -1 5 ? package s 44-pin tsop (400 mil) t s 44-pin tqfp t ? power consumptio n standard non e ? temperatur e commercial none ( 0 c to 70c ) general descriptio n the gvt73128s16 is organized as a 65,536 x 16 x 2 sram using a four-transistor memory cell with a high performance, silicon gate, low-power cmos process. galvantech srams are fabricated using triple-layer polysilicon, double-layer metal technology . this device consists of two banks of 64k x 16 memory. each bank of memory has its own chip enable pin and the highest order address. memory bank a has cea# and a15a as its chip enable and high order address. memory bank b has ceb# and a15b as its chip enable and high order address. the other low order addresses (a0 to a14) along with the write enable (we#) and output enable (oe#) are shared by both memory banks . this device offers center power and ground pins for improved performance and noise immunity. static design eliminates the need for external clocks or timing strobes. for increased system flexibility and eliminating bus contention problems, this device offers chip enables (cea# and ceb#) and output enable (oe#) with this organization . writing to these devices is accomplished when write enable (we#) and chip enables (cea# and/or ceb#) inputs are both low. reading is accomplished when (cea# or ceb#) and (oe#) go low with (we#) remaining high . the device offers a low power standby mode when both banks of memory are not selected. this allows system designers to meet low standby power requirements .
january 22, 199 9 2 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , functional block diagra m pin assignmen t address buffer row decoder column decoder memory array 256 rows x 256 x 16 columns i/o control we# oe# dq16 dq1 a14 a0 cea# vcc vss a15a ceb# address buffer row decoder column decoder memory array 256 rows x 256 x 16 columns i/o control a14 a0 a15b 1 2 3 4 5 6 7 8 9 10 32 31 30 29 28 27 26 25 24 23 19 20 21 11 12 13 14 15 16 22 18 17 a6 a7 dq12 dq11 ceb# a8 a9 a10 a11 oe# nc dq16 dq15 vss vcc a15a a15b dq3 dq4 we# a1 a14 a13 a12 a0 cea# dq1 dq2 vcc vss a5 a3 pin assignment 44-pin tsop 33 34 35 36 a4 nc nc 41 42 43 44 37 38 39 40 dq7 dq8 dq5 dq6 dq10 dq9 dq14 dq13 a2 1 2 3 4 5 27 26 25 24 23 6 7 8 9 10 11 dq12 dq11 ceb# dq16 dq15 vss vcc dq3 dq4 cea# dq1 dq2 vcc vss pin assignment 44-pin tqfp 28 29 30 31 32 33 dq7 dq8 dq5 dq6 dq10 dq9 dq14 dq13 a10 a9 oe# nc a11 nc 36 37 38 39 34 35 a14 a15b a15a a13 a12 41 42 43 44 40 nc a5 a6 a7 a4 a8 20 19 18 17 22 21 we# a0 a1 a2 a3 15 14 13 12 16
january 22, 199 9 3 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , truth table pin description s mod e cea # ceb # we # oe # dq1- dq1 6 powe r bank a memory rea d l h h l q activ e bank b memory rea d h l h l q activ e bank a memory writ e l h l x d activ e bank b memory writ e h l l x d activ e both bank memory writ e l l l x d activ e output disabl e l h h h high- z activ e h l h h high- z activ e standb y h h x x high- z standb y tqfp pin number s tsop pin number s symbo l typ e descriptio n 13-17, 19-22, 37-41, 4 4 5, 19, 18, 2, 1, 44, 43, 42, 27, 26, 25, 24, 22, 21, 2 0 a0-a1 4 inpu t low order addresses inputs: these inputs, along with the high order address, determine which cell is addressed . 4 2 3 a15 a inpu t high order addresses input: this input, along with a0-a14, determine which cell of bank a memory is addressed . 4 3 4 a15 b inpu t high order addresses input: this input, along with a0-a14, determine which cell of bank b memory is addressed . 1 2 1 7 we # inpu t write enable: this input determines if the cycle is a read or write cycle. we# is low for a write cycle and high for a read cycle . 1 6 cea # inpu t bank a enable: this active low input is used to enable bank a of the device. when cea# is low, bank a of the chip is selected. when cea# is high, bank a of the chip is disabled . 2 3 2 8 ceb # inpu t bank b enable: this active low input is used to enable bank b of the device. when ceb# is low, bank b of the chip is selected. when ceb# is high, bank b of the chip is disabled . 3 6 4 1 oe # inpu t output enable: this active low input enables the output drivers . 2, 3, 4, 5, 8, 9, 10, 11, 24,25, 26, 27, 30, 31, 32, 3 3 7, 8, 9, 10, 13, 14, 15, 16, 29, 30, 31, 32, 35, 36, 37, 3 8 dq1-dq1 6 input/outpu t sram data i/o: data inputs and data outputs . 6, 2 8 11, 3 3 vc c suppl y power supply: 3.3v + 0.3 v 7, 2 9 12, 3 4 vs s suppl y groun d 18, 34, 3 5 23, 39, 4 0 n c - n0 connect: these signals are not internally connected .
absolute maximum ratings * voltage on vcc supply relative to vss........-0.5v to +4.6 v v in ..........................................................-0.5v to vcc+1.0 v storage temperature (plastic) ..........................-5 5 o c to +12 5 o junction temperature .....................................................+12 5 o power dissipation ...........................................................1.0 w short circuit output current .......................................50m a *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device.this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . january 22, 199 9 4 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , dc electrical characteristics and recommended operating condition s (all temperature ranges; vcc = 3.3v + 0.3v unless otherwise noted ) capacitanc e descriptio n condition s symbo l mi n ma x unit s note s input high (logic 1) voltag e v i h 2. 2 vcc+0. 5 v 1, 2 input low (logic 0) voltag e v i l -0. 5 0. 8 v 1, 2 input leakage curren t 0v < v i n < vc c i l i - 5 5 u a output leakage curren t output(s) disabled, 0 v < v ou t < vc c i l o - 5 5 u a output high voltag e i o h = -4.0m a v o h 2. 4 v 1 output low voltag e i o l = 8.0m a v o l 0. 4 v 1 supply voltag e vc c 3. 0 3. 6 v 1 descriptio n condition s sy m ty p powe r -1 0 -1 2 -1 5 unit s note s power supply current: operatin g device selected; cea# or ceb# < v i l ; vcc =max; f= f ma x ; outputs ope n ic c 7 0 standar d 23 0 20 0 17 0 m a 3, 1 4 lo w 21 0 18 0 15 0 ttl standb y cea# and ceb# > v i h ; vcc = max; f= f ma x i sb 1 1 0 standar d 3 5 3 0 2 5 m a 1 4 lo w 3 0 2 5 2 0 cmos standb y cea# and ceb# > vcc -0. 2 ; vcc = max ; all other inputs < vss +0.2 or > vcc -0.2; all inputs static; f= 0 i sb 2 0.0 2 standar d 1 0 1 0 1 0 m a 1 4 lo w 1. 5 1. 5 1. 5 descriptio n condition s symbo l ma x unit s note s input capacitanc e t a = 2 5 o c; f = 1 mh z vcc = 3.3 v c i 6 p f 4 input/output capacitance (dq ) c i/ o 8 p f 4
january 22, 199 9 5 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , ac electrical characteristics (note 5) (all temperature ranges; vcc = 3.3 v + 0.3v ) descriptio n - 1 0 - 1 2 - 1 5 sy m mi n ma x mi n ma x mi n ma x unit s note s read cycl e read cycle tim e t r c 1 0 1 2 1 5 n s address access tim e t a a 1 0 1 2 1 5 n s chip enable access tim e t ac e 1 0 1 2 1 5 n s output hold from address chang e t o h 3 3 3 n s chip enable to output in low- z t lzc e 3 4 4 n s 4, 7 chip disable to output in high- z t hzc e 5 6 7 n s 4, 6, 7 output enable access tim e t ao e 5 6 7 n s output enable to output in low- z t lzo e 0 0 0 n s output enable to output in high- z t h z o e 5 6 7 n s 4, 6 chip enable to power-up tim e t p u 0 0 0 n s 4 chip disable to power-down tim e t p d 1 0 1 2 1 5 n s 4 write cycl e write cycle tim e t w c 1 0 1 2 1 5 n s chip enable to end of writ e t c w 8 8 9 n s address valid to end of write, with oe# hig h t a w 8 8 9 n s address setup tim e t a s 0 0 0 n s address hold from end of writ e t a h 0 0 0 n s write pulse widt h t wp 2 1 0 1 0 1 1 n s write pulse width, with oe# hig h t wp 1 8 8 9 n s data setup tim e t d s 5 6 7 n s data hold tim e t d h 0 0 0 n s write disable to output in low- z t lzw e 3 4 5 n s 4, 7 write enable to output in high- z t hzw e 5 6 7 n s 4, 6, 7
ac test condition s input pulse level s 0v to 3.0v input rise and fall time s 1.5ns input timing reference level s 1.5v output reference level s 1.5v output loa d see figures 1 and 2 output load s vt = 1.5v 30 pf dq z 0 = 50 w fig. 1 output load equivalent 50 w dq 3.3v 317 w 351 w fig. 2 output load equivalent 5 pf january 22, 199 9 6 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , note s 1. all voltages referenced to vss (gnd) . 2. overshoot: v i h +6.0v for t t rc /2 . undershoot: v i l -2.0v for t t rc / 2 3. i c c is given with no output current. i c c increases with greater output loading and faster cycle times . 4. this parameter is sampled . 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted . 6. output loading is specified with c l =5pf as in fig. 2. transition is measured + 500mv from steady state voltage . 7. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe . 8. we# is high for read cycle . 9. device is continuously selected. chip enable and output enables are held in their active state . 10. address valid prior to, or coincident with, latest occurring chip enable . 11. t r c = read cycle time . 12. chip enable and write enable can initiate and terminate a write cycle . 13. capacitance derating applies to capacitance different from the load capacitance shown in fig. 1. 14. typical values are measured at 3.3v, 2 5 o c and 20ns cycle time .
january 22, 199 9 7 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , read cycle no. 1 (8, 9 ) read cycle no. 2 (7, 8, 10, 12 ) addr valid t rc data valid t oh t aa previous data valid q ce# t rc data valid t lzce t ace oe# high z t aoe t lzoe t hzce t hzoe q undefined don't care
january 22, 199 9 8 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , write cycle no. 1 (7, 12, 13 ) (write enable controlled with output enable oe# active low) ) write cycle no. 2 (12, 13 ) (write enable controlled with output enable oe# inactive high ) addr t wc t ah t ds data valid ce# we# d q t dh t wp2 t as t aw t cw high z t hzwe t lzwe addr t wc t ah t ds data valid high z ce# we# d q t dh t wp1 t as t aw t cw undefined don't care
january 22, 199 9 9 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , write cycle no. 3 (12, 13 ) (chip enable controlled ) note: ce# goes to low means cea# or ceb# goes to low, namely, ce#=cea#*ceb# . addr t wc t ah t ds don't care data valid ce# we# d q t dh t wp1 t as t aw t cw high z
january 22, 199 9 1 0 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , package dimension s note: all dimensions in inches (millimeters) .741 (18.81) .721 (18.31) .402 (10.21) .398 (10.11) pin #1 index .0315 (0.80) typ .018 (0.45) .010 (0.25) max min or typical, max where noted. seating plane .008 (0.20) .002 (0.05) .007 (0.18) .005 (0.12) .467 (11.86) .459 (11.66) 44-pin 400 mil plastic tsop (ts) .047 (1.20) max .032 (0.80) .024 (0.60) .016 (0.40)
january 22, 199 9 1 1 galvantech, inc. reserves the right to change products or specifications without notice . rev. 1/9 9 gvt73128s16 revolutionary pinout 64k x 16 x 2 galvantec h , 44-pin tqfp package dimension s ordering informatio n gv t 73128s1 6 x x - x x x x pin 1 note: all dimensions in millimeters 0.37 typ. 0.80 typ. 1.40 + 0.05 1.65 max 0.60 + 0.15 10.00 + 0.10 8.00 typ. 12.00 + 0.15 10.00 + 0.10 8.00 typ. 12.00 + 0.15 1.00 typ. galvantech prefi x part numbe r package (t = 44 pin tqfp, speed (10=10ns, 12=12ns, 15= 15ns) ts = tsop type ii) temperature (blank = commercial) power (blank= standard)

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