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16mb lw r-r and r-r w/ ls, rev 1.0 1 / 25 october 18, 2001 CXK77Q36B160GB sony 28/33/4 16mb lw ls r-r hstl high speed synchronous sram (512k x 36) preliminary description features ? 3 speed bins cycle time / access time -28 2.8ns / 1.5ns -33 3.3ns / 1.6ns -4 4.0ns / 1.8ns ? single 2.5v power supply (v dd ): 2.5v 5% ? dedicated output supply voltage (v ddq ): 1.5v typical ? hstl-compatible i/o interface with dedicated input reference voltage (v ref ): 0.75v typical ? register - register (r-r) read protocol ? late write (lw) write protocol ? conventional or late select (ls) mode of operation, selectable via dedicated mode pin (m2) ? full read/write coherency ? byte write capability ? two cycle deselect ? differential input clocks (k/ k ) ? asynchronous output enable ( g ) ? programmable output driver impedance ? sleep (power down) mode via dedicated mode pin (zz) ? jtag boundary scan (subset of ieee standard 1149.1) ? 119 pin (7x17), 1.27mm pitch, 14mm x 22mm ball grid array (bga) package the CXK77Q36B160GB is a high speed cmos synchronous static ram with common i/o pins, organized as 524,288 words by 36 bits. this synchronous sram integrates input registers, high speed ram, output registers, and a one-deep write buffer onto a single monolithic ic. register - register (r-r) read operations and late write (lw) write operations are supported, pro- viding a high-performance user interface. two distinct r-r modes of operation are supported, selectable via the m2 mode pin. when m2 is ?high?, this device functions as a conventional r-r sram, and pin 4p functions as a conventional sa address input. when m2 is ?low?, this device functions as a late select (ls) r-r sram, and pin 4p functions as a late select sas address input. when late select r-r mode is selected, the sram is divided into two banks internally. during write operations, sas is reg- istered in the same cycle as the other address and control signals, and is used to select to which bank input data is ultimately written (through one stage of write pipelining). during read operations, sas is registered one full clock cycle after the other address and control signals, and is used to select from which bank output data is read. all address and control input signals except g (output enable) and zz (sleep mode) are registered on the rising edge of k (input clock). during read operations, output data is driven valid from the rising edge of k, one full clock cycle after all address and contro l input signals (except sas) are registered. during write operations, input data is registered on the rising edge of k, one full clock cycle after all address and control in put signals (including sas) are registered. output drivers are series terminated, and output impedance is programmable via the zq input pin. by connecting an external control resistor rq between zq and v ss , the impedance of all data output drivers can be precisely controlled. sleep (power down) mode control is provided through the asynchronous zz input. 350 mhz operation is obtained from a single 2.5v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 2 / 25 october 18, 2001 pin assignment (top view) notes: 1. pad locations 2t and 6t are true no-connects. however, they are defined as sa address inputs in x18 lw srams. 2. pad location 6u must be left unconnected. it is used by sony for internal test purposes. 3. pad location 3r is defined as an m1 mode pin in lw srams. however, it must be tied ?low? in this device. 4. pad location 5r is defined as an m2 mode pin in this device. it must be tied ?high? or ?low?. when m2 is tied ?high?, this device functions as a conventional r-r sram. when m2 is tied ?low?, this device functions as a late select r-r sram. 5. pad location 4p is defined as an sa address input in lw srams. however, it functions as a conventional sa ad- dress input in this device only when m2 is tied ?high?. it functions as a late select sas address input in this device when m2 is tied ?low?. 1 2 3 4 5 6 7 a v ddq sa sa nc sa sa v ddq b nc sa sa nc sa sa nc c nc sa sa v dd sa sa nc d dqc dqc v ss zq v ss dqb dqb e dqc dqc v ss ss v ss dqb dqb f v ddq dqc v ss g v ss dqb v ddq g dqc dqc sbw c nc sbw b dqb dqb h dqc dqc v ss nc v ss dqb dqb j v ddq v dd v ref v dd v ref v dd v ddq k dqd dqd v ss k v ss dqa dqa l dqd dqd sbw d k sbw a dqa dqa m v ddq dqd v ss sw v ss dqa v ddq n dqd dqd v ss sa v ss dqa dqa p dqd dqd v ss sa / sas (5) v ss dqa dqa r nc sa m1 (3) v dd m2 (4) sa nc t nc nc (1) sa sa sa nc (1) zz u v ddq tms tdi tck tdo rsvd (2) v ddq
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 3 / 25 october 18, 2001 pin description symbol type description sa input synchronous address inputs - registered on the rising edge of k. sas input synchronous late select address input (late select r-r mode only) - registered on the rising edge of k. sampled one cycle after the other address and control inputs during read operations. sampled in the same cycle as the other address and control inputs during write operations. dqa, dqb dqc, dqd i/o synchronous data inputs / outputs - registered on the rising edge of k during write operations. driven from the rising edge of k during read operations. dqa - indicates data byte a dqb - indicates data byte b dqc - indicates data byte c dqd - indicates data byte d k, k input differential input clocks ss input synchronous select input - registered on the rising edge of k. ss = 0 specifies a write operation when sw = 0 specifies a read operation when sw = 1 ss = 1 specifies a deselect operation sw input synchronous global write enable input - registered on the rising edge of k. sw = 0 specifies a write operation when ss = 0 sw = 1 specifies a read operation when ss = 0 sbw a, sbw b, sbw c, sbw d input synchronous byte write enable inputs - registered on the rising edge of k. sbw a = 0 specifies write data byte a when ss = 0 and sw = 0 sbw b = 0 specifies write data byte b when ss = 0 and sw = 0 sbw c = 0 specifies write data byte c when ss = 0 and sw = 0 sbw d = 0 specifies write data byte d when ss = 0 and sw = 0 g input asynchronous output enable input - deasserted (high) disables the data output drivers. zz input asynchronous sleep mode input - asserted (high) forces the sram into low-power mode. m1 input read operation protocol select 1 - this mode pin must be tied ?low? at power-up to select reg- ister - register read operations m2 input read operation protocol select 2 - this mode pin must be tied ?high? or ?low? at power-up. m2 = 0 selects late select r-r functionality m2 = 1 selects conventional r-r functionality zq input output impedance control resistor input - this pin must be connected to v ss through an exter- nal resistor rq to program data output driver impedance. see the programmable output driver impedance section for further information. v dd 2.5v core power supply - core supply voltage. v ddq output power supply - output buffer supply voltage. v ref input reference voltage - input buffer threshold voltage. v ss ground tck input jtag clock tms input jtag mode select - weakly pulled ?high? internally. tdi input jtag data in - weakly pulled ?high? internally. tdo output jtag data out rsvd reserved - this pin is used for sony test purposes only. it must be left unconnected. nc no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd , v ddq , or v ss .
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 4 / 25 october 18, 2001 ? clock truth table ? dynamic m2 mode pin state changes although m2 is defined as a static input (that is, it must be tied ?high? or ?low? at power-up), in some instance (such as during device testing) it may be desirable to change its state dynamically (that is, without first powering off the sram) while preserving the contents of the memory array. if so, the following criteria must be met: 1. at least two (2) consecutive deselect operations must be initiated prior to changing the state of m2, to ensure that the most recent read or write operation completes successfully. 2. at least thirty-two (32) consecutive deselect operations must be initiated after changing the state of m2 before any read or write operations can be initiated, to allow the sram sufficient time to recognize the change in state. ? sleep (power down) mode sleep (power down) mode is provided through the asynchronous input signal zz. when zz is asserted (high), the output drivers will go to a hi-z state, and the sram will begin to draw standby current. contents of the memory array will be preserved. an enable time (t zze ) must be met before the sram is guaranteed to be in sleep mode, and a recovery time (t zzr ) must be met before the sram can resume normal operation. ? programmable output driver impedance this device has programmable impedance output drivers. the output impedance is controlled by an external resistor rq connected between the sram?s zq pin and v ss , and is equal to one-fifth the value of this resistor, nominally. see the dc electrical characteristics section for further information. output driver impedance power-up requirements output driver impedance will reach the programmed value within 8192 cycles after power-up. consequently, it is recom- mended that read operations not be initiated until after the initial 8192 cycles have elapsed. output driver impedance updates output driver impedance is updated during write and deselect operations when the output driver is disabled. ? power-up sequence for reliability purposes, sony recommends that power supplies power up in the following sequence: v ss , v dd , v ddq , v ref , and inputs. v ddq should never exceed v dd . if this power supply sequence cannot be met, a large bypass diode may be required between v dd and v ddq . please contact sony memory application department for further information. k zz ss (t n ) sw (t n ) sbw x (t n ) g operation dq (t n ) dq (t n+1 ) x h x x x x sleep (power down) mode hi - z hi - z l ? h l h x x x deselect x hi - z l ? h l l h x h read hi - z hi - z l ? h l l h x l read x q(t n ) l ? h l l l l x write all bytes x d(t n ) l ? h l l l x x write bytes with sbw x = l x d(t n ) l ? h l l l h x abort write x hi - z
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 5 / 25 october 18, 2001 ? absolute maximum ratings (1) (1) stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. ? bga package thermal characteristics ? i/o capacitance (t a = 25 o c, f = 1 mhz) note: these parameters are sampled and are not 100% tested. parameter symbol rating units supply voltage v dd -0.5 to +3.0 v output supply voltage v ddq -0.5 to +2.3 v input voltage (address, control, data, clock) v in -0.5 to v ddq + 0.5 (2.3v max) v input voltage (m1, m2) v min -0.5 to v dd + 0.5 (3.0v max) v input voltage (tck, tms, tdi)) v tin -0.5 to +3.8 v operating temperature t a 0 to 85 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c parameter symbol rating units junction to case temperature q jc 1.0 c/w parameter symbol test conditions min max units input capacitance address c in v in = 0v --- 4.2 pf control c in v in = 0v --- 4.2 pf clock c kin v kin = 0v --- 3.5 pf output capacitance data c out v out = 0v --- 4.8 pf
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 6 / 25 october 18, 2001 ? dc recommended operating conditions ( v ss = 0v , t a = 0 to 85 o c) 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component. 2. v ih (max) ac = v ddq + 0.75v for pulse widths less than one-quarter of the cycle time (t cyc /4). 3. v il (min) ac = -0.75v for pulse widths less than one-quarter of the cycle time (t cyc /4). parameter symbol min typ max units notes supply voltage v dd 2.37 2.5 2.63 v output supply voltage v ddq 1.4 1.5 1.6 v input reference voltage v ref 0.6 0.75 0.9 v 1 input high voltage (address, control, data) v ih v ref + 0.2 --- v ddq + 0.3 v 2 input low voltage (address, control, data) v il -0.3 --- v ref - 0.2 v 3 input high voltage (m1, m2) v mih 1.2 --- v dd + 0.3 v input low voltage (m1, m2) v mil -0.3 --- 0.4 v clock input signal voltage v kin -0.3 --- v ddq + 0.3 v clock input differential voltage v dif 0.2 --- v ddq + 0.6 v clock input common mode voltage v cm 0.6 0.75 0.9 v
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 7 / 25 october 18, 2001 ? dc electrical characteristics (v dd = 2.5v 5%, v ss = 0v, t a = 0 to 85 o c) 1. for maximum output drive (i.e. minimum impedance), the zq pin can be tied directly to v ss . 2. for minimum output drive (i.e. maximum impedance), the zq pin can be left unconnected or tied to v ddq . 3. this parameter is guaranteed by design through extensive corner lot characterization. 4. average power supply operating current in devices marked as ?-33? is guaranteed (by test) to meet both the i dd-33 specification at 300 mhz operation and the i dd-4 specification at 250 mhz operation. parameter symbol test conditions min typ max units notes input leakage current (address, control, clock) i li v in = v ss to v ddq -5 --- 5 ua input leakage current (m1, m2) i mli v min = v ss to v dd -5 --- 5 ua output leakage current i lo v out = v ss to v ddq g = v ih -5 --- 5 ua average power supply operating current i dd-28 i dd-33 i dd-4 i out = 0 ma ss = v il , zz = v il --- --- --- --- --- --- 900 800 700 ma 4 power supply deselect operating current (nop current) i dd2 i out = 0 ma ss = v ih , zz = v il --- --- 300 ma power supply standby current i sb i out = 0 ma zz = v ih --- --- 250 ma output high voltage v oh i oh = -6.0 ma rq = 250 w v ddq - 0.4 --- --- v output low voltage v ol i ol = 6.0 ma rq = 250 w --- --- 0.4 v output driver impedance r out v oh , v ol = v ddq /2 rq < 150 w --- --- 33 (30*1.1) w 1,3 v oh , v ol = v ddq /2 150 w rq 300 w (rq/5)* 0.9 rq/5 (rq/5)* 1.1 w 3 v oh , v ol = v ddq /2 rq > 300 w 54 (60*0.9) --- --- w 2,3
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 8 / 25 october 18, 2001 ? ac electrical characteristics (t a = 0 to 85 o c) all parameters are measured from the mid-point of the object signal to the mid-point of the reference signal, unless otherwise n oted. 1. these parameters are measured from v ref 200mv to the clock mid-point. 2. these parameters are verified through device characterization, and are not 100% tested. 3. these parameters are measured at 50mv from steady state voltage. parameter symbol -28 -33 -4 units notes min max min max min max k cycle time t khkh 2.8 --- 3.3 --- 4.0 --- ns k clock high pulse width t khkl 1.1 --- 1.3 --- 1.5 --- ns k clock low pulse width t klkh 1.1 --- 1.3 --- 1.5 --- ns address / late select setup time t avkh 0.3 --- 0.3 --- 0.3 --- ns 1 address / late select hold time t khax 0.5 --- 0.6 --- 0.7 --- ns write enables setup time t wvkh 0.3 --- 0.3 --- 0.3 --- ns 1 write enables hold time t khwx 0.5 --- 0.6 --- 0.7 --- ns synchronous select setup time t svkh 0.3 --- 0.3 --- 0.3 --- ns 1 synchronous select hold time t khsx 0.5 --- 0.6 --- 0.7 --- ns data input setup time t dvkh 0.3 --- 0.3 --- 0.3 --- ns 1 data input hold time t khdx 0.5 --- 0.6 --- 0.7 --- ns k clock high to output valid t khqv --- 1.5 --- 1.6 --- 1.8 ns k clock high to output hold t khqx 0.7 --- 0.7 --- 0.7 --- ns 2 k clock high to output low-z t khqx1 0.7 --- 0.7 --- 0.7 --- ns 2,3 k clock high to output high-z t khqz 0.7 1.7 0.7 1.8 0.7 2.0 ns 2,3 output enable low to output valid t glqv --- 1.7 --- 1.8 --- 2.0 ns output enable low to output low-z t glqx 0.3 --- 0.3 --- 0.3 --- ns 2,3 output enable high to output high-z t ghqz --- 1.7 --- 1.8 --- 2.0 ns 2,3 sleep mode enable time t zze --- 15 --- 15 --- 15 ns 2 sleep mode recovery time t zzr 20 --- 20 --- 20 --- ns 2
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 9 / 25 october 18, 2001 ? ac test conditions (v dd = 2.5v 5%, v ddq = 1.5v 0.1v, t a = 0 to 85 c ) parameter symbol conditions units notes input reference voltage v ref 0.75 v input high level v ih 1.25 v input low level v il 0.25 v input rise & fall time 2.0 v/ns input reference level 0.75 v clock input high voltage v kih 1.25 v v dif = 1.0v clock input low voltage v kil 0.25 v v dif = 1.0v clock input common mode voltage v cm 0.75 v clock input rise & fall time 2.0 v/ns clock input reference level k/ k cross v output reference level 0.75 v output load conditions rq = 250 w see figure 1 below dq 0.75 v figure 1: ac test output load (v ddq = 1.5v) 50 w 50 w 5 pf 16.7 w 0.75 v 50 w 50 w 5 pf 16.7 w 16.7 w
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 10 / 25 october 18, 2001 conventional r-r mode: timing diagram of read-write-read operations synchronously controlled via ss and deselect operations ( g = low) a4 a6 a7 sa sw g = v il dq q1 d5 d6 q2 q3 d4 t khdx t dvkh a1 q7 read read read deselect deselect write write write read read read figure 2 k k a2 a5 ss t khqx t khqz t khqx1 t khqv t khwx t wvkh sbw x t khax t avkh t khwx t wvkh t khsx t svkh a3 a8 a9 t khkh t klkh t khkl note: in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the application, one deselect operation may be sufficient.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 11 / 25 october 18, 2001 conventional r-r mode: timing diagram of read-write-read operations asynchronously controlled via g and dummy read operations ( ss = low) a4 a6 a7 sa sw g dq q1 d5 d6 q2 q3 d4 a1 q7 read read read read read write write write read read read figure 3 k k a2 a5 ss = v il t khqx t khqz t khqx1 t khqv sbw x a3 t glqx t glqv t ghqz dummy dummy a8 a9 t khdx t dvkh t khwx t wvkh t khax t avkh t khwx t wvkh t khkh t klkh t khkl note: in the diagram above, two dummy read operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the application, one dummy read operation may be sufficient.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 12 / 25 october 18, 2001 a4 a6 a7 sa sw g = v il dq q1 d5 d6 q2 q3 d4 a1 q7 read read read deselect deselect write write write read read read figure 4 k k a2 a5 ss t khwx t wvkh sbw x t khwx t wvkh t khsx t svkh a3 a8 a9 a4 a6 sas a1 a5 t khax t avkh a2 a7 a8 a3 t khdx t dvkh t khqx t khqz t khqx1 t khqv t khax t avkh t khkh t klkh t khkl late select r-r mode: timing diagram of read-write-read operations synchronously controlled via ss and deselect operations ( g = low) note: in the diagram above, two deselect operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the ap- plication, one deselect operation may be sufficient.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 13 / 25 october 18, 2001 late select r-r mode: timing diagram of read-write-read operations asynchronously controlled via g and dummy read operations ( ss = low) a4 a6 a7 sa sw a1 read read read read read write write write read read read figure 5 k k a2 a5 ss = v il sbw x a3 dummy dummy a8 a9 a4 a6 sas a1 a5 a2 a7 a8 a3 g dq q1 d5 d6 q2 q3 d4 q7 t khqx t khqz t khqx1 t khqv t glqx t glqv t ghqz t khdx t dvkh t khwx t wvkh t khwx t wvkh t khax t avkh t khax t avkh t khkh t klkh t khkl note: in the diagram above, two dummy read operations are inserted between read and write operations to control the data bus transition from output to input. this depiction is for clarity purposes only. it is not a requirement. depending on the application, one dummy read operation may be sufficient.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 14 / 25 october 18, 2001 timing diagram of sleep (power-down) mode operation asynchronously controlled via zz k k sa zz dq a1 figure 6 a4 t zzr t zze begin i sb ss q1 a2 a3 q2 sw sbw x deselect read read read read deselect (note 1) (note 2) (note 2) (note 5) (note 5) (note 5) deselect (note 4) (note 3) g = v il sas a3 a2 a1 note 1: this can be any valid operation. the depiction of a read operation here is provided only as an example. note 2: before zz is asserted, at least two (2) deselect operations must be initiated after the last read or write operation is initiated, in order to ensure the successful completion of the last read or write operation. note 3: while zz is asserted, all of the sram?s address, control, data, and clock inputs are ignored. note 4: after zz is deasserted, deselect operations must be initiated until the specified recovery time (t zzr ) has been met. read and write operations may not be initiated during this time. note 5: this can be any valid operation. the depiction of a read operation here is provided only as an example.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 15 / 25 october 18, 2001 ? test mode description this device provides a jtag test access port (tap) and boundary scan interface using a limited set of ieee std. 1149.1 functions. this test mode is intended to provide a mechanism for testing the interconnect between master (processor, con- troller, etc.), srams, other components, and the printed circuit board. in conformance with a subset of ieee std. 1149.1, this device contains a tap controller and four tap registers. the tap registers consist of one instruction register and three data registers (id, bypass, and boundary scan registers). the tap consists of the following four signals: tck: test clock induces (clocks) tap controller state transitions. tms: test mode select inputs commands to the tap controller. sampled on the rising edge of tck. tdi: test data in inputs data serially to the tap registers. sampled on the rising edge of tck. tdo: test data out outputs data serially from the tap registers. driven from the falling edge of tck. disabling the tap when jtag is not used, tck should be tied ?low? to prevent clocking the sram. tms and tdi should either be tied ?high? through a pull-up resistor or left unconnected. tdo should be left unconnected. note: operation of the tap does not interfere with normal sram operation except when the sample-z instruction is selected. consequently, tck, tms, and tdi can be controlled any number of ways without adversely affecting the func- tionality of the device. jtag dc recommended operating conditions (v dd = 2.5v 5%, t a = 0 to 85 c ) jtag ac test conditions (v dd = 2.5v 5%, t a = 0 to 85 c ) parameter symbol test conditions min max units jtag input high voltage v tih --- 1.4 3.6 v jtag input low voltage v til --- -0.3 0.8 v jtag output high voltage (cmos) v toh i toh = -100ua v dd - 0.1 --- v jtag output low voltage (cmos) v tol i tol = 100ua --- 0.1 v jtag output high voltage (ttl) v toh i toh = -4.0ma v dd - 0.4 --- v jtag output low voltage (ttl) v tol i tol = 4.0ma --- 0.4 v jtag input leakage current i tli v tin = 0v to 3.6v -10 10 ua parameter symbol conditions units notes jtag input high level v tih 2.5 v jtag input low level v til 0.0 v jtag input rise & fall time 1.0 v/ns jtag input reference level 1.25 v jtag output reference level 1.25 v jtag output load condition see fig.1 (page 9)
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 16 / 25 october 18, 2001 jtag ac electrical characteristics jtag timing diagram parameter symbol min max unit tck cycle time t thth 100 ns tck high pulse width t thtl 40 ns tck low pulse width t tlth 40 ns tms setup time t mvth 10 ns tms hold time t thmx 10 ns tdi setup time t dvth 10 ns tdi hold time t thdx 10 ns tck low to tdo valid t tlqv 20 ns tck low to tdo hold t tlqx 0 ns figure 7 t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlqv t tlqx tck tms tdi tdi tdo
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 17 / 25 october 18, 2001 tap registers tap registers are serial shift registers that capture serial input data (from tdi) on the rising edge of tck, and drive serial output data (to tdo) on the subsequent falling edge of tck. they are divided into two groups: ?instruction registers?, of which there is one- the instruction register, and ?data registers?, of which there are three - the id register, the bypass register, and the boundary scan register. individual tap registers are ?selected? (inserted between tdi and tdo) when the appropriate sequence of commands is given to the tap controller. instruction register (3 bits) the instruction register stores the instructions that are executed by the tap controller when the tap controller is in the ?run-test / idle? state, or in any of the various ?data register? states. it is loaded with the idcode instruction at power- up, or when the tap controller is in the ?test-logic reset? state or the ?capture-ir? state. it is inserted between tdi and tdo when the tap controller is in the ?shift-ir? state, at which time it can be loaded with a new instruction. how- ever, newly loaded instructions are not executed by the tap controller until the tap controller has reached the ?update- ir? state. the instruction register is 3 bits wide, and is encoded as follows: bit 0 is the lsb of the instruction register, and bit 2 is the msb. when the instruction register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. id register (32 bits) the id register is loaded with a predetermined device- and manufacturer-specific identification code when the idcode instruction has been loaded into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the idcode instruction has been loaded into the instruction register and the tap control- ler is in the ?shift-dr? state. the id register is 32 bits wide, and is encoded as follows: bit 0 is the lsb of the id register, and bit 31 is the msb. when the id register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. code (2:0) instruction description 000 bypass inserts the bypass register between tdi and tdo. 001 idcode inserts the id register between tdi and tdo. 010 sample-z captures the sram?s i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. disables the sram?s data out- put drivers. 011 bypass inserts the bypass register between tdi and tdo. 100 sample captures the sram?s i/o ring contents in the boundary scan register. inserts the boundary scan register between tdi and tdo. 101 private do not use. reserved for manufacturer use only. 110 bypass inserts the bypass register between tdi and tdo. 111 bypass inserts the bypass register between tdi and tdo. revision number (31:28) part number (27:12) sony id (11:1) start bit (0) xxxx 0000 0000 0100 1010 0000 1110 001 1
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 18 / 25 october 18, 2001 bypass register (1 bit) the bypass register is one bit wide, and provides the minimum length serial path between tdi and tdo. it is loaded with a logic ?0? when the bypass instruction has been loaded in the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the bypass instruction has been loaded into the in- struction register and the tap controller is in the ?shift-dr? state. boundary scan register (70 bits) the boundary scan register is equal in length to the number of active signal connections to the sram (excluding the tap pins) plus a number of place holder locations reserved for density and/or functional upgrades. the boundary scan register is loaded with the contents of the sram?s i/o ring when the sample or sample-z instruction has been load- ed into the instruction register and the tap controller is in the ?capture-dr? state. it is inserted between tdi and tdo when the sample or sample-z instruction has been loaded into the instruction register and the tap controller is in the ?shift-dr? state. the boundary scan register contains the following bits: for deterministic results, all signals composing the sram?s i/o ring must meet setup and hold times with respect to tck (same as tdi and tms) when sampled. k/ k are connected to a differential input receiver that generates a single-ended input clock signal to the device. therefore, in order to capture specific values for these signals in the boundary scan register, these signals must be at opposite logic levels when sampled. place holders are required for some nc pins to allow for future density and/or functional upgrades. they are connected to v ss internally, regardless of pin connection externally. the boundary scan register bit order assignment table that follows depicts the order in which the bits from the table above are arranged in the boundary scan register. in the notation, bit 1 is the lsb of the register, and bit 70 is the msb. when the boundary scan register is selected, tdi serially shifts data into the msb, and the lsb serially shifts data out through tdo. dq 36 sa, sas 19 k, k 2 ss , sw , sbw x 6 g , zz 2 m1, m2 2 zq 1 place holder 2
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 19 / 25 october 18, 2001 boundary scan register bit order assignment (by exit sequence) note 1: nc pins at pad locations 4g and 4h are connected to v ss internally, regardless of pin connection externally. bit signal pad bit signal pad 1 m2 5r 36 sa 3b 2 sa / sas 4p 37 sa 2b 3 sa 4t 38 sa 3a 4 sa 6r 39 sa 3c 5 sa 5t 40 sa 2c 6 zz 7t 41 sa 2a 7 dqa 6p 42 dqc 2d 8 dqa 7p 43 dqc 1d 9 dqa 6n 44 dqc 2e 10 dqa 7n 45 dqc 1e 11 dqa 6m 46 dqc 2f 12 dqa 6l 47 dqc 2g 13 dqa 7l 48 dqc 1g 14 dqa 6k 49 dqc 2h 15 dqa 7k 50 dqc 1h 16 sbw a 5l 51 sbw c 3g 17 k 4l 52 zq 4d 18 k 4k 53 ss 4e 19 g 4f 54 nc (1) 4g 20 sbw b 5g 55 nc (1) 4h 21 dqb 7h 56 sw 4m 22 dqb 6h 57 sbw d 3l 22 dqb 7g 58 dqd 1k 24 dqb 6g 59 dqd 2k 25 dqb 6f 60 dqd 1l 26 dqb 7e 61 dqd 2l 27 dqb 6e 62 dqd 2m 28 dqb 7d 63 dqd 1n 29 dqb 6d 64 dqd 2n 30 sa 6a 65 dqd 1p 31 sa 6c 66 dqd 2p 32 sa 5c 67 sa 3t 33 sa 5a 68 sa 2r 34 sa 6b 69 sa 4n 35 sa 5b 70 m1 3r
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 20 / 25 october 18, 2001 tap instructions idcode idcode is the default instruction loaded into the instruction register at power-up, and when the tap controller is in the ?test-logic reset? state. when the idcode instruction is selected, a predetermined device- and manufacturer-specific identification code is load- ed into the id register when the tap controller is in the ?capture-dr? state, and the id register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. normal sram operation is not disrupted when the idcode instruction is selected. bypass when the bypass instruction is selected, a logic ?0? is loaded into the bypass register when the tap controller is in the ?capture-dr? state, and the bypass register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. normal sram operation is not disrupted when the bypass instruction is selected. sample when the sample instruction is selected, the individual logic states of all signals composing the sram?s i/o ring (see the boundary scan register description for the complete list of signals) are loaded into the boundary scan register when the tap controller is in the ?capture-dr? state, and the boundary scan register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. normal sram operation is not disrupted when the sample instruction is selected. sample-z when the sample-z instruction is selected, the individual logic states of all signals composing the sram?s i/o ring (see the boundary scan register description for the complete list of signals) are loaded into the boundary scan register when the tap controller is in the ?capture-dr? state, and the boundary scan register is inserted between tdi and tdo when the tap controller is in the ?shift-dr? state. additionally, when the sample-z instruction is selected, the sram?s data output drivers are disabled. consequently, normal sram operation is disrupted when the sample-z instruction is selected. read operations initi- ated while the sample-z instruction is selected will fail.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 21 / 25 october 18, 2001 tap controller the tap controller is a 16-state state machine that controls access to the various tap registers and executes the opera- tions associated with each tap instruction. state transitions are controlled by tms and occur on the rising edge of tck . the tap controller enters the ?test-logic reset? state in one of two ways: 1. at power up. 2. when a logic ?1? is applied to tms for at least 5 consecutive rising edges of tck. the tdi input receiver is sampled only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. the tdo output driver is active only when the tap controller is in either the ?shift-ir? state or the ?shift-dr? state. tap controller state diagram figure 8 test-logic reset run-test / idle select dr-scan select ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 0 0 0 1 1 0 1 0 1
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 22 / 25 october 18, 2001 ? ordering information part number v dd i/o type size speed (cycle time / data access time) CXK77Q36B160GB-28 2.5v hstl 512k x 36 2.8ns / 1.5ns CXK77Q36B160GB-33 2.5v hstl 512k x 36 3.3ns / 1.6ns CXK77Q36B160GB-4 2.5v hstl 512k x 36 4.0ns / 1.8ns sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illus - trating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuit s.
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 23 / 25 october 18, 2001 13.0 a x4 b 2.5 max 0.6 0.1 s 7.62 1.27 119 - f 0.75 0.15 s ab (7x17) 119 pin bga package dimensions s 14.0 s a 0.15 1 2 3 4 5 6 7 a b c d e f g h j k l m n p r t u f 0.15 m 0.15 0.20 p r e l i m i n a r y p r e l i m i n a r y 4 - c 0 . 7 4 - c 1 . 0 1 9 . 0 2 2 . 0 0 . 1 5 s b 0 . 3 5 s 2 0 . 3 2 sony code eiaj code jedec code package material borad treatment lead material package mass solder package structure bga-119p-021 bga119-p-1422 epoxy resin copper-clad laminate 1.3g
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 24 / 25 october 18, 2001 ? revision history rev. # rev. date description of modification rev 0.0 07/18/00 initial version rev 0.1 05/18/01 1. modified i/o capacitance (p. 5). address (c addr ) and control (c ctrl ) 3.5pf to 4.2pf data (c data ) 4.5pf to 4.8pf 2. modified dc recommended operating conditions (p. 6). v ddq (max) 1.6v to 1.9v v ref , v cm (max) 0.9v to 1.0v v mih (min) v ref + 0.3v to 1.2v v mil (max) v ref - 0.3v to 0.4v 3. modified dc electrical characteristics (p. 7). i dd-28 (max) 830ma to 930ma i dd-33 (max) 700ma to 840ma i dd-37 (max) 640ma to 780ma i dd-4 (max) 590ma to 740ma i dd3 (max) 200ma to 300ma i sb (max) 130ma to 250ma 4. modified ac electrical characteristics (p. 8). -37 t khqv 1.7ns to 1.8ns 5. combined 1.5v v ddq ac test conditions for v dd = 2.5v and 3.3v (p.9). 6. added 1.8v v ddq ac test conditions for v dd = 2.5v and 3.3v (p.10). 7. modified jtag dc recommended operating conditions (p. 16). v toh-3.3 (min) at i toh = -100ua 2.7v to 2.6v v toh-3.3 (min) at i toh = -8ma 2.4v to 2.3v rev 0.2 09/18/01 1. removed 3.3v v dd support and ac test conditions. 2. removed 1.8v v ddq support and ac test conditions. 3. modified absolute maximum ratings (p. 5). v dd (max) 3.8v to 3.0v 4. modified dc recommended operating conditions (p. 6). v dd (max) 3.47v to 2.63v v ddq (max) 1.9v to 1.6v v ref , v cm (max) 1.0v to 0.9v v ih (min) v ref + 0.1v to v ref + 0.2v v il (max) v ref - 0.1v to v ref - 0.2v 5. modified dc electrical characteristics (p. 7). i dd-28 (max) 930ma to 900ma i dd-33 (max) 840ma to 800ma i dd-4 (max) 740ma to 700ma removed i dd3 (max) spec (3 mhz operating current). added i dd2 (max) spec (deselect operating current) 300ma 6. modified ac electrical characteristics (p. 8). removed ?-37? bin. removed ?a? sub-bin from ?-4? bin. 7. modified jtag dc recommended operating conditions (p. 15). removed v toh-33 (min) specs. i toh test condition for v toh (min) = v dd - 0.4v -8ma to -4ma i tol test condition for v tol (max) = 0.4v 8ma to 4ma
sony ? CXK77Q36B160GB preliminary 16mb lw r-r and r-r w/ ls, rev 1.0 25 / 25 october 18, 2001 rev 1.0 10/18/01 1. updated the programmable output driver impedance description (p. 4). 2. modified dc electrical characteristics (p. 7). added note 4 stating that average power supply operating current in devices marked as ?-33? is guaranteed (by test) to meet both the i dd-33 specification at 300 mhz opera- tion and the i dd-4 specification at 250 mhz operation. i mli (min/max) 10ua to 5ua i lo (min/max) 10ua to 5ua 3. modified ac electrical characteristics (p. 8). removed output enable setup and hold time specifications. rev. # rev. date description of modification

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