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freescale semiconductor data sheet: advance information document number: mpc5602d rev. 3.1, 02/2011 ? freescale semiconductor, inc., 2009, 2010. all rights reserved. preliminary?subject to change without notice this document contains information on a new product. specifications and information herein are subject to change without notice. mpc5602d 100 lqfp 14 mm x 14 mm 64 lqfp 10 mm x 10 mm ? single issue, 32-bit cpu core complex (e200z0) ? compliant with the power architecture ? embedded category ? includes an instruction set enhancement allowing variable length encoding (vle) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. ? up to 256 kb on-chip code flash supported with flash controller and ecc ? 64 kb on-chip data flash with ecc ? up to 16 kb on-chip sram with ecc ? interrupt controller (intc) with multiple interrupt vectors, including 20 exte rnal interrupt sources and 18 external interrupt/wakeup sources ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or sram from multiple bus masters ? boot assist module (bam) supports internal flash programming via a serial link (can or sci) ? timer supports input/output channels providing a range of 16-bit input captu re, output compare, and pulse width modulation functions (emios-lite) ? up to 33 channel 12-bit analog-to-digital converter (adc) ? 2 serial peripheral interface (dspi) modules ? 3 serial communication interface (linflex) modules ? 1 enhanced full can (flexcan) module with configurable buffers ? up to 79 configurable general purpose pins supporting input and output operations (package dependent) ? real time counter (rtc) with clock source from 128 khz or 16 mhz internal rc oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds ? up to 4 periodic interrupt timers (pit) with 32-bit counter resolution ? 1 system module timer (stm) ? nexus development interface (ndi) per ieee-isto 5001-2003 class 1 standard ? device/board boundary scan testing supported with per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator (vreg) for regulation of input supply for all internal levels mpc5602d microcontroller data sheet
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 2 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 document overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3 package pinouts and signal descriptions . . . . . . . . . . . . . . . . .7 3.1 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2 pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .20 4.3 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.3.1 nvusro[pad3v5v] field description . . . . . . . .20 4.3.2 nvusro[oscillator_margin] field description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21 4.5 recommended operating conditions . . . . . . . . . . . . . .22 4.6 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .24 4.6.1 package thermal characteristics . . . . . . . . . . . .24 4.6.2 power considerations. . . . . . . . . . . . . . . . . . . . .25 4.7 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . .25 4.7.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .25 4.7.2 i/o input dc characteristics . . . . . . . . . . . . . . . .26 4.7.3 i/o output dc characteristics. . . . . . . . . . . . . . .26 4.7.4 output pin transition times . . . . . . . . . . . . . . . . .29 4.7.5 i/o pad current specification . . . . . . . . . . . . . . .29 4.8 reset electrical characteristics. . . . . . . . . . . . . . . . . .34 4.9 power management electrical characteristics. . . . . . . .36 4.9.1 voltage regulator electrical characteristics . . . .36 4.9.2 voltage monitor electrical characteristics. . . . . .38 4.10 low voltage domain power consumption . . . . . . . . . . .39 4.11 flash memory electrical charac teristics . . . . . . . . . . . 40 4.11.1 program/erase characteristics . . . . . . . . . . . . . 40 4.11.2 flash power supply dc characteristics . . . . . . 42 4.11.3 start-up/switch-off timings . . . . . . . . . . . . . . . . 43 4.12 electromagnetic compatibility (emc) characteristics. . 43 4.12.1 designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . 44 4.12.2 electromagnetic interference (emi) . . . . . . . . . 44 4.12.3 absolute maximum ratings (electrical sensitivity)44 4.13 fast external crystal oscillator (4 to 16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.14 fmpll electrical characteristics . . . . . . . . . . . . . . . . . 49 4.15 fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.16 slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.17 adc electrical characteristics . . . . . . . . . . . . . . . . . . . 52 4.17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.17.2 input impedance and adc accuracy . . . . . . . . 52 4.17.3 adc electrical characteristics . . . . . . . . . . . . . 57 4.18 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.18.1 current consumption . . . . . . . . . . . . . . . . . . . . 60 4.18.2 dspi characteristics. . . . . . . . . . . . . . . . . . . . . 62 4.18.3 jtag characteristics. . . . . . . . . . . . . . . . . . . . . 68 5 package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 69 5.1.1 100 lqfp mechanical outline drawing. . . . . . . 69 5.1.2 64 lqfp mechanical outline drawing. . . . . . . . 73 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
introduction mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 3 1 introduction 1.1 document overview this document describes the device features and highlight s the important electrical and physical characteristics. 1.2 description these 32-bit automotive microcontrollers ar e a family of system-on-chip (soc) de vices designed to be central to the development of the next wave of central vehicle body controll er, smart junction box, front module, peripheral body, door contro l and seat control applications. this family is one of a series of next -generation integrated automotive microcon trollers based on the power architecture technology and designed specifica lly for embedded applications. the advanced and cost-efficient e200z0 host processor core of this automotive controller family complies with the power architecture technology and only implements the vle (variable- length encoding) apu (auxiliary processing unit), providing improved code density. it operates at speeds of up to 48 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infras tructure of current power arch itecture devices and is supported with software drivers, operating syst ems and configuration code to assist with the user?s implementations. the device platform has a single level of memory hierarchy and can support a wide range of on-chip static random access memory (sram) and internal flash memory. table 1. mpc5602d device comparison feature device MPC5601DXLH mpc5601dxll mpc5602dxlh mpc5602dxll cpu e200z0 execution speed static ? up to 48 mhz code flash 128 kb 256 kb data flash 64 kb (4 16 kb) sram 12 kb 16 kb edma 16 ch adc 16 ch, 12-bit 33 ch, 12-bit 16 ch, 12-bit 33 ch, 12-bit ctu 16 ch total timer i/o 1 emios 13 ch, 16-bit 28 ch, 16-bit 13 ch, 16-bit 28 ch, 16-bit ? type x 2 2ch 5ch 2ch 5ch ? type y 3 ?9ch?9ch ? type g 4 7ch 7ch 7ch 7ch ? type h 5 4ch 7ch 4ch 7ch sci (linflex) 3 spi (dspi) 2 can (flexcan) 1 gpio 6 45 79 45 79
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice introduction freescale semiconductor 4 debug jtag package 64 lqfp 100 lqfp 64 lqfp 100 lqfp 1 refer to emios section of device reference manual for information on the channel configuration and functions. 2 type x = mc + mcb + opwmt + opwmb + opwfmb + saic + saoc 3 type y = opwmt + opwmb + saic + saoc 4 type g = mcb + ipwm + ipm + daoc + opwmt + opwmb + opwfmb + opwmcb + saic + saoc 5 type h = ipwm + ipm + daoc + opwmt + opwmb + saic + saoc 6 i/o count based on multiplexing with peripherals table 1. mpc5602d device comparison (continued) feature device MPC5601DXLH mpc5601dxll mpc5602dxlh mpc5602dxll
block diagram mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 5 2 block diagram figure 1 shows a top-level block diagram of the mpc5602d device series. figure 1. mpc5602d series block diagram 2 x dspi fmpll nexus 1 sram siul reset control 16 kb external imux gpio & jtag pad control jtag port e200z0h interrupt requests 64-bit 3 x 3 crossbar switch 1 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . . . . . . . . . . intc 3 x linflex 1 x emios 33 ch. adc cmu sram flash code flash 256 kb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface ecsm error correction status module edma enhanced direct memory access emios enhanced modular input output system flash flash memory flexcan controller area network (flexcan) fmpll frequency-modulated phase-locked loop imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit xbar crossbar switch edma ecsm from peripheral blocks wkpu request interrupt request (master)
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice block diagram freescale semiconductor 6 table 2 summarizes the functions of all blocks present in the mpc5602d series of microcontrollers. please note that the presence and number of blocks varies by device and package. table 2. mpc5602d series block summary block function analog-to-digital converter (adc) multi-channel, 12-bit analog-to digital-converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit crossbar switch (xbar) supports si multaneous connections between two master po rts and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configurat ion and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors re ported by error-correcting codes enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol frequency-modulated phase-locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral interface on the different pins of the device interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load clock generation module (mc_cgm) provides logic and contro l required for the generatio n of system and peripheral clocks mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional st ates; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu
package pinouts and signal descriptions mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 7 3 package pinouts and signal descriptions 3.1 package pinouts the available lqfp pinouts are provided in the following figures. for pin signal descriptions, please refer to table 3 . reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device non-maskable interrupt (nmi) handles external events t hat must produce an immediate response, such as power down detection periodic interrupt timer (pit) produces periodic interrupts and triggers real-time counter (rtc) provides a free-running counte r and interrupt generation capability that can be used for timekeeping applications system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration static random-access memory (sram) provides storage for program code, constants, and variables system status and configuration module (sscm) provides system configurati on and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. table 2. mpc5602d series block summary (continued) block function
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 8 figure 2 shows the mpc5602d in the 100 lqfp package. figure 2. 100 lqfp pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] vdd_hv vss_hv pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa [ 1 5 ] pa [ 1 4 ] pa [ 4 ] pa [ 1 3 ] pa [ 1 2 ] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pe[12] 100 lqfp
package pinouts and signal descriptions mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 9 figure 3 shows the mpc5602d in the 64 lqfp package. figure 3. 64 lqfp pin configuration (top view) 3.2 pin muxing table 3 defines the pin list and muxing for this device. each entry of table 3 shows all the possible configura tions for each pin, via the altern ate functions. the default function assigned to each pin after reset is indicated by af0. table 3. functional port pin descriptions port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp port a pa [ 0 ] p c r [ 0 ] a f 0 af1 af2 af3 ? gpio[0] e0uc[0] clkout e0uc[13] wkup[19] 3 siul emios_0 cgl emios_0 wkpu i/o i/o o i/o i m tristate 5 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 pb[3] pc[9] pa [ 2 ] pa [ 1 ] pa [ 0 ] vpp_test vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[10] pb[0] pb[1] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa[9] pa[8] pa[7] pa[3] pb[15] pb[14] pb[13] pb[12] pb[11] pb[7] pb[6] pb[5] vdd_hv_adc vss_hv_adc pc[7] pa[15] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pb[4] pb[2] pc[8] pc[4] pc[5] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa[6] pa [ 5 ] pc[2] pc[3] 64 lqfp
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 10 pa [ 1 ] p c r [ 1 ] a f 0 af1 af2 af3 ? ? gpio[1] e0uc[1] ? ? nmi 4 wkup[2] 3 siul emios_0 ? ? wkpu wkpu i/o i/o ? ? i i s tristate 4 7 pa [ 2 ] p c r [ 2 ] a f 0 af1 af2 af3 ? gpio[2] e0uc[2] ? ? wkup[3] 3 siul emios_0 ? ? wkpu i/o i/o ? ? i s tristate 3 5 pa [ 3 ] p c r [ 3 ] a f 0 af1 af2 af3 ? ?? gpio[3] e0uc[3] ? ? eirq[0] adc1_s[0] siul emios_0 ? ? siul adc i/o i/o ? ? i i s tristate 43 68 pa [ 4 ] p c r [ 4 ] a f 0 af1 af2 af3 ? gpio[4] e0uc[4] ? ? wkup[9] 3 siul emios_0 ? ? wkpu i/o i/o ? ? i s tristate 20 29 pa [ 5 ] p c r [ 5 ] a f 0 af1 af2 af3 gpio[5] e0uc[5] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate 51 79 pa [ 6 ] p c r [ 6 ] a f 0 af1 af2 af3 ? gpio[6] e0uc[6] ? ? eirq[1] siul emios_0 ? ? siul i/o i/o ? ? i s tristate 52 80 pa [ 7 ] p c r [ 7 ] a f 0 af1 af2 af3 ? ? gpio[7] e0uc[7] ? ? eirq[2] adc1_s[1] siul emios_0 ? ? siul adc i/o i/o ? ? i i s tristate 44 71 pa [ 8 ] p c r [ 8 ] a f 0 af1 af2 af3 ? n/a 5 gpio[8] e0uc[8] e0uc[14] ? eirq[3] abs[0] siul emios_0 emios_0 ? siul bam i/o i/o ? ? i i s input, weak pull-up 45 72 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
package pinouts and signal descriptions mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 11 pa [ 9 ] p c r [ 9 ] a f 0 af1 af2 af3 n/a 5 gpio[9] e0uc[9] ? ? fab siul emios_0 ? ? bam i/o i/o ? ? i spull- down 46 73 pa[10] pcr[10] af0 af1 af2 af3 ? gpio[10] e0uc[10] ? lin1tx adc1_s[2] siul emios_0 ? linflex_1 adc i/o i/o ? o i s tristate 47 74 pa[11] pcr[11] af0 af1 af2 af3 ? ? ? gpio[11] e0uc[11] ? ? eirq[16] adc1_s[3] lin2rx siul emios_0 ? ? siul adc linflex_2 i/o i/o ? ? i i i s tristate 48 75 pa[12] pcr[12] af0 af1 af2 af3 ? ? gpio[12] ? ? ? eirq[17] sin_0 siul ? ? ? siul dspi_0 i/o ? ? ? i i s tristate 22 31 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 ? ? siul dspi_0 ? ? i/o o ? ? m tristate 21 30 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i m tristate 19 28 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkup[10] 3 siul dspi_0 dspi_0 emios_0 wkpu i/o i/o i/o i/o i m tristate 18 27 port b pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx ? ? siul flexcan_0 ? ? i/o o ? ? m tristate 14 23 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 12 pb[1] pcr[17] af0 af1 af2 af3 ? ? gpio[17] ? ? ? wkup[4] 3 can0rx siul ? ? ? wkpu flexcan_0 i/o ? ? ? i i s tristate 15 24 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx ? ? siul linflex_0 ? ? i/o o ? ? mtristate64 100 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] ? ? ? wkup[11] 3 lin0rx siul ? ? ? wkpu linflex_0 i/o ? ? ? i i s tristate 1 1 pb[4] pcr[20] af0 af1 af2 af3 ? gpio[20] ? ? ? adc1_p[0] siul ? ? ? adc i ? ? ? i i tristate 32 50 pb[5] pcr[21] af0 af1 af2 af3 ? gpio[21] ? ? ? adc1_p[1] siul ? ? ? adc i ? ? ? i i tristate 35 53 pb[6] pcr[22] af0 af1 af2 af3 ? gpio[22] ? ? ? adc1_p[2] siul ? ? ? adc i ? ? ? i i tristate 36 54 pb[7] pcr[23] af0 af1 af2 af3 ? gpio[23] ? ? ? adc1_p[3] siul ? ? ? adc i ? ? ? i i tristate 37 55 pb[8] pcr[24] af0 af1 af2 af3 ? ? gpio[24] ? ? ? adc1_s[4] wkup[25] 3 siul ? ? ? adc wkpu i ? ? ? i i i tristate 30 39 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
package pinouts and signal descriptions mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 13 pb[9] pcr[25] af0 af1 af2 af3 ? ? gpio[25] ? ? ? adc1_s[5] wkup[26] 3 siul ? ? ? adc wkpu i ? ? ? i i i tristate 29 38 pb[10] pcr[26] af0 af1 af2 af3 ? ? gpio[26] ? ? ? adc1_s[6] wkup[8] 3 siul ? ? ? adc wkpu i/o ? ? ? i i j tristate 31 40 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc1_s[12] siul emios_0 ? dspi_0 adc i/o i/o ? i/o i j tristate 38 59 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc1_x[0] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 39 61 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc1_x[1] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 40 63 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc1_x[2] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 41 65 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc1_x[3] siul emios_0 ? dspi_0 adc i/o i/o ? o i j tristate 42 67 port c pc[0] 6 pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 59 87 pc[1] 6 pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f tristate 54 82 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 14 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 ? ? eirq[5] siul dspi_1 ? ? siul i/o i/o ? ? i m tristate 50 78 pc[3] pcr[35] af0 af1 af2 af3 ? gpio[35] cs0_1 ma[0] ? eirq[6] siul dspi_1 adc ? siul i/o i/o o ? i s tristate 49 77 pc[4] pcr[36] af0 af1 af2 af3 ? ? gpio[36] ? ? ? sin_1 eirq[18] siul ? ? ? dspi_1 siul i/o ? ? ? i i m tristate 62 92 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 ? ? eirq[7] siul dspi_1 ? ? siul i/o o ? ? i m tristate 61 91 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx ? ? siul linflex_1 ? ? i/o o ? ? s tristate 16 25 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? ? ? lin1rx wkup[12] 3 siul ? ? ? linflex_1 wkpu i/o ? ? ? i i s tristate 17 26 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx ? ? siul linflex_2 ? ? i/o o ? ? s tristate 63 99 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? ? ? lin2rx wkup[13] 3 siul ? ? ? linflex_2 wkpu i/o ? ? ? i i s tristate 2 2 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] ? ? ma[1] siul ? ? adc i/o ? ? o m tristate 13 22 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
package pinouts and signal descriptions mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 15 pc[11] pcr[43] af0 af1 af2 af3 ? gpio[43] ? ? ma[2] wkup[5] 3 siul ? ? adc wkpu i/o ? ? o i s tristate ? 21 pc[12] pcr[44] af0 af1 af2 af3 ? gpio[44] e0uc[12] ? ? eirq[19] siul emios_0 ? ? siul i/o i/o ? ? i m tristate ? 97 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? 98 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] ? ? eirq[8] siul emios_0 ? ? siul i/o i/o ? ? i s tristate ? 3 pc[15] pcr[47] af0 af1 af2 af3 ? gpio[47] e0uc[15] ? ? eirq[20] siul emios_0 ? ? siul i/o i/o ? ? i m tristate ? 4 port d pd[0] pcr[48] af0 af1 af2 af3 ? ? gpio[48] ? ? ? wkup[27] 3 adc1_p[4] siul ? ? ? wkpu adc i ? ? ? i i i tristate ? 41 pd[1] pcr[49] af0 af1 af2 af3 ? ? gpio[49] ? ? ? wkup[28] 3 adc1_p[5] siul ? ? ? wkpu adc i ? ? ? i i i tristate ? 42 pd[2] pcr[50] af0 af1 af2 af3 ? gpio[50] ? ? ? adc1_p[6] siul ? ? ? adc i ? ? ? i i tristate ? 43 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 16 pd[3] pcr[51] af0 af1 af2 af3 ? gpio[51] ? ? ? adc1_p[7] siul ? ? ? adc i ? ? ? i i tristate ? 44 pd[4] pcr[52] af0 af1 af2 af3 ? gpio[52] ? ? ? adc1_p[8] siul ? ? ? adc i ? ? ? i i tristate ? 45 pd[5] pcr[53] af0 af1 af2 af3 ? gpio[53] ? ? ? adc1_p[9] siul ? ? ? adc i ? ? ? i i tristate ? 46 pd[6] pcr[54] af0 af1 af2 af3 ? gpio[54] ? ? ? adc1_p[10] siul ? ? ? adc i ? ? ? i i tristate ? 47 pd[7] pcr[55] af0 af1 af2 af3 ? gpio[55] ? ? ? adc1_p[11] siul ? ? ? adc i ? ? ? i i tristate ? 48 pd[8] pcr[56] af0 af1 af2 af3 ? gpio[56] ? ? ? adc1_p[12] siul ? ? ? adc i ? ? ? i i tristate ? 49 pd[9] pcr[57] af0 af1 af2 af3 ? gpio[57] ? ? ? adc1_p[13] siul ? ? ? adc i ? ? ? i i tristate ? 56 pd[10] pcr[58] af0 af1 af2 af3 ? gpio[58] ? ? ? adc1_p[14] siul ? ? ? adc i ? ? ? i i tristate ? 57 pd[11] pcr[59] af0 af1 af2 af3 ? gpio[59] ? ? ? adc1_p[15] siul ? ? ? adc i ? ? ? i i tristate ? 58 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
package pinouts and signal descriptions mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 17 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc1_s[8] siul dspi_0 emios_0 ? adc i/o o i/o ? i j tristate ? 60 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc1_s[9] siul dspi_1 emios_0 ? adc i/o i/o i/o ? i j tristate ? 62 pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? adc1_s[10] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? 64 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? adc1_s[11] siul dspi_1 emios_0 ? adc i/o o i/o ? i j tristate ? 66 port e pe[0] pcr[64] af0 af1 af2 af3 ? gpio[64] e0uc[16] ? ? wkup[6] 3 siul emios_0 ? ? wkpu i/o i/o ? ? i s tristate ? 6 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] ? ? siul emios_0 ? ? i/o i/o ? ? m tristate ? 8 pe[2] pcr[66] af0 af1 af2 af3 ? ? gpio[66] e0uc[18] ? ? eirq[21] sin_1 siul emios_0 ? ? siul dspi_1 i/o i/o ? ? i i m tristate ? 89 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? m tristate ? 90 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i m tristate ? 93 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package pinouts and signal descriptions freescale semiconductor 18 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc i/o i/o i/o o m tristate ? 94 pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[21] siul emios_0 dspi_0 adc siul i/o i/o o o i m tristate ? 95 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[21] siul emios_0 dspi_0 adc siul i/o i/o o o i m tristate ? 96 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] ? e0uc[22] ? siul ? emios_0 ? i/o ? i/o ? m tristate ? 9 pe[9] pcr[73] af0 af1 af2 af3 ? gpio[73] ? e0uc[23] ? wkup[7] 3 siul ? emios_0 ? wkpu i/o ? i/o ? i s tristate ? 10 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] ? cs3_1 ? eirq[10] siul ? dspi_1 ? siul i/o ? o ? i s tristate ? 11 pe[11] pcr[75] af0 af1 af2 af3 ? gpio[75] e0uc[24] cs4_1 ? wkup[14] 3 siul emios_0 dspi_1 ? wkpu i/o i/o o ? i s tristate ? 13 pe[12] pcr[76] af0 af1 af2 af3 ? ? gpio[76] ? ? ? adc1_s[7] eirq[11] siul ? ? ? adc siul i/o ? ? ? i i s tristate ? 76 port h ph[9] 6 pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 60 88 table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 19 4 electrical characteristics 4.1 introduction this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this can be done by the internal pull-up or pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. caution all of the following parameter values can vary depending on the application and must be confirmed during silicon validation, silicon characterization or silicon reliability trial. ph[10] 6 pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 53 81 1 alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 ? af0; pcr.pa = 01 ? af1; pcr.pa = 10 ? af2; pcr.pa = 11 ? af3. this is intended to select the output functions; to use one of th e input functions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 multiple inputs are routed to all respective modules internally. the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3 all wkup pins also support external interrupt capability. see ?wakeup unit? chapter for further details. 4 nmi has higher priority than alternate function. w hen nmi is selected, the pcr.af field is ignored. 5 ?not applicable? because these functions are available only wh ile the device is booting. refer to ?bam? chapter of the device reference manual for details. 6 out of reset all the functional pins except pc[0:1] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). it is up to the user to configur e these pins as gpio when needed. table 3. functional port pin descriptions (continued) port pin pcr register alternate function 1 function peripheral i/o direction 2 pad type reset config. pin no. 64 lqfp 100 lqfp
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 20 4.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 4 are used and the parameters are ta gged accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 4.3 nvusro register portions of the device configuration, such as high voltage supp ly, oscillator margin, and watch dog enable/disable after reset a re controlled via bit values in the non-volatil e user options register (nvusro) register. for a detailed description of the nvusro regist er, please refer to the mpc5602d reference manual. 4.3.1 nvusro[pad3v5v] field description table 5 shows how nvusro[pad3v5v] controls the device configuration. the dc electrical characteristics are dependent on the pad3v5v bit value. 4.3.2 nvusro[oscillator_margin] field description table 6 shows how nvusro[oscillator_margin] controls the device configuration. table 4. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 5. pad3v5v field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 '1' is delivery value. it is part of shadow flash, thus programmable by customer. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 21 the fast external crystal oscillator consumptio n is dependent on the osci llator_margin bit value. 4.4 absolute maximum ratings table 6. oscillator_margin field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 '1' is delivery value. it is part of shadow flash, thus programmable by customer. description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 7. absolute maximum ratings symbol c parameter conditions value unit min max v ss sr ? digital ground on vss_hv pins ? 0 0 v v dd sr ? voltage on vdd_hv pins with respect to ground (v ss ) ? ? 0.3 6.0 v v ss_lv sr ? voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss +0.1 v v dd_bv sr ? voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ? ? 0.3 6.0 v relative to v dd v dd ? 0.3 v dd +0.3 v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) ?v ss ? 0.1 v ss +0.1 v v dd_adc sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ? ? 0.3 6.0 v relative to v dd v dd ? 0.3 v dd +0.3 v in sr ? voltage on any gpio pin with respect to ground (v ss ) ? ? 0.3 6.0 v relative to v dd v dd ? 0.3 v dd +0.3 i injpad sr ? injected input current on any pin during overload condition ? ? 10 10 ma i injsum sr ? absolute sum of all injected input currents during overload condition ? ? 50 50 ma i avgseg sr ? sum of all the static i/o current within a supply segment 1 1 supply segments are described in section 4.7.5, ?i/o pad current specification . v dd = 5.0 v 10%, pad3v5v = 0 ?70ma v dd = 3.3 v 10%, pad3v5v = 1 ?64 i corelv sr ? low voltage static current sink through vdd_bv ??150ma t storage sr ? storage temperature ? ? 55 150 c
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 22 note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 23 note sram data retention is guaranteed with v dd_lv not below 1.08 v. table 9. recommended operating conditions (5.0 v) symbol c parameter conditions value unit min max v ss sr ? digital ground on vss_hv pins ? 0 0 v v dd 1 sr ? voltage on vdd_hv pins with respect to ground (v ss ) ?4.55.5v voltage drop 2 3.0 5.5 v ss_lv 3 sr ? voltage on vss_lv (low vo ltage digital supply) pins with respect to ground (v ss ) ?v ss ? 0.1 v ss +0.1 v v dd_bv 4 sr ? voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ?4.55.5v voltage drop (2) 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v ss_adc sr ? voltage on vss_hv_adc (a dc reference) pin with respect to ground (v ss ?v ss ? 0.1 v ss +0.1 v v dd_adc 5 sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?4.55.5v voltage drop (2) 3.0 5.5 relative to v dd v dd ? 0.1 v dd +0.1 v in sr ? voltage on any gpio pin with respect to ground (v ss ) ?v ss ? 0.1 ? v relative to v dd ?v dd +0.1 i injpad sr ? injected input current on any pin during overload condition ? ? 55ma i injsum sr ? absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr ? v dd slope to ensure correct power up 6 ? tbd 0.25 v/s t a sr ? ambient temperature under bias f cpu ? 48 mhz ? 40 125 c t j sr ? junction temperature under bias ? ? 40 150 1 100 nf capacitance needs to be provided between each v dd /v ss pair. 2 full device operation is guaranteed by design when the vo ltage drops below 4.5 v down to 3.6 v. however, certain analog electrical characteristics will not be guaranteed to stay wit hin the stated limits. 3 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4 470 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteristics). 5 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6 guaranteed by device validation
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 24 4.6 thermal characteristics 4.6.1 package thermal characteristics table 10. lqfp thermal characteristics 1 1 thermal characteristics are targets based on simulation th at are subject to change per device characterization. symbol c parameter conditions 2 2 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c pin count value 3 3 all values need to be confirmed during device validation. unit r ? ja cc d thermal resistance, junction-to-ambient natural convection 4 4 junction-to-ambient thermal resistance determined pe r jedec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. when greek letters are not available, the symbols are typed as r thja and r thjma . single-layer board ?1s 64 72.1 c/w 100 65.2 four-layer board ? 2s2p 64 57.3 100 51.8 r ? jb cc d thermal resistance, junction-to-board 5 5 junction-to-board thermal resistance determined pe r jedec jesd51-8. thermal test board meets jedec specification for the specified package. when greek le tters are not available, the symbols are typed as r thjb . single-layer board ? 1s 64 45.6 c/w 100 42.6 four-layer board ? 2s2p 64 44.1 100 41.3 r ? jc cc d thermal resistance, junction-to-case 6 6 junction-to-case at the top of the package determi ned using mil-std 883 method 1012.1. the cold plate temperature is used for the case temperature. reported valu e includes the thermal resistance of the interface layer. when greek letters are not available, the symbols are typed as r thjc . single-layer board ? 1s 64 26.5 c/w 100 23.9 four-layer board ? 2s2p 64 26.2 100 23.7 ? jb cc d junction-to-board thermal characterization parameter, natural convection single-layer board ? 1s 64 41 c/w 100 41.6 four-layer board ? 2s2p 64 43 100 43.4 ? jc cc d junction-to-case thermal characterization parameter, natural convection single-layer board ? 1s 64 11.5 c/w 100 10.4 four-layer board ? 2s2p 64 11.1 100 10.2
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 25 4.6.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : t j = t a + (p d x r ? ja ) eqn. 1 where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambie nt thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273 c) eqn. 2 therefore, solving equations 1 and 2 : k = p d x (t a + 273 c) + r ? ja x p d 2 eqn. 3 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 4.7 i/o pad electrical characteristics 4.7.1 i/o pad types the device provides four main i/o pad types depe nding on the associated alternate functions: ? slow pads?these pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads?these pads provide transition fast enough for the serial communicati on channels with controlled current to reduce elect romagnetic emission. ? input only pads?these pads are associated to adc channels (adc_p[x]) providing low input leakage. medium pads can use slow configuration to reduce electromagnetic emission except for pc[1 ], that is medium only, at the cost of reducing ac performance.
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 26 4.7.2 i/o input dc characteristics table 11 provides input dc electrical characteristics as described in figure 4 . figure 4. i/o input dc electrical characteristics definition 4.7.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: table 11. i/o input dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg cc p digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 ? na pt a = 25 c ? 2 ? dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi 3 3 in the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. sr p digital input filtered pulse ? ? ? 40 ns w nfi 3 sr p digital input not filtered pulse ? 1000 ? ? ns v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0?
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 27 ? table 12 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 13 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 14 provides output driver char acteristics for i/o pads when in medium configuration. table 12. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max |i wpu | cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurat ion during power-up. all pads but reset are configured in inpu t or in high impedance state. 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd | cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 2 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 table 13. slow configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc p output high level slow configuration push pull i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? v ci oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configurat ion during power-up. all pads but reset are configured in inpu t or in high impedance state. 0.8v dd ?? ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? v ol cc p output low level slow configuration push pull i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v ci ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 28 table 14. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc c output high level medium configuration push pull i oh = ? 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v pi oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ?? ci oh = ? 1ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset are configured in input or in hi gh impedance state. 0.8v dd ?? ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ? ? ci oh = ? 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ?? v ol cc c output low level medium configuration push pull i ol = 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.2v dd v pi ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd ci ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) ? ? 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 ci oh = 100 a, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.1v dd
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 29 4.7.4 output pin transition times 4.7.5 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 16 . table 17 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. table 15. output pin transition times symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max t tr cc d output transition time output pin 3 slow configuration 3 c l includes device and package capacitances (c pkg < 5 pf). c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ? ? 50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ? ? 50 tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 t tr cc d output transition time output pin (3) medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ? ? 10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 table 16. i/o supply segment package supply segment 1234 100 lqfp pin 16 ? pin 35 pin 37 ? pin 69 pin 70 ? pin 83 pin 84 ? pin 15 64 lqfp pin 8 ? pin 26 pin 28 ? pin 55 pin 56 ? pin 7 ?
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 30 table 18 provides the weight of concurrent switching i/os. in order to ensure device functionality, the sum of the weight of concurrent switching i/os on a single segment should remain below 100%. table 17. i/o consumption symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max i swtslw ,3 3 stated maximum values represent peak consumption that lasts only a few ns during i/o transition. cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??20ma v dd = 3.3 v 10%, pad3v5v = 1 ??16 i swtmed (3) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??29ma v dd = 3.3 v 10%, pad3v5v = 1 ??17 i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??2.3ma c l = 25 pf, 4 mhz ? ? 3.2 c l = 100 pf, 2 mhz ? ? 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??1.6 c l = 25 pf, 4 mhz ? ? 2.3 c l = 100 pf, 2 mhz ? ? 4.7 i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.6ma c l = 25 pf, 40 mhz ? ? 13.4 c l = 100 pf, 13 mhz ? ? 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ?? 5 c l = 25 pf, 40 mhz ? ? 8.5 c l = 100 pf, 13 mhz ? ? 11 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 31 table 18. i/o weight 1 pad 100/64 lqfp weight 5v src = 0 weight 5v src = 1 weight 3.3v src = 0 weight 3.3v src = 1 pb[3] 9% 9% 10% 10% pc[9] 8% 8% 10% 10% pc[14] 8% 8% 10% 10% pc[15] 8% 11% 9% 10% pa [ 2 ] 8 % 8 % 9 % 9 % pe[0] 7% 7% 9% 9% pa [ 1 ] 7 % 7 % 8 % 8 % pe[1] 7% 10% 8% 8% pe[8] 6% 9% 8% 8% pe[9] 6% 6% 7% 7% pe[10] 6% 6% 7% 7% pa [ 0 ] 5 % 7 % 6 % 7 % pe[11] 5% 5% 6% 6% pc[11] 7% 7% 9% 9% pc[10] 8% 11% 9% 10% pb[0] 8% 11% 9% 10% pb[1] 8% 8% 10% 10% pc[6] 8% 8% 10% 10% pc[7] 8% 8% 10% 10% pa[15] 8% 11% 9% 10% pa[14] 7% 11% 9% 9% pa [ 4 ] 7 % 7 % 8 % 8 % pa[13] 7% 10% 8% 9% pa[12] 7% 7% 8% 8% pb[9] 1% 1% 1% 1% pb[8] 1% 1% 1% 1% pb[10] 5% 5% 6% 6% pd[0] 1% 1% 1% 1% pd[1] 1% 1% 1% 1% pd[2] 1% 1% 1% 1% pd[3] 1% 1% 1% 1% pd[4] 1% 1% 1% 1% pd[5] 1% 1% 1% 1%
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 32 pd[6] 1% 1% 1% 1% pd[7] 1% 1% 1% 1% pd[8] 1% 1% 1% 1% pb[4] 1% 1% 1% 1% pb[5] 1% 1% 1% 1% pb[6] 1% 1% 1% 1% pb[7] 1% 1% 1% 1% pd[9] 1% 1% 1% 1% pd[10] 1% 1% 1% 1% pd[11] 1% 1% 1% 1% pb[11] 9% 9% 11% 11% pd[12] 8% 8% 10% 10% pb[12] 8% 8% 10% 10% pd[13] 8% 8% 9% 9% pb[13] 8% 8% 9% 9% pd[14] 7% 7% 9% 9% pb[14] 7% 7% 8% 8% pd[15] 7% 7% 8% 8% pb[15] 6% 6% 7% 7% pa [ 3 ] 6 % 6 % 7 % 7 % pa [ 7 ] 4 % 4 % 5 % 5 % pa [ 8 ] 4 % 4 % 5 % 5 % pa [ 9 ] 4 % 4 % 5 % 5 % pa[10] 5% 5% 6% 6% pa[11] 5% 5% 6% 6% pe[12] 5% 5% 6% 6% pc[3] 5% 5% 6% 6% pc[2] 5% 7% 6% 6% pa [ 5 ] 5 % 6 % 5 % 6 % pa [ 6 ] 4 % 4 % 5 % 5 % pc[1] 5% 17% 4% 12% pc[0] 6% 9% 7% 8% pe[2] 7% 10% 8% 9% table 18. i/o weight 1 (continued) pad 100/64 lqfp weight 5v src = 0 weight 5v src = 1 weight 3.3v src = 0 weight 3.3v src = 1
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 33 pe[3] 7% 10% 9% 9% pc[5] 8% 11% 9% 10% pc[4] 8% 11% 9% 10% pe[4] 8% 12% 10% 10% pe[5] 8% 12% 10% 11% pe[6] 9% 12% 10% 11% pe[7] 9% 12% 10% 11% pc[12] 9% 13% 11% 11% pc[13] 9% 9% 11% 11% pc[8] 9% 9% 11% 11% pb[2] 9% 13% 11% 12% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified table 18. i/o weight 1 (continued) pad 100/64 lqfp weight 5v src = 0 weight 5v src = 1 weight 3.3v src = 0 weight 3.3v src = 1
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 34 4.8 reset electrical characteristics the device implements a dedi cated bidirectional reset pin. figure 5. start-up reset requirements figure 6. noise filtering on reset signal v il v dd device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 35 table 19. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.4 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 3 3 this is a transient configuration during power-up, up to the end of reset phase2 (refer to rgm module section of the device reference manual). ? ? 0.1v dd push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc d output transition time output pin 4 medium configuration 4 c l includes device and package capacitance (c pkg <5pf). c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 10 ns c l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??20 c l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ??40 c l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??12 c l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??25 c l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ??40 w frst sr p reset input filtered pulse ???40ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 5 5 the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration du ring power-up. all pads but reset are configured in input or in high impedance state. 10 ? 250
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 36 4.9 power management electrical characteristics 4.9.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: ? hv: high voltage external power supply for voltage regulator module. this must be provided externally through v dd power pin. ? bv: high voltage external power supply for internal ballast module. this must be provided externally through v dd_bv power pin. voltage values should be aligned with v dd . ? lv: low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the internal voltage regulator but provided outside to connect stability capacito r. it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla: low voltage supply for code flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla: low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll: low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 7. voltage regulator capacitance connection the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. ca pacitances should be placed on the board as near as po ssible to the associated pins . care should also be taken to limit the seri al inductance of the board to less than 5 nh. c reg1 (lv_cor/lv_dfla) device v ss_lv v dd_bv v dd_lv c dec1 (ballast decoupling) v ss_lv v dd_lv v dd v ss_lv v dd_lv c reg2 (lv_cor/lv_cfla) c reg3 (lv_cor/lv_pll) c dec2 (supply/io decoupling) device v dd_bv i v dd_lvn v ref v dd voltage regulator v ss v ss_lvn gnd gnd gnd gnd
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 37 each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 4.5, ?recommen ded operating conditions ). table 20. voltage regulator electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max c regn sr ? internal voltage regulator external capacitance ? 200 ? 500 nf r reg sr ? stability capacitor equivalent serial resistance ???0.2 ? c dec1 sr ? decoupling capacitance 3 ballast v dd_bv /v ss_lv pair: v dd_bv = 4.5 v to 5.5 v 100 4 470 5 ?nf v dd_bv /v ss_lv pair: v dd_bv = 3v to 3.6v 400 ? c dec2 sr ? decoupling capacitance regulator supply v dd /v ss pair 10 100 ? nf v mreg cc t main regulator output voltage before exiting from reset ? 1.32 ? v p after trimming tbd 1.28 tbd i mreg sr ? main regulator current provided to v dd_lv domain ??? 150 ma i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg cc p low power regulator output voltage after trimming tbd 1.23 tbd v i lpreg sr ? low power regulator current provided to v dd_lv domain ? ?? 15 ma i lpregint cc d low power regulator module current consumption i lpreg = 15 ma; t a = 55 c ?? 600 a ? i lpreg = 0 ma; t a = 55 c ? 5 ? v ulpreg cc p ultra low power regulator output voltage after trimming tbd 1.23 tbd v i ulpreg sr ? ultra low power regulator current provided to v dd_lv domain ??? 5 ma i ulpregint cc d ultra low power regulator module current consumption i ulpreg = 5 ma; t a = 55 c ?? 100 a i ulpreg = 0 ma; t a = 55 c ? 2 ? i dd_bv cc d in-rush current on v dd_bv during power-up ?? ? 400 6 ma
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 38 4.9.2 voltage monitor electrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initialization, as well as four low voltage detectors (lvds) to monitor the v dd and the v dd_lv voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 note when enabled, power domain no. 2 is monitored through lvd_digbkp. figure 8. low voltage monitor vs. reset 3 this capacitance value is driven by the constraint s of the external voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. 4 this value is acceptable to guaran tee operation from 4.5 v to 5.5 v. 5 external regulator and capacitance circuitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. 6 in-rush current is seen only for short time during power-up and on standby exit (max 20 s, depending on external capacitances to be load). v dd v lvdhvxh reset v lvdhvxl
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 39 4.10 low voltage domain power consumption table 22 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 21. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v porup sr p supply for functional por module ? 1.0 ? 5.5 v v porh cc p power-on reset threshold t a = 25 c, after trimming 1.5 ? 2.6 t ? 1.5 ? 2.6 v lv d h v 3 h cc t lvdhv3 low voltage detector high threshold ? ? ? 2.9 v lv d h v 3 l cc p lvdhv3 low voltage detector low threshold ? 2.6 ? tbd v lvd h v 5 h 3 3 data based on characterization results, not tested in production cc t lvdhv5 low voltage detector high threshold ? ? ? 4.4 v lv d h v 5 l cc p lvdhv5 low voltage detector low threshold ? 3.8 ? tbd v lvd lv c o r l cc p lvdlvcor low voltage detector low threshold ? 1.08 ? ? v lvdlvbkpl cc p lvdlvbkp low voltage detector low threshold ? 1.08 ? 1.11 table 22. low voltage power domain electrical characteristics symbol c parameter conditions 1 value unit min typ max i ddmax 2 cc d run mode maximum average current ??100tbd 3 ma i ddrun 4 cc t run mode typical average current 5 f cpu = 8 mhz ? tbd ? ma tf cpu = 16 mhz ? tbd ? tf cpu = 32 mhz ? tbd ? pf cpu = 48 mhz ? tbd ? i ddhalt cc c halt mode current 6 slow internal rc oscillator (128 khz) running t a =25c ? tbd tbd ma pt a = 125 c ? tbd tbd i ddstop cc p stop mode current 7 slow internal rc oscillator (128 khz) running t a =25c ? 150 tbd 8 a dt a =55c ? tbd ? dt a =85c ? tbd ? ma dt a = 105 c ? tbd ? pt a = 125 c ? tbd tbd 8
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 40 4.11 flash memory electrical characteristics the data flash operation depends strongly on the code flash operation. if code flash is switched-off, the data flash is disabled. 4.11.1 program/erase characteristics table 23 shows the program and erase characteristics. i ddstdby cc p standby mode current 9 slow internal rc oscillator (128 khz) running t a =25c ? 25 tbd a dt a =55c ? tbd ? dt a =85c ? ? dt a = 105 c ? ? pt a = 125 c ? tbd 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 running consumption is given on voltage regulator supply (v ddreg ). it does not include consumption linked to i/os toggling. this value is highly dependent on the application. the given value is thought to be a worst case value with all peripherals running, and code fetched from code flash wh ile modify operation on-going on data flash. note that this value can be significantly reduced by application: sw itch off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from sram most used functions, use low power mode when possible. 3 higher current may be sinked by device during power-up and standby exit. please refer to in rush current on ta bl e 2 0 . 4 run current measured with typical applicat ion with accesses on both flash and sram. 5 only for the ?p? classification: code fetched from sram: serial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multiplier) peripherals on (emios/ctu/adc) and running at max frequency, periodic sw/wdg timer reset enabled. 6 data flash power down. code flash in low power. rc-osc 128 khz & rc-osc 16 mhz on. 10 mhz xtal clock. flexcan: 0 on (clocked but no reception or transmission). li nflex: instances: 0, 1, 2 on (clocked but no reception or transmission), instance: 3 clocks gate d. emios: instance: 0 on (16 channels on pa[0]?pa[11] and pc[12]?pc[15]) with pwm 20 khz, instance: 1 clock gated. dspi: instan ce: 0 (clocked but no communication). rtc/api on.pit on. stm on. adc on but no conversion except 2 analog watchdogs. 7 only for the ?p? classification: no clock, rc-osc 16 mhz off, rc-osc 128 khz on, pll off, hpvreg off, ulpvreg/lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 8 when going from run to stop mode and the core consumpt ion is > 6 ma, it is normal operation for the main regulator module to be kept on by the on-chip current moni toring circuit. this is most likely to occur with junction temperatures exceeding 125 c and under these circumstances, it is possible for the current to initially exceed the maximum stop specification by up to 2 ma. after enteri ng stop, the application junction temperature will reduce to the ambient level and the main regulator will be automatica lly switched off when the load current is below 6 ma. 9 only for the ?p? classification: ulpvreg on, hp/lpvre g off, 16 kb sram on, device configured for minimum consumption, all possible modules switched off. table 22. low voltage power domain electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 41 table 23. program and erase specifications (code flash) symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/ erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/er ase cycles. these maximum values are characterized but not guaranteed. t dwprogram cc c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ? 22 50 500 s t 16kpperasec 16 kb block preprogram and erase time ? 300 500 5000 ms t 32kpperasec 32 kb block preprogram and erase time ? 400 600 5000 ms t 128kpperasec 128 kb block preprogram and erase time ? 800 1300 7500 ms t esus erase suspend latency tbd tbd tbd tbd s table 24. program and erase specifications (data flash) symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t swprogram cc c single word (32 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?3070300s t 16kpperase 16 kb block preprogram and erase time ? 700 800 1500 ms t bank_d 64 kb block preprogram and erase time ? 1900 2300 4800 ms
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 42 ecc circuitry provides correction of single bit faults and is us ed to improve further automotive reliability results. some unit s will experience single bit corrections throughout the life of the product with no impact to product reliability. 4.11.2 flash power supply dc characteristics table 27 shows the power supply dc char acteristics on external supply. note power supply for data flash is actually provided by code flash, this means that data flash cannot work if code flash is not powered. table 25. flash module life symbol c parameter conditions value unit min typ max p/e cc c number of program/erase cycles per block for 16 kb blocks over the operating temperature range (t j ) ? 100 ? ? kcycles p/e cc c number of program/erase cycles per block for 32 kb blocks over the operating temperature range (t j ) ?10100 1 1 to be confirmed ? kcycles p/e cc c number of program/erase cycles per block for 128 kb blocks over the operating temperature range (t j ) ?1100 (1) ? kcycles retention cc c minimum data retention at 85 c average ambient temperature 2 2 ambient temperature averaged over application duration. it is recommended not to exceed the product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? ? years blocks with 1,001?10,000 p/e cycles 10 ? ? years blocks with 10,001?100,000 p/e cycles 5??years table 26. flash read access timing symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified max unit f read cc p maximum frequency for flash reading 2 wait states 48 mhz c 1 wait state 40 c 0 wait states 20
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 43 4.11.3 start-up/switch-off timings 4.12 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sa mple basis during produ ct characterization. table 27. flash power supply dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max i cfread cc d sum of the current consumption on v ddhv and v ddbv on read access flash module read f cpu = 48 mhz code flash ? ? 33 ma i dfread data flash ? ? 4 i cfmod cc d sum of the current consumption on v ddhv and v ddbv on matrix modification (program/erase) program/erase on-going while reading flash registers, f cpu = 48 mhz code flash ? ? 33 ma i dfmod data flash ? ? 6 i flpw cc d sum of the current consumption on v ddhv and v ddbv during flash low-power mode ? code flash ? ? 910 a i cfpwd cc d sum of the current consumption on v ddhv and v ddbv during flash power-down mode ? code flash ? ? 125 a i dfpwd data flash ? ? 25 table 28. start-up time/switch-off time symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max t flarstexit cc t delay for flash module to exit reset mode code flash ? ? 125 s data flash ? ? 150 t flalpexit cc t delay for flash module to exit low-power mode 2 2 data flash does not support low-power mode code flash ? ? 0.5 t flapdexit cc t delay for flash module to exit power-down mode code flash ? ? 30 data flash 30 3 3 if code flash is already switched-on. t flalpentry cc t delay for flash module to enter low-power mode code flash ? ? 0.5 t flapdentry cc t delay for flash module to enter power-down mode code flash ? ? 1.5 data flash ? ? 4 (3)
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 44 4.12.1 designing hardened software to avoid noise problems emc characterization and optimiza tion are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and prequalification tests in relation with the emc level requested for his application. ? software recommendations ?? the software flowchart must include the ma nagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) ? prequalification trials ?? most of the common failures (unexpected re set and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prev ent unrecoverable errors occurring. 4.12.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec 61967-1 standard, which specifies the general conditions for emi measurements. 4.12.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement me thods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 4.12.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size depends on the number of supply pins in the device (3 parts * (n + 1) supply pin). this test conforms to the aec-q100-002/-003/-011 standard. table 29. emi radiated emission measurement 1,2 1 emi testing and i/o port waveforms per iec 61967-1, -2, -4 2 for information on conducted emission and susceptibility measurement (norm iec 61967-4), please contact your local marketing representative. symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.150 ? 1000 mhz f cpu sr ? operating frequency ? ? 48 ? mhz v dd_lv sr ? lv operating voltages ? ? 1.28 ? v s emi cc t peak level v dd = 5v, t a =25c, 100 lqfp package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 48 mhz no pll frequency modulation ??tbddbv 2% pll frequency modulation ??tbd 3 3 all values need to be confirmed during device validation dbv
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 45 4.12.3.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 4.13 fast external crystal oscill ator (4 to 16 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 9 describes a simple model of the internal oscillator driver and provides an example of a connection for an oscillator or a resonator. table 30. esd absolute maximum ratings 1 2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. symbol c ratings conditions class max value unit v esd(hbm) cc t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) cc t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) cc t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) table 31. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 125 c conforming to jesd 78 ii level a
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 46 table 32 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. figure 9. crystal oscillator and resonator connection scheme c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd note : xtal/extal must not be directly used to drive external circuits.
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 47 figure 10. fast external crystal oscillator (4 to 16 mhz) electrical characteristics table 32. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c 1 = c 2 (pf) 1 1 the values specified for c 1 and c 2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. shunt capacitance between xtalout and xtalin c0 2 (pf) 2 the value of c 0 specified here includes 2 pf additional capaci tance for parasitics (to be seen with bond-pads, package, etc.). 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0?
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 48 table 33. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max f fxosc sr ? fast external crystal oscillator frequency ? 4.0 ? 16.0 mhz ? fxosc cc t fast external crystal oscillator frequency duty cycle ?30?70% ? t fxjit cc t fast external crystal oscillator jitter ???tbdns g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 ? 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 ? 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 ? 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 ? 9.2 v fxosc cc t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 ? ? v f osc = 16 mhz, oscillator_margin = 1 1.3 ? ? v fxoscop cc p oscillation operating point ? ? 0.95 v i fxosc ,3 3 stated values take into account only analog module cons umption but not the digital contributor (clock tree and enabled peripherals) cc t fast external crystal oscillator consumption ??23ma t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 ?? 6ms f osc = 16 mhz, oscillator_margin = 1 ??1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 ? 0.35v dd v
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 49 4.14 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmp ll) module to generate a fast system clock from the main oscillator driver. 4.15 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast internal rc oscillator. this is used as the default clock at the power-up of the device. table 34. fmpll electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f pllin sr ? fmpll reference clock 3 3 pllin clock retrieved directly from fxosc clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . ?4?48mhz ? pllin sr ? fmpll reference clock duty cycle (3) ?40?60% f pllout cc d fmpll output clock frequency ? 16 ? 48 mhz f vco 4 4 frequency modulation is considered 4%. cc p vco frequency without frequency modulation ? 256 ? 512 mhz vco frequency with frequency modulation ? 245.76 ? 532.48 f cpu sr ? system clock frequency ? ? ? 48 mhz f free cc p free-running frequency ? 20 ? 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) ? 40 100 s ? t ltjit cc ? fmpll long term jitter f pllin = 16 mhz (resonator) , f pllclk at 48 mhz, 4,000 cycles ? ? 10 ns i pll cc c fmpll consumption t a = 25 c ? ? 4 ma table 35. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 i fircrun 3, cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? 10 a
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 50 4.16 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator. this can be used as the reference clock for the rtc module. i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? t fircsu cc c fast internal rc oscillator start-up time t a = 55 c v dd = 5.0 v 10% ? 1.1 2.0 s ?v dd = 3.3 v 10% ? 1.2 tbd ?t a = 125 c v dd = 5.0 v 10% ? ? 2.0 ?v dd = 3.3 v 10% ? ? tbd ? fircpre cc c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1? 1% ? firctrim cc c fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar cc c fast internal rc oscillator variation in temperature and supply with respect to f firc at t a = 55 c in high-frequency configuration ? ? 5? 5% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 36. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150 i sirc 3, cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s table 35. fast internal rc oscillator (16 mhz) electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 51 ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2? 2% ? sirctrim cc c slow internal rc oscillator trimming step ??2.7? ? sircvar cc p slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 ? 10 % 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 36. slow internal rc oscillator (128 khz) electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 52 4.17 adc electrical characteristics 4.17.1 introduction the device provides a 12-bit successive approxima tion register (sar) analog-to-digital converter. figure 11. adc characteristic and error definitions 4.17.2 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 53 possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (f c *c s ), where f c represents the conversion rate at the considered channel). to minimize the error indu ced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ?
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 54 equation 4 generates a constraint for external network design, in pa rticular on a resistive path. internal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 12. input equivalent circui t (precise channels) figure 13. input equivalent circuit (extended channels) r f c f r s r l r sw1 c p2 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 55 a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit in figure 13 ): a charge sharing phenomenon is installed when the sampling phase is st arted (a/d switch close). figure 14. transient behavior during sampling phase in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 2. a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? =
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 56 eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 15. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : ? 2 r l ? c s c p1 c p2 ++ ?? ? ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 57 eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 4.17.3 adc electrical characteristics table 37. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin ? 1 ? na ct a = 25 c ? 1 ? ct a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 38. adc conversion characteristics symbol c parameter conditions 1 value unit min typ max v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) 2 ? ? 0.1 ? 0.1 v v dd_adc sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ?v dd ? 0.1 ? v dd +0.1 v v ainx sr ? analog input voltage 3 ?v ss_adc ? 0.1 ? v dd_adc +0.1 v f adc sr ? adc analog frequency v dd =5.0v 3.33 ? 32 + 4% mhz v dd =3.3v 3.33 ? 20 + 4% ? adc_sys sr ? adc clock duty cycle (ipg_clk) adclksel = 1 4 45 ?55 % t adc_pu sr ? adc power up delay ? ?? 1.5 s v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? ?
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 58 t adc_s cc t sample time 5 v dd = 3.3 v f adc = 20 mhz, inpsamp = 12 600 ? ? ns t sample time 5 v dd = 5.0 v f adc = 32 mhz, inpsamp = 17 500 ? ? t sample time 5 v dd = 3.3 v f adc = 3.33 mhz, inpsamp = 255 ? ? 76.2 s t sample time 5 v dd = 5.0 v f adc = 3.33 mhz, inpsamp = 255 ??76.2 t adc_c cc p conversion time 6 v dd = 3.3 v f adc = 20 mhz, inpcmp = 0 2.4 ? ? s p conversion time 6 v dd = 5.0 v f adc = 13.33 mhz, inpcmp = 0 1.5 ? ? s p conversion time 6 v dd = 3.3 v f adc = 13.33 mhz, inpcmp = 0 ??3.6s p conversion time 6 v dd = 5.0 v f adc = 32 mhz, inpcmp = 0 ??3.6s c s cc d adc input sampling capacitance ? 5 pf c p1 cc d adc input pin capacitance 1 ? 3 pf c p2 cc d adc input pin capacitance 2 ? 1 pf c p3 cc d adc input pin capacitance 3 ? 1.5 pf r sw1 cc d internal resistance of analog source ??? 1 k ? r sw2 cc d internal resistance of analog source ??? 2 k ? r ad cc d internal resistance of analog source ??? 0.3 k ? i inj sr ? input current injection current injection on one adc input, different from the converted one v dd = 3.3 v 10% ? 5? 5 ma v dd = 5.0 v 10% ? 5 ? 5 inlp cc t absolute integral non-linearity-precise channels no overload ?1 3 lsb inlx cc t absolute integral non-linearity-extended channels no overload ?1.5 5 lsb table 38. adc conversion characteristics (continued) symbol c parameter conditions 1 value unit min typ max
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 59 dnl cc t absolute differential non-linearity no overload ?0.5 1 lsb ofs cc t absolute offset error ? ?2 ? lsb gne cc t absolute gain error ? ?2 ? lsb tuep 7 cc p total unadjusted error for precise channels, input only pins without current injection ?6 6 lsb t with current injection ?8 8 tuex 7 cc t total unadjusted error for extended channel without current injection ?10 10 lsb t with current injection ?12 12 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ss_adc and v dd_adc limits, remaining on absolute maximu m ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xfff. 4 duty cycle is ensured by using system clock without prescaling. when adclksel = 0, the duty cycle is ensured by internal divider by 2. 5 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 6 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 7 total unadjusted error: the maximum error that occurs wit hout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 38. adc conversion characteristics (continued) symbol c parameter conditions 1 value unit min typ max
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 60 4.18 on-chip peripherals 4.18.1 current consumption table 39. on-chip peripherals current consumption 1 symbol c parameter conditions value 2 unit typ i dd_bv(can) cc t can (flexcan) supply current on v dd_bv 500 kbps total (static + dynamic) consumption: ? flexcan in loop-back mode ? xtal at 8 mhz used as can engine clock source ? message sending period is 580 s 8 * f periph + 85 a 125 kbps 8 * f periph + 27 i dd_bv(emios) cc t emios supply current on v dd_bv static consumption: ? emios channel off ? global prescaler enabled 29 * f periph dynamic consumption: ? it does not change varying the frequency (0.003 ma) 3 i dd_bv(sci) cc t sci (linflex) supply current on v dd_bv total (static + dynamic) consumption: ? lin mode ? baudrate: 20 kbps 5 * f periph + 31 i dd_bv(spi) cc t spi (dspi) supply current on v dd_bv ballast static consumption (only clocked) 1 ballast dynamic consumption (continuous communication): ? baudrate: 2 mbit ? transmission every 8 s ? frame: 16 bits 16 * f periph i dd_bv(adc) cc t adc supply current on v dd_bv v dd = 5.5 v ballast st atic consumption (no conversion) 41 * f periph a v dd = 5.5 v ballast dynamic consumption (continuous conversion) 3 5 * f periph i dd_hv_adc(adc) cc t adc supply current on v dd_hv_adc v dd = 5.5 v analog static consumption (no conversion) 2 * f periph v dd = 5.5 v analog dynamic consumption (continuous conversion) 75 * f periph + 32 i dd_hv(flash) cc t cflash + dflash supply current on v dd_hv v dd = 5.5 v ? tbd i dd_hv(pll) cc t pll supply current on v dd_hv v dd = 5.5 v ? 30 * f periph
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 61 1 operating conditions: t a = 25 c, f periph = 8 mhz to 48 mhz 2 f periph is in absolute value. 3 during the conversion, the total current consumption is gi ven from the sum of the stat ic and dynamic consumption, i.e., (41 + 5) * f periph
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 62 4.18.2 dspi characteristics table 40. dspi characteristics 1 1 operating conditions: c out = 10 to 50 pf, slew in = 3.5 to 15 ns. no. symbol c parameter dspi0/dspi1 unit min typ max 1t sck sr d sck cycle time master mode (mtfe = 0) 125 ? ? ns d slave mode (mtfe = 0) 125 ? ? d master mode (mtfe = 1) 83 ? ? d slave mode (mtfe = 1) 83 ? ? ?f dspi sr d dspi digital controller frequency ? ? f cpu mhz ? ? t csc cc d internal delay between pad associated to sck and pad associated to csn in master mode master mode ? ? 130 2 2 maximum is reached when csn pad is configured as slow pad while sck pad is configured as medium pad. ns ? ? t asc cc d internal delay between pad associated to sck and pad associated to csn in master mode for csn1 ? 1 master mode ? ? 130 (2) ns 2t cscext 3 3 the t csc delay value is configurable through a register. when configuring t csc (using pcssck and cssck fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t csc to ensure positive t cscext . sr d cs to sck delay slave mode 32 ? ? ns 3t ascext 4 sr d after sck delay slave mode 1/f dspi + 5 ? ? ns 4t sdc cc d sck duty cycle master mode ? t sck /2 ? ns sr d slave mode t sck /2 ? ? 5t a sr d slave access time ? 1/f dspi +70 ? ? ns 6t di sr d slave sout disable time ? 7 ? ? ns 9t sui sr d data setup time for inputs master mode 43 ? ? ns slave mode 5 ? ? 10 t hi sr d data hold time for inputs master mode 0 ? ? ns slave mode 2 5 ?? 11 t suo 6 cc d data valid after sck edge master mode ? ? 32 ns slave mode ? ? 52 12 t ho (6) cc d data hold time for outputs master mode 0 ? ? ns slave mode 8 ? ?
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 63 4 the t asc delay value is configurable through a register. when configuring t asc (using pasc and asc fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than ? t asc to ensure positive t ascext . 5 this delay value corresponds to smpl_pt = 00b which is bit field 9 and 8 of dspi_mcr register. 6 sck and sout configured as medium pad
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 64 figure 16. dspi classic spi timing ? master, cpha = 0 figure 17. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta b l e 4 0 . data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 0 .
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 65 figure 18. dspi classic spi timing ? slave, cpha = 0 figure 19. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 0 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 0 .
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 66 figure 20. dspi modified transfer format timing ? master, cpha = 0 figure 21. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 0 . pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 0 .
electrical characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 67 figure 22. dspi modified transfer format timing ? slave, cpha = 0 figure 23. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference ta b l e 4 0 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 0 .
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice electrical characteristics freescale semiconductor 68 4.18.3 jtag characteristics figure 24. timing diagram ? jtag boundary scan table 41. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 83.33 ? ? ns 2t tdis cc d tdi setup time 15 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 15 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns 6t tdov cc d tck low to tdo valid ? ? 49 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference ta bl e 4 1 . 3/5 2/4 7 6
package characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 69 5 package characteristics 5.1 package mechanical data 5.1.1 100 lqfp mechanical outline drawing
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package characteristics freescale semiconductor 70 figure 25. 100 lqfp package mechanical drawing (part 1 of 3)
package characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 71 figure 26. 100 lqfp package mechanical drawing (part 2 of 3) 2
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package characteristics freescale semiconductor 72 figure 27. 100 lqfp package mechanical drawing (part 3 of 3)
package characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 73 5.1.2 64 lqfp mechanical outline drawing figure 28. 64 lqfp package mechanical drawing (part 1 of 3)
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice package characteristics freescale semiconductor 74 figure 29. 64 lqfp package mechanical drawing (part 2 of 3)
package characteristics mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 75 figure 30. 64 lqfp package mechanical drawing (part 3 of 3)
mpc5602d microcontroller data sheet, rev. 3.1 preliminary?subject to change without notice ordering information freescale semiconductor 76 6 ordering information figure 31. commercial product code structure qualification status power architecture core automotive platform core version flash size (core dependent) product fab and mask indicator mpc56 demll example code: 02 temperature spec. package code qualification status m = mc status s = auto qualified p = pc status automotive platform 56 = power architecture in 90 nm core version 0 = e200z0 flash size (z0 core) 1= 128 kb 2 = 256 kb product d = access family fab and mask indicator e = data flash (blank if none) r = tape & reel (blank if tray) r temperature spec. c = ?40 to 85 c v = ?40 to 105 c m = ?40 to 125 c package code lh = 64 lqfp ll = 100 lqfp
document number: mpc5602d rev. 3.1 02/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org ? freescale semiconductor, inc. 2009, 2010. all rights reserved. preliminary?subject to change without notice

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