 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| NX2309 1 rev. 2.0 12/19/05 typical application description the NX2309 controller ic is a combination synchronous buck and ldo controller ic designed to convert single 12v supply to low cost dual on board supply applica- tions. the synchronous controller is used for high cur- rent high efficiency step down dc to dc converter appli- cations while the ldo controller in conjunction with an external low cost n ch mosfet can be used as a very low drop out regulator in applications such as converting 3.3v to 2.5v output. internal uvlo keeps both regula- tors off until the supply voltage exceeds 9v where inde- pendent internal digital soft starts get initiated to ramp up both outputs.the switching section has fixed hiccup current limit by sensing the rdson of synchronous mosfet. the ldo controller has feedback under voltage lock out as a short circuit protection.other fea- tures includes: 12v gate drive capability , adaptive dead band control. n 12v pwm controller plus ldo controller n fixed hiccup current limit by sensing rdson of mosfet n 12v high side and low side driver n fixed internal 300khz for switching controller n dual independent digital soft start function n adaptive deadband control n shut down switching via pulling down comp pin n pb-free and rohs compliant ordering information features single supply 12v synchronous pwm controller with nmos ldo controller applications n pci graphic card on board converters n mother board on board dc to dc applications n on board single supply 12v dc to dc such as 12v to 3.3v, 2.5v or 1.8v n set top box and lcd display preliminary data sheet evaluation board available. figure1 - typical application of NX2309 150pf c10 150uf 25mohm c8 47uf c9 n x 2 3 0 9 +1.2v/2a vout2 +1.8v vout1 r8 5k 10k r9 m3 irfr3706 1uf c12 gnd ldo fb ldo out vcc c5 6.8nf c3 c2 d1 mbr0530t1 r4 8k c6 r2 2.7nf +12v vin1 +1.8v/10a vout1 r3 10k 47uf 180uf r5 5.36k l1 1uh 0.1uf c4 c7 l2 1.5uh m2 irfr3709z m1 irfr3709z bst fb comp sw hdrv ldrv 1.43k 10 r14 c13 200pf 4sepc560m 560uf,7mohm device temperature package frequency pb-free NX2309cutr 0 to 70 o c msop - 10l 300khz yes NX2309cmtr 0 to 70 o c mlpd - 10l 300khz yes pb free product
NX2309 2 rev. 2.0 12/19/05 absolute maximum ratings (note1) vcc to pgnd & bst to sw voltage .................... -0.3v to 16v bst to pgnd voltage ...................................... -0.3v to 35v sw to pgnd .................................................... -2v to 35v all other pins .................................................... -0.3v to 6.5v storage temperature range ............................... -65 o c to 150 o c operating junction temperature range ............... -40 o c to 125 o c caution: stresses above those listed in "absolute maximum ratings", may cause permanent damage to the device. this is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. package information 10-lead plastic msop 10-lead plastic mlpd electrical specifications unless otherwise specified, these specifications apply over vcc =12v, v bst -v sw =12v, and t a = 0 to 70 o c . typical values refer to t a = 25 o c . q?200/ o ja cw 4 3 2 1 7 8 9 10 bst ldrv gnd hdrv ldo_fb fb comp sw 5 vcc 6 ldo_out 7 8 9 10 4 3 2 1 bst nc gnd (pad) hdrv ldo_out ldo_fb fb sw 6 vcc 5 comp ldrv q?52/ o ja cw parameter sym test condition min typ max units reference voltage ref voltage v ref 0.8 v ref voltage line regulation 10v<=vcc<=14v 0.2 % supply voltage(vcc) v cc voltage range v cc 7 14 v v cc supply current (dynamic) i cc (dynamic) c l =3300pf 17 ma supply voltage(v bst) v bst voltage range v bst to v sw 7 14 v v bst supply current v bst (dynamic) c l =3300pf 12 ma under voltage lockout v cc -threshold v cc _uvlo v cc rising 6.6 v v cc -hysteresis v cc _hyst v cc falling 0.3 v v cc supply current (static) i cc (static) ma outputs not switching 5 NX2309 3 rev. 2.0 12/19/05 n parameter sym test condition min typ max units oscillator frequency f s 300 khz ramp-amplitude voltage v ramp 1.1 v max duty cycle 95 % min duty cycle 0 % error amplifiers open loop gain 50 65 db transconductance gm 2000 umho input bias current ib 100 na en & ss soft start time tss 6.8 ms comp sd threshold 0.2 v high side driver, hdrv, bst, sw (c l =3300pf) rise time thdrv(rise) 10% to 90% 30 ns fall time thdrv(fall) 90% to 10% 20 ns low side driver , ldrv, pvcc, pgnd(c l =3300pf) output impedance, sourcing current r source (ldrv) i=200ma 2.2 ohm output impedance, sinking current r sink (ldrv) i=200ma 1 ohm rise time tldrv(rise) 10% to 90% 30 ns fall time tldrv(fall) 90% to 10% 20 ns ldo controller fb pin- bias current 100 na high output voltage 11.1 v low output voltage 0.2 v high output source current 1.9 ma low output sink current 0.9 ma open loop gain gbnt(note 2) 50 db fb under voltage trip point 50 % fixed ocp ocp voltage threshold 240 mv output impedance , sourcing current r source (hdrv) i=200ma tdead(l to h) deadband time ldrv going low to hdrv going high, 10% to 10% deadband time tdead(h to l) sw going low to ldrv going high, 10% to 10% 50 ns 50 ns ohm 3.6 1 ohm output impedance , sinking current r sink (hdrv) i=200ma NX2309 4 rev. 2.0 12/19/05 pin descriptions pin # pin symbol pin description power supply voltage. a high freq 1uf ceramic capacitor is placed as close as possible to and connected to this pin and ground pin. the maximum rating of this pin is 16v. this pin supplies voltage to high side fet driver. a high freq 0.1uf ceramic capacitor is placed as close as possible to and connected to this pin and sw pin. power ground. this pin is the error amplifiers inverting input. this pin is connected via resistor divider to the output of the switching regulator to set the output dc voltage. this pin is the output of the error amplifier and together with fb pin is used to compensate the voltage control feedback loop. this pin is also used as a shut down pin. when this pin is pulled below 0.2v, both drivers are turned off and internal soft start is reset. this pin is connected to source of high side fets and provide return path for the high side driver. it is also used to hold the low side driver low until this pin is brought low by the action of high side turning off. ldrv can only go high if sw is below 1v threshold . high side gate driver output. low side gate driver output. ldo controller feedback input. this pin is connected via resistor divider to the out- put of the switching regulator to set the output dc voltage.if the ldofb pin is pulled below 0.4v, an internal comparator after a delay pulls down ldoout pin and ini- tiates the hiccup circuitry. during the startup this latch is not activated, allowing the ldofb pin to come up and follow the soft started vref voltage. ldo controller output. this pin is controlling the gate of an external nch mosfet. the maximum rating of this pin is 16v. 5 1 3 8 9 10 2 4 6 7 vcc bst gnd fb comp sw hdrv ldrv ldo_fb ldo_out note1: in actual circuit application, the ensw pin is used to program converter start up and hysteresis threshold voltage. note2: this parameter is guaranteed by design but not tested in production(gbnt). NX2309 5 rev. 2.0 12/19/05 bias generator 1.25v 0.8v bst hdrv sw ldrv fb comp osc r s q digital start up uvlo por gnd control logic ocp comparator vcc ramp ldo digital start up ldoout ldofb por 0.4 bias regulator 0.2v comp oc start start hiccup logic oc 1.3v clamp 0.6v clamp start pwm 0.8v 240mv vcc 7.2/6.8v block diagram figure 2 - simplified block diagram of the NX2309 NX2309 6 rev. 2.0 12/19/05 application information symbol used in application information: v in - input voltage v out - output voltage i out - output current d v ripple - output voltage ripple f s - switching frequency d i ripple - inductor current ripple design example power stage design requirements: v in =12v v out =1.8v i out =10a d v ripple <=25mv d v tran <=100mv @ 5a step f s =300khz output inductor selection the selection of inductor value is based on induc- tor ripple current, power rating, working frequency and efficiency. larger inductor value normally means smaller ripple current. however if the inductance is chosen too large, it brings slow response and lower efficiency. usu- ally the ripple current ranges from 20% to 40% of the output current. this is a design freedom which can be decided by design engineer according to various appli- cation requirements. the inductor value can be calcu- lated by using the following equations: inout out out rippleins rippleoutput v-vv 1 l= ivf i=ki ...(1) where k is between 0.2 to 0.4. select k=0.4, then out out 12v-1.8v1.8v1 l= 0.410a12v300khz l=1.3uh choose l out =1.5uh, then coilcraft inductor do5010p-152hc is a good choice. current ripple is calculated as = inout out ripple outins v-vv 1 i= lvf 12v-1.8v1.8v1 =3.4a 1.5uh12v300khz ...(2) output capacitor selection output capacitor is basically decided by the amount of the output voltage ripple allowed during steady state(dc) load condition as well as specification for the load transient. the optimum design may require a couple of iterations to satisfy both condition. based on dc load condition the amount of voltage ripple during the dc load condition is determined by equation(3). d d=d+ ripple rippleripple sout i vesri 8fc ...(3) where esr is the output capacitors' equivalent series resistance,c out is the value of output capacitors. typically when large value capacitors are selected such as aluminum electrolytic,poscap and oscon types are used, the amount of the output voltage ripple is dominated by the first term in equation(3) and the second term can be neglected. for this example, oscon are chosen as output capacitors, the esr and inductor current typically de- termines the output voltage ripple. d ==w d ripple desire ripple v 25mv esr=7.3m i3.4a ...(4) if low esr is required, for most applications, mul- tiple capacitors in parallel are better than a big capaci- tor. for example, for 25mv output ripple, oscon 4sepc560m with 7m w are chosen. eripple ripple esri n v d = d . ..(5) number of capacitor is calculated as w = 7m3.4a n 25mv n =0.95 the number of capacitor has to be round up to a integer. choose n =1. NX2309 7 rev. 2.0 12/19/05 if ceramic capacitors are chosen as output ca- pacitors, both terms in equation (3) need to be evalu- ated to determine the overall ripple. usually when this type of capacitors are selected, the amount of capaci- tance per single unit is not sufficient to meet the tran- sient specification, which results in parallel configura- tion of multiple capacitors. for example, one 100uf, x5r ceramic capacitor with 2m w esr is used . the amount of output ripple is d=w+ =+= ripple 3.4a v2m3.4a 8300khz100uf 6.8mv14.1mv20.9mv although this meets dc ripple spec, however it needs to be studied for transient requirement. based on transient requirement typically, the output voltage droop during transient is specified as d v droop d v tran < @step load d i step during the transient, the voltage droop during the transient is composed of two sections. one section is dependent on the esr of capacitor, the other section is a function of the inductor, output capacitance as well as input, output voltage. for example, for the over- shoot when load from high load to light load with a d i step transient load, if assuming the bandwidth of system is high enough, the overshoot can be esti- mated as the following equation. 2 out overshootstep out v vesri 2lc d=d+t ...(6) where t is the a function of capacitor,etc. crit step outcrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(7) where outouteeout crit stepstep esrcvesrcv l ii == dd ...(8) where esr e and c e represents esr and capaci- tance of each capacitor if multiple capacitors are used in parallel. the above equation shows that if the selected out- put inductor is smaller than the critical inductance, the voltage droop or overshoot is only dependent on the esr of output capacitor. for low frequency capacitor such as electrolytic capacitor, the product of esr and ca- pacitance is high and crit ll is true. in that case, the transient spec is mostly like to dependent on the esr of capacitor. most case, the output capacitor is multiple capaci- tor in parallel. the number of capacitor can be calcu- lated by the following estep 2 out tranetran esri v n v2lcv d =+t dd ...(9) where crit step eecrit out 0ifll li esrcifll v ? d t= -3 ? ? ...(10) for example, assume voltage droop during tran- sient is 100mv for 5a load step. if the oscon 4sepc560m (560uf, 7mohm esr) is used, the crticial inductance is given as eeout crit step esrcv l i 7m560f1.8v 1.42h 5a == d wm =m the selected inductor is 1.5uh which is bigger than critical inductance. in that case, the output voltage tran- sient not only dependent on the esr, but also capaci- tance. number of capacitor is step ee out li esrc v 1.5h5a 7m560f0.25us 1.8v d t=- m =-wm= estep 2 out tranetran 2 esri v n v2lcv 7m5a1.8v (0.25us) 100mv21.5h560f100mv 0.35 d =+t dd w =+ mm = NX2309 8 rev. 2.0 12/19/05 the number of capacitors has to satisfied both ripple and transient requirement. overall, we choose n=1. it should be considered that the proposed equa- tion is based on ideal case, in reality, the droop or over- shoot is typically more than the calculation. the equa- tion gives a good start. for more margin, more capaci- tors have to be chosen after the test. typically, for high frequency capacitor such as high quality poscap es- pecially ceramic capacitor, 20% to 100% (for ceramic) more capacitors have to be chosen since the esr of capacitors is so low that the pcb parasitic can affect the results tremendously. more capacitors have to be selected to compensate these parasitic parameters. compensator design due to the double pole generated by lc filter of the power stage, the power system has 180 o phase shift , and therefore, is unstable by itself. in order to achieve accurate output voltage and fast transient response, compensator is employed to provide highest possible bandwidth and enough phase margin. ideally, the bode plot of the closed loop system has crossover frequency between 1/10 and 1/5 of the switching frequency, phase margin greater than 50 o and the gain crossing 0db with - 20db/decade. power stage output capacitors usually decide the compensator type. if electrolytic capacitors are chosen as output capacitors, type ii compensator can be used to compensate the system, because the zero caused by output capacitor esr is lower than cross- over frequency. otherwise type iii compensator should be chosen. a. type iii compensator design for low esr output capacitors, typically such as sanyo oscap and poscap, the frequency of esr zero caused by output capacitors is higher than the cross- over frequency. in this case, it is necessary to compen- sate the system with type iii compensator. the follow- ing figures and equations show how to realize the type iii compensator by transconductance amplifier. = p = p+ = p = p + z1 42 z2 233 p1 33 p2 12 4 12 1 f ...(11) 2rc 1 f ...(12) 2(rr)c 1 f ...(13) 2rc 1 f ...(14) cc 2r cc where f z1 ,f z2 ,f p1 and f p2 are poles and zeros in the compensator. the transfer function of type iii compensator for transconductance amplifier is given by: e mf out minin1 v 1gz v1gzz/r - = ++ for the voltage amplifier, the transfer function of compensator is e f out in v z vz - = to achieve the same effect as voltage amplifier, the compensator of transconductance amplifier must satisfy this condition: r4>>2/gm. and it would be desir- able if r1||r2||r3>>1/gm can be met at the same time, zin zf vout vref fb r2 r1 r3 r4 c3 c1 c2 ve gm figure 3 - type iii compensator using transconductance amplifier NX2309 9 rev. 2.0 12/19/05 case 1: f lc NX2309 12 rev. 2.0 12/19/05 = p = p = lc outout 1 f 2lc 1 21.5uh4500uf 1.94khz = p = pw = esr out 1 f 2esrc 1 26.33m4500uf 5.6khz 2.set crossover frequency f o =30khz>>f esr . 3. set r 2 equal to10k w . based on output voltage, using equation 21, the final selection of r 1 is 20k w. 4.calculate r 3 value by the following equation. p p w w w osco 32 in v2fl r=r vesr 1.1v230khz1.5uh =10k 12v6.33m =37.2k choose r 3 =37.4k w. 5. calculate c 1 by setting compensator zero f z at 75% of the lc double pole. p pw 1 3z 1 c= 2rf 1 = 237.4k0.751.94khz =2.9nf choose c 1 =2.7nf. 6. calculate c 2 by setting compensator pole p f at half the swithing frequency. p pw 2 3s 1 c= rf 1 = 37.4k150khz =57pf choose c 2 =56pf. case 2: type ii compensator can also be realized by simple rc circuit without feedback as shown in figure 15. r 3 and c 1 introduce a zero to cancel the double pole effect. c 2 introduces a pole to suppress the switching noise. the following equations show the compensator pole zero location and constant gain. 1 m3 12 z 31 p 32 r gain=gr ... (18) r+r 1 f= ... (19) 2rc 1 f ... (20) 2rc p ? p gm r3 c1 c2 ve vout vref fb r2 r1 figure 8 - type ii compensator with transconductance amplifier(case 2) the following is parameters for type ii compensa- tor design. input voltage is 12v, output voltage is 2.5v, output inductor is 2.2uh, output capacitors are two 680uf with 41m w electrolytic capacitors. see figure 20. 1.calculate the location of lc double pole f lc and esr zero f esr . = p = p = lc outout 1 f 2lc 1 22.2uh1360uf 2.9khz NX2309 13 rev. 2.0 12/19/05 = p = pw = esr out 1 f 2esrc 1 220.5m1360uf 5.7khz 2.set r 2 equal to10k w . using equation 18, the fi- nal selection of r 1 is 4.7k w. 3. set crossover frequency at 1/10~ 1/5 of the swithing frequency, here f o =30khz. 4.calculate r 3 value by the following equation. p p w w oscoout 3 inesrmref v2flv 1 r= vrgv 1.1v230khz2.2uh1 = 1220.5m2ma/v 2.5v 0.8v =2.9k choose r 3 =2.87k w . 5. calculate c 1 by setting compensator zero f z at 75% of the lc double pole. p pw 1 3z 1 c= 2rf 1 = 22.87k0.752.9khz =25nf choose c 1 =27nf. 6. calculate c 2 by setting compensator pole p f at half the swithing frequency. p pw 2 3s 1 c= rf 1 = 2.87k150khz =369pf choose c 2 =390pf. output voltage calculation output voltage is set by reference voltage and ex- ternal voltage divider. the reference voltage is fixed at 0.8v. the divider consists of two ratioed resistors so that the output voltage applied at the fb pin is 0.8v when the output voltage is at the desired value. the following equation applies to figure 9, which shows the relation- ship between out v , ref v and voltage divider. . vout vref fb r2 r1 figure 9 - voltage divider 2ref 1 out ref rv r= v-v ...(21) where r 2 is part of the compensator, and the value of r 1 value can be set by voltage divider. see compensator design for r 1 and r 2 selection. input capacitor selection input capacitors are usually a mix of high frequency ceramic capacitors and bulk capacitors. ceramic ca- pacitors bypass the high frequency noise, and bulk ca- pacitors supply switching current to the mosfets. usu- ally 1uf ceramic capacitor is chosen to decouple the high frequency noise.the bulk input capacitors are de- cided by voltage rating and rms current rating. the rms current in the input capacitors can be calculated as: rmsout out in iid1-d v d v = = ...(22) v in = 12v, v out =1.8v, i out =10a, using equation (19), the result of input rms current is 3.6a. for higher efficiency, low esr capacitors are recommended. one sanyo os-con 16svp180m 16v 180uf 20m w with 3.64a rms rating are chosen as input bulk capacitors. NX2309 14 rev. 2.0 12/19/05 power mosfets selection the NX2309 requires two n-channel power mosfets. the selection of mosfets is based on maximum drain source voltage, gate source voltage, maximum current rating, mosfet on resistance and power dissipation. the main consideration is the power loss contribution of mosfets to the overall converter efficiency. in this design example, two irfr3706 are used. they have the following parameters: v ds =30v, i d =75a,r dson =9m w ,q gate =23nc. there are two factors causing the mosfet power loss:conduction loss, switching loss. conduction loss is simply defined as: - + 2 hconoutds(on) 2 lconoutds(on) totalhconlcon p=idrk p=i(1d)rk p=pp ...(23) where the r ds(on) will increases as mosfet junc- tion temperature increases, k is r ds(on) temperature dependency. as a result, r ds(on) should be selected for the worst case, in which k approximately equals to 1.4 at 125 o c according to irfr3706 datasheet. conduction loss should not exceed package rating or overall sys- tem thermal budget. switching loss is mainly caused by crossover conduction at the switching transition. the total switching loss can be approximated. swinoutsws 1 pvitf 2 = . ..(24) and t f which can be found in mosfet datasheet, and f s is switching frequency. swithing loss p sw is frequency dependent. also mosfet gate driver loss should be consid- ered when choosing the proper power mosfet. mosfet gate driver loss is the loss generated by dis- charg i ng the gate capacitor and is dissipated in driver circuits.it is proportional to frequency and is defined as: gatehgatehgslgatelgss p(qvqv)f =+ ...(25) where q hgate is the high side mosfets gate charge,q lgate is the low side mosfets gate charge,v hgs is the high side gate source voltage, and v lgs is the low side gate source voltage. this power dissipation should not exceed maxi- mum power dissipation of the driver device. over current limit protection over current limit for step down converter is achieved by sensing current through the low side mosfet. for NX2309, the current limit is decided by the r dson of the low side mosfet. when synchronous fet is on, and the voltage on sw pin is below 240mv, the over current occurs. the over current limit can be calculated by the following equation. = setdson i240mv/r the mosfet r dson is calculated in the worst case situation, then the current limit for mosfet irfr3706 is === w set dson 240mv240mv i17a r1.49m ldo selection guide NX2309 offers a ldo controller. the selection of mosfet to meet ldo is more straight forward. the selection is that the rdson of mosfet should meet the dropout requirement. for example. v ldoin =1.8v v ldoout =1.2v i load =2a the maximum rdson of mosfet should be rdsonldoinldooutload r(vv)i (1.8v1.2v)/2a0.3 =- =-=w most of mosfets can meet the requirement. more important is that mosfet has to be selected right pack- age to handle the thermal capability. for ldo, maxi- mum power dissipation is given as lossldoinldooutload p(vv)i (1.8v1.2v)2a1.2w =- =-= select ir mosfet irfr3706 with 9m w r dson is sufficient. ldo compensation the diagram of ldo controller including vcc regu- lator is shown in above figure 9. for low frequency ca- NX2309 15 rev. 2.0 12/19/05 pacitor such as electrolytic, poscap, oscon, etc, the compensation parameter can be calculated as follows. m c of1m gesr 1 c= 2fr1+gesr p where f o is the desired loop gain. r r rc cc + ldo input rload esr co vref f1 f2 figure 10 - NX2309 ldo controller. typically, f o has to be higher than zero caused by esr. f o is typically around several tens khz to a few hundred khz. for this example, we select fo=100khz. g m is the forward trans-conductance of mosfet. for irfr3706, g m =53. select r f1 =5kohm. output capacitor is sanyo poscap 4tpe150mi with 150uf, esr=18mohm. c 15318m c= =155pf 2100khz5k1+5318m w pww choose c c =150pf. for electrolytic or poscap, r c is typically selected to be zero. r f2 is determined by the desired output voltage f2f1refldooutref rrv/(vv) 5k0.8v/(1.2v0.8)10k =- =w-=w choose r f2 =10k w. current limit for ldo current limit of ldo is achieved by sensing the ldo feedback voltage. when ldo_fb pin is below 0.4v, the ic goes into hiccup mode. the ic will turn off all the channel for 2048 cycles and start to restart system again. layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. there are two sets of components considered in the layout which are power components and small sig- nal components. power components usually consist of input capacitors, high-side mosfet, low-side mosfet, inductor and output capacitors. a noisy environment is generated by the power components due to the switch- ing power. small signal components are connected to sensitive pins or nodes. a multilayer layout which in- cludes power plane, ground plane and signal plane is recommended . layout guidelines: 1. first put all the power components in the top layer connected by wide, copper filled areas. the input capacitor, inductor, output capacitor and the mosfets should be close to each other as possible. this helps to reduce the emi radiated by the power loop due to the high switching currents through them. 2. low esr capacitor which can handle input rms ripple current and a high frequency decoupling ceramic cap which usually is 1uf need to be practically touch- ing the drain pin of the upper mosfet, a plane connec- tion is a must. 3. the output capacitors should be placed as close as to the load as possible and plane connection is re- quired. 4. drain of the low-side mosfet and source of the high-side mosfet need to be connected thru a plane ans as close as possible. a snubber nedds to be placed as close to this junction as possible. 5. source of the lower mosfet needs to be con- nected to the gnd plane with multiple vias. one is not enough. this is very important. the same applies to the output capacitors and input capacitors. 6. hdrv and ldrv pins should be as close to mosfet gate as possible. the gate traces should be wide and short. a place for gate drv resistors is needed to fine tune noise if needed. NX2309 16 rev. 2.0 12/19/05 7. vcc capacitor, bst capacitor or any other by- passing capacitor needs to be placed first around the ic and as close as possible. the capacitor on comp to gnd or comp back to fb needs to be place as close to the pin as well as resistor divider. 8. the output sense line which is sensing output back to the resistor divider should not go through high frequency signals. 9. all gnds need to go directly thru via to gnd plane. 10. the feedback part of the system should be kept away from the inductor and other noise sources, and be placed close to the ic. 11. in multilayer pcb, separate power ground and analog ground. these two grounds must be connected together on the pc board layout at a single point. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive ana- log control function. |
Price & Availability of NX2309
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |