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june 2006 rev 2 1/43 1 STW81102 multi-band rf frequency synth esizer with integrated vcos feature summary integer-n frequency synthesizer dual differential integrated vcos with automatic center frequency calibration: ? 3000 - 3620 mhz (direct output) ? 4000 - 4650 mhz (direct output) ? 1500 - 1810 mhz (internal divider by 2) ? 2000 - 2325 mhz (internal divider by 2) ? 750 - 905 mhz (internal divider by 4) ? 1000 - 1162.5 mhz (internal divider by 4) excellent integrated phase noise fast lock time: 150s dual modulus programmable prescaler (16/17 or 19/20) 2 programmable counters to achieve a feedback division ratio from 256 to 65551 (prescaler 16/17) and from 361 to 77836 (prescaler 19/20). programmable reference frequency divider (10 bits) phase frequency comparator and charge pump programmable charge pump current digital lock detector dual digital bus interface: spi and i 2 c bus with 3 bit programmable address (1100a 2 a 1 a 0 ) 3.3v power supply power down mode (hw and sw) small size exposed pad vfqfpn28 package 5x5x1.0mm process: bicmos 0.35m sige applications 2.5g and 3g cellular infrastructure equipment catv equipment instrumentation and test equipment other wireless communication systems description the stmicroelectronics STW81102 is an integrated rf synthesizer with voltage controlled oscillators (vcos). showing high performance, high integration, low power, and multi-band performances, STW81102 is a low cost one chip alternative to discrete pll and vcos solutions. STW81102 includes an integer-n frequency synthesizer and two fully integrated vcos featuring low phase noise performance and a noise floor of -155dbc/hz. the combination of wide frequency range vcos (thanks to center- frequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover from 750mhz to 905mhz and 1000mhz to 1162.5mhz, from 1500mhz to 1810mhz and 2000mhz to 2325mhz, from 3000mhz to 3620mhz and 4000mhz to 4650mhz bands. the STW81102 is designed with stmicroelectronics advanced 0.35m sige process. order codes vfqfpn28 part number temp range, cpackage packing STW81102at -40 to 85 vfqfpn28 tray STW81102atr -40 to 85 vfqfpn28 tape & reel www.st.com
contents STW81102 2/43 contents 1 block diagram and pin co nfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.1 reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.2 reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.3 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1.4 a and b counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.5 phase frequency detector (pfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.6 lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.7 charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.8 voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 vco selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 vco frequency calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 vco voltage amplitude control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5i 2 c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.1 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.2 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.3 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1.4 byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.5 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STW81102 contents 3/43 5.1.6 single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.7 multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.8 current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 i 2 c registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.1 functional_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3.2 b_counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.3 a_counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.4 ref_divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.5 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3.6 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.7 read-only register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.3.8 default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.4 vco calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 spi digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2 timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.3 bits table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3.1 default configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.4 vco calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 direct output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 divided by 2 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 divided by 4 output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.4 evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
list of tables STW81102 4/43 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. operating conditions (refer to application diagram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 7. current value vs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. vco a performances vs. amplitude setting (freq=3.3ghz). . . . . . . . . . . . . . . . . . . . . . . . 21 table 9. vco b performances vs. amplitude setting (freq=4.3ghz). . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11. multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13. data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14. start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15. acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16. write-only registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17. different functional mode of the functional_mode register . . . . . . . . . . . . . . . . . . . . 26 table 18. spi data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 19. address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 20. spi timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 21. bits (serial interface address = 00h; register name = st1) . . . . . . . . . . . . . . . . . . . . . . . 32 table 22. bits (serial interface address = 01h; register name = st2) . . . . . . . . . . . . . . . . . . . . . . . 33 table 23. order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 24. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
STW81102 list of figures 5/43 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. vco a (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. vco b (direct output) open loop phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. vco a (direct output) closed loop phase noise at 3.6ghz . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. vco b (direct output) closed loop phase noise at 4.3ghz . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 7. vco a (div. by 2 output) closed loop phase noise at 1.65ghz . . . . . . . . . . . . . . . . . . . . . 15 figure 8. vco b (div. by 2 output) closed loop phase noise at 2.15ghz . . . . . . . . . . . . . . . . . . . . . 15 figure 9. vco a (div. by 4 output) closed loop phase noise at 825mhz . . . . . . . . . . . . . . . . . . . . . 15 figure 10. vco b (div. by 4 output) closed loop phase noise at 1.075ghz . . . . . . . . . . . . . . . . . . . . 15 figure 11. pfd frequency spurs (direct output; f pfd =200khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. pfd frequency spurs (div. by 2 output; f pfd =400khz) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 13. pfd frequency spurs (div. by 4 output; f pfd =800khz) . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 14. settling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 15. reference frequency input buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. vco divider diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 17. pfd diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18. loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 19. vco sub-bands frequency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 20. data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 21. start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 22. byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 23. data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 24. start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 25. acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 26. spi input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 27. spi timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 28. differential/single ended output network in the 3.0 - 4.65ghz range . . . . . . . . . . . . . . . . . 35 figure 29. lc lumped balun and matching network (match_lc_lump_4g.dsn) . . . . . . . . . . . . . . 36 figure 30. evaluation board (evb4g) matching network (match_evb4g.dsn) . . . . . . . . . . . . . . . . 36 figure 31. differential/single ended output network in the 1.5 - 2.325ghz range . . . . . . . . . . . . . . . . 37 figure 32. lc lumped balun for divided by 2 output (match_lc_lump_2g.dsn) . . . . . . . . . . . . . . 37 figure 33. evaluation board (evb2g) matching network (match_evb2g.dsn) . . . . . . . . . . . . . . . 38 figure 34. lc lumped balun for the divided by 4 output (match_lc_lump_1g.dsn) . . . . . . . . . . . 38 figure 35. evaluation board (evb1g) matching network (match_evb1g.dsn) . . . . . . . . . . . . . . . 39 figure 36. application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 37. vfqfpn28 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
block diagram and pin configuration STW81102 6/43 1 block diagram and pin configuration 1.1 block diagram figure 1. block diagram vco buff vdd_vcoa vctrl extvco_inn extvco_inp div 4 div 2 di v 4 bu f di v 2 bu f ext vco buf vss_vcoa vdd_vcob vss_vcob vdd_bufvco vss_bufvco vdd_outbuf vss_outbuf vdd_div4 vss_div4 vdd_div2 vss_div2 vdd_esd vss_esd add0 / load add1 add2 vdd_dbus vss_dbus vco divider ref divider buf p f d c p up dn icp lock_det buf vdd_cp vss_cp dbus sda / data scl / clk dbus_sel vco calibrator vc o b uf test1 ext_pd test2 outbufp outbufn ref_clk vdd_pll vss_pll rext
STW81102 block diagram and pin configuration 7/43 1.2 pin configuration figure 2. pin connection (top view) table 1. pin description pin no name description observation 1 vdd_vcoa vcoa power supply 2 vdd_div2 divider by 2 power supply 3 vdd_outbuf output buffer power supply 4 outbufp lo buffer posit ive output open collector 5 outbufn lo buffer negative output open collector 6 vdd_div4 divider by 4 power supply 7 vdd_vcob vcob power supply 8 vdd_esd esd positive rail power supply 9 vctrl vco control voltage 10 icp pll charge pump output 11 rext external resistance connection for pll charge pump 12 vdd_cp power supply for charge pump 13 test1 test input 1 test purpose only; must be connected to gnd 14 lock_det lock detector cmos output vfqfpn28 outbufn vdd_div4 vdd_div2 vdd_outbuf scl/c l k add1 vdd _db us vdd_bufvco extvco_inn vdd_pll icp rext test2 vdd_esd vctrl vdd_vcob ref_clk vdd_vcoa v dd_ cp test1 lock_det dbus_sel add0/ lo ad add2 ex t_ p d outbufp sda / data extvco_inp
block diagram and pin configuration STW81102 8/43 15 test2 test input 2 test purpose only; must be connected to gnd 16 ref_clk reference clock input 17 vdd_pll pll digital power supply 18 extvco_inn external vco negative input test purpose only; must be connected to gnd 19 extvco_inp external vco positive input test purpose only; must be connected to gnd 20 vdd_bufvco vco buffer power supply 21 dbus_sel digital bus interface select cmos input 22 vdd_dbus spi and i 2 c bus power supply 23 ext_pd power down hardware cmos input 24 sda/data i2cbus/spi data line cmos bidir schmitt triggered 25 scl/clk i2cbus/spi clock line cmos input 26 add0/load i2cbus address select pin/ spi load line cmos input 27 add1 i2cbus address select pin cmos input 28 add2 i2cbus address select pin cmos input table 1. pin description (continued) pin no name description observation
STW81102 electrical specifications 9/43 2 electrical specifications 2.1 absolute maximum ratings 2.2 operating conditions 2.3 digital logic levels table 2. absolute maximum ratings symbol parameter values unit av cc analog supply voltage 0 to 4.6 v dv cc digital supply voltage 0 to 4.6 v t stg storage temperature -65 to 150 c esd electrical static discharge - hbm (1) - cdm-jedec standard - mm 4 1.5 0.2 kv 1. the maximum rating of the esd protec tion circuitry on pi n 4 and pin 5 is 800v. table 3. operating conditions (refer to application diagram) symbol parameter test conditions min typ max unit av dd analog supply voltage 3.0 3.3 3.6 v dv dd digital supply voltage 3.0 3.3 3.6 v i vdd1 v dd1 current consumption 100 ma i vdd2 v dd2 current consumption 15 ma t amb operating ambient temperature -40 85 c t j maximum junction temperature 125 c r th j-amb junction to ambient package thermal resistance multilayer jedec board 35 c/w table 4. digital logic levels symbol parameter test conditions min typ max unit v il low level input voltage 0.2*vdd v v ih high level input voltage 0.8*vdd v v hyst schmitt trigger hysteresis 0.8 v v ol low level output voltage 0.4 v v oh high level output voltage 0.85*vdd v
electrical specifications STW81102 10/43 2.4 electrical characteristics table 5. electrical characteristics all the electrical specifications are intended at 3.3v supply voltage. symbol parameter test conditions min typ max unit output frequency range f outa output frequency range with vcoa direct output 3000 3620 mhz divider by 2 1500 1810 mhz divider by 4 750 905 mhz f outb output frequency range with vcob direct output 4000 4650 mhz divider by 2 2000 2325 mhz divider by 4 1000 1162.5 mhz vco dividers n vco divider ratio prescaler 16/17 256 65551 prescaler 19/20 361 77836 reference clock and phase frequency detector f ref reference input frequency 10 200 mhz reference input sensitivity (1) 0.35 1 1.5 vpeak r reference divider ratio 2 1023 f pfd pfd input frequency 16 mhz f step frequency step (2) prescaler 16/17 f out / 65551 f out / 256 hz prescaler 19/20 f out / 77836 f out / 361 hz charge pump i cp icp sink/source (3) 3bit programmable 5 ma v ocp output voltage compliance range 0.4 v dd -0.3 v spurious (4) direct output (f pfd = 200khz) -73 dbc divider by 2 (f pfd = 400khz) -83 dbc divider by 4 (f pfd = 800khz) -91 dbc vcos k vcoa vcoa sensitivity (5) lower frequency range 40 55 70 mhz/v intermediate frequency range 60 75 95 mhz/v higher frequency range 80 105 140 mhz/v k vcob vcob sensitivity (5) lower frequency range 30 45 60 mhz/v intermediate frequency range 40 55 70 mhz/v higher frequency range 50 70 90 mhz/v
STW81102 electrical specifications 11/43 vco a pushing (5) 4 7 mhz/v vco b pushing (5) 14 20 mhz/v v ctrl vco control voltage (5) 0.4 3 v lo harmonic spurious (5) -20 dbc i vcoa vcoa current consumption f vco =3.3ghz ; amplitude [11] 30 ma f vco =3.3ghz ; amplitude [00] 16 ma i vcob vcob current consumption f vco =4.3ghz ; amplitude [11] 22 ma f vco =4.3ghz ; amplitude [00] 11 ma i vcobuf vco buffer consumption 15 ma i div2 divider by 2 consumption 17 ma i div4 divider by 4 consumption 13 ma lo output buffer p lo output level 0 dbm r l return loss (5) matched to 50ohm 15 db i outbuf current consumption div4 buff 27 ma div2 buff 23 ma direct output 39 ma external vco (test purpose only) frequency range 3.0 4.65 ghz input level 0 +6 dbm current consumption vco internal buffer 15 ma pll miscellaneous i pll current consumption input buffer, prescaler, digital dividers, misc. 12 ma t lock lock up time (5), (6) 25khz pll bandwidth; within 1 ppm of frequency error 150 s 1. in order to achieve best phase noise performance 1v peak level is suggested. 2. the frequency step is related to the pfd input frequency as follows: - f step = f pfd for direct output - f step = f pfd /2 for divided by 2 output - f step = f pfd /4 for divided by 4 output 3. see relationship between icp and rext in t he circuit description section (charge pump) 4. the level of the spurs may change depending on pfd frequenc y, charge pump current, selected channel and pll loop bw. 5. guaranteed by design and characterization. 6. frequency jump from 2300 to 2150 mhz; it includes the time required by the vco calibration procedure (7 f pfd cycles with f pfd =400khz). table 5. electrical characteristics (continued) all the electrical specifications are intended at 3.3v supply voltage. symbol parameter test conditions min typ max unit
electrical specifications STW81102 12/43 2.5 phase noise specification table 6. phase noise specification parameter test conditions min typ max unit phase noise performance (1) in band phase noise floor ? closed loop (2) normalized in band phase noise floor icp=4ma, pll bw = 50khz; including reference clock contribution -222 dbc/hz in band phase noise floor direct output icp=4ma, pll bw = 50khz; including reference clock contribution -222+20log(n)+10log( f pfd )dbc/hz in band phase noise floor divider by 2 - 228+20log(n)+10log( f pfd )dbc/hz in band phase noise floor divider by 4 - 234+20log(n)+10log( f pfd )dbc/hz pll integrated phase noise ? direct output integrated phase noise 100hz to 40mhz f out = 4.3 ghz, f pfd = 200khz, f step =200 khz, pll bw = 15khz, icp=4ma -35 dbc 1.4 rms pll integrated phase noise ? divider by 2 integrated phase noise 100hz to 40mhz f out = 2.15 ghz, f pfd = 400khz, f step =200 khz, pll bw = 20khz, icp=3ma -44 dbc 0.52 rms pll integrated phase noise ? divider by 4 integrated phase noise 100hz to 40mhz f out = 1.075 ghz, f pfd = 800khz, f step =200 khz, pll bw = 30khz, icp=2.5ma -51 dbc 0.22 rms vco a direct (3000mhz-3620mhz) ? open loop (3) phase noise @ 1 khz -56 dbc/hz phase noise @ 10 khz -83 dbc/hz phase noise @ 100 khz -107 dbc/hz phase noise @ 1 mhz -129 dbc/hz phase noise @ 10 mhz -149 dbc/hz phase noise @ 40 mhz -159 dbc/hz vco b direct (4000mhz-4650mhz) ? open loop (3) phase noise @ 1 khz -54 dbc/hz phase noise @ 10 khz -82 dbc/hz phase noise @ 100 khz -106 dbc/hz phase noise @ 1 mhz -128 dbc/hz phase noise @ 10 mhz -148 dbc/hz phase noise @ 40 mhz -158 dbc/hz
STW81102 electrical specifications 13/43 upon request an evaluation kit is available including a powerful simulation tool (stwpllsim) which allows to estimate very accurately the phase noise of the device according to the desired project parameters (vco frequency, selected output stage, reference clock, frequency step, ?); refer to the application information ( section 7 ) for more details. vco a with divider by 2 (1500mhz-1810mhz) ? open loop (3) phase noise @ 1 khz -62 dbc/hz phase noise @ 10 khz -89 dbc/hz phase noise @ 100 khz -113 dbc/hz phase noise @ 1 mhz -135 dbc/hz phase noise @ 10 mhz -151.5 dbc/hz phase noise floor @ 40 mhz -155 dbc/hz vco b with divider by 2 (2000mhz-2325mhz) ? open loop (3) phase noise @ 1 khz -60 dbc/hz phase noise @ 10 khz -88 dbc/hz phase noise @ 100 khz -112 dbc/hz phase noise @ 1 mhz -134 dbc/hz phase noise @ 10 mhz -151.5 dbc/hz phase noise floor @ 40 mhz -155 dbc/hz vco a with divider by 4 (750mhz-905mhz) ? open loop (3) phase noise @ 1 khz -68 dbc/hz phase noise @ 10 khz -95 dbc/hz phase noise @ 100 khz -119 dbc/hz phase noise @ 1 mhz -141 dbc/hz phase noise @ 10 mhz -154 dbc/hz phase noise floor @ 40 mhz -155 dbc/hz vco b with divider by 4 (1000mhz-1162.5mhz) ? open loop (3) phase noise @ 1 khz -66 dbc/hz phase noise @ 10 khz -94 dbc/hz phase noise @ 100 khz -118 dbc/hz phase noise @ 1 mhz -140 dbc/hz phase noise @ 10 mhz -154 dbc/hz phase noise floor @ 40 mhz -155 dbc/hz 1. phase noise ssb. vco amplitude setting to value [11]. all the closed-loop performances are s pecified using a reference clock signal at 76.8 mhz with phase noise of -135dbc/hz @1khz offset, -145dbc/hz @10khz offset and -149.5dbc/hz of noise floor. 2. normalized pn = measured pn ? 20log(n) ? 10log(f pfd ) where n is the vco divider ratio (n=b*p+a) and f pfd is the comparison frequency at the pfd input 3. typical phase noise at centre band frequency table 6. phase noise specification (continued) parameter test conditions min typ max unit
typical performance characteristics STW81102 14/43 3 typical performance characteristics the phase noise is measured with the agilent e5052a signal source analyzer. all the closed-loop measurements are done with f step =200 khz setting properly the f pfd and the charge pump current. the loop filter configuration used is depicted in the paragraph 8 (application diagram) and the reference clock signal is at 76.8 mhz with phase noise of - 135dbc/hz @1khz offset, -145dbc/hz @10khz offset and -149.5dbc/hz of noise floor. figure 3. vco a (direct output) open loop phase noise figure 4. vco b (direct output) open loop phase noise figure 5. vco a (direct output) closed loop phase noise at 3.6ghz (f step =200khz; f pfd =200khz; i cp =3ma) figure 6. vco b (direct output) closed loop phase noise at 4.3ghz (f step =200khz; f pfd =200khz; i cp =4ma) 1.2 rms 1.4 rm s
STW81102 typical performance characteristics 15/43 figure 7. vco a (div. by 2 output) closed loop phase noise at 1.65ghz (f step =200khz; f pfd =400khz; i cp =2ma) figure 8. vco b (div. by 2 output) closed loop phase noise at 2.15ghz (f step =200khz; f pfd =400khz; i cp =3ma) figure 9. vco a (div. by 4 output) closed loop phase noise at 825mhz (f step =200khz; f pfd =800khz; i cp =1.5ma) figure 10. vco b (div. by 4 output) closed loop phase noise at 1.075ghz (f step =200khz; f pfd =800khz; i cp =2.5ma) 0 . 5 rm s 0 . 5 7 rm s 0 .2 rm s 0 .24 rm s
typical performance characteristics STW81102 16/43 figure 11. pfd frequency spurs (direct output; f pfd =200khz) figure 12. pfd frequency spurs (div. by 2 output; f pfd =400khz) figure 13. pfd frequency spurs (div. by 4 output; f pfd =800khz) figure 14. settling time (final frequency=2.15 ghz; f pfd =400khz; i cp =3ma) -73 dbc @200khz -83 dbc @400khz -91 dbc @800khz
STW81102 general description 17/43 4 general description the block diagram of figure 1 shows the different blocks, which have been integrated to achieve an integer-n pll frequency synthesizer. the STW81102 consists of 2 internal low-noise vcos with buffer blocks, a divider by 2, a divider by 4, a low-noise pfd (phase frequency detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dual- modulus prescaler. the a-counter (5 bits) and b counter (12 bits) counters, in conjunction with the dual modulus prescaler p/p+1 (16/17 or 19/20), implement an n integer divider, where n = b*p +a. the division ratio of both reference and vco dividers is controlled through the selected digital interface (i 2 c bus or spi). the selection of the digital interface type is done by the proper hardware connection of the pin dbus_sel (0 v for i 2 c bus, 3.3 v for spi). all devices operate with a power supply of 3.3 v and can be powered down when not in use. 4.1 circuit description 4.1.1 reference input stage the reference input stage is shown in figure 15 . the resistor network feeds a dc bias at the fref input while the inverter used as the frequency reference buffer is ac coupled. figure 15. reference frequency input buffer 4.1.2 reference divider the 10-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the pfd. the division ratio is programmed through the digital interface. 4.1.3 prescaler the dual-modulus prescaler p/p+1 takes the cm l clock from the vco buffer and divides it down to a manageable frequency for the cmos a and b counters. the modulus (p) is programmable and can be set to 16 or 19. it is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input. inv buf vdd fref power down
general description STW81102 18/43 4.1.4 a and b counters the a (5 bits) and b (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the refe rence division ratio. thus, the division ratio and the vco output frequency are given by these formulas: n = b p + a where: f vco : output frequency of vco. p: modulus of dual modulus prescaler (16 or 19 selected through the digital interface). b: division ratio of the main counter. a: division ratio of the swallow counter. f ref : input reference frequency. r: division ratio of reference counter. n: division ratio of pll for a correct work of the vco divider, b must be strictly higher than a. a can take any value ranging from 0 to 31. the range of the n number can vary from 256 to 65551 (p=16) or from 361 to 77836 (p=19). figure 16. vco divider diagram 4.1.5 phase frequency detector (pfd) the pfd takes inputs from the reference and the vco dividers and produces an output proportional to the phase error. the pfd includes a delay gate that controls the width of the anti-backlash pulse. this pulse ensures that there is no dead zone in the pfd transfer function. figure 17 is a simplified schematic of the pfd. f vco bp a + ? () f ref ? r ------------------------------------------ = 5 bit a counter 12 bit b counter to pfd modulus vcobuf+ vcobuf- prescaler 16/17 or 19/20
STW81102 general description 19/43 figure 17. pfd diagram 4.1.6 lock detect this signal indicates that the difference between rising edges of both up and down pfd signals is found to be shorter than the fixed delay (roughly 5 ns). lock detect signal is high when the pll is locked. when power down is activated, lock detect is let to high level (lock detect consumes current only during pll transients). 4.1.7 charge pump this block drives two matched current sources, iup and idown, which are controlled respectively by up and down pfd outputs. the nominal value of the output current is controlled by an external resistor (to be connected to the rext input pin) and a selection among 8 by a 3 bit word. the minimum value of the output current is: i min = 2*vbg/rext (vbg~1.17 v) note: the current is output on pin icp. during the vco auto calibration, icp and vctrl pins are forced to vdd/2 d ff r fref vdd r d ff fref vdd delay up down abl table 7. current value vs selection cpsel2 cpsel1 cpsel0 current va lue for rext=4.7 k ? 000i min 0.5 ma 0012*i min 1.0 ma 0103*i min 1.5 ma 0114*i min 2.0 ma 1005*i min 2.5 ma 1016*i min 3.0 ma 1107*i min 3.5 ma 1118*i min 4.0 ma
general description STW81102 20/43 figure 18. loop filter connection 4.1.8 voltage controlled oscillators vco selection within STW81102 two low-noise vcos are integrated to cover a wide band from 3000mhz to 3620mhz and 4000mhz to 4650mhz (direct output), from 1500mhz to 1810mhz and 2000mhz to 2325mhz (selecting divider by 2), from 750mhz to 905mhz and 1000mhz to 1162.5mhz (selecting divider by 4). vco a frequency range 3000mhz-3620mhz vco b frequency range 4000mhz-4650mhz vco frequency calibration both vcos can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. these frequency ranges are intended to cover the wide band of operation and compensate for process variation on the vco center frequency. an automatic selection of the range is performed when the bit sercal rises from "0" to "1". the charge pump is inhibited and the pins icp & vctrl are at vdd/2 volts. then the ranges are tested to select the one which with this vco input voltage is the nearest to the desired output frequency (fout = n*fref /r). when this selection is achieved the signal endcalb (which means end of calibration) falls to "0", then the charge pump is enabled again and sercal should be reset to "0" before the next channel step. the pll has just to perform fine adjustment around vdd/2 on the loop filter to reach fout, which enables a fast settle. figure 19. vco sub-bands frequency characteristics charge pump icp vctrl buf vdd buf cal bit r1 c1 c3 r3 c2 c3 r3 c2
STW81102 general description 21/43 the sercal bit should be set to "1" at each division ratio change. it should be noted that in order to reset the autocalibrator state machine after a power-up, and anyway before the first calibration, the initcal bit should be set to "1" and back to "0" (this operation is automatically performed by the power on reset circuitry). the calibration takes approximately 7 periods of the pfd frequency. the maximum allowed f pfd to perform the calibration process is 1 mhz. using an higher f pfd the following procedure should be adopted: 1. calibrate the vco at the desired frequency with an f pfd less than 1 mhz 2. set the a, b and r dividers ratio for the desired f pfd vco voltage amplitude control the voltage swing of the vcos can be adjusted over 4 levels by means of two dedicated programming bits (pll_a1 and pll_a0). higher amplitudes provide best phase noise while lower ones save power. the following table gives the voltage level expected on the resonator nodes, the current consumption and the phase noise @1mhz. table 8. vco a performances vs. amplitude setting (freq=3.3ghz) pll_a[1:0] differential voltage swing (vp) current consumption (ma) pn @1mhz (dbc/hz) 00 1.1 16 -125 01 1.3 18 -126 10 1.9 27 -128.5 11 2.1 30 -129 table 9. vco b performances vs. amplitude setting (freq=4.3ghz) pll_a[1:0] differential voltage swing (vp) current consumption (ma) pn @1mhz (dbc/hz) 00 1.1 11 -124 01 1.3 14 -125 10 1.9 20 -127.5 11 2.1 22 -128
i 2 c bus interface STW81102 22/43 5 i 2 c bus interface the i 2 c bus interface is selected by hardware connection of the pin #21 (dbus_sel) to 0 v. data transmission from microprocessor to the STW81102 takes place through the 2 wires (sda and scl) i 2 c-bus interface. the STW81102 is always a slave device. the i 2 c-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. the device that controls the data transfer is known as the master and the othe rs as the slave. the master will always initiate the transfer and will provide the serial clock for synchronization. 5.1 general features 5.1.1 data validity data changes on the sda line must only occur when the scl is low. sda transitions while the clock is high are used to identify start or stop condition. figure 20. data validity 5.1.2 start condition a start condition is identified by a high to low transition of the data bus sda while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. 5.1.3 stop condition a low to high transition of the data bus sda identifies stop while the clock signal scl is stable in the high state. a stop condition terminates communications between the STW81102 and the bus master. sda scl change data allowed data line stable data valid sda scl change data allowed data line stable data valid
STW81102 i 2 c bus interface 23/43 figure 21. start and stop condition 5.1.4 byte format and acknowledge every byte transferred on the sda line must contain bits. each byte must be followed by an acknowledge bit. the msb is transferred first. an acknowledge bit is used to indicate a successful data transfer. the bus transmitter, either master or slave, will release the sda bus after sending 8 bits of data. during the 9th clock pulse the receiver pulls the sda low to acknowledge the receipt of 8 bits data. figure 22. byte format and acknowledge 5.1.5 device addressing to start the communication between the master and the STW81102, the master must initiate with a start condition. following this, the master sends onto the sda line 8 bits (msb first) corresponding to the device select address and read or write mode. the first 7 msb's are the device address identifier, corresponding to the i 2 c-bus definition. for the STW81102 the address is set as "1100a 2 a 1 a 0 ", 3bits programmable. the 8th bit (lsb) is the read or write operation bit (rw; set to 1 in read mode and to 0 in write mode). after a start condition the STW81102 identifies on the bus the device address and, if matched, it will acknowledge the identification on sda bu s during the 9th clock pulse. 5.1.6 single-byte write mode following a start condition the master sends a device select code with the rw bit set to 0. the STW81102 gives an acknowledge and waits for the internal sub-address (1 byte). this byte provides access to any of the internal registers. after the reception of the sub-address internal byte the STW81102 again responds with an acknowledge. a single-byte write to sub-address 00h will change the "functional_mode" register, so a single-b yte write with sub-ad dress 04h will change the "control" register and so on. sda scl start stop sda scl start stop sda scl start // // acknowledgment from receiver 1 2 37 8 9 msb sda scl start // // acknowledgment from receiver 1 2 37 8 9 msb
i 2 c bus interface STW81102 24/43 5.1.7 multi-byte write mode the multi-byte write mode can start from any internal address. the master sends the data bytes and each one is acknowledged. the master terminates the transfer by generating a stop condition. the sub-address decides the starting byte . a multi-byte with sub-address 01h and 2 data_in bytes will change the "b_counter" and "a_counter" registers (01h,02h), so a multi-byte with sub-address 00h and and 6 data_in bytes will change all the STW81102 registers. 5.1.8 current byte address read in the current byte address read mode, following a start condition, the master sends the device address with the rw bit set to 1 (no su b-address is needed as there is only 1 byte read register). the STW81102 acknowledges this and outputs the data byte. the master does not acknowledge the received byte, but terminates the transfer with a stop condition. 5.2 timing specification figure 23. data and clock table 10. single-byte write mode s 1100a 2 a 1 a 0 0 ack sub-address byte ack data in ack p table 11. multi-byte write mode s 1100a 2 a 1 a 0 0 ack sub-address byte ack data in ack .... data in ack p table 12. current byte address read s 1100 a 2 a 1 a 0 1 ack data out no ack p table 13. data and clock symbol parameter minimum time (ns) t cs data to clock set up time 2 t ch data to clock hold time 2 t cwh clock pulse width high 10 t cwl clock pulse width low 5 t cs t ch t cwh t cwl sda scl t cs t ch t cwh t cwl sda scl
STW81102 i 2 c bus interface 25/43 figure 24. start and stop figure 25. acknowledge table 14. start and stop symbol parameter minimum time (ns) t start clock to data start time 2 t stop data to clock down stop time 2 table 15. acknowledge symbol parameter minimum time (ns) t d1 ack begin delay 2 t d2 ack end delay 2 sda scl td2 89 td1 sda scl td2 89 td1
i 2 c bus interface STW81102 26/43 5.3 i 2 c registers STW81102 has 6 write-only registers and 1 read-only register. the following table gives a short description of the write-only registers list. 5.3.1 functional_mode functional_mode register is used to select different functional mode for the STW81102 synthesizer according to the following table: table 16. write-only registers list hex code dec code description 0x00 0 functional_mode 0x01 1 b_counter 0x02 2 a_counter 0x03 3 ref_divider 0x04 4 control 0x05 5 calibration msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pd6 pd5 pd4 pd3 pd2 pd1 pd0 b11 table 17. different functional mode of the functional_mode register decimal value description 0 power down mode 1 enable vco a, output frequency divided by 2 2 enable vco b, output frequency divided by 2 3 enable external vco, output frequency divided by 2 4 enable vco a, output frequency divided by 4 5 enable vco b, output frequency divided by 4 6 enable external vco, output frequency divided by 4 7 enable vco a, direct output 8 enable vco b, direct output 9 enable external vco, direct output
STW81102 i 2 c bus interface 27/43 5.3.2 b_counter b[10:3]. counter value (bit b11 in the previous register, bits b[2:0] in the next register) 5.3.3 a_counter bits b[2:0] for b counter, a counter value. 5.3.4 ref_divider reference clock divider ratio r[9:1] (bits r1, r0 in th e next register). 5.3.5 control the control register is used to set the charge pump current, the vco output voltage amplitude and the prescaler modulus. pll_a[1:0]: vco amplitude cpsel[2:0]: charge pu mp output current psc_sel: prescaler modulus select ('0' for p=16, '1' for p=19) the lo output frequency is programmed by setting the proper value for a,b and r according to the following formula: msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b10b9b8b7b6b5b4b3 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 b2 b1 b0 a4 a3 a2 a1 a0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 r9 r8 r7 r6 r5 r4 r3 r2 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 r1 r0 pll_ a1 pll_ a0 cp sel2 cp sel1 cp sel0 psc_ sel f out d r bp a + ? () f ref_clk r --------------------------- - ?? =
i 2 c bus interface STW81102 28/43 and p is the selected prescaler modulus 5.3.6 calibration this register controls vco calibrator. initcal: resets the auto-calibrator state machine (writing to "1" and back to "0") sercal: at "1" starts the vco auto-calibration (should be reset to "0" at the end of calibration) selextcal: test purpose only; must be set to '0' cal[4:0]: test purpose only; must be set to '0' 5.3.7 read-only register this register is automatically addressed in the 'current byte address read mode'. dev_id[1:0]: device identifier bits; returns '00' lock_det: "1" when pll is locked intcal[4:0]: internal value of the vco control word 5.3.8 default configuration at power on reset the following configuration is automatically loaded: ? functional mode = 1 (vcoa with divided by 2 output) ? a counter = 8 ? b counter = 562 ? r divider = 192 ? pll_a[1:0] = [10] ? cp_sel[2:0] = [111] ? psc_mod_sel set to "0" (modulus = 16) this is corresponding to an output frequency of 1800mhz and a pfd frequency of 400khz using a 76.8mhz reference clock (calibration al gorithm of the vco is automatically started). 1 for direct output where d r equals 0.5 for output divided by 2 0.25 for output divided by 4 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 init cal ser cal sel ext cal cal4 cal3 cal2 cal1 cal0 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 dev_id1 dev_id0 lock_ det int cal4 int cal3 int cal2 int cal1 int cal0 {
STW81102 i 2 c bus interface 29/43 5.4 vco calibration procedure the calibration of the vco center frequency is activated by a '0' to '1' transition of the sercal bit (calibration register bit[6]). in order to program properly the device, ensuring the vco calibration, the following procedure is required before every channel change: a) reset the "calibration" register using a single-byte write sequence (sub- address 05h) with all the bits set to '0' b) program all the registers using a multi-byte write sequence with the desired settings (functional mode, b and a counters, r counter, vco amplitude, charge pump, prescaler modulus) and the sercal bit of the "calibration" register (05h) set to '1' the maximum allowed pfd frequency (f pfd ) to perform the calibration process is 1 mhz; if the desired f pfd is higher than 1mhz the following steps are needed: ? perform all the steps of the calibration procedure programming the desired vco frequency with a proper setting of r, b and a counter so that f pfd is 1mhz. ? program the device with the proper setting for the desired vco and pfd frequencies according to the above step b) only.
spi digital interface STW81102 30/43 6 spi digital interface 6.1 general features the spi digital interface is selected by hardware connection of the pin #21 (dbus_sel) to 3.3v. the STW81102 ic is programmed by means of a high-speed serial-to-parallel interface with write option only. the 3-wires bus can be clocked at a frequency as high as 100mhz to allow fast programming of the registers containing the data for rf ic configuration. the programming of the chip is done through serial words with whole length of 26 bits. the first 2 msb represent the address of the registers. the others 24 lsb represent the value of the registers. each data bit is stored in the internal shift register on the rising edge of the clock signal. on the rising edge of the load signal the outputs of the selected register are sent to the device. figure 26. spi input and output bit order
STW81102 spi digital interface 31/43 6.2 timing specification figure 27. spi timing specification table 18. spi data structure msb lsb address data for register (24 bits) a1 a0 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 table 19. address decoder and outputs address outputs a1 a0 databits d23-d0 no name function 00240st1 reference divider, vco amplitude, vco calibration, charge pump current, prescaler modulus 0 1 24 1 st2 functional modes, vco dividers 1 0 24 2 st3 reserved 1 1 24 3 st4 reserved table 20. spi timing specification parameter description min. typ. max. unit tsetup data to cloc k setup time 0.8 ns thold data to clock hold time 0.2 ns tclk clock cycle period 10 ns tload load pulse width 3 ns tclk_loadr clock to load rising edge 2 ns tclk_loadf clock to load falling edge 0.5 ns
spi digital interface STW81102 32/43 6.3 bits table table 21. bits (serial interface address = 00h; register name = st1) bit name description [23] r9 reference clock divider ratio [22] r8 [21] r7 [20] r6 [19] r5 [18] r4 [17] r3 [16] r2 [15] r1 [14] r0 [13] pll_a1 vco amplitude control [12] pll_a0 [11] cpsel2 charge pump output current control [10] cpsel1 [9] cpsel0 [8] psc_sel prescaler modulus select (?0? for p=16, ?1? for p=19) [7] initcal test purpose only; must be set to ?0? [6] sercal enable vco calibration (see section 6.4 ) [5] selextcal test purpose only; must be set to ?0? [4] cal4 test purpose only; must be set to ?0? [3] cal3 [2] cal2 [1] cal1 [0] cal0
STW81102 spi digital interface 33/43 the lo output frequency is programmed by setting the proper value for a,b and r according to the following formula: and p is the selected prescaler modulus table 22. bits (serial interface address = 01h; register name = st2) bit name description [23] pd6 device functional modes 0. power down 1. enable vco a, output frequency divided by 2 2. enable vco b, output frequency divided by 2 3. enable external vco, output frequency divided by 2 4. enable vco a, output frequency divided by 4 5. enable vco b, output frequency divided by 4 6. enable external vco, output frequency divided by 4 7. enable vco a, direct output 8. enable vco b, direct output 9. enable external vco, direct output [22] pd5 [21] pd4 [20] pd3 [19] pd2 [18] pd1 [17] pd0 [16] b11 b counter bits [15] b10 [14] b9 [13] b8 [12] b7 [11] b6 [10] b5 [9] b4 [8] b3 [7] b2 [6] b1 [5] b0 [4] a4 a counter bits [3] a3 [2] a2 [1] a1 [0] a0 1 for direct output where d r equals 0.5 for output divided by 2 0.25 for output divided by 4 f out d r bp a + ? () f ref_clk r --------------------------- - ?? = {
spi digital interface STW81102 34/43 6.3.1 default configuration at power on reset the following configuration is automatically loaded: ? functional mode = 1 (vcoa with divided by 2 output) ? a counter = 8 ? b counter = 562 ? r divider = 192 ? pll_a[1:0] = [10] ? cp_sel[2:0] = [111] ? psc_mod_sel set to "0" (modulus = 16) this is corresponding to an output frequency of 1800mhz and a pfd frequency of 400khz using a 76.8mhz reference clock (calibration al gorithm of the vco is automatically started). 6.4 vco calibration procedure the calibration of the vco center frequency is activated by a '0' to '1' transition of the sercal bit (st1 register bit[6]). in order to program properly the device, ensuring the vco calibration, the following procedure is required before every channel change: a) program the st1 register with the desired settings (r counter, vco amplitude, charge pump, prescaler modulus) and sercal bit set to '0' b) program the st2 register with the desired settings (functional mode, b and a counters) c) program the st1 register with the desired settings (r counter, vco amplitude, charge pump, prescaler modulus) and sercal bit set to '1' the maximum allowed pfd frequency (f pfd ) to perform the calibration process is 1 mhz; if the desired f pfd is higher than 1mhz the following steps are needed: ? perform all the steps of the calibration procedure programming the desired vco frequency with a proper setting of r, b and a counter so that f pfd is 1mhz. ? program the device with the proper setting for the desired vco and pfd frequencies according to the above step a) and b) only.
STW81102 application information 35/43 7 application information the STW81102 features three different alternatively selectable bands: direct output (3.0 to 3.62ghz and 4.0 to 4.65ghz), divided by 2 (1.5 to 1.81ghz and 2.0 to 2.325ghz) and divided by 4 (750 to 905mhz and 1000 to 1162.5mhz). in order to achieve a suitable power level, a good matching network is needed to adapt the output stage to a 50 ? load. moreover, since most of commercial rf components have single ended input and output terminations, a differential to single ended conversion could be required. below different matching configurations for the three bands are suggested as a guideline for the design of own application board. the user can find in the evaluation kit th e ads design for each matching configuration suggested in this section. the name of the corresponding ads design is reported in each figure. the ads designs provide only a first indication of the output stage matching and they should be reworked according to the user choice for layout, board substrate, components and so on. the ads designs of the evaluation boards are provided with a complete electromagnetic modelling (board, components, ...). 7.1 direct output if a differential to single conversion is not needed it is possible to match the output buffer of the STW81102 in the simple way shown in figure 28 . figure 28. differential/single ended output network in the 3.0 - 4.65ghz range (match_lc_lump_4g_diff.dsn) since most of discrete components for microwave applications are single ended, the user can easily use one of the two outputs and terminate the other one to 50 ? with a 3db power loss. rf outp rf outn v cc 5.5nh 50 ohm 10pf 5.5nh 10pf v cc 100 ohm 100 ohm 50 ohm rf outp rf outn v cc 5.5nh 50 ohm 10pf 5.5nh 10pf v cc 100 ohm 100 ohm 50 ohm
application information STW81102 36/43 alternatively it is possible to combine the 2 outputs in different ways. a first topology for the direct output (3ghz to 4.65ghz) is suggested in figure 29 . it basically consists of a simple lc balun and a matching network to adapt the output to a 50 ? load. the two lc networks shift output signal phase of -90 and +90 thus combining the 2 outputs. this topology, designed for a center frequency of 4ghz, is intrinsically narrow band, since the lc balun is tuned at a single frequency. if the application requires a different sub-band, the lc combiner could be easily adjusted to be tuned at the frequency of interest. figure 29. lc lumped balun and matching network (match_lc_lump_4g.dsn) the 1.9nh shunt inductor works as a dc feed for one of the open collector terminal as well as a matching element along with the other components. the 1.9nh series inductors are used to resonate the parasitic capacitance of the chip. for an optimum output matching it is recommended to use 0402 murata or avx capacitors and 0403 or 0604 hq coilcraft inductors. it is also advisable to use short interconnection paths to minimize losses and undesired impedance shift. an alternative topology, which allows for a more broadband matching and balanced to unbalanced conversion, is shown it figure 30 . figure 30. evaluation board (evb4g) matching network (match_evb4g.dsn) for the differential to single conversion the 50 to 100 ? johanson balun is recommended (3700bl15b100). rf outp rf outn v cc 1.9nh 1.9nh 0.8pf 0.8pf 2.5pf 50 ohm v cc 1.9nh 1.9nh 0.8pf 0.8pf 50 ohm 50 ohm rf outp rf outn v cc 1.9nh 1.9nh 0.8pf 0.8pf 2.5pf 50 ohm v cc 1.9nh 1.9nh 0.8pf 0.8pf 50 ohm 50 ohm rf outp rf outn v cc 5.5nh 50 ohm 12pf 12pf 5.5nh 12pf 2:1 v cc 50 ohm 50 ohm 1pf 1pf 4.7pf 1.2pf 1.2pf rf outp rf outn v cc 5.5nh 50 ohm 12pf 12pf 5.5nh 12pf 2:1 v cc 50 ohm 50 ohm 1pf 1pf 4.7pf 1.2pf 1.2pf
STW81102 application information 37/43 7.2 divided by 2 output if the user's application does not require a balanced to unbalanced conversion, the output matching reduces to the simple circuit shown below ( figure 31 ). this solution can be easily used to provide one single ended output just terminating the other output at 50 ? with a 3db power loss. figure 31. differential/single ended output network in the 1.5 - 2.325ghz range (match_lc_lump_2g_diff.dsn) a first solution to combine the differential outputs is the lumped lc type balun tuned in the 2ghz band ( figure 32 ). figure 32. lc lumped balun for divide d by 2 output (match_lc_lump_2g.dsn) the same recommendation for the smd components applies also for the divided by 2 output. another topology suitable to combine the two outputs for the divided by 2 frequencies is represented in figure 33 . rf outp rf outn v cc 22nh 50 ohm 10pf 22nh 10pf v cc 50 ohm 50 ohm 50 ohm rf outp rf outn v cc 2.7nh 2.7nh 2pf 2pf 3pf 50 ohm 3nh v cc 2.7nh 2.7nh 2pf 2pf 50 ohm 50 ohm rf outp rf outn v cc 2.7nh 2.7nh 2pf 2pf 3pf 50 ohm 3nh v cc 2.7nh 2.7nh 2pf 2pf 50 ohm 50 ohm
application information STW81102 38/43 figure 33. evaluation board (evb2g) matching network (match_evb2g.dsn) for the differential to single conversion the 50 to 100 ? johanson balun (1600bl15b100) is recommended. 7.3 divided by 4 output the same topology, components values and considerations of figure 31 , applies also for the divided by 4 output (match_lc_lump_1g_diff.dsn). as for the previous sections, a solution to combine the differential outputs is the lumped lc type balun tuned in the 1ghz band ( figure 34 ). figure 34. lc lumped balun for the divided by 4 output (match_lc_lump_1g.dsn) if the user prefers to use an rf balun it is possible to adopt the same topology depicted in figure 33 , just changing the balun and the matching components ( figure 35 ). the suggested balun for the 0.75 - 1.17ghz frequency range is the 1:1 johanson 900bl15c050. rf outp rf outn v cc 5.5nh 50 ohm 22pf 22pf 5.5nh 22pf 2:1 v cc 50 ohm 50 ohm 1.2pf 1.9nh rf outp rf outn v cc 5.5nh 50 ohm 22pf 22pf 5.5nh 22pf 2:1 v cc 50 ohm 50 ohm 1.2pf 1.9nh rf outp rf outn v cc 5.5nh 5.5nh 4pf 4pf 6pf 50 ohm 14nh v cc 5.5nh 5.5nh 4pf 4pf 25 ohm 25 ohm
STW81102 application information 39/43 figure 35. evaluation board (evb1g) matching network (match_evb1g.dsn) 7.4 evaluation kit upon request an evaluation kit can be delivered. it includes: evaluation board gui (graphical user interface) to program the device measured s parameters of the rf output ads2005 schematics providing guidelines for application board design stwpllsim software for pll loop filter design and noise simulation three different evaluation kits are available, one optimized for 1ghz frequency range, one for 2ghz frequency range and the last one for 4ghz range. while ordering please specify the following order codes: the three evaluation kits differ only for the output stage network and can be adapted from one frequency band variant to a different one replacing properly the macthing components and the balun. rf outp rf outn v cc 18nh 8.2pf 22pf 18nh 8.2pf 1:1 v cc 25 ohm 25 ohm 50 ohm 0.5pf 2.1nh rf outp rf outn v cc 18nh 8.2pf 22pf 18nh 8.2pf 1:1 v cc 25 ohm 25 ohm 50 ohm 0.5pf 2.1nh table 23. order code of the evaluation kit part number description STW81102-evb1g 1ghz frequency range - divider by 4 output optimized STW81102-evb2g 2ghz frequency range - divider by 2 output optimized STW81102-evb4g 4ghz frequency ra nge - direct output optimized
application diagram STW81102 40/43 8 application diagram figure 36. application diagram note: 1 see application information ( section 7 ) for further information on output matching topology. 2 ext_pd, add2, add1 (and add0 when i 2 c bus is selected) can be hard wired directly on the board. 3 loop filter values are for 200khz frequency step. vdd_esd vdd_vcoa dbus_sel scl/clk sda/data ext_pd add1 add0/load add2 vdd_dbus vdd_div2 vdd_outbuf outbufp outbufn vdd_div4 vdd_vcob vctrl icp rext vdd_cp test1 lock_det vdd_bufvco extvco_inp extvco_inn vdd_pll ref_clk test2 10 22p 1n 10 22p 1n 270p 68p 2.7n 10 22p 1n 51 1.8n STW81102 from/to ? controller to ? controller loop filter vdd 1 rf out ref clk vdd 1 vdd 1 vdd 1 vdd 1 vdd 2 10 22p 1n i2c spi 100 100 15p 15p 100 15p 4.7k 8.2k 2.2k vdd_esd vdd_vcoa dbus_sel scl/clk sda/data ext_pd add1 add0/load add2 vdd_dbus vdd_div2 vdd_outbuf outbufp outbufn vdd_div4 vdd_vcob vctrl icp rext vdd_cp test1 lock_det vdd_bufvco extvco_inp extvco_inn vdd_pll ref_clk test2 10 22p 1n 10 22p 1n 270p 68p 2.7n vdd_esd vdd_vcoa dbus_sel scl/clk sda/data ext_pd add1 add0/load add2 vdd_dbus vdd_div2 vdd_outbuf outbufp outbufn vdd_div4 vdd_vcob vctrl icp rext vdd_cp test1 lock_det vdd_bufvco extvco_inp extvco_inn vdd_pll ref_clk test2 10 22p 1n 10 22p 1n 270p 68p 2.7n 10 22p 1n 51 1.8n STW81102 from/to ? controller to ? controller loop filter vdd 1 rf out ref clk vdd 1 vdd 1 vdd 1 vdd 1 vdd 2 10 22p 1n i2c spi 100 100 15p 15p 100 15p 4.7k 8.2k 2.2k
STW81102 package information 41/43 9 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: http://www.st.com. figure 37. vfqfpn28 mechanical data & package dimensions outline and mechanical data ref. mm inch min. typ. max. min. typ. max. a 0.800 0.900 1.000 0.031 0.035 0.039 a1 0.020 0.050 0.0008 0.0019 a2 0.650 1.000 0.025 0.039 a3 0.200 0.0078 b 0.180 0.250 0.300 0.007 0.0098 0.012 d 4.850 5.000 5.150 0.191 0.197 0.203 d1 4.750 0.187 d2 2.950 3.100 3.250 0.116 0.122 0.128 e 4.850 5.000 5.150 0.191 0.197 0.203 e1 4.750 0.187 e2 2.950 3.100 3.250 0.116 0.122 0.128 e 0.500 0.020 l 0.350 0.550 0.750 0.014 0.022 0.029 p 0.60 0.0236 k 14? 14? ddd 0.080 0.003 notes: 1) vfqfpn stands for thermally enhanced very thin fine pitch quad packages no lead. very thin: a = 1.00 max. 2) the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other fea- ture of package body. exact shape and size of this feature is optional. vfqfpn-28 (5x5x1.0mm) v ery f ine q uad f lat p ackage n o lead 7655832 a
revision history STW81102 42/43 10 revision history table 24. document revision history date revision changes 06-mar-2006 1 initial release. 16-jun-2006 2 changed from preliminary data to maturity. updated section 2: electrical specifications ; section 7: application information and section 8: application diagram .
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