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| tms320vc5470 fixed-point digital signal processor data manual literature number: sprs017b december 2001 ? revised december 2002 production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third ? party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2002, texas instruments incorporated iii revision history revision date product status highlights * december 2001 production data original a july 2002 production data updated arm sram read and write timing diagrams b december 2002 production data added industrial temperature specifications to the recommended operating conditions and the absolute maximum ratings (page 44). updated mechanical diagram (page 82) iv contents v december 2001 ? revised december 2002 sprs017b contents section page 1 tms320vc5470 features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 pin assignments 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 terminal functions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 dsp subsystem functional overview 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 dsp core 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 dsp memory space and buses 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 dsp scan-based emulation logic 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 dsp memory 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 dsp on-chip ram 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 normal mode dsp memory map 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 api boot mode 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.4 api boot-mode dsp memory map 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.5 dsp extended program memory 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.6 dsp relocatable interrupt vector table 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 dsp registers 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 bank-switching control register 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 programmable bank-switching wait-states 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.3 processor mode status register 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 dsp peripherals 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 multichannel buffered serial port (mcbsp) 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 dsp direct memory access (dma) controller 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 arm port interface (api) 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 dsp external memory interface 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.5 dsp software-programmable wait-state generator 24 . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.6 dsp timer 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.7 dsp clocking 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 dsp power management 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 dsp interrupts 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 mcu subsystem functional overview 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 mcu core 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 arm7tdmi emulation features 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 mcu memory space 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 mcu memory interface 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 mcu memory interface wait-states 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 mcu api interface 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 mcu sdram memory interface 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . contents vi december 2001 ? revised december 2002 sprs017b section page 4.3 mcu peripherals 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 mcu universal asynchronous receiver/transmitter (uart) interfaces 32 . . . . . . . . . 4.3.2 mcu serial peripheral interface (spi) 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 mcu general-purpose i/o 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.4 mcu inter-integrated circuit (i 2 c) interface 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.5 mcu timers 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.6 mcu interrupt handler 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 mcu power-down modes 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 mcu peripheral clock management 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 initialization 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 initial mcu code 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 dsp boot mode 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 emulation support 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 documentation support 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 absolute maximum ratings 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 recommended operating conditions 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 electrical characteristics over recommended operating case temperature (unless otherwise noted) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 package thermal resistance characteristics 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 timing parameter symbology 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 divide-by-two/divide-by-four clock option timing 47 . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 multiply-by-n clock option (pll enabled) timing 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 memory and parallel i/o interface timing 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.1 memory read 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.2 memory write 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.3 parallel i/o port read timing requirements 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6.4 parallel i/o port write switching characteristics 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 ready timing for externally generated wait-states 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 interrupt timings 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 instruction acquisition (dsp_iaq ) and interrupt acknowledge (dsp_iack ) timings 59 . . . . . . . 6.10 external flag (dsp_xf) and dsp_tout timings 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 multichannel buffered serial port (mcbsp) timings 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.1 mcbsp receive and transmit timings 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.2 mcbsp general-purpose timings 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11.3 mcbsp as spi master or slave timings 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 synchronous dram timings 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 i 2 c bus timings 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 arm clock timings 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 spi clock timings 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 mechanical data 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 ball grid array mechanical data 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures vii december 2001 ? revised december 2002 sprs017b list of figures figure page 2 ? 1 5470 functional block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 257-ball ghk package (bottom view) 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 5470 dsp subsystem functional block diagram 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 memory map for dsp accesses (dsp_apibn = 1 or abmdis = 1) 13 . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 api boot mode memory map for dsp accesses (dsp_apibn = 0 and abmdis = 0) 14 . . . . . . . . . . 3 ? 4 dsp extended program memory map 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 bank-switching control register (bscr) 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 pin control register (pcr) 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 ifr and imr registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 5470 mcu subsystem functional block diagram 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 clock management module 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 3.3-v test load circuit 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 2 external divide-by-two clock timing 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 3 external multiply-by-one clock timing 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 4 memory read 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 5 memory write 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 6 parallel i/o port read 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 7 parallel i/o port write 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 8 memory read with externally generated wait-states 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 9 memory write with externally generated wait-states 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 10 i/o read with externally generated wait-states 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 11 i/o write with externally generated wait-states 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 12 interrupt timing 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 13 dsp_iaq and dsp_iack timings 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 14 dsp_xf timing 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 15 dsp_tout timing 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 16 mcbsp receive timings 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 17 mcbsp transmit timings 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 18 mcbsp general-purpose i/o timings 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 19 mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 65 . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 20 mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 66 . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 21 mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 67 . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 22 mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 68 . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 23 sdram read command (cas latency 3) 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 24 sdram write command 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 25 sdram active command 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 26 sdram precharge command 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 27 sdram deactivate command 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figures viii december 2001 ? revised december 2002 sprs017b figure page 6 ? 28 sdram refresh command 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 29 sdram mode register set command 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 30 definition of timing on the i 2 c bus 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 31 i 2 c bus timings (stop and start conditions) 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 32 i 2 c bus timings (repeated start condition) 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 33 arm sram write timing 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 34 arm sram read timing 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 35 spi falling edge timings 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 36 spi rising edge timings 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ? 1 tms320vc5470 257-ball microstar bga plastic ball grid array package 82 . . . . . . . . . . . . . . . . . . . tables ix december 2001 ? revised december 2002 sprs017b list of tables table page 2 ? 1 pin assignments for the ghk package 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 2 terminal functions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ? 3 internal pullup/pulldown terminal list 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 1 cpu memory-mapped registers 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 2 peripheral memory-mapped registers 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 3 mcbsp control registers and subaddresses 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 4 bank-switching control register (bscr) bit fields 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 5 relationship between bnkcmp and bank size 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 6 state of signals when external bus interface is disabled (exio = 1) 20 . . . . . . . . . . . . . . . . . . . . . . . 3 ? 7 sample rate generator clock source selection 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 8 dma interrupts 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 9 dma synchronization events 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 10 dma channel interrupt selection 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 11 dsp clock scaler values and minimum refclk frequencies 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 12 dsp interrupt mapping 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ? 13 ifr and imr register bit fields 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 1 mcu memory space 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 2 gpio control/status bits 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 3 gpio_irq bits definition 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 4 mcu peripheral interrupt mapping 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 5 reset management 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 6 dsp boot memory 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 7 emulation mode selection 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 ? 8 jtag tap controller instruction register lengths 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 1 thermal resistance characteristics 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 2 divide-by-two/divide-by-four clock option timing requirements 47 . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 3 divide-by-two/divide-by-four clock option switching characteristics 47 . . . . . . . . . . . . . . . . . . . . . . 6 ? 4 multiply-by-n timing requirements 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 5 multiply-by-n switching characteristics 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 6 memory read timing requirements 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 7 memory read switching characteristics 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 8 memory write switching characteristics 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 9 parallel i/o port read timing requirements 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 10 parallel i/o port read switching characteristics 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 11 parallel i/o port write switching characteristics 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 12 ready timing for externally generated wait-states timing requirements 55 . . . . . . . . . . . . . . . . . . 6 ? 13 reset and interrupt timing requirements 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 14 dsp_iaq and dsp_iack switching characteristics 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 15 dsp_xf and dsp_tout switching characteristics 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 16 mcbsp receive and transmit timing requirements 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 17 mcbsp receive and transmit switching characteristics 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 18 mcbsp general-purpose timing requirements 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 19 mcbsp general-purpose switching characteristics 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tables x december 2001 ? revised december 2002 sprs017b table page 6 ? 20 mcbsp as spi master or slave timing requirements (clkstp = 10b and clkxp = 0) 65 . . . . . . . 6 ? 21 mcbsp as spi master or slave switching characteristics (clkstp = 10b and clkxp = 0) 65 . . . 6 ? 22 mcbsp as spi master or slave timing requirements (clkstp = 11b and clkxp = 0) 66 . . . . . . . 6 ? 23 mcbsp as spi master or slave switching characteristics (clkstp = 11b and clkxp = 0) 66 . . . 6 ? 24 mcbsp as spi master or slave timing requirements (clkstp = 10b and clkxp = 1) 67 . . . . . . . 6 ? 25 mcbsp as spi master or slave switching characteristics (clkstp = 10b and clkxp = 1) 67 . . . 6 ? 26 mcbsp as spi master or slave timing requirements (clkstp = 11b and clkxp = 1) 68 . . . . . . . 6 ? 27 mcbsp as spi master or slave switching characteristics (clkstp = 11b and clkxp = 1) 68 . . . 6 ? 28 synchronous dram timing requirements 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 29 synchronous dram switching characteristics 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 30 i 2 c bus device switching characteristics of the sda and scl bus lines 73 . . . . . . . . . . . . . . . . . . . 6 ? 31 i 2 c bus device timing requirements (stop and start conditions) 74 . . . . . . . . . . . . . . . . . . . . . . 6 ? 32 i 2 c bus device timing requirements (repeated start condition) 74 . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 33 arm sram switching characteristics 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 34 arm sram timing requirements (write) 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 35 arm sram timing requirements (read) 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 36 spi clock switching characteristics 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 37 spi falling edge timing requirements 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ? 38 spi rising edge timing requirements 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . features 1 december 2001 ? revised december 2002 sprs017b 1 tms320vc5470 features dual cpu processor integrating a tms320c54x ? dsp and an arm7tdmi ? risc mcu 16-bit low-power dsp with 72k x 16-bit integrated sram operates at up to 100 mhz smart power management and low-power modes for dsp and mcu subsystems integrated dsp subsystem peripherals ? two high-speed, full-duplex multichannel buffered serial ports (mcbsps) allowing the dsp core to interface directly with codecs ? six-channel direct memory access (dma) controller enabling six independent block transfers with no intervention from the dsp ? arm ? port interface (api) provides 2k x 16-bit shared memory interface for efficient information exchange between the mcu subsystem and the dsp subsystem cpus ? external memory interface ? software-programmable wait-state generator capable of extending external bus cycles by up to 14 machine cycles ? one software-programmable hardware timer for control operations ? programmable phase-locked loop (pll) clock generator arm7tdmi risc microcontroller core with 16k bytes of integrated sram and enhanced emulation capabilities operates at up to 47.5 mhz integrated mcu subsystem peripherals ? universal asynchronous receiver/ transmitter (uart) ? uart/irda interface which supports the slow infrared (sir) protocol ? serial peripheral interface ? thirty-six general-purpose i/o pins ? inter-integrated circuit (i 2 c) interface ? two general-purpose timers ? one watchdog timer ? interrupt handler ? interface to external memory supports flash, sram, sdram, rom ? flexible clock management for mcu peripherals ? programmable phase-locked loop (pll) clock generator on-chip scan-based emulation logic, ieee std 1149.1 ? (jtag) boundary scan logic of dsp and mcu cores supports scan-based emulation of dsp and mcu cores 257-ball microstar bga ? (ghk suffix) package other trademarks are the property of their respective owners. arm7tdmi is a trademark of arm limited. tms320c54x and microstar bga are trademarks of texas instruments. ? ieee standard 1149.1-1990 standard-test-access port and boundary scan architecture. arm is a registered trademark of arm limited. introduction 2 december 2001 ? revised december 2002 sprs017b 2 introduction this section describes the main features, gives a brief functional overview of the tms320vc5470, lists the pin assignments, and provides a signal description table. the data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data section describing the available packaging. note: this data manual is designed to be used in conjunction with the tms320c54x ? dsp functional overview (literature number spru307) and the tms320vc547x cpu and peripherals reference guide (literature number spru038). 2.1 description the tms320vc5470 integrates a dsp subsystem based on the tms320c54x architecture and a risc microcontroller subsystem based on the arm7tdmi core as shown in figure 2 ? 1. the dsp subsystem includes 72k x 16-bit sram, a timer, a dma controller, an external memory interface, and two mcbsps. the mcu subsystem includes three timers, general-purpose i/o, and an external memory interface. the tms320vc5470 is implemented as two major subsystems that are highly independent. the dsp subsystem includes the following modules: ? tms320c54x ? dsp core ? 72k x 16-bit internal sram organized as 32k x 16-bit of data sram and 40k x 16-bit of program sram. ? arm port interface (api) to provide access by the mcu to 8k x 16 of the dsp ? s data sram ? two multichannel buffered serial ports (mcbsps) ? phase-locked loop (pll) ? timer ? direct memory access (dma) controller ? programmable wait-state generator ? external memory interface the mcu subsystem includes the following modules: ? arm7tdmi cpu core (32/16-bit risc processor) with extended emulation capabilities ? mcu memory interface for external sram, flash, rom, and sdram. ? on-chip 16k-byte (4k x 32) zero wait-state sram. ? mcu general-purpose i/os (gpios), including support for an 8 x 8 keyboard. ? three timers (two general-purpose, one watchdog) ? irda-compatible uart, supporting two modes ? irda mode ? uart mode without hardware flow control ? uart/modem, with ? hardware flow control support ? autobaud function ? mcu subsystem interrupt handler ? clock generator and control ? i 2 c ? master-only ? interface ? serial peripheral interface ? phase-locked loop (pll) introduction 3 december 2001 ? revised december 2002 sprs017b interrupt handler i 2 c 8 k 16 prog ram 8 k 16 prog ram 8 k 16 prog ram 8 k 16 prog ram c54x ? dsp arm7tdmie dma mcbsp timer mcbsp 8 k 16 data ram 8 k 16 prog ram api pll memory i/f dspss i/f xio timer timer watchdog spi clock manager pll 4k 32 ram uart uart/irda gpio/keypad async, flash, sdram, etc. i2c device keypad general- purpose i/os spi device irda transceiver rs232 transceiver clock oscillator external dsp memory codec codec dsp subsystem tms320vc5470 8 k 16 data ram 8 k 16 data ram 8 k 16 data ram mcu subsystem figure 2 ? 1. 5470 functional block diagram c54x is a trademark of texas instruments. introduction 4 december 2001 ? revised december 2002 sprs017b 2.2 pin assignments figure 2 ? 2 illustrates the ball locations for the 257-ball ball grid array (bga) package and is used in conjunction with table 2 ? 1 to locate signal names and ball grid numbers. 19 17 16 13 14 15 11 12 9 8 10 v u w r n p l m k t 7 5 6 3 4 h f g e c d 1 a b 2 j 18 figure 2 ? 2. 257-ball ghk package (bottom view) table 2 ? 1. pin assignments for the ghk package ball no. signal name ball no. signal name ball no. signal name ball no. signal name b2 gpio02 b1 gpio03 d3 gpio04 c2 gpio05/ sdram_cke c1 gpio06/ clk16x_irda/sd_irda d2 gpio07/ tx_irda/txir_irda d1 gpio08/ rx_irda/rxir_irda e3 dv dd f5 gpio09/ tx_modem g6 v ss e2 gpio10/ rx_modem e1 gpio11/ cts_modem f3 gpio12/ rts_modem f2 gpio13/ dcd_modem g5 cv dd f1 gpio18/ audio_clk h6 gpio19/ timer_out g3 gpio00 g2 gpio14/ mcuen2 g1 gpio16/ sda h5 dv dd h3 gpio17/ scl h2 v ss h1 kbgpio14/ dsp_clkout j1 kbgpio02/ arm_opc j2 kbgpio03/ arm_mreq j3 kbgpio04/ arm_exec j5 kbgpio06/ arm_fiq j6 kbgpio07/ arm_irq k1 kbgpio13/ dsp_tout k2 kbgpio11/ dsp_iaq k3 cv dd k5 kbgpio05/ arm_tbit k6 kbgpio01/ dsp_xf l1 kbgpio15/ arm_mclk l2 kbgpio00 l3 v ss l6 kbgpio12/ dsp_msc l5 kbgpio10/ dsp_iack m1 kbgpio08 note: dv dd is the 3.3 v power supply for the i/o pins while cv dd is the 1.8 v power supply for the core cpu. v ss is the ground for both the i/o pins and the core cpu. introduction 5 december 2001 ? revised december 2002 sprs017b table 2 ? 1. pin assignments for the ghk package (continued) ball no. signal name ball no. signal name ball no. signal name ball no. signal name m2 kbgpio09 m3 gpio01 m6 gpio15/ mcuen1 m5 clkx_spi n1 mcudi/ extern0 n2 mcudo/ extern1 n3 dv dd n6 mcuen0 p1 n/c p2 n/c n5 v ss p3 n/c r1 n/c p6 n/c r2 n/c p5 cv dd r3 n/c t1 n/c t2 n/c u1 n/c t3 dv dd u2 n/c v1 n/c u3 n/c v2 n/c w2 n/c u4 n/c v3 n/c w3 n/c v4 n/c w4 n/c u5 n/c r6 v ss p7 n/c v5 n/c w5 n/c u6 dv dd v6 n/c r7 n/c w6 n/c p8 n/c u7 n/c v7 n/c w7 n/c r8 cv dd u8 n/c v8 emu1 w8 trst w9 tck v9 tdi u9 v ss r9 tdo p9 dv dd w10 tms v10 emu0 u10 refclk r10 reset p10 reset_out w11 add17 v11 add16 u11 add15 p11 add14 r11 add13 w12 add12/ sdram_a12 v12 add11/ sdram_a11 u12 v ss p12 add10/ sdram_a10 r12 dv dd w13 add01/ sdram_a01 v13 add09/ sdram_a09 u13 add08/ sdram_a08 p13 add07/ sdram_a07 w14 add06/ sdram_a06 v14 add05/ sdram_a05 r13 cv dd u14 add04/ sdram_a04 w15 add03/ sdram_a03 p14 v ss v15 add02/ sdram_a02 r14 dv dd u15 add00/ sdram_a00 w16 add18/ sdram_ba0 v16 add19 sdram_ba1 w17 add20/ sdram_we u16 add21/ sdram_cas v17 add22/ sdram_ras w18 cs4/ bigend u17 data00 v18 data01 v19 data02 t17 v ss u18 data03 u19 data04 t18 dv dd t19 data05 r17 data06 p15 data07 n14 cv dd r18 data08 r19 data09 p17 data10 p18 data11 n15 v ss p19 data12 m14 dv dd n17 data13 n18 data14 n19 data15 m15 data16 m17 data17 m18 data18 m19 data19 l19 data20 l18 data21 l17 v ss l15 data22 l14 data23 k19 be0 / sdram_dqm0 k18 dv dd k17 be1 / sdram_dqm1 k15 be2 / sdram_dqm2 k14 be3 / sdram_dqm3 j19 cs0 j18 cs1 j17 cs2 j14 cs3 / romsize16 j15 v ss h19 oe h18 wait h17 dv dd h14 r/w h15 sdram_clk g19 sdram_cs g18 data24 g17 cv dd g14 data25 f19 data26 f18 data27 g15 v ss f17 data28 note: dv dd is the 3.3 v power supply for the i/o pins while cv dd is the 1.8 v power supply for the core cpu. v ss is the ground for both the i/o pins and the core cpu. introduction 6 december 2001 ? revised december 2002 sprs017b table 2 ? 1. pin assignments for the ghk package (continued) ball no. signal name ball no. signal name ball no. signal name ball no. signal name e19 data29 f14 data30 e18 data31 f15 dv dd e17 bdx0 d19 bfsx0 d18 bclkx0 c19 bdr0 d17 v ss c18 bclkr0 b19 bfsr0 c17 bdr1 b18 bfsr1 a18 bclkr1 c16 bfsx1 b17 bclkx1 a17 bdx1 b16 dsp_a00 a16 dsp_a01 c15 dsp_a02 e14 dv dd f13 v ss b15 dsp_a03 a15 dsp_a04 c14 dsp_a05 b14 dsp_a06 e13 dsp_a07 a14 dsp_a08 f12 v ss c13 dsp_a09 b13 dsp_a10 a13 dsp_a11 e12 dv dd c12 dsp_a12 b12 dsp_a13 a12 dsp_a14 a11 dsp_a15 b11 dsp_a16 c11 v ss e11 dsp_a17 f11 dsp_a18 a10 dsp_a19 b10 cv dd c10 dsp_d00 e10 dv dd f10 dsp_d01 a9 dsp_d02 b9 dsp_d03 c9 v ss f9 dsp_d04 e9 dsp_d05 a8 dsp_d06 b8 dsp_d07 c8 dv dd f8 dsp_d08 e8 dsp_d09 a7 dsp_d10 b7 dsp_d11 c7 v ss f7 dsp_d12 a6 dsp_d13 b6 dsp_d14 e7 dv dd c6 dsp_d15 a5 cv dd f6 dsp_mstrb b5 dsp_ds e6 v ss c5 dsp_int0 a4 dsp_iostrb b4 dsp_is a3 dsp_ps c4 dv dd b3 dsp_ready a2 dsp_r/w c3 v ss e5 n/c note: dv dd is the 3.3 v power supply for the i/o pins while cv dd is the 1.8 v power supply for the core cpu. v ss is the ground for both the i/o pins and the core cpu. introduction 7 december 2001 ? revised december 2002 sprs017b 2.3 terminal functions table 2 ? 2 lists each terminal name, function, and operating mode(s) for the 5470 device. some of the 5470 pins can be configured for one of two functions ? a primary function and a secondary function. table 2 ? 3 provides a list of pins containing an internal pullup or pulldown function, including each pins functional pullup or pulldown value. table 2 ? 2. terminal functions terminal name i/o/z ? description gpio00 ? gpio04 i/o general-purpose input/output 00 through general-purpose input/output 04 gpio05/sdram_cke i/o general-purpose input/output 05 or sdram cke signal gpio06/clk16x_irda/sd_irda i/o general-purpose input/output 06 or 16x serial transmit clock or irda transceiver shutdown gpio07/tx_irda/txir_irda i/o general-purpose input/output 07 or irda transmit data or irda transmit pulse gpio08/rx_irda/rxir_irda i/o general-purpose input/output 08 or irda receive data or irda receive pulse gpio09/tx_modem i/o general-purpose input/output 09 or modem tx data output gpio10/rx_modem i/o general-purpose input/output 10 or modem rx data input gpio11/cts_modem i/o general-purpose input/output 11 or modem clear-to-send input gpio12/rts_modem i/o general-purpose input/output 12 or modem ready-to-send output gpio13/dcd_modem i/o general-purpose input/output 13 or modem carrier detect output gpio14/mcuen2 i/o general-purpose input/output 14 or spi enable trigger bit 2 gpio15/ mcuen1 i/o general-purpose input/output 15 or spi enable trigger bit 1 gpio16/sda i/o general-purpose input/output 16 or i2c serial data gpio17/scl i/o general-purpose input/output 17 or i2c serial clock gpio18/audio_clk i/o general-purpose input/output 18 or audio clock output gpio19/timer_out i/o general-purpose input/output 19 or mcu timer 2 output kbgpio00 i/o keyboard input/output 0 kbgpio01/dsp_xf i/o keyboard input/output 1or dsp xf output kbgpio02/arm_opc i/o keyboard input/output 2 or active-low mcu opcode fetch output kbgpio03/arm_mreq i/o keyboard input/output 3 or active-low mcu memory request output kbgpio04/arm_exec i/o keyboard input/output 4 or active-low mcu executed output kbgpio05/arm_tbit i/o keyboard input/output 5 or mcu 16/32-bit instruction execution output kbgpio06/arm_fiq i/o keyboard input/output 6 or active-low mcu fast interrupt output kbgpio07/arm_irq i/o keyboard input/output 7 or mcu normal interrupt output kbgpio08 ? kbgpio09 i/o keyboard input/output bits 8 ? 9 ? kbgpio10/dsp_iack i/o keyboard input/output 10 or dsp interrupt acknowledge output ? kbgpio11/dsp_iaq i/o keyboard input/output 11 or active-low dsp instruction acquisition signal output ? kbgpio12/dsp_msc i/o keyboard input/output 12 or active-low dsp microstate complete signal output ? kbgpio13/dsp_tout i/o keyboard input/output 13 or dsp timer output ? kbgpio14/ dsp_clkout i/o keyboard input/output 14 or dsp clock output ? kbgpio15/arm_mclk i/o keyboard input/output 15 or mcu clock output ? clkx_spi o spi serial clock mcudi/extern0 i spi input serial data/mcu extern0 test signal input mcudo/extern1 i/o spi output serial data/mcu extern1 test signal input ? i = input, o = output, z = high-impedance ? the kbgpio[15:8] pins include integrated pullup resistors. the arm7tdmi core can operate in either little- or big-endian mode. the 5470 configures the arm7tdmi core ? s endianness by sampling this pin at the reset rising edge. ? 5470 only supports mcu boot from a 16-bit or a 32-bit-wide memory implementation on cs0 . the 5470 configures the arm7tdmi starting instruction size, and width of memory connected to cs0 , by sampling this pin at the reset rising edge. introduction 8 december 2001 ? revised december 2002 sprs017b table 2 ? 2. terminal functions (continued) terminal name description i/o/z ? mcuen0 o spi enable trigger (edge/level, positive/negative) emu0 ? emu1 i/o test emulation pins 0 and 1, active-low trst i test reset input, active-low. a pulldown resistor is suggested to allow both normal device operation and emulation. tck i test clock tdi i test data input tdo o test data output tms i test mode select refclk i reference input clock reset i chip power-on reset, active-low ? reset_out o reset to external peripherals, active-low add00/ sdram_a00 ? add12/sdram_a12 o mcu address bus bits 0 through 12 for flash, sram, and sdram add13 ? add17 o mcu address bus bits 13 through 17 for flash and sram add18/ sdram_ba0 o mcu address bus bit 18 for flash and sram or sdram ba0 signal add19/ sdram_ba1 o mcu address bus bit 19 for flash and sram or sdram ba1 signal add20/ sdram_we o mcu address bus bit 20 for flash and sram or active-low sdram we signal add21/ sdram_cas o mcu address bus bit 21 for flash and sram or active-low sdram cas signal add22/ sdram_ras o mcu address bus bit 22 for flash and sram or active-low sdram ras signal cs4/ bigend i/o mcu chip select 4 (active-high). this pin is sampled at the reset rising edge to determine the endian mode as defined below: 0 = little endian 1 = big endian for best results, an external pullup or pulldown should be installed to ensure proper sampling. data00 ? data31 i/o mcu data bus bits 0 through 31 for flash, sram, and sdram be0 / sdram_dqm0 o mcu byte-enable for non-sdram cycles, or sdram byte-enable (for read) and mask (for write), active-low be1 / sdram_dqm1 o mcu byte-enable for non-sdram cycles, or sdram byte-enable (for read) and mask (for write), active-low be2 / sdram_dqm2 o mcu byte-enable for non-sdram cycles, or sdram byte-enable (for read) and mask (for write), active-low be3 / sdram_dqm3 o mcu byte-enable for non-sdram cycles, or sdram byte-enable (for read) and mask (for write), active-low cs0 o mcu chip select 0, active-low cs1 o mcu chip select 1, active-low cs2 o mcu chip select 2, active-low cs3 / romsize16 i/o mcu chip select 3, active-low. ? input sampled at reset rising edge to determine the width of the arm processor during initialization as defined below: 0 = 16 bits 1 = 32 bits for best results, an external pullup or pulldown should be installed to ensure proper sampling. ? i = input, o = output, z = high-impedance ? the kbgpio[15:8] pins include integrated pullup resistors. the arm7tdmi core can operate in either little- or big-endian mode. the 5470 configures the arm7tdmi core ? s endianness by sampling this pin at the reset rising edge. ? 5470 only supports mcu boot from a 16-bit or a 32-bit-wide memory implementation on cs0 . the 5470 configures the arm7tdmi starting instruction size, and width of memory connected to cs0 , by sampling this pin at the reset rising edge. introduction 9 december 2001 ? revised december 2002 sprs017b table 2 ? 2. terminal functions (continued) terminal name description i/o/z ? oe o mcu output-enable for peripherals connected to the mcu memory interface (not for sdram), active-low wait i mcu wait request, active-low. if this signal is unused, it must be pulled high with an external pullup resistor. r/w o asynchrouous memory active-high read / active-low write signal (not for sdram) sdram_clk o sdram clock sdram_cs o sdram chip-select, active-low bdx0 o/z mcbsp0 transmit serial data bfsx0 i/o/z mcbsp0 transmit frame synchronization bclkx0 i/o/z mcbsp0 transmit clock bdr0 i mcbsp0 receive serial data bclkr0 i/o/z mcbsp0 receive clock bfsr0 i/o/z mcbsp0 receive frame synchronization bdr1 i mcbsp1 receive serial data bfsr1 i/o/z mcbsp1 receive frame synchronization bclkr1 i/o/z mcbsp1 receive clock bfsx1 i/o/z mcbsp1 transmit frame synchronization bclkx1 i/o/z mcbsp1 transmit clock bdx1 o/z mcbsp1 transmit data dsp_a00 ? dsp_a19 o/z dsp address bits 0 through 19 dsp_d00 ? dsp_d15 i/o/z dsp data bus bits 0 through 15 dsp_mstrb o/z dsp memory strobe signal, active-low dsp_ds o/z dsp data space select, active-low dsp_int0 i dsp external interrupt, active-low. if this signal is unused, it should be pulled high with an external pullup resistor. dsp_iostrb o/z dsp i/o strobe signal, active-low dsp_is o/z dsp i/o space select, active-low dsp_ps o/z dsp program space select, active-low dsp_ready i dsp data ready input (tie high if not used), active-high. if this signal is unused, it must be pulled high with an external pullup resistor. dsp_r/w o/z dsp active-high read / active-low write signal v ss ground cv dd 1.8-v supply for core logic dv dd 3.3-v supply for i/o cells n/c no connection ? i = input, o = output, z = high-impedance ? the kbgpio[15:8] pins include integrated pullup resistors. the arm7tdmi core can operate in either little- or big-endian mode. the 5470 configures the arm7tdmi core ? s endianness by sampling this pin at the reset rising edge. ? 5470 only supports mcu boot from a 16-bit or a 32-bit-wide memory implementation on cs0 . the 5470 configures the arm7tdmi starting instruction size, and width of memory connected to cs0 , by sampling this pin at the reset rising edge. introduction 10 december 2001 ? revised december 2002 sprs017b table 2 ? 3. internal pullup/pulldown terminal list terminal name i/o ball # type dsp_d00 i/o/z c10 ps100, 100- a pullup dsp_d01 i/o/z f10 ps100, 100- a pullup dsp_d02 i/o/z a9 ps100, 100- a pullup dsp_d03 i/o/z b9 ps100, 100- a pullup dsp_d04 i/o/z f9 ps100, 100- a pullup dsp_d05 i/o/z e9 ps100, 100- a pullup dsp_d06 i/o/z a8 ps100, 100- a pullup dsp_d07 i/o/z b8 ps100, 100- a pullup dsp_d08 i/o/z f8 ps100, 100- a pullup dsp_d09 i/o/z e8 ps100, 100- a pullup dsp_d10 i/o/z a7 ps100, 100- a pullup dsp_d11 i/o/z b7 ps100, 100- a pullup dsp_d12 i/o/z f7 ps100, 100- a pullup dsp_d13 i/o/z a6 ps100, 100- a pullup dsp_d14 i/o/z b6 ps100, 100- a pullup dsp_d15 i/o/z c6 ps100, 100- a pullup kbgpio08 i/o m1 ps100, 100- a pullup kbgpio09 i/o m2 ps100, 100- a pullup kbgpio10/dsp_iack i/o l5 ps100, 100- a pullup kbgpio11/dsp_iaq i/o k2 ps100, 100- a pullup kbgpio12/dsp_msc i/o l6 ps100, 100- a pullup kbgpio13/dsp_tout i/o k1 ps100, 100- a pullup kbgpio14/dsp_clkout i/o h1 ps100, 100- a pullup kbgpio15/arm_mclk i/o l1 ps100, 100- a pullup gpio16/sda i/o g1 ps100, 100- a pullup cs4/bigend i/o w18 pe100, 100- a pulldown cs3/romsize16 i/o j14 ps100, 100- a pullup emu0 i/o v10 ps100, 100- a pullup emu1 i/o v8 ps100, 100- a pullup tck i w9 pe100, 100- a pulldown trst i w8 pe100, 100- a pulldown tms i/o w10 ps100, 100- a pullup tdi i/o v9 ps100, 100- a pullup dsp subsystem functional overview 11 december 2001 ? revised december 2002 sprs017b 3 dsp subsystem functional overview the dsp subsystem is based on the tms320c54x dsp core, on-chip memories and peripherals, and is code-compatible with other c54x products. the following description of the 5470 dsp subsystem is based on figure 3 ? 1. 8 k 16 prog ram 8 k 16 prog ram 8 k 16 prog ram 8 k 16 prog ram c54x ? dsp dma mcbsp timer mcbsp 8 k 16 data ram 8 k 16 prog ram api pll xio external dsp memory codec codec dsp subsystem 8 k 16 data ram 8 k 16 data ram 8 k 16 data ram mcu subsystem figure 3 ? 1. 5470 dsp subsystem functional block diagram 3.1 dsp core the 5470 dsp subsystem ? s fixed-point, digital signal processor (dsp) is based on an advanced modified harvard architecture that has one program memory bus and three data memory buses. this processor provides an arithmetic logic unit (alu) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. the basis of the operational flexibility and speed of this dsp is a highly specialized instruction set. separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. two read operations and one write operation can be performed in a single cycle. instructions with parallel store and application-specific instructions can fully utilize this architecture. in addition, data can be transferred between data and program spaces. such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. in addition, the 5470 dsp subsystem includes the control mechanisms to manage repeated operations, function calls, and dsp interrupts. the dsp core includes the following features: ? low-power c54x ? dsp cpu, operating at up to 100 mhz ? software-programmable wait-state generator with bank-switching wait-state logic ? external memory interface ? program space ? data space ? i/o space ? scan-based emulation logic dsp subsystem functional overview 12 december 2001 ? revised december 2002 sprs017b the 5470 dsp subsystem includes the dsp cpu core, a programmable phase-locked loop (pll) for clock generation, an interface to external parallel devices, a timer, 72k words of ram, two multichannel buffered serial interfaces, an interface to allow mcu access to part of the dsp subsystem memory map, and a jtag interface. 3.1.1 dsp memory space and buses the 5470 subsystem has multiple memory spaces and four parallel buses that allow you to access both program and data simultaneously. each of the four buses access different memory spaces for different aspects of the dsp operation: ? the dsp subsystem includes 72k words of on-chip ram, as well as an extensive external memory range, which can be used to interface to a variety of memory types or peripherals. ? the program bus (pb) reads from program memory space, which contains the instructions to be executed. ? the write data bus (eb) writes into data memory space, which stores data used by the instructions and tables eventually used in execution. it also writes into i/o memory space. ? the two read data buses (cb and db) read data from the data memory space and the db data bus accesses i/o memory space. the i/o memory space interfaces to external memory-mapped peripherals and can serve as extra data storage space. 3.1.2 dsp scan-based emulation logic the 5470 dsp subsystem includes a dedicated emulation port for in-circuit emulation. the emulation port is accessed directly by the texas instruments (ti) extended development system (xds) hardware emulator and provides emulation. 3.2 dsp memory the 5470 device implements 72k words of on-chip ram as follows: ? 40k words of program-space single-access ram (saram) ? 16k words of data space dual-access ram (daram) ? 16k words of data space single-access ram (saram) each block of daram may perform up to two dsp accesses in one machine cycle. the dsp subsystem may also perform multiple accesses to separate memory blocks in one machine cycle. after a ? normal ? reset, the data-space ram blocks in the addresses between 0x0000 and 0x7fff are mapped into data memory space only, and the program space ram blocks between 0x06000 and 0x0ffff are mapped only to program space. the ovly and drom bits can affect this as shown in figure 3 ? 2 and figure 3 ? 3. 3.2.1 dsp on-chip ram the dsp subsystem features 72k x 16-bit of on-chip ram (two blocks of 8k x 16-bit daram and seven blocks of 8k x 16-bit saram). the dsp cpu can perform two accesses to a daram in one machine cycle (two reads in one cycle, or a read and a write in one cycle). it can also perform multiple accesses to separate memory blocks in one machine cycle. after reset, the lower address range of the program space is mapped to external memory, the lower address range of the data space is mapped with on-chip ram blocks. however, the ovly bit in the pmst register can be used to map these ram blocks into both program and data space. 3.2.2 normal mode dsp memory map the normal mode dsp subsystem provides the memory map shown in figure 3 ? 2. this is the memory map that applies when the api boot mode feature is not enabled. the normal mode memory map applies any time that dsp register bscr[4] (abmdis) is 1, or when mcu register dsp_reg[9] (dsp_apibn) is 1. dsp subsystem functional overview 13 december 2001 ? revised december 2002 sprs017b hex page 0 program, mp/mc = 1 (microprocessor mode) hex page 0 program, mp/mc = 0 (microcomputer mode) hex data 0000 ovly = 1 ovly = 0 0000 ovly = 1 ovly = 0 0000 007f reserved external program space memory 007f reserved external program space memory 007f memory mapped registers, scratch-pad ram 0080 on-chip data daram external program space 0080 on-chip data daram external program space 0080 on-chip data daram (8k ? 0x80 words) 1fff daram s pace memory 1fff daram s pace memory 1fff (8k ? 0 x 80 w or d s ) 2000 on-chip data daram api external program 2000 on-chip data daram api external program 2000 on-chip data daram, api accessible 3fff daram , api accessible program space memory 3fff daram , api accessible program space memory 3fff api a ccess ibl e (8k words) 4000 on-chip data external program 4000 on-chip data external program 4000 on-chip data saram 5fff on chip data saram program space memory 5fff on chip data saram program space memory 5fff on chip data saram (8k words) 6000 external program space memory 6000 on-chip program saram (8k words program only) 6000 on-chip data saram, (8k words data only) 7fff memory 7fff (8k words, program only) 7fff (8k words, data only) 8000 8000 on-chi p pro g ram saram 8000 9fff on-chip program saram (8k words, program only) external data space memory a000 on-chi p pro g ram saram external data space memory external program space bfff on-chip program saram (8k words, program only) bfff external program space memory c000 on-chip program saram c000 drom=1 drom=0 y dfff on chip program saram (8k words) on - chip external e000 on-chip program saram o n- chi p program saram e x t erna l data-space memory ffff ffff on chip program saram (8k words) ffff saram memory figure 3 ? 2. memory map for dsp accesses (dsp_apibn = 1 or abmdis = 1) 3.2.3 api boot mode under normal dsp subsystem reset conditions, the dsp will begin operation either from code that has been previously uploaded to internal program-space ram (when in microcontroller mode) or from external memory on the xio bus (microprocessor mode). uploading the code to internal program-space ram may be performed by the mcu. when the dsp subsystem is in api boot mode, the upper 2k words of the 8k-word api saram is shadowed so that it is found both in dsp data space at 0x3800 ? 0x3fff and in dsp program space at 0xf800 to 0xffff, which includes the dsp ? s reset vector. to make use of this mode, the mcu directly controls the dsp ? s reset and api boot mode signals. it holds the dsp in reset, enables api boot mode, and loads the dsp boot code via the api. once it has loaded the code to the appropriate location in the api saram, the mcu releases the dsp from reset, and the dsp begins executing from the normal reset location, where the uploaded code now resides. once the dsp code has completed any api boot activity, it may disable the memory remapping provided by the api boot mode by writing a 1 to bscr[4] (abmdis). it is recommended that the mcu change the api boot mode input signal only when the dsp is held in reset. dsp subsystem functional overview 14 december 2001 ? revised december 2002 sprs017b 3.2.4 api boot-mode dsp memory map the memory map when the api boot mode feature is enabled is shown in figure 3 ? 3. api boot mode is enabled when dsp_reg[9] (dsp_apibn) is 0 and bscr[4] (abmdis) is 0. hex page 0 program, mp/mc = 1 (microprocessor mode) hex page 0 program, mp/mc = 0 (microcomputer mode) hex data 0000 ovly = 1 ovly = 0 0000 ovly = 1 ovly = 0 0000 007f reserved external program space 007f reserved external program space 007f memory mapped registers, scratch-pad ram 0080 on-chip data daram 0080 on-chip data daram 0080 on-chip data daram (8k ? 0x80 words) 1fff daram 1fff daram 1fff (8k ? 0 x 80 w or d s ) 2000 external 2000 external 2000 on-chip data daram, api-accessible 37ff on-chip data daram , program space 37ff on-chip data daram , external program space 37ff api - a ccess ibl e (8k words) 3800 daram , api-accessible space 3800 daram , api-accessible g space 3800 (shadowed portion) 3fff 3fff 3fff ( s h a d owe d port i on ) 4000 on-chip data 4000 on-chip data 4000 on-chip data saram 5fff on chip data saram 5fff on chip data saram 5fff on chip data saram (8k words ? data only) 6000 6000 6000 on-chip data saram 7fff on chip data saram (8k words) 8000 external data space memory bfff e xterna l d ata s pace m emory c000 drom=1 drom=0 external program space external program space dfff on-chip program saram (8k words) external data space e000 on-chip program s pace memory f7ff f7ff f7ff program saram (6k words) f800 shadowed api daram (2k) f800 shadowed api daram (2k) f800 external data space memory ffff sh a d owe d api daram (2k) ffff sh a d owe d api daram (2k) ffff e xterna l d ata s pace m emory ? when dsp_reg[9] (dsp_apibn) = 0 and bscr[4] (abmdis) = 0, 2k words of the api daram are remapped to program-space, regardless o f dsp_reg[10] (mp/mc ) value. all other internal program-space rams are disabled in program space. overlayable data-space rams may be dual-mapped to program-space via ovly. figure 3 ? 3. api boot mode memory map for dsp accesses (dsp_apibn = 0 and abmdis = 0) ? dsp subsystem functional overview 15 december 2001 ? revised december 2002 sprs017b 3.2.5 dsp extended program memory the dsp subsystem includes a memory paging scheme to extend the number of addressable program space locations from 64k to 1m words. the four extended address pins (dsp_a16 to dsp_a19) are used to address 15 pages of program memory. each page includes 64k addressable locations. the extended program addresses are supported by eight instructions: fb[d], fbacc[d], fcala[d], fcall[d], fret[d], frete[d], reada, and writa. ? fb[d] ? far branch ? fbacc[d] ? far branch to the location specified by the value in accumulator a or accumulator b ? fcala[d] ? far call to the location specified by the value in accumulator a or accumulator b ? fcall[d] ? far call ? fret[d] ? far return ? frete[d] ? far return with interrupts enabled ? reada ? read program memory addressed by accumulator a and store in data memory ? writa ? write data to program memory addressed by accumulator a for more information on these instructions, please refer to the tms320c54x dsp reference set, volume 2: mnemonic instruction set (literature number spru172). when the ovly bit is set, each page of program memory is made up of two parts: a common block of 24k words maximum and a unique block of 40k words minimum. the common block is shared by all pages, and each unique block is accessible only through its assigned page. the value of the program counter extension register (xpc) defines the page selection. at a hardware reset, the xpc is initialized to 0. 0 0000 1 0000 1 5fff page 1 lower 24k ? external 2 0000 2 5fff page 2 lower 24k ? external . . . . . . f 0000 f 5fff page 15 lower 24k ? external page 0 1 6000 2 6000 f 6000 g 64k page 1 upper 40k external page 2 upper 40k external . . . . . . page 15 upper 40k external 0 ffff 1 ffff 2 ffff f ffff ? accesses to the lower 24k words of pages 1 through 15 are to external program memory only when the ovly bit is cleared to 0. if the ovly bit is set to 1, on-chip ram is mapped to 0x0 to 0x5fff of pages 1 through 15. note external address pins are provided to support 1 5 external pages. figure 3 ? 4. dsp extended program memory map 3.2.6 dsp relocatable interrupt vector table the reset, interrupt, and trap vectors are addressed in program space. these vectors are soft ? meaning that the processor, when taking the trap, loads the program counter (pc) with the trap address and executes the code at the vector location. four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead. dsp subsystem functional overview 16 december 2001 ? revised december 2002 sprs017b at device reset, the reset, interrupt, and trap vectors are mapped to address ff80h in program space. however, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. this is done by loading the interrupt vector pointer (iptr) bits in the pmst register with the appropriate 128-word page boundary address. after loading iptr, any user interrupt or trap vector is mapped to the new 128-word page. note: the hardware reset (rs) vector cannot be remapped because a hardware reset loads the iptr with 1s. therefore, the reset vector is always fetched at location ff80h in program space. 3.3 dsp registers the 5470 has 27 memory-mapped cpu registers, which are mapped in data memory space addresses 0h to 1fh. table 3 ? 1 gives a list of cpu memory-mapped registers (mmrs) available on 5470. the device also has a set of memory-mapped registers associated with peripherals as shown in table 3 ? 2. table 3 ? 1. cpu memory-mapped registers name address description name dec hex description imr 0 0 interrupt mask register ifr 1 1 interrupt flag register ? 2 ? 5 2 ? 5 reserved for testing st0 6 6 status register 0 st1 7 7 status register 1 al 8 8 accumulator a low word (15 ? 0) ah 9 9 accumulator a high word (31 ? 16) ag 10 a accumulator a guard bits (39 ? 32) bl 11 b accumulator b low word (15 ? 0) bh 12 c accumulator b high word (31 ? 16) bg 13 d accumulator b guard bits (39 ? 32) treg 14 e temporary register trn 15 f transition register ar0 16 10 auxiliary register 0 ar1 17 11 auxiliary register 1 ar2 18 12 auxiliary register 2 ar3 19 13 auxiliary register 3 ar4 20 14 auxiliary register 4 ar5 21 15 auxiliary register 5 ar6 22 16 auxiliary register 6 ar7 23 17 auxiliary register 7 sp 24 18 stack pointer register bk 25 19 circular buffer size register brc 26 1a block repeat counter rsa 27 1b block repeat start address rea 28 1c block repeat end address pmst 29 1d processor mode status (pmst) register xpc 30 1e extended program page register ? 31 1f reserved dsp subsystem functional overview 17 december 2001 ? revised december 2002 sprs017b this lists the 5470 dsp subsystem peripheral registers and describes those that are specific to the 5470 or are different from the standard c54x registers. the standard c54x registers are defined in the tms320vc5409 fixed-point digital signal processor data sheet (literature number sprs082) and the tms320vc5402 fixed-point digital signal processor data sheet (literature number sprs079). the dsp subsystem peripheral mapping is shown in table 3 ? 2. table 3 ? 2. peripheral memory-mapped registers name address description type drr20 20h data receive register 2 mcbsp #0 drr10 21h data receive register 1 mcbsp #0 dxr20 22h data transmit register 2 mcbsp #0 dxr10 23h data transmit register 1 mcbsp #0 tim 24h timer register timer prd 25h timer period counter timer tcr 26h timer control register timer ? 27h reserved swwsr 28h software wait-state register external bus bscr 29h bank-switching control register external bus, api ? 2ah reserved swcr 2bh software wait-state control register external bus ? 2ch ? 37h reserved spsa0 38h mcbsp0 subbank address register mcbsp #0 spsd0 39h mcbsp0 subbank data register mcbsp #0 ? 3ah ? 3bh reserved gpiocr 3c general-purpose i/o pins control register gpio gpiosr 3d general-purpose i/o pins status register gpio ? 3e ? 3f reserved drr21 40h data receive register 2 mcbsp #1 drr11 41h data receive register 1 mcbsp #1 dxr21 42h data transmit register 2 mcbsp #1 dxr11 43h data transmit register 1 mcbsp #1 ? 44h ? 47h reserved spsa1 48h mcbsp1 subbank address register mcbsp #1 spsd1 49h mcbsp1 subbank data register mcbsp #1 ? 4ah ? 53h reserved dmprec 54h dma channel priority and enable control register dma dmsa 55h dma subbank address register dma dmsdi 56h dma subbank data register with autoincrement dma dmsdn 57h dma subbank data register dma clkmd 58h clock mode register pll ? 59h ? 5fh reserved dsp subsystem functional overview 18 december 2001 ? revised december 2002 sprs017b table 3 ? 3. mcbsp control registers and subaddresses mcbsp0 mcbsp1 sub description name address name address sub address description spcr10 39h spcr11 49h 00h serial port control register 1 spcr20 39h spcr21 49h 01h serial port control register 2 rcr10 39h rcr11 49h 02h receive control register 1 rcr20 39h rcr21 49h 03h receive control register 2 xcr10 39h xcr11 49h 04h transmit control register 1 xcr20 39h xcr21 49h 05h transmit control register 2 srgr10 39h srgr11 49h 06h sample rate generator register 1 srgr20 39h srgr21 49h 07h sample rate generator register 2 mcr10 39h mcr11 49h 08h multichannel register 1 mcr20 39h mcr21 49h 09h multichannel register 2 rcera0 39h rcera1 49h 0ah receive channel enable register partition a rcerb0 39h rcerb1 49h 0bh receive channel enable register partition b xcera0 39h xcera1 49h 0ch transmit channel enable register partition a xcerb0 39h xcerb1 49h 0dh transmit channel enable register partition b pcr0 39h pcr1 49h 0eh pin control register 3.3.1 bank-switching control register the 5470 bank-switching control register (bscr) controls both the bank-switching wait-state generation functions that are consistent with the 5409, and several 5470-specific features. these special features include control of configuration of some dsp subsystem external memory interface functionality and some aspects of the interface whereby the mcu may access a portion of the dsp subsystem ram. the bscr is shown in figure 3 ? 5 and the bits are described in table 3 ? 4. the bscr register also gives the dsp some control over the arm programming interface, the mechanism which enables the mcu to access portions of the dsps internal ram. included are the api mode (apimode), an interrupt to the mcu (hint), and dsp memory map selection (abmdis). 15 12 11 10 5 4 3 2 1 0 bnkcmp ps ? ds reserved abm dis hint api mode reserved exio r/w-1111 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 legend: r = read, w = write figure 3 ? 5. bank-switching control register (bscr) dsp subsystem functional overview 19 december 2001 ? revised december 2002 sprs017b table 3 ? 4. bank-switching control register (bscr) bit fields bit reset function no. name reset value function 15 ? 12 bnkcmp 1111 bank compare. determines the external bank size. bnkcmp is used to mask the four msbs of an address. for example, if bnkcmp = 1111b, the four msbs (bits 15 ? 12) are compared, resulting in a bank size of 4k words. bank sizes of 4k words to 64k words are allowed. table 3 ? 5 shows the relationship between bnkcmp and the address range. 11 ps ? ds 1 program read ? data read access. inserts an extra cycle between consecutive accesses of program read and data read, or data read and program read. ? ps ? ds = 0: no extra cycles are inserted by this feature ? ps ? ds = 1: one extra cycle is inserted between consecutive data and program reads. 10 ? 5 reserved 0 these bits are reserved and will retain written values. 4 abmdis 0 api boot mode disable. this bit will force the dsp out of api boot mode. this bit has no effect when the dsp_apibn is high. when dsp_apibn is low, a 0 in this bit enables api boot mode and a 1 disables api boot mode. note that a dsp subsystem reset will clear this bit and thus re-enable the dsp_apibn port. ? abmdis = 0: api boot mode is under the control of dsp_apibn ? abmdis = 1: dsp_apibn is ignored and dsp subsystem is kept out of api boot mode . 3 hint 0 host processor interrupt. this bit enables/disables an interrupt to the mcu from the dsp. at reset, the hint bit is cleared. to send a proper interrupt to the mcu, the dsp must write a 1 to hint, delay an appropriate time, then write a 0 to hint to create a pulse of an appropriate duration on the interrupt signal to the mcu. ? hint = 0: interrupt signal to the mcu is not active ? hint = 1: interrupt signal to the mcu is active 2 apimode 0 hom/sam enable. this bit enables/disables the api host-only mode. ? apimode = 0: the shared-access mode (sam) is enabled. both the dsp and the mcu may access the api ram. ? apimode = 1: the host-only mode (hom) is enabled. the mcu may access the api ram; the dsp may not access the api ram. dsp writes to the api ram are ignored, and dsp reads from the api ram return undefined values. dsp idle modes have no effect on mcu accesses to the api memory when in host-only mode. 1 reserved 0 these bits are reserved and will retain written values. 0 exio 0 external bus interface off. the exio bit controls the external bus-off function. ? exio = 0: the external bus interface functions as usual. ? exio = 1: the address bus, data bus, and control signals become inactive after completing the current bus cycle. table 3 ? 6 lists the states of the external interface signals when the interface is disabled. note that the drom, mp/mc , and ovly bits in the pmst and the hm bit of st1 cannot be modified when the interface is disabled. 3.3.2 programmable bank-switching wait-states the bank-switching features of the programmable bank-switching logic of the 5470 dsp subsystem is functionally equivalent to that of the 5409. this feature automatically inserts one cycle when accessing across memory-bank boundaries within program or data memory space. a bank-switching wait-state can also be automatically inserted when accessing across the data space to program space boundary. these features are programmed via the bnkcmp and ps ? ds bits in the bscr. the relationship between bnkcmp, the address bits to be compared, and the bank size is summarized in table 3 ? 5. the bnkcmp values that are not listed in the table are not allowed. dsp subsystem functional overview 20 december 2001 ? revised december 2002 sprs017b table 3 ? 5. relationship between bnkcmp and bank size bnkcmp msbs to compare bank size bit 15 bit 14 bit 13 bit 12 msbs to compare (16-bit words) 0 0 0 0 none 64k 1 000 15 32k 1 100 15 ? 14 16k 1 110 15 ? 13 8k 1 1 1 1 15 ? 12 4k the external memory interface can be disabled when not used. this feature can be used to reduce the power consumption of the 5470 dsp subsystem. table 3 ? 6 lists the states of the external interface pins, when the interface is disabled (exio=1). table 3 ? 6. state of signals when external bus interface is disabled (exio = 1) signal state signal state dsp_a(19 ? 0) previous state dsp_mstrb high level dsp_d(15 ? 0) high impedance dsp_iostrb high level dsp_ps high level dsp_r/w high level dsp_ds high level kbgpio12/dsp_msc ? high level dsp_is high level kbgpio11/dsp_iaqz ? high level ? only applies when kbgpio12 is enabled to output dsp_msc . ? only applies when kbgpio11 is enabled to output dsp_iaq 3.3.3 processor mode status register the 5470 dsp subsystem processor mode status register (pmst) differs from the typical c54x design in that the pmst clkout bit has no effect on the clkout port of the subsystem. this port is always clocking when the dsp subsystem ? s pll is active. dsp subsystem functional overview 21 december 2001 ? revised december 2002 sprs017b 3.4 dsp peripherals the following section describes how the 5470 dsp subsystem peripherals differ from standard peripherals as found on the tms320vc5409. 3.4.1 multichannel buffered serial port (mcbsp) the 5470 provides high-speed, full-duplex serial ports that are similar to those found on the 5409 device. they allow direct interface to other 54x devices, codecs, and other devices in a system. there are two multichannel buffered serial ports (mcbsps) within the dsp subsystem. 3.4.1.1 deriving sample clock from an external clock to accommodate applications that require an external reference clock to be divided down to create the frame sync clock and internal sample rate clock, the 5470 mcbsp allows either the receive clock pin (bclkr) or the transmit clock pin (bclkx) to be configured as the input clock to the sample rate generator. this enhancement is enabled through two register bits: pin control register (pcr) bit 7 [enhanced sample clock mode (sclkme)] and sample rate generator register 2 (srgr2) bit 13 [mcbsp sample rate generator clock mode (clksm)]. sclkme is an addition to the pcr contained in the mcbsps on previous tms320c5000 ? dsp platform devices. the new bit layout of the pcr is shown in figure 3 ? 6. for a description of the remaining bits, see tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302). 15 14 13 12 11 10 9 8 reserved xioen rioen fsxm fsrm clkxm clkrm rw rw rw rw rw rw rw 76543210 sclkme clks stat dx stat dr stat fsxp fsrp clkxp clkrp rw rw rw rw rw rw rw rw legend: r = read, w = write figure 3 ? 6. pin control register (pcr) the selection of the sample rate generator (srg) clock input source is made by the combination of the clksm and sclkme bit values as shown in table 3 ? 7. table 3 ? 7. sample rate generator clock source selection sclkme clksm srg clock source 0 0 reserved 0 1 dsp_cpu clock 1 0 bclkr pin 1 1 bclkx pin when either of the bidirectional pins, bclkr or bclkx, is configured as the clock input, its output buffer is automatically disabled. for example, with sclkme = 1 and clksm = 0, the bclkr pin is configured as the srg input. in this case, both the transmitter and receiver circuits can be synchronized to the srg output by setting the pcr bits (9:8) for clkxm = 1 and clkrm = 1. however, the srg output is only driven onto the bclkx pin since the bclkr pin is used in input mode. tms320c5000 is a trademark of texas instruments. dsp subsystem functional overview 22 december 2001 ? revised december 2002 sprs017b 3.4.2 dsp direct memory access (dma) controller the dsp subsystem includes a six-channel dma controller, for performing data transfers independent of the dsp. there are several limitations that the 5470 dma controller places on its dma transfers. the dma controller has no access to the rams that are normally in program space, cannot access rams that are implemented in the mcu subsystem, and cannot access the ram block in dsp data space that is connected to the api interface. the dma controller cannot transfer between the mcbsp drr and dxr registers, nor can it transfer between mcbsp drr or dxr registers and external resources. the dma controller cannot perform 32-bit accesses to external resources. 3.4.2.1 dma controllers view of the dsp memory map note that the dma controller has access only to the data space daram at 0x0080 to 0x1fff and the data space sarams that are at 0x4000 to 0x7fff. it does not have access to any of the sarams in program space between 0x6000 and 0xffff, or to the api daram at 0x2000 to 0x3fff. the api module has access to the 8k x 16 daram block at data space 0x2000 to 0x3fff. note also that the dma controller can access external data space devices with extended addressing, while the dsp can only access page 0 of external data space. 3.4.2.2 dsp dma external access the dma supports external accesses to extended program space, extended data space, and extended i/o space. ? no more than one channel may be programmed for external writes at any time ? no more than one channel may be programmed for external reads at any time ? only single-word transfers are supported for external accesses. ? the dma does not support transfers from peripherals to external memory. ? the dma does not support transfers from external memory to the peripherals. 3.4.2.3 dsp dma transfers in doubleword mode (internal only) doubleword mode allows the dma to transfer 32-bit words in any index mode. in doubleword mode, two consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated following each transfer. in this mode, each 32-bit word is considered to be one element. 3.4.2.4 dsp dma interrupts the ability of the dma to interrupt the dsp based on the status of the data transfer is configurable and is determined by the imod and dinm bits in the dma channel mode control register (dmmcrn). the available modes are shown in table 3 ? 8. table 3 ? 8. dma interrupts mode dinm imod interrupt abu (non-decrement) 1 0 at full buffer only abu (non-decrement) 1 1 at half buffer and full buffer multi-frame 1 0 at block transfer complete (dmctrn = dmsefcn[7:0] = 0) multi-frame 1 1 at end of frame and end of block (dmctrn = 0) abu or multi-frame 0 x no interrupt generated abu or multi-frame 0 x no interrupt generated dsp subsystem functional overview 23 december 2001 ? revised december 2002 sprs017b 3.4.2.5 dma controller synchronization events the internal transfers associated with each dma channel can be synchronized to one of several events. the dsyn bit field of the dmsefcn register selects the synchronization event for a channel. the list of possible events and the dsyn values are shown in table 3 ? 9. table 3 ? 9. dma synchronization events dsyn value dma synchronization event 0000b no synchronization used 0001b mcbsp0 receive event 0010b mcbsp0 transmit event 0011b reserved 0100b reserved 0101b mcbsp1 receive event 0110b mcbsp1 transmit event 0111b reserved 1000b reserved 1001b reserved 1010b reserved 1011b reserved 1100b reserved 1101b timer interrupt event 1110b external interrupt 0 1111b reserved 3.4.2.6 dsp dma channel interrupt selection the dma controller can generate a dsp interrupt for each of the six channels. however, due to a limit on the number of internal dsp interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. dma channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the mcbsp. when the dsp is reset, the interrupts from these three dma channels are deselected. the intsel bit field in the dmprec register can be used to select these interrupts, as shown in table 3 ? 10. table 3 ? 10. dma channel interrupt selection intsel value imr/ifr[6] imr/ifr[7] imr/ifr[10] imr/ifr[11] 00b (reset) reserved reserved brint1 bxint1 01b reserved reserved dmac2 dmac3 10b dmac0 dmac1 dmac2 dmac3 11b reserved 3.4.3 arm port interface (api) information is exchanged between the mcu and the dsp through the on-chip shared api memory. the api memory is a 8k 16-bit word daram (dual-access ram) block. the api memory can also be used by the dsp as general-purpose data or program daram. in this circuit, only the dsp memory has daram. the api has two modes of operation selected by the bank switching control register (bscr): shared-access mode (sam) and host-only mode (hom). in sam, both the dsp and the mcu can access the api memory. in sam, asynchronous host accesses from the mcu are resynchronized internally. if the dsp and the mcu try to perform an access at the same time, the mcu has access priority and the dsp waits one cycle. sam can be run when the dsp is in idle1 mode. in hom, only the mcu can access the api memory. when hom is selected, api memory blocks are disabled for dsp access, no value can be read from nor written to those memory locations. dsp subsystem functional overview 24 december 2001 ? revised december 2002 sprs017b sam is the default configuration when the dsp exits from a reset phase. sam is normally selected whenever the dsp is in normal operating mode or in idle 1. hom is normally selected before the dsp is placed in idle2 or idle3. 3.4.4 dsp external memory interface the 5470 external memory interface is largely identical to that of the 5409. significant differences include the lack of a mp/mc pin, and multiplexing of dsp_msc , dsp_iaq , dsp_iack , and dsp_clkout functions on kbgpio pins. 3.4.5 dsp software-programmable wait-state generator the 5470 dsp subsystem ? s software wait-state generator is compatible with the 5409. wait-states programmed in the swwsr register apply to both dsp-generated and dma-generated cycles to external memory peripherals on the dsp ? s xio bus. 3.4.6 dsp timer the 5470 dsp timer is identical to that found on the 5409. 3.4.7 dsp clocking the dsp subsystem is capable of operating in div mode and pll (normal) mode. the mcu may program the initial dsp initial clocking mode, and dsp code may change to other clocking modes. the dsp controls the clocking mode of operation via the settings in the clkmd register. the dsp subsystem ? s pll module, when operating in pll (normal) mode, provides a multiplied version of the refclk input clock as the dsp subsystem clock. the pll can multiply by integer values between 1 and 15, by 0.5*n (for integer values of n between 1 and 15, inclusive), or by 0.25*n (for integer values of n between 1 and 15, inclusive). to ensure that the pll locks to the input frequency, the input clock frequency must meet the minimum frequency as shown for each set of scaling values in table 3 ? 11. dsp subsystem functional overview 25 december 2001 ? revised december 2002 sprs017b table 3 ? 11. dsp clock scaler values and minimum refclk frequencies k (scaler) minimum refclk frequency (mhz) k = n, for integer values of n between 1 and 15, inclusive 5 k = 0.5 * n, for integer values of n between 1 and 15, inclusive 10 k = 0.25 * n, for integer values of n between 1 and 15, inclusive 20 when in div mode, the pll minimum input frequencies do not apply. the pll_dsp output frequency is dynamically selected by the contents of the memory-mapped dsp_clkmd peripheral register. the initial settings for this register are controlled by a memory-mapped register, dsp_reg, on the risc processor. the pll should not be programmed to exceed the dsp subsystem ? s maximum operating frequency as defined in the parametric portion of this data manual. 3.5 dsp power management the dsp subsystem has three power-down modes, which are activated by the idle1, idle2, and idle3 instructions. in these modes, the c54x dsp core enters a dormant state and dissipates considerably less power than in normal operation. the idle1 mode halts all dsp activities except the dsp system clock. because the system clock remains applied to the dsp subsystem peripheral modules, the dsp peripheral circuits continue operating and the dsp_clkout pin remains active. thus, peripherals such as serial ports and timers can take the dsp out of its power-down state. the idle2 mode halts the dsp subsystem peripherals as well as the dsp core, but the dsp subsystem ? s phase-locked loop clock multiplier will remain active to allow for a rapid resume from idle2. because the dsp subsystem peripherals are stopped in this mode, they cannot be used to generate the interrupt to wake up the c54x as with idle1. however, power is significantly reduced because the device is completely stopped. to terminate idle2, activate either reset or dsp_int0 with a pulse that meets the requirements defined in the parametric section of this data manual. note that reset assertion will cause the mcu subsystem to hold the dsp subsystem in reset. the idle3 mode functions like idle2 but it also halts the dsp phase-locked loop (pll) circuit. idle3 is used to achieve the lowest possible dsp power consumption. this mode reduces power dissipation more than idle2. furthermore, the idle3 state allows you to reconfigure the dsp pll externally if the system requires the c54x to operate at a lower speed to save power. to terminate idle3, activate reset or dsp_int0 with a pulse that meets the requirements defined in the parametric section of this data manual. note that reset assertion will cause the mcu subsystem to hold the dsp subsystem in reset. dsp subsystem functional overview 26 december 2001 ? revised december 2002 sprs017b 3.6 dsp interrupts the dsp subsystem interrupts are mapped as shown in table 3 ? 12. table 3 ? 12. dsp interrupt mapping name address priority function name dec hex priority function rs, sintr 0 00 1 reset sint16 4 04 2 software interrupt #16 sint17 8 08 ? software interrupt #17 sint18 12 0c ? software interrupt #18 sint19 16 10 ? software interrupt #19 sint20 20 14 ? software interrupt #20 sint21 24 18 ? software interrupt #21 sint22 28 1c ? software interrupt #22 sint23 32 20 ? software interrupt #23 sint24 36 24 ? software interrupt #24 sint25 40 28 ? software interrupt #25 sint26 44 2c ? software interrupt #26 sint27 48 30 ? software interrupt #27 sint28 52 34 ? software interrupt #28 sint29 56 38 ? software interrupt #29 sint30 60 3c ? software interrupt #30 int0, sint0 64 40 3 external user interrupt 0 sint1 68 44 4 software interrupt #1 sint2 72 48 5 software interrupt #2 tint, sint3 76 4c 6 timer interrupt brint0, sint4 80 50 7 mcbsp #0 receive interrupt (default) bxint0, sint5 84 54 8 mcbsp #0 transmit interrupt (default) dmac0, sint6 88 58 9 dma channel 0, software interrupt #6 dmac1, sint7 92 5c 10 dma channel 1, software interrupt #7 sint8 96 60 11 software interrupt #8 aint, sint9 100 64 12 api interrupt brint1, dmac2, sint10 104 68 13 mcbsp #1 receive interrupt (default) bxint1, dmac3, sint11 108 6c 14 mcbsp #1 transmit interrupt (default) dmac4,sint12 112 70 15 dma channel 4 interrupt (default) dmac5,sint13 116 74 16 dma channel 5 interrupt (default) ? 120 ? 127 78 ? 7f ? reserved dsp subsystem functional overview 27 december 2001 ? revised december 2002 sprs017b the bits of the interrupt flag register (ifr) and interrupt mask register (imr) are arranged as shown in figure 3 ? 7. the function of each bit is described in table 3 ? 13. 15 14 13 12 11 10 9 8 reserved dmac5 dmac4 bxint1/ dmac3 brint1/ dmac2 aint reserved 7 654321 0 dmac1 dmac0 bxint0 brint0 tint reserved int0 figure 3 ? 7. ifr and imr registers table 3 ? 13. ifr and imr register bit fields bit function number name function 15 ? 14 ? reserved 13 dmac5 dma channel 5 interrupt flag/mask bit 12 dmac4 dma channel 4 interrupt flag/mask bit 11 bxint1/dmac3 mcbsp1 transmit interrupt flag/mask bit 10 brint1/dmac2 mcbsp1 receive interrupt flag/mask bit 9 aint arm-to-dsp interrupt flag/mask 8 ? reserved 7 dmac1 dma channel 1 interrupt flag/mask bit 6 dmac0 dma channel 0 interrupt flag/mask bit 5 bxint0 mcbsp0 transmit interrupt flag/mask bit 4 brint0 mcbsp0 receive interrupt flag/mask bit 3 tint timer interrupt flag/mask bit 2 ? 1 ? reserved 0 int0 external interrupt 0 flag/mask bit mcu subsystem functional overview 28 december 2001 ? revised december 2002 sprs017b 4 mcu subsystem functional overview the 5470 mcu subsystem includes ti ? s emulation-enhanced arm7tdmi microcontroller core and several peripherals including spi and i 2 c interfaces, uarts, timers, general-purpose input/output, and external memory interface. the mcu subsystem provides 4k x 32 bits of general-purpose ram and 4k x 32 bits of ethernet packet ram. the following description of the 5470 mcu subsystem is based on figure 4 ? 1. 4.1 mcu core the mcu subsystem uses texas instruments ? emulation-enhanced arm71tdmie core, a derivative of the arm limited arm7tdmi core. the arm7tdmi processor core is a member of the arm7 thumb ? family. it is a low power 32-bit risc processor incorporating the thumb 16-bit compressed instruction set. this microprocessor executes 32-bit or 16-bit instructions and on 32-, 16-, or 8-bit data. the excellent code density achieved with thumb leads to system cost reductions by reducing the required memory size and achieving 32-bit system performance from 16-bit wide memories. interrupt handler i 2 c arm7tdmie memory i/f dspss i/f timer timer watchdog spi clock manager pll 4k 32 packet ram uart uart/irda gpio/keypad flash, sdram, etc. i2c device keypad general- purpose i/os spi device irda transceiver rs232 transceiver clock oscillator mcu subsystem dsp subsystem figure 4 ? 1. 5470 mcu subsystem functional block diagram 4.1.1 arm7tdmi emulation features the mcu subsystem ? s arm7tdmi core has been enhanced by ti with additional debugging features that are available to emulation tools which understand ti ? s arm7tdmie core. arm7tdmi emulation tools which are not specifically created with support for the arm7tdmie core ? s emulation extensions are unable to take advantage of these debugging features. thumb is a registered trademark of arm limited. mcu subsystem functional overview 29 december 2001 ? revised december 2002 sprs017b the enhanced emulation features provide the following debugging capabilities: ? single processor (mcu only) and multiprocessor (mcu and dsp) debug ? high-level language and assembly debug (run, halt, step...) ? real-time (mcu continuously running) or non-real-time (mcu stopped) debug options ? supports both 32- and 16-bit arm7tdmi modes ? endianess transparency ? unlimited breakpoints via opcode replacement (software breakpoint) ? two hardware breakpoints (one configurable as software breakpoint) with maskable cycle type, address and data compare ? two external breakpoint events (emu0 , emu1 pins) ? internal events generate external triggers ? benchmarking/profiling capability 4.1.2 mcu memory space the mcu memory space includes internal ram, internal peripherals, and areas for access to external memories and peripherals connected to the cs0 ? cs3 and cs4 pins, and external sdram. the mcu memory map is summarized in table 4 ? 1. table 4 ? 1. mcu memory space name start address stop address size in bytes data access cs0 0000:0000 007f:ffff 8m 8/16/32 cs1 0080:0000 00ff:ffff 8m 8/16/32 cs2 0100:0000 017f:ffff 8m 8/16/32 cs3 0180:0000 01ff:ffff 8m 8/16/32 cs4 0200:0000 027f:ffff 8m 8/16/32 reserved 0280:0000 0fff:ffff sdram_cs 1000:0000 11ff:ffff 32m 8/16/32 reserved 1200:0000 ffbf:ffff internal sram ffc0:0000 ffc0:3fff 16k 8/16/32 reserved ffc0:4000 ffdf:ffff api ram ffe0:0000 ffe0:3fff 16k 16/32 reserved ffe0:4000 fff3:ffff api registers ffe4:0000 ffe4:0001 2 16 reserved ffe4:0002 ffff:07ff uart_irda ffff:0800 ffff:0fff 2k 32 uart ffff:1000 ffff:17ff 2k 32 i2c ffff:1800 ffff:1fff 2k 32 spi ffff:2000 ffff:27ff 2k 32 gpio ffff:2800 ffff:28ff 256 32 kgpio ffff:2900 ffff:29ff 256 32 timer0 ffff:2a00 ffff:2aff 256 32 timer1 ffff:2b00 ffff:2bff 256 32 timer2 ffff:2c00 ffff:2cff 256 32 inth ffff:2d00 ffff:2dff 256 32 memint ffff:2e00 ffff:2eff 256 32 clkm ffff:2f00 ffff:2fff 256 32 sdramif ffff:3000 ffff:30ff 256 32 reserved ffff:3100 ffff:31ff arm_pll ffff:3200 ffff:32ff 256 32 reserved ffff:3300 ffff:ffff mcu subsystem functional overview 30 december 2001 ? revised december 2002 sprs017b 4.2 mcu memory interface the mcu memory interface connects the mcu to the internal and external memories and peripherals via a 32-bit-wide data bus. this bus supports mcu access sizes of 8 bits, 16 bits, and 32 bits. all peripheral control registers are implemented as 32-bit devices and should only be accessed using 32-bit operations. the mcu memory interface allows endian configuration. generally, a system should be configured so that all peripherals operate in the same endian mode. in cases where mixed endianness is used, the software engineer must carefully control accesses to resources which are configured for the endianness that is opposite to that of the mcu. the mcu memory interface also provides management of external accesses. external devices supported include rom (flash), sram, and sdram. the external data bus is a 32-bit bidirectional bus. the following access management features for mcu accesses to external memory and peripherals are provided: ? five external chip-select signals, each with a dedicated 8m-byte range of the mcu memory map. ? mcu access duration management (wait-state insertion) to enable the connection of slow memory devices, and support for intercycle delays to prevent external data bus contention. ? mcu read and write access size adaptation for mcu accesses to external non-sdram memory or peripherals with 32-bit, 16-bit, and 8-bit data bus width. ? mcu read and write access size adaptation for mcu accesses to external sdram memory with 32-bit or 16-bit data bus width. the mcu memory ranges associated with each external memory chip-select (cs0 ? cs3 , cs4) may be configured in little-endian or big-endian mode. the mcu processor is also configured to operate in big/little endian mode based on the state of ? bigend ? during power-up/reset time. mcu code that accesses a resource that is configured with a different endianness than the mcu must perform the appropriate address calculations (depending on the data size used to write the data, and the data size being used to read the data). 4.2.1 mcu memory interface wait-states mcu accesses to internal peripherals and internal memories are generally performed at 0 wait state. sdram refresh cycles delay any mcu access. mcu accesses to the api ram require multiple clocks as determined by the programming of the api_reg register. timing for mcu accesses to external sdram memory is controlled by sdram interface registers which control cas latency, ras latency, back-to-back timing, refresh rate, etc. external memories or peripherals controlled by cs0 ? cs3 and cs4 may be programmed to provide various cycle timings. additionally, the wait input pin may be used to insert wait-states under external hardware control. 4.2.2 mcu api interface the api interface, which provides mcu access to a small portion of dsp memory, provides a 16-bit data path to the api ram in the dsp subsystem. all 32-bit transactions are divided into two 16-bit api transactions. the api interface supports back-to-back access with programmable insertion of wait state to ensure correct synchronization of signals between the mcu subsystem and the dsp subsystem. mcu subsystem functional overview 31 december 2001 ? revised december 2002 sprs017b 4.2.3 mcu sdram memory interface the sdram memory interface main features are: ? it operates with the mcu memory interface (memint) so that sdram memories can be used on the same board with flash and/or sram. ? supports 16- and 32-bit-wide data bus to sdram parts ? can address up to 256m bits of sdram ? operates at the mcu clock speed (47.5 mhz) ? flexible programming of sdram timing parameters ? supports four open sdram pages ? minimal burst operations supported. (in 16-bit-wide mode, a burst of two is supported.) the sdram interface must be properly initialized before the sdram memory can be used. the following steps are needed for initializing the sdram interface: ? program sdram_reg for data bus size and the number of dummy cycles used after access to slower memory device. ? program sdram parameters in sdram_config, sdram_ref_count, and sdram_init_conf ? write a ? 1 ? in the init bit of the sdram_cntl register ? wait until a ? 1 ? is read inside the ready bit of the sdram_cntl register before accessing the sdram. note: by writing a ? 1 ? in the init bit of the sdram_cntl register, the initialization state machine of the sdram interface module will do the following: wait for the number of cycles that is programmed in init_nop_max_cnt (should be 100 s or greater). send the specified number of refresh commands that have been programmed into the init_ref_max_cnt register. the sdram load-mode-register command is used to configure the sdram device mode. parameters used in the load-mode-register command are based on the values programmed in the sdram interface registers. mcu subsystem functional overview 32 december 2001 ? revised december 2002 sprs017b 4.3 mcu peripherals the following section describes the 5470 mcu subsystem peripherals. 4.3.1 mcu universal asynchronous receiver/transmitter (uart) interfaces the uart modules perform serial-to-parallel conversion on data characters received and parallel-to-serial conversion on data characters transmitted by the processor. 4.3.1.1 uart modes uart mode supports data transmission and data reception via two 64-word-deep fifos. five different parity types are enabled, with three different stop bit formats. the word length is between 5 and 8, and line break can be generated and detected. the baud rate is generated from the mcu subsystem clock by a programmable divisor. all transmitting parameters can be detected in reception mode by an auto-bauding mechanism that recognizes speed, word size, parity, and the number of stop bits. software flow control is available in the uart/irda when in uart mode. the uart/modem supports both software and hardware flow control when in uart mode. hardware flow control can reduce the mcu software overhead required to process data interrupts. uart/modem mode the uart/modem provides an autobauding mechanism. all operations are controllable either via a software interface or using hardware flow control signals. the uart/modem provides five external pin signals (multiplexed with gpio pins): ? gpio09/tx_modem: output - transmit data ? gpio10/rx_modem: input - receive data ? gpio11/cts_modem: input - clear to send ? gpio12/rts_modem: output - request to send ? gpio13/dcd_modem: output - data carrier detected the uart/modem features: ? line-break generation and detection ? interrupt system control ? loop-back capabilities for internal test ? the autobauding supports speeds between 1200 and 115.2 kbits/s. ? hardware flow control (dcd, rts, cts) uart/irda mode in the uart/irda mode, an infrared data association (irda) protocol encoder/decoder manages the rxir and txir signals to an irda transceiver. it includes the slow infrared (sir) protocol in order to be connected with an infrared transmitter to any external data peripherals with an irda compliant data interface. the uart/irda provides three external pin signals (multiplexed with gpio pins): ? gpio07/tx_irda/txir_irda: output ? transmit data ? gpio08/rx_irda/rxir_irda: input ? receive data ? gpio06/clk16x_irda/sd_irda: output ? shut down the ir transceiver mcu subsystem functional overview 33 december 2001 ? revised december 2002 sprs017b uart/irda irda mode features: ? irda 1.0 sir support allows serial communication at baud rates up to 115.2 kbits/s. ? sending a single infrared pulse signals a zero. a one is signaled by not sending any pulse. the width of the pulse can be either 1.6 s or 3/16th of a single bit time. ? in irda 1.0 sir mode, the device operation is similar to the operation in uart mode. however, the data transfer operations are normally performed in half-duplex. the modem control and status signals are not used. ? frame formatting: addition of variable xbof characters and eof characters ? uplink/downlink crc generation/detection ? asynchronous transparency (automatic insertion of break character) ? eight characters status fifo available to monitor frame length and frame errors ? variable frame length for rx and tx irda frame. the format of the serial data is similar to the uart/modem data format. each data word is sent with a zero value start bit, followed by 8 data bits, and ending with at least one stop bit with a binary value of one. in sir mode, data transfer takes place between mcu and peripheral devices at speeds up to 115200 bits/s. a sir transmit frame consists of start flags (either a single c0h, multiple c0hs, or a single c0h preceded by a number of ffh flags), followed by frame data supplied by the mcu, then a crc-16 word, and a terminating stop flag (c1h). the transmit state machine attaches start flags, crc-16, and stop flags to the transmit data provided by the mcu. if necessary, it also applies sir data transparency. note: blr[4] is used to select whether c0h or ffh start patterns are to be used when multiple start flags are required. sir transparency is carried out if the outgoing data (between the start and stop flags) contains c0h, c1h, or 7dh. if one of these characters is about to be transmitted, then the sir state machine sends an escape character (7dh) first, then inverts the fifth bit of the real data to be sent, and sends this data immediately after the 7dh character. the sir receiver state machine recovers the receive clock, removes the start flags, removes any transparency from the incoming data, and determines frame boundary with reception of the stop flag. it also checks for errors such as: frame abort (7dh character followed immediately by a c1h stop flag, without transparency), crc error, and frame-length error. once a frame is received, the state machine generates an interrupt to the mcu. the mcu reads the lsr (status register) to check for receive errors, and processes any valid receive data. note that the uart/irda is capable of operating in full-duplex, but that the sir standard disallows full-duplex operation. the infrared output in sir mode can implement either 1.6 s or 3/16-bit encoding, which is selected by acreg[7]. in 1.6- s encoding, the infrared pulse width is 1.6 s. in 3/16-encoding, the infrared pulse width is 3/16th of a bit duration (1/baud-rate). 4.3.1.2 fifo operation the transmit fifo is written via the thr register. transmit fifo status is reflected in the lsr. the receive fifo is read via the rhr register. the receive fifo tracks reception of break, framing errors, and parity errors on a byte-by-byte basis. the lsr bits which reflect receive status show the status for the byte that is at the top of the fifo. reads of lsr do not advance the receive fifo pointer. lsr[7] is set when there is an error anywhere in the rx fifo and is cleared only when there are no more errors remaining in the fifo. mcu subsystem functional overview 34 december 2001 ? revised december 2002 sprs017b 4.3.1.3 uart clocking the uart clock divisors must be set based on the mcu subsystem clock rate and the desired baud rate. the uart_div_115k register is a prescaler which divides the mcu subsystem clock down to a rate usable by the uart state machines. the uart_div_bitrate register is the divider which provides the bit clock to the uart from the pre-scaled clock. uart_div_bitrate = mcu clock frequency / uart_div_115k / desired bit rate for autobaud function on the uart/modem, the uart_div_115k value must result in a 115200-hz clock rate: uart_div_115k = mcu clock frequency / 115200 hz. 4.3.2 mcu serial peripheral interface (spi) the spi is a bidirectional 3-line interface dedicated to the transfer of data to and from external devices offering a 3-line serial interface. the spi interface is fully-duplexed and is configurable from 1 to 32 bits, providing three enable signals programmable either as positive or negative edge- or level-sensitive. this serial port is based on a looped shift-register which allows for both transmit (parallel-in, serial-out) and receive (serial-in, parallel-out) modes. the serial port is fully controlled by the mcu memory interface (data write, data read, and activation of serialization operations). the serial clock period (t clkx_spi ) is derived from the mcu subsystem clock, based on a prescale divider (ptv): spi clock rate = mcu clock rate / (4 * ptv) where ptv is 2, 4, 8, or 16. 4.3.3 mcu general-purpose i/o the 5470 provides 36 general-purpose i/os (gpios) configurable in read or write mode by internal registers. the gpios are divided into two groups, gpio(19:0) and kbgpio(15:0). kbgpios are keyboard gpio pins, which are implemented similarly to the gpio(19:0) pins, although some kbgpio pins have internal pullup resistors. some of the gpio and kbgpio pins share functionality with signals from other modules. register bits configure whether the pin is used for the normal gpio or kbgpio functionality, or for the alternate functionality. each gpio is associated with 6 configuration/status bits whose description is given in table 4 ? 2 and table 4 ? 3. mcu subsystem functional overview 35 december 2001 ? revised december 2002 sprs017b table 4 ? 2. gpio control/status bits bit name description io i/o bit: writable when i/o is configured as an output (cio=0) reads value on i/o pin when i/o is configured as an input (cio=1) cio configure i/o: 0: output 1: input (default) gpio_irqa see table 4 ? 3 gpio_irqb see table 4 ? 3 ddio delta detect bit: if gpio is configured as an output (cio=0), always reads as ? 0 ? if gpio is configured as an input (cio=1), reads a ? 1 ? if io has changed since ddio was last cleared gpio_en selects register for muxed gpios: 0: other signal 1: gpio (default) non-shared gpios are always available at the i/o pin independent of the value of gpio_en table 4 ? 3. gpio_irq bits definition gpio_irqb gpio_irqa function 0 0 the associated device pin does not cause assertion of a gpio interrupt. 0 1 a rising edge on the associated device pin causes assertion of a gpio interrupt. 1 0 a falling edge on the associated device pin causes assertion of a gpio interrupt. 1 1 any change on the associated device pin causes assertion of a gpio interrupt. the configuration/status bits are accessible through 12 memory-mapped registers: gpio_io, kbgpio_io, gpio_cio, kbgpio_cio, gpio_irqa, kbgpio_irqa, gpio_irqb, kbgpio_irqb, gpio_ddio, kbgpio_ddio, gpio_en and kbgpio_en. the pins kbgpio(15:8) have on-chip pullup resistors, making them suitable for use as keypad row inputs. to configure the 5470 for an 8x8 keypad [with keypad columns connected to kbgpio(7:0) and rows connected to kbgpio(15:8)], use the following settings: ? kbgpio(15:8) pins are configured as inputs (cio=1) for row lines ? kbgpio(7:0) pins are configured as outputs (cio=0) for column lines keypad scanning can be done by setting the output values on all of the column kbgpio pins to 0 and enabling kbgpio(15:8) interrupts. when a kbgpio(15:8) interrupt is seen, all but one of the the kgbpio column output values are be changed to 1, and then the kbgpio row pins are read. if the kbgpio pin row input value is all 1s, then there are no keys in the column currently driven to 0 that are set. any bit in the kgbpio pin row input value that is 0 indicates a closed switch. next, select a different column by writing a new value to kbgpio column pins with just one output pin value 0 and the remainder 1. repeat the kbgpio row read and check for closed switches. repeat this for each column in the keyboard array. once the keypad has been read, the interrupt service routine should set all column outputs back to 0 so that the next key press may be sensed. mcu subsystem functional overview 36 december 2001 ? revised december 2002 sprs017b 4.3.4 mcu inter-integrated circuit (i 2 c) interface the master i 2 c interface module provides an interface between the mcu subsystem bus and the i 2 c pins, allowing the mcu to control external peripheral devices connected to the i 2 c pins. fundamentally, the i 2 c interface module is a parallel-to-serial and serial-to-parallel converter. the parallel data received from the mcu for transmit has to be converted to a suitable serial form for external peripheral devices on the i 2 c bus ? . conversely, the serial data received from the i 2 c bus has to be converted to a suitable parallel form for passing to the mcu. the i 2 c interface features are: ? operates as an i 2 c master only; cannot be configured as an i 2 c slave ? supports 7-bit i 2 c device address ? supports an 8-bit i 2 c device subaddress ? master write to slave receiver in single or multiple mode (data loop) ? provides a 16-byte transmit fifo to reduce mcu overhead ? supports simple read cycle, read combined cycle ? a 3-bit programmable prescale internal clock divider and 7-bit programmable scl clock divider to support a wide range of input clock frequencies. the i 2 c scl clock frequency are: ? i 2 c standard mode: 100 khz ? i 2 c fast mode: 400 khz ? 3-bit programmable spike filter to provide noise filtering on the i 2 c data input signal the module does not support: ? i 2 c bus 10-bit addressing ? i 2 c bus cbus compatibility ? multi-master i 2 c ? clock synchronization as a handshake: slave devices are not allowed to hold the scl line low to force the master (5470) into a wait state until the slave is ready for the next transfer. 4.3.5 mcu timers the 5470 mcu subsystem implements three 16-bit timers configurable either in ? auto reload ? or in ? count down to zero and stop ? modes. each timer can generate an interrupt to the mcu when it counts down to zero. the timer0 may be configured as either a watchdog counter or as a general-purpose timer. the two others (timer1 and timer2) are general-purpose timers. timer2 may be used to provide timing to an external device via the shared pin gpio19/timer_out. when this pin is configured to provide timer_out, the pin will provide a low pulse when the timer2 interrupt occurs. 4.3.5.1 general-purpose timers timer1 and timer2, are general-purpose timers, and can be programmed to provide specific timing via a clock prescale value (ptv) and a starting count value (load_tim). the timer counts down to zero from the load_tim value, changing value every n mcu subsystem clocks, depending on the ptv value. the time between interrupts to the mcu interrupt handler is defined as: t int = t clk * (load_tim + 1 ) * 2 (ptv + 1 ) if the counter ? s auto-reload (ar) bit is set when the counter reaches zero, the timer will auto-reload the load_tim value into its counter and start counting again. the counter will only run when its start (st) bit is set. the ptv and ar bits of the cntl_timer register and load_tim must not be programmed when the timer is running. the timern current counter value may be read via the value_timn register. i 2 c bus is a trademark of philips electronics n. v. corporation. mcu subsystem functional overview 37 december 2001 ? revised december 2002 sprs017b 4.3.5.2 timer0 as a watchdog timer by default, timer0 is configured as a watchdog timer. the watchdog is designed to detect user programs stuck in infinite loops resulting in loss of program control or ? runaway ? programs. when configured as a watchdog counter, timer0 will reset the mcu subsystem if it counts down to zero. the mcu ? s reset initialization code may examine the watchdog_stat register to determine if a mcu reset was caused by the watchdog. the user program should write periodically into load_tim register before the counter reaches 0 in order to reload the timer with this new value. a load_tim write is taken into account only if the new loaded value is different from the previous one. when the watchdog counter reaches 0, it resets the mcu core and all the mcu subsystem peripherals. on power up, the watchdog is enabled and the value loaded into load_tim register is set to the maximum value (0xffff) and ptv is set to seven. this gives to user a time of 16,777,216 * t clk to switch to normal timer mode or to set a different watchdog timer time out to timer0. if a programmer does not want to have this default watchdog functionality, he must write a specific sequence into a dedicated register (timer_mode) in order to configure it as a general-purpose timer. disabling timer0 watchdog function timer0 may be configured as a general-purpose timer by writing a predefined sequence (0xf5 followed by 0xa0) in the watchdog_dis bits of the cntl_timer0 register. if the watchdog disable function sees a write to cntl_timer0 with watchdog_dis set to 0xf5, it begins watching for another write to cntl_timer0 with watchdog_dis set to 0xa0. if watchdog_dis in the next write is 0xa0, timer0 is set for general-purpose mode. if the next write is instead 0xf5, timer0 remains in watchdog mode and the disable function begins watching again for 0xf5. re-enabling timer0 watchdog function to switch timer0 from general-purpose timer mode to watchdog timer mode, write a ? 1 ? in the watchdog bit of the cntl_timer0 register. when watchdog is set to 1, the load_tim value is forced to 0xffff. due to internal sequencing, the mcu code should wait at least three timer clock periods before re-initializing load_tim or pvt to values that meet system watchdog timing needs. 4.3.6 mcu interrupt handler the mcu subsystem interrupt handler prioritizes and masks interrupts from up to 16 mcu subsystem interrupt sources (irq0 ? 15). it also steers these interrupts to the mcu ? s two interrupt inputs: arm_irq (low-priority interrupt request) and arm_fiq (fast interrupt request). it receives interrupts from both internal modules and the external chip environment. external interrupts to the mcu subsystem interrupt handler may be provided through gpio and/or kbgpio pins. each interrupt source has an interrupt level register (ilr) which defines the priority of the corresponding interrupt. when multiple interrupts are pending, the interrupt with the highest-priority interrupt level register value is sent to the mcu first. in the case of multiple pending interrupts with identical ilr priority values (with no other pending interrupts with higher priority), the highest interrupt number is sent to the mcu first. each interrupt source can be individually routed to one of the two input interrupt lines of the mcu, by properly setting the fiq bit in the interrupt ? s ilr_irq_n register. mcu subsystem functional overview 38 december 2001 ? revised december 2002 sprs017b the following paragraph lists the typical irq sequence. the fiq sequence is similar. ? as the interrupt handler sees unmasked interrupt inputs go active, it sets the corresponding it_reg bit. ? at this time, there are three possible cases: ? if the new_int_agr bit in the int_ctrl_reg is set, a previous interrupt has not yet been completely serviced, and the new interrupt cannot be sent to the mcu. ? if new_int_agr is 0 and there is only one interrupt marked as active in the it_reg, that interrupt number is selected as the interrupt to be passed to the mcu. this selected interrupt number is stored in sir_irq_reg. ? if new_int_agr is 0 and there are more than one interrupt marked as active in the it_reg, the interrupt handler selects the highest-priority interrupt based on ilr_irq_n register priority values and, where priority values are identical, interrupt numbers. this selected interrupt number is stored in sir_irq_reg. ? the interrupt is sent to the mcu via its irq port. ? the mcu begins execution at the irq vector. mcu code reads sir_irq_reg to determine which interrupt source caused the interrupt. mcu code branches to the appropriate interrupt service routine. ? the mcu software must write a ? 1 ? to the int_ctrl_reg register new_irq_agr bit in order to reset the irq output and sir_irq_reg register. this enables the interrupt handler to send new interrupts to the mcu via the irq signal. mcu subsystem interrupt numbers are shown in table 4 ? 4. table 4 ? 4. mcu peripheral interrupt mapping irq request mcu interrupt source irq0 watchdog timer0 interrupt irq1 timer1 interrupt irq2 timer2 interrupt irq3 gpio0 interrupt irq4 reserved irq5 kbgpio(7:0) interrupt irq6 uart interrupts irq7 uart_irda interrupt irq8 kbgpio(15:8) interrupt irq9 gpio03 irq10 gpio02 irq11 i 2 c interrupt irq12 gpio1 interrupt irq13 spi interrupt irq14 gpio(19:4) interrupt irq15 api interrupt 4.4 mcu power-down modes the mcu can be shut down and awaken by setting the appropriate bit into the clkm_reg and wakeup_reg. it is the software ? s responsibility to put the arm_clock in bypass or low-frequency mode before the mcu is shut down. the mcu is woken by the first interrupt received from one of the peripherals. the mcu subsystem peripherals can be individually shut down and awaken by setting the corresponding bits in the clkm_reg and wakeup_reg register. it is the software ? s responsibility to power down or wake up individual peripherals. mcu subsystem functional overview 39 december 2001 ? revised december 2002 sprs017b 4.5 mcu peripheral clock management the 5470 device is clocked by the external clock input, refclk. the 5470 refclk input does not provide a clock oscillator, so it must be driven by a square-wave input signal that meets v ih and v il requirements. both subsystems (dsp and mcu) derive their clocks from refclk using software-programmable plls. immediately following reset or power up, the contents of the respective clkmd registers for both subsystems depend on the status of the programmable internal ports on their respective plls. for the mcu subsystem, these internal ports are hardwired so that the programmable capability of default mode is not available. for the dsp subsystem, the programmable internal ports to the dsp pll are connected to the output of a register (dsp_reg) that is controlled by the risc processor. this allows the dsp pll default values to be programmable under the control of the mcu subsystem. the clock management scheme is shown in figure 4 ? 2. 2(n+1) arm_clock audio_clk refclk pll_dsp dsp_clock arm pll_arm d power- down module shut-down dsp uart irda uart spi i2c d=512 timer select_arm_clk inth asynchronous wake-up irda _clock uart_clock spi_clock i2c_clock timer_clock interrupts from peripherals gpio gpio_clock shut-down figure 4 ? 2. clock management module the mcu subsystem operates in one of three modes: pll (normal) mode, div mode, or power-down mode. in power-down mode, the input clock frequency is divided by a large value (512 ? 1023). configuring the operation of the mcu subsystem clock module in power-down mode and using divisor values below 512 will result in stopping the clock. similar to the dsp clock, the mcu subsystem clock is also derived from the scaled version of the input clock, refclk. the pll used by the risc has the same look and feel as the dsp pll. for this reason, the risc processor uses the same minimum input-clock-frequency restriction and scaling values as the dsp. mcu subsystem functional overview 40 december 2001 ? revised december 2002 sprs017b 4.6 initialization the reset input is the master reset that resets both the dsp and mcu subsystems. the reset_out signal can be used to reset external peripherals under control of the mcu. table 4 ? 5 describes how reset events are propagated to the mcu subsystem, the dsp subsystem, and the reset_out pin. table 4 ? 5. reset management activated reset signal mcu reset dsp reset external reset (reset_out ) reset yes yes yes rst_cmd watchdog yes no no dsp software reset (in register clkm_cntl_rst) no yes no reset_out (software controlled by bit in register clkm_cntl_rst) no no yes clkm_cntl_rst is a control register mapped in the mcu memory space at address 0xffff2f10. when the mcu subsystem is reset, the mcu program counter begins execution at address 0x00000000. when the dsp subsystem is reset, the dsp program counter begins execution from 0xff80. each mcu subsystem peripheral may be independently held in reset via control bits in the mcu subsystem register reset_reg. by default, these bits are set as soon as the mcu subsystem reset is activated, which leaves all mcu subsystem peripherals active. 4.6.1 initial mcu code since the mcu begins execution from address 0x00000000 after mcu subsystem reset, the initialization code for the mcu subsystem must be provided by the memory device connected to the cs0 pin. this code may be either 32-bit or 16-bit (thumb) arm code. the value of the cs3 /romsize16 pin is sampled at the rising edge of reset to determine the mode that the arm7tdmi core will execute. cs3 /romsize16 input value at reset rising edge arm7tdmi initial mode 0 16-bit instruction (thumb) mode 1 32-bit instruction mode similarly, the mcu subsystem initializes the arm7tdmi for big-endian or little-endian operation based on the value sampled on the cs4_bigend pin at the rising edge of the reset signal. cs4/bigend input value at reset rising edge arm7tdmi initial mode 0 little-endian 1 big-endian mcu subsystem functional overview 41 december 2001 ? revised december 2002 sprs017b 4.6.2 dsp boot mode when the dsp comes out of reset, it begins execution from 0xff80. it can execute code either from external memory or from internal memory, depending on the value of the dsp_mpnmc bit in the mcu ? s dsp_pll_reg register. once the appropriate mode is set, and, if necessary, code is downloaded via the api module, the mcu may release the dsp subsystem from reset by clearing the dsp_reset bit in the mcu subsystem ? s clkm_cntl_rst register. for the case where dsp execution starts from internal memory, the mcu should download the appropriate dsp code via the api interface (before releasing the dsp from reset). this is done by properly setting the dsp_mpnmc and dsp_apibn bits in the dsp_pll_reg mcu memory-mapped register, and then downloading the code via the api interface. the dsp_apibn bit, when 0, causes the 2k-word block of dsp data memory at 0x3800 ? 0x3fff to appear also in dsp program space beginning at 0xf800. table 4 ? 6 shows the combinations of the dsp_pll_reg register dsp_mpnmc and dsp_apibn bits that control where the dsp fetches code immediately following release of dsp reset. table 4 ? 6. dsp boot memory dsp_mpnmc dsp_apibn dsp boot memory at dsp program space address 0xff80 0 0 shadow of the api-accessible on-chip data-space ram 0 1 on-chip program-only ram which is not accessible to the api module 1 0 shadow of the api-accessible on-chip data-space ram 1 1 external dsp memory 4.6.3 emulation support the 5470 provides flexible emulation capabilities. it supports both ti ? s emulation tools and tools developed by third parties. since the emulation tools may understand both the c54x ? dsp core and the arm7tdmie core, or just the c54x ? dsp core, just the arm7tdmie core, or just the arm7tdmi core, multiple emulation modes are required. to allow configuration of the internal jtag chains used by the various emulators, the 5470 samples the emu1 and emu0 pins at trst rising edge. based on the values of these pins, the internal scan chain is configured for different emulation modes. these modes are summarized in table 4 ? 7. table 4 ? 7. emulation mode selection values at trst rising edge scan chain order emu0 emu1 scan chain order 0 0 only the arm7tdmie core is in the chain. (this is also the mode for tools which only understand the arm7tdmi core.) 0 1 only the c54x ? dsp core is in the chain 1 0 reserved 1 1 arm7tdmie core followed by c54x ? dsp core followed by asic logic test access port (tap) controller mcu subsystem functional overview 42 december 2001 ? revised december 2002 sprs017b some tools that only understand one type of processor may be configured for use with 5470 even when other devices are on the asic scan chain. this is done by instructing the tools to place the other ? unrecognized ? devices on the jtag scan chain in their ? bypass ? modes. while the exact configuration methods are beyond the scope of this document, the key is to understand the length of the instruction registers for the tap controllers so that the correct bypass instructions can be issued. for the 5470, this methodology would only apply to the 5470 emulation mode where all three tap controllers are in the jtag scan chain (emu1 = emu0 = ? 1 ? at trst rising edge). the jtag tap controller instruction register lengths are listed in table 4 ? 8. table 4 ? 8. jtag tap controller instruction register lengths instruction register length jtag tap controller 4 bits arm7tdmie core 8 bits c54x ? dsp core 8 bits asic logic tap controller documentation support 43 december 2001 ? revised december 2002 sprs017b 5 documentation support extensive documentation supports all tms320 ? dsp family of devices from product announcement through applications development. the following types of documentation are available to support the design and use of the c5000 ? platform of dsps: ? tms320vc547x cpu and peripherals reference guide (literature number spru038) ? tms320c54x ? dsp functional overview (literature number spru307) ? device-specific data sheets ? complete user ? s guides ? development support tools ? hardware and software application reports the five-volume tms320c54x dsp reference set (literature number spru210) consists of: ? volume 1: cpu and peripherals (literature number spru131) ? volume 2: mnemonic instruction set (literature number spru172) ? volume 3: algebraic instruction set (literature number spru179) ? volume 4: applications guide (literature number spru173) ? volume 5: enhanced peripherals (literature number spru302) the reference set describes in detail the tms320c54x ? dsp products currently available and the hardware and software applications, including algorithms, for fixed-point tms320 ? dsp family of devices. a series of dsp textbooks is published by prentice-hall and john wiley & sons to support digital signal processing research and education. the tms320 ? dsp newsletter, details on signal processing , is published quarterly and distributed to update tms320 ? dsp customers on product information. information regarding ti dsp products is also available on the worldwide web at http://www.ti.com uniform resource locator (url). tms320 and c5000 are trademarks of texas instruments. electrical specifications 44 december 2001 ? revised december 2002 sprs017b 6 electrical specifications this section provides the absolute maximum ratings and the recommended operating conditions for the device. 6.1 absolute maximum ratings the list of absolute maximum ratings are specified over operating case temperature. stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all supply voltage (core and i/o) values are with respect to v ss . supply voltage i/o range, dv dd ? 0.5 v to 4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage core range, cv dd ? 0.5 v to 2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i ? 0.5 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o ? 0.5 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating case temperature range, t c (commercial) 0 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t c (industrial) ? 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg ? 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 recommended operating conditions min nom max unit dv dd device supply voltage, i/o (level shifter) ? 3 3.3 3.6 v cv dd device supply voltage, core ? 1.71 1.8 1.95 v v ss supply voltage, gnd 0 v v ih high-level input voltage, i/o 0.6*dv dd v v il low-level input voltage 0.3*dv dd v i oh high-level output current dsp_r/w , dsp_ps , dsp_is , dsp_ds , dsp_iostrb , dsp_mstrb , dsp_a[19:0], dsp_d[15:0], kbgpio01/dsp_xf, kbgpio10/dsp_iack , kbgpio14/dsp_clkout ? 8 ma all other outputs not including power/ground/dsp signals. ? 4 i ol low-level output current dsp_r/w , dsp_ps , dsp_is , dsp_ds , dsp_iostrb , dsp_mstrb , dsp_a[19:0], dsp_d[15:0], kbgpio01/dsp_xf, kbgpio10/dsp_iack , kbgpio14/dsp_clkout 8 ma all other outputs not including power/ground/dsp signals. 4 t c operating case temperature commercial 0 85 c industrial ? 40 85 ? texas instrument dsps do not require specific power sequencing between the core supply and the i/o supply. however, systems sho uld be designed to ensure that neither supply is powered up for extended periods of time if the other supply is below the proper opera ting voltage. excessive exposure to these conditions can adversely affect the long-term reliability of the devices. system-level concerns such as bus c ontention may require supply sequencing to be implemented. in this case, the core supply should be powered up at the same time as or prior to the i/o buffers, and then powered down after the i/o buffers. electrical specifications 45 december 2001 ? revised december 2002 sprs017b 6.3 electrical characteristics over recommended operating case temperature (unless otherwise noted) parameter test conditions min typ max unit v oh high-level output voltage i oh = rated 0.8*dv dd v v ol low-level output voltage i ol = rated 0.22*dv dd v cs4/bigend dv dd max, v i = v ss to dv dd ? 300 10 i iz input current for outputs in high impedance emu[1:0] , gpio16/sda, cs3 /romsize16, kbgpio12/dsp_msc , kbgpio13/dsp_tout, kbgpio11/dsp_iaq , kbgpio10/dsp_iack , kbgpio14/dsp_clkout , kbgpio15/arm_mclk, kbgpio[9:8], dsp_d[15:0], dsp_a[19:0] dv dd max, v i = v ss to dv dd ? 10 310 a all other inputs dv dd max, v i = v ss to dv dd ? 10 10 tdi, tms ? 10 310 i i input current trst , tck dv dd max, v i = v ss to dv dd ? 300 10 a i i in ut current all other input-only pins dv dd max, v i v ss to dv dd ? 10 10 a i ddc supply current, core mcu (cv dd ) cv dd max, dv dd max, f (dsp_clkout) = 100 mhz, f (arm_mclk) = 47.5 mhz, t c = 25 c 70 ? ma i ddp supply current, i/os (dv dd ) cv dd max, dv dd max, f (dsp_clkout) = 100 mhz, f (arm_mclk) = 47.5 mhz, t c = 25 c 50 ? ma c i input capacitance 5 pf c o output capacitance 5 pf ? the current measurements were taken with the following nominal conditions: cv dd = 1.8v, dv dd = 3.3v, temperature = 25c, with the dsp executing program code from internal sram consisting of 50% nop / 50% macd instructions @ 100 mhz, and the arm executing dhrystone progra m code from external sram @ 47.5 mhz. actual operating current varies with program being executed and external pin usage. electrical specifications 46 december 2001 ? revised december 2002 sprs017b 6.4 package thermal resistance characteristics table 6 ? 1 provides the thermal resistance characteristics for the recommended package type used on the tms320vc5470 dsp. table 6 ? 1. thermal resistance characteristics parameter ghk package unit r ja 34 c/w r jc 9.5 c/w 6.5 timing parameter symbology timing parameter symbols used are created in accordance with jedec standard 100. to shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: lowercase subscripts and their meanings: letters and symbols and their meanings: a access time h high c cycle time (period) l low d delay time v valid dis disable time z high impedance en enable time f fall time h hold time r rise time su setup time t transition time v valid time w pulse duration (width) x unknown, changing, or don ? t care level the following load circuit in figure 6 ? 1 was used on all outputs pins and i/o pins in input mode. all timing measurements in this data manual were measured from the 5470 connection to the following load circuit. tester pin electronics v load i ol c t i oh output under test 50 ? where: i ol = 8 ma (all outputs) i oh = 8 ma (all outputs) v load = 1.65 v c t = 13-pf typical load circuit capacitance figure 6 ? 1. 3.3-v test load circuit electrical specifications 47 december 2001 ? revised december 2002 sprs017b 6.5.1 divide-by-two/divide-by-four clock option timing the frequency of the reference clock provided at the refclk pin can be divided by a factor of two or four to generate the internal machine cycle. the selection of the clock mode is described in section 3.4.7. note: the frequency injected must conform to specifications listed in table 6 ? 2. table 6 ? 2 and table 6 ? 3 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 2). table 6 ? 2. divide-by-two/divide-by-four clock option timing requirements min max unit t c(ci) cycle time, refclk 20 ? ns t f(ci) fall time, refclk 8 ns t r(ci) rise time, refclk 8 ns t w(cil) pulse duration, refclk low 5 ns t w(cih) pulse duration, refclk high 5 ns ? this device utilizes a fully static design and therefore can operate with t c(ci) approaching . the device is characterized at frequencies approaching 0 hz. unless otherwise noted, the same switching characteristics that apply to dsp_clkout also apply to arm_mclk. table 6 ? 3. divide-by-two/divide-by-four clock option switching characteristics parameter min typ max unit t c(co) cycle time, dsp_clkout 40 2t c(ci) ? ns t d(cih-co) delay time, refclk high to dsp_clkout high/low 4 10 17 ns t f(co) fall time, dsp_clkout 2 ns t r(co) rise time, dsp_clkout 2 ns t w(col) pulse duration, dsp_clkout low h ? 2 h h + 2 ns t w(coh) pulse duration, dsp_clkout high h ? 2 h h + 2 ns ? this device utilizes a fully static design and therefore can operate with t c(ci) approaching . the device is characterized at frequencies approaching 0 hz. t r(co) t f(co) dsp_clkout refclk t w(col) t d(cih-co) t f(ci) t r(ci) t c(co) t c(ci) t w(coh) t w(cih) t w(cil) figure 6 ? 2. external divide-by-two clock timing electrical specifications 48 december 2001 ? revised december 2002 sprs017b 6.5.2 multiply-by-n clock option (pll enabled) timing the frequency of the reference clock provided at the refclk pin can be multiplied by a factor of n to generate the internal machine cycle. the selection of the clock mode and the value of n is described in section 3.4.7. note: the external frequency injected must conform to specifications listed in the table 6 ? 4. table 6 ? 4 and table 6 ? 5 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 3). table 6 ? 4. multiply-by-n timing requirements min max unit integer pll multiplier n (n = 1 ? 15) ? 20 ? 200 t c ( ci ) cycle time, refclk pll multiplier n = x.5 ? 20 ? 100 ns t c(ci) cycle time, refclk pll multiplier n = x.25, x.75 ? 20 ? 50 ns t f(ci) fall time, refclk 8 ns t r(ci) rise time, refclk 8 ns t w(cil) pulse duration, refclk low 5 ns t w(cih) pulse duration, refclk high 5 ns ? n = multiplication factor ? the multiplication factor and minimum refclk cycle time should be chosen such that the resulting dsp_clkout cycle time is withi n the specified range (t c(co) ). minimum t c(ci) for the arm cpu is 21 ns. unless otherwise noted, the same switching characteristics that apply to dsp_clkout also apply to arm_mclk. table 6 ? 5. multiply-by-n switching characteristics parameter min typ max unit t c(co)dsp cycle time, dsp_clkout 10 t c(ci) /n ? ns t c(co)arm cycle time, arm_mclk 21 t c(ci) /n ? ns t d(ci-co) delay time, refclk high/low to dsp_clkout high/low 4 10 17 ns t f(co) fall time, dsp_clkout 2 ns t r(co) rise time, dsp_clkout 2 ns t w(col) pulse duration, dsp_clkout low h ? 2 h h + 2 ns t w(coh) pulse duration, dsp_clkout high h ? 2 h h + 2 ns t p transitory phase, pll lock up time 30 s ? n = multiplication factor t c(co) t c(ci) t w(coh) t f(co) t r(co) t f(ci) refclk dsp_clkout t d(ci-co) t w(col) t r(ci) t p unstable t w(cih) t w(cil) figure 6 ? 3. external multiply-by-one clock timing electrical specifications 49 december 2001 ? revised december 2002 sprs017b 6.6 memory and parallel i/o interface timing 6.6.1 memory read table 6 ? 6 and table 6 ? 7 assume testing over recommended operating conditions with dsp_mstrb = 0 and h = 0.5t c(co) (see figure 6 ? 4). table 6 ? 6. memory read timing requirements ? min max unit t a(a)m access time, read data access from address valid 2h ? 15 ? ns t a(mstrbl) access time, read data access from dsp_mstrb low 2h ? 15 ? ns t su(d)r setup time, read data before dsp_clkout low 4 ns t h(d)r hold time, read data after dsp_clkout low 4 ns t h(a-d)r hold time, read data after address invalid 0 ns t h(d)mstrbh hold time, read data after dsp_mstrb high 0 ns ? address, dsp_ps , and dsp_ds timings are all included in timings referenced as address. ? this access timing reflects a zero wait-state timing. table 6 ? 7. memory read switching characteristics ? parameter min max unit t d(clkl-a) delay time, dsp_clkout low to address valid 1.5 11.5 ns t d(clkh-a) delay time, dsp_clkout high (transition) to address valid ? 1.5 11.5 ns t d(clkl-msl) delay time, dsp_clkout low to dsp_mstrb low 1.5 11.5 ns t d(clkl-msh) delay time, dsp_clkout low to dsp_mstrb high 1.5 11.5 ns t h(clkl-a)r hold time, address valid after dsp_clkout low 1.5 11.5 ns t h(clkh-a)r hold time, address valid after dsp_clkout high ? 1.5 11.5 ns ? address, dsp_ps , and dsp_ds timings are all included in timings referenced as address. in the case of a memory read preceded by a memory read ? in the case of a memory read preceded by a memory write electrical specifications 50 december 2001 ? revised december 2002 sprs017b dsp_ps , dsp_ds dsp_r/w dsp_mstrb dsp_d[15:0] dsp_a[19:0] dsp_clkout t h(d)r t h(clkl-a)r t d(clkl-msh) t d(clkl-a) t d(clkl-msl) t su(d)r t a(a)m t a(mstrbl) t h(a-d)r t h(d)mstrbh figure 6 ? 4. memory read electrical specifications 51 december 2001 ? revised december 2002 sprs017b 6.6.2 memory write table 6 ? 8 assumes testing over recommended operating conditions with dsp_mstrb = 0 and h = 0.5t c(co) (see figure 6 ? 5). table 6 ? 8. memory write switching characteristics ? parameter min max unit t d(clkh-a) delay time, dsp_clkout high to address valid ? 1.5 11.5 ns t d(clkl-a) delay time, dsp_clkout low to address valid 1.5 11.5 ns t d(clkl-msl) delay time, dsp_clkout low to dsp_mstrb low 1.5 11.5 ns t d(clkl-d)w delay time, dsp_clkout low to data valid 1.5 11.5 ns t d(clkl-msh) delay time, dsp_clkout low to dsp_mstrb high 1.5 11.5 ns t d(clkh-rwl) delay time, dsp_clkout high to dsp_r/w low 1.5 11.5 ns t d(clkh-rwh) delay time, dsp_clkout high to dsp_r/w high 1.5 11.5 ns t d(rwl-mstrbl) delay time, dsp_r/w low to dsp_mstrb low h ? 3 h + 3 ns t h(a)w hold time, address valid after dsp_clkout high ? 1.5 11.5 ns t h(d)msh hold time, write data valid after dsp_mstrb high h ? 3 h+3 ns t w(sl)ms pulse duration, dsp_mstrb low 2h ? 3 ns t su(a)w setup time, address valid before dsp_mstrb low 2h ? 3 ns t su(d)msh setup time, write data valid before dsp_mstrb high 2h ? 3 2h+3 ns t en(d ? rwl) enable time, data bus driven after dsp_r/w low h ? 3 ns t dis(rwh ? d) disable time, dsp_r/w high to data bus high impedance 2 ns ? address, dsp_ps , and dsp_ds timings are all included in timings referenced as address. ? in the case of a memory write preceded by a memory write in the case of a memory write preceded by an i/o cycle electrical specifications 52 december 2001 ? revised december 2002 sprs017b dsp_ps , dsp_ds dsp_r/w dsp_mstrb dsp_d[15:0] dsp_a[19:0] dsp_clkout t d(clkh-rwh) t h(a)w t d(clkl-msh) t su(d)msh t d(clkl-d)w t w(sl)ms t su(a)w t d(clkl-msl) t h(d)msh t d(clkl-a) t d(clkh-rwl) t d(rwl-mstrbl) t d(clkh-a) t en(d-rwl) t dis(rwh-d) figure 6 ? 5. memory write electrical specifications 53 december 2001 ? revised december 2002 sprs017b 6.6.3 parallel i/o port read timing requirements table 6 ? 9 and table 6 ? 10 assume testing over recommended operating conditions with dsp_iostrb = 0 and h = 0.5t c(co) (see figure 6 ? 6). table 6 ? 9. parallel i/o port read timing requirements ? min max unit t a(a)io access time, read data access from address valid ? 3h ? 15 ns t a(istrbl)io access time, read data access from dsp_iostrb low ? 2h ? 15 ns t su(d)ior setup time, read data before dsp_clkout high 4 ns t h(d)ior hold time, read data after dsp_clkout high 0 ns t h(istrbh-d)r hold time, read data after dsp_iostrb high 0 ns ? address and dsp_is timings are included in timings referenced as address. ? this access timing reflects a zero wait-state timing. table 6 ? 10. parallel i/o port read switching characteristics ? parameter min max unit t d(clkl-a) delay time, dsp_clkout low to address valid 1.5 11.5 ns t d(clkh-istrbl) delay time, dsp_clkout high to dsp_iostrb low 1.5 11.5 ns t d(clkh-istrbh) delay time, dsp_clkout high to dsp_iostrb high 1.5 11.5 ns t h(a)ior hold time, address after dsp_clkout low 1.5 11.5 ns ? address and dsp_is timings are included in timings referenced as address. dsp_is dsp_r/w dsp_iostrb dsp_d[15:0] dsp_a[19:0] dsp_clkout t h(a)ior t d(clkh-istrbh) t h(d)ior t su(d)ior t a(a)io t d(clkh-istrbl) t d(clkl-a) t a(istrbl)io t h(istrbh-d)r figure 6 ? 6. parallel i/o port read electrical specifications 54 december 2001 ? revised december 2002 sprs017b 6.6.4 parallel i/o port write switching characteristics table 6 ? 11 assumes testing over recommended operating conditions with dsp_iostrb = 0 and h = 0.5t c(co) (see figure 6 ? 7). table 6 ? 11. parallel i/o port write switching characteristics ? parameter min max unit t d(clkl-a) delay time, dsp_clkout low to address valid 1.5 11.5 ns t d(clkh-istrbl) delay time, dsp_clkout high to dsp_iostrb low 1.5 11.5 ns t d(clkh-d)iow delay time, dsp_clkout high to write data valid 1.5 11.5 ns t d(clkh-istrbh) delay time, dsp_clkout high to dsp_iostrb high 1.5 11.5 ns t d(clkl-rwl) delay time, dsp_clkout low to dsp_r/w low 1.5 11.5 ns t d(clkl-rwh) delay time, dsp_clkout low to dsp_r/w high 1.5 11.5 ns t h(a)iow hold time, address valid after dsp_clkout low 1.5 11.5 ns t h(d)iow hold time, write data after dsp_iostrb high h ? 3 h+3 ns t su(d)dsp_iostrbh setup time, write data before dsp_iostrb high h ? 3 h+3 ns t su(a)dsp_iostrbl setup time, address valid before dsp_iostrb low h ? 3 h+3 ns ? address and dsp_is timings are included in timings referenced as address. dsp_is dsp_r/w dsp_iostrb dsp_d[15:0] dsp_a[19:0] dsp_clkout t d(clkh-istrbh) t h(a)iow t h(d)iow t d(clkh-d)iow t d(clkh-istrbl) t d(clkl-a) t d(clkl-rwl) t d(clkl-rwh) t su(a)dsp_iostrbl t su(d)dsp_iostrbh figure 6 ? 7. parallel i/o port write electrical specifications 55 december 2001 ? revised december 2002 sprs017b 6.7 ready timing for externally generated wait-states table 6 ? 12 assumes testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 8, through figure 6 ? 11). table 6 ? 12. ready timing for externally generated wait-states timing requirements ? min max unit t su(rdy) setup time, dsp_ready before dsp_clkout low 5 ns t h(rdy) hold time, dsp_ready after dsp_clkout low 3 ns t v(rdy)mstrb valid time, dsp_ready after dsp_mstrb low ? 4h ? 11 ns t h(rdy)mstrb hold time, dsp_ready after dsp_mstrb low ? 4h ns t v(rdy)dsp_iostrb valid time, dsp_ready after dsp_iostrb low ? 5h ? 11 ns t h(rdy)dsp_iostrb hold time, dsp_ready after dsp_iostrb low ? 5h ns t v(mscl) valid time, dsp_msc low after dsp_clkout low 1.5 11.5 ns t v(msch) valid time, dsp_msc high after dsp_clkout low 1.5 11.5 ns ? the hardware wait-states can be used only in conjunction with the software wait-states to extend the bus cycles. to generate wa it-states using dsp_ready, at least two software wait-states must be programmed. ? these timings are included for reference only. the critical timings for dsp_ready are those referenced to dsp_clkout. dsp_msc dsp_mstrb dsp_ready dsp_a[19:0] dsp_clkout t v(msch) t v(mscl) t h(rdy) t h(rdy)mstrb t v(rdy)mstrb wait state generated by dsp_ready wait-states generated internally t su(rdy) figure 6 ? 8. memory read with externally generated wait-states electrical specifications 56 december 2001 ? revised december 2002 sprs017b dsp_msc dsp_mstrb dsp_ready dsp_d[15:0] dsp_a[19:0] dsp_clkout t v(msch) t h(rdy) wait state generated by dsp_ready wait-states generated internally t h(rdy)mstrb t v(rdy)mstrb t v(mscl) t su(rdy) figure 6 ? 9. memory write with externally generated wait-states t su(rdy) dsp_msc dsp_iostrb dsp_ready dsp_a[19:0] dsp_clkout t v(msch) t h(rdy) wait state generated by dsp_ready wait-states generated internally t v(rdy)dsp_iostrb t v(mscl) t h(rdy)dsp_iostrb figure 6 ? 10. i/o read with externally generated wait-states electrical specifications 57 december 2001 ? revised december 2002 sprs017b dsp_iostrb dsp_msc dsp_ready dsp_d[15:0] dsp_a[19:0] dsp_clkout t h(rdy) wait state generated by dsp_ready wait-states generated internally t v(rdy)dsp_iostrb t su(rdy) t v(msch) t v(mscl) t h(rdy)dsp_iostrb figure 6 ? 11. i/o write with externally generated wait-states electrical specifications 58 december 2001 ? revised december 2002 sprs017b 6.8 interrupt timings table 6 ? 13 assumes testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 12). table 6 ? 13. reset and interrupt timing requirements min max unit t w(inth)s pulse duration, dsp_int0 high (synchronous) 2h+1 ns t w(intl)s pulse duration, dsp_int0 low (synchronous) 2h+1 ns t w(intl)a pulse duration, dsp_int0 low (asynchronous) 4h ns t w(intl)wkp pulse duration, dsp_int0 low for idle2/idle3 wakeup 10 ns t su(int) setup time, dsp_int0 before dsp_clkout low ? 8 10 ns ? the external interrupt is synchronized to the core cpu by way of a two-flip-flop synchronizer which samples these inputs with c onsecutive falling edges of dsp_clkout. the input to the interrupt pin is required to represent a 1-0-0 sequence at the timing that is correspondi ng to three dsp_clkout sampling sequences. dsp_int0 dsp_clkout t h(int) t su(int) t su(int) t w(intl)a t w(inth)a figure 6 ? 12. interrupt timing electrical specifications 59 december 2001 ? revised december 2002 sprs017b 6.9 instruction acquisition (dsp_iaq ) and interrupt acknowledge (dsp_iack ) timings table 6 ? 14 assumes testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 13). table 6 ? 14. dsp_iaq and dsp_iack switching characteristics parameter min max unit t d(clkl-iaql) delay time, dsp_clkout low to dsp_iaq low 1.5 11.5 ns t d(clkl-iaqh) delay time, dsp_clkout low to dsp_iaq high 1.5 11.5 ns t d(a)iaq delay time, address valid to dsp_iaq low 1 ns t d(clkl-iackl) delay time, dsp_clkout low to dsp_iack low 1.5 11.5 ns t d(clkl-iackh) delay time , dsp_clkout low to dsp_iack high 1.5 11.5 ns t d(a)iack delay time, address valid to dsp_iack low 1 ns t h(a)iaq hold time, dsp_iaq high after address invalid ? 2 ns t h(a)iack hold time, dsp_iack high after address invalid ? 2 ns t w(iaql) pulse duration, dsp_iaq low 2h ? 3 ns t w(iackl) pulse duration, dsp_iack low 2h ? 3 ns dsp_mstrb dsp_iack dsp_iaq dsp_a[19:0] dsp_clkout t d(a)iack t d(a)iaq t w(iackl) t h(a)iack t d(clkl-iackl) t w(iaql) t h(a)iaq t d(clkl-iaql) t d(clkl-iackh) t d(clkl-iaqh) figure 6 ? 13. dsp_iaq and dsp_iack timings electrical specifications 60 december 2001 ? revised december 2002 sprs017b 6.10 external flag (dsp_xf) and dsp_tout timings table 6 ? 15 assumes testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 14 and figure 6 ? 15). table 6 ? 15. dsp_xf and dsp_tout switching characteristics parameter min typ max unit t delay time, dsp_clkout low to dsp_xf high 1.5 11.5 t d(xf) delay time, dsp_clkout low to dsp_xf low 1.5 11.5 ns t d(touth) delay time, dsp_clkout low to dsp_tout high 1.5 11.5 ns t d(toutl) delay time, dsp_clkout low to dsp_tout low 1.5 11.5 ns t w(tout) pulse duration, dsp_tout 2h ? 3 2h 2h+3 ns dsp_xf dsp_clkout t d(xf) figure 6 ? 14. dsp_xf timing dsp_tout dsp_clkout t w(tout) t d(toutl) t d(touth) figure 6 ? 15. dsp_tout timing electrical specifications 61 december 2001 ? revised december 2002 sprs017b 6.11 multichannel buffered serial port (mcbsp) timings 6.11.1 mcbsp receive and transmit timings table 6 ? 16 and table 6 ? 17 assume testing over recommended operating conditions and h = 0.5t c(co) (see figure 6 ? 16 and figure 6 ? 17). note: polarity bits clkrp = clkxp = fsrp = fsxp = 0. if the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. table 6 ? 16. mcbsp receive and transmit timing requirements min max unit t c(bckrx) cycle time, bclk_r/x bclk_r/x ext 4h ns t w(bckrx) pulse duration, bclk_r/x or bclk_r/x high bclk_r/x ext 2h ? 1 ns t hold time external bfsr high after bclkr low bclkr int 0 ns t h(bckrl-bfrh) hold time, external bfsr high after bclkr low bclkr ext 7 ns t hold time bdr valid after bclkr low bclkr int 0 ns t h(bckrl-bdrv) hold time, bdr valid after bclkr low bclkr ext 7 ns t hold time external bfsx high after bclkx low bclkx int 0 ns t h(bckxl-bfxh) hold time, external bfsx high after bclkx low bclkx ext 7 ns t setup time external bfsr high before bclkr low bclkr int 9 ns t su(bfrh-bckrl) setup time, external bfsr high before bclkr low bclkr ext 2 ns t setup time bdr valid before bclkr low bclkr int 9 ns t su(bdrv-bckrl) setup time, bdr valid before bclkr low bclkr ext 2 ns t setup time external bfsx high before bclkx low bclkx int 9 ns t su(bfxh-bckxl) setup time, external bfsx high before bclkx low bclkx ext 2 ns t r(bckrx) rise time, bclkr_r/x bclk_r/x ext 5 ns t f(bckrx) fall time, bclkr_r/x bclk_r/x ext 5 ns electrical specifications 62 december 2001 ? revised december 2002 sprs017b table 6 ? 17. mcbsp receive and transmit switching characteristics parameter min max unit t c(bckrx) cycle time, bclk_r/x bclk_r/x int 4h ns t w(bckrxh) pulse duration, bclk_r/x high bclk_r/x int d ? 6 ? d+1 ? ns t w(bckrxl) pulse duration, bclk_r/x low bclk_r/x int c ? 6 ? c+1 ? ns t d(bckrh-bfrv) delay time, bclkr high to internal bfsr valid bclkr int ? 1 8 ns t delay time bclkx high to internal bfsx valid bclkx int 1 9 ns t d(bckxh-bfxv) delay time, bclkx high to internal bfsx valid bclkx ext 4 15 ns t disable time bclkx high to bdx high impedance following last data bit bclkx int ? 1 8 ns t dis(bckxh-bdxhz) disable time, bclkx high to bdx high impedance following last data bit bclkx ext 4 16 ns dela y time, bclkx hi g h to bdx valid. this applies to all bits except the first bclkx int 0 7 delay time , bclkx high to bdx valid . this a lies to all bits exce t the first bit transmitted. bclkx ext 4 16 t d(bckxh-bdxv) delay time, bclkx high to bdx valid. ? only applies to first bit transmitted when in data delay 1 or 2 bclkx int 7 ns only applies to first bit transmitted when in data delay 1 or 2 (xdatdly=01b or 10b) modes bclkx ext 16 t enable time, bclkx high to bdx driven. ? only applies to first bit transmitted when data delay 1 or 2 bclkx int ? 4 ns t en(bckxh-bdx) only applies to first bit transmitted when data delay 1 or 2 (xdatdly=01b or 10b) modes bclkx ext 2 ns t delay time, bfsx high to bdx valid. ? only applies to first bit transmitted when data delay 0 (xdatdly 00b) bfsx int 3 ns t d(bfxh-bdxv) only applies to first bit transmitted when data delay 0 (xdatdly=00b) mode. bfsx ext 14 ns t enable time, bfsx high to bdx driven. ? only applies to first bit transmitted when in data delay 0 (xdatdly 00b) bfsx int ? 1 ns t en(bfxh-bdx) only applies to first bit transmitted when in data delay 0 (xdatdly=00b) mode bfsx ext 2 ns ? t = bclkr/x period = (1 + clkgdv) * 2h c = bclkr/x low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2h when clkgdv is even d = bclkr/x high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * 2h when clkgdv is even ? see the tms320c54x dsp reference set, volume 5: enhanced peripherals (literature number spru302) for a description of the data delay features of the mcbsp. the transmit delay enable (dxena) and a-bis mode (abis) features of the mcbsp are not implemented on the tms320vc5470. electrical specifications 63 december 2001 ? revised december 2002 sprs017b (n ? 2) bit (n ? 1) (n ? 3) (n ? 2) bit (n ? 1) (n ? 4) (n ? 3) (n ? 2) bit (n ? 1) t h(bckrl ? bdrv) t su(bdrv ? bckrl) t h(bckrl ? bdrv) t su(bdrv ? bckrl) t su(bdrv ? bckrl) t h(bckrl ? bdrv) t h(bckrl ? bfrh) t su(bfrh ? bckrl) t d(bckrh ? bfrv) t d(bckrh ? bfrv) t f(bckrx) t r(bckrx) t w(bckrxl) t c(bckrx) t w(bckrxh) (rdatdly=10b) bdr (rdatdly=01b) bdr (rdatdly=00b) bdr bfsr (ext) bfsr (int) bclkr figure 6 ? 16. mcbsp receive timings t en(bckxh ? bdx) t d(bckxh ? bdxv) t d(bckxh ? bdxv) t en(bckxh ? bdx) t dis(bckxh ? bdxhz) t d(bckxh ? bdxv) t d(bfxh ? bdxv) t en(bfxh ? bdx) (xdatdly=10b) bdx (xdatdly=01b) bdx (xdatdly=00b) bdx (n ? 2) bit (n ? 1) bit 0 (n ? 4) bit (n ? 1) (n ? 3) (n ? 2) bit 0 (n ? 3) (n ? 2) bit (n ? 1) bit 0 t h(bckxl ? bfxh) t f(bckrx) t r(bckrx) t w(bckrxl) t c(bckrx) t w(bckrxh) bfsx (ext) bfsx (int) bclkx t d(bckxh ? bfxv) t d(bckxh ? bfxv) t su(bfxh ? bckxl) figure 6 ? 17. mcbsp transmit timings electrical specifications 64 december 2001 ? revised december 2002 sprs017b 6.11.2 mcbsp general-purpose timings table 6 ? 18 and table 6 ? 19 assume testing over recommended operating conditions (see figure 6 ? 18). table 6 ? 18. mcbsp general-purpose timing requirements min max unit t su(bgpio-coh) setup time, bgpiox input mode before dsp_clkout high ? 9 ns t h(coh-bgpio) hold time, bgpiox input mode after dsp_clkout high ? 0 ns ? bgpiox refers to bclkrx, bfsrx, bdrx, bclkxx, or bfsxx when configured as a general-purpose input. table 6 ? 19. mcbsp general-purpose switching characteristics parameter min max unit t d(coh-bgpio) delay time, dsp_clkout high to bgpiox output mode ? ? 10 10 ns ? bgpiox refers to bclkrx, bfsrx, bclkxx, bfsxx, or bdxx when configured as a general-purpose output. note: only the dsp subsystem can access the mcbsps as gpios; they are not available to the arm subsystem. t su(bgpio-coh) t h(coh-bgpio) t d(coh-bgpio) dsp_clkout bgpiox input mode ? bgpiox output mode ? ? bgpiox refers to bclkrx, bfsrx, bdrx, bclkxx, or bfsxx when configured as a general-purpose input. ? bgpiox refers to bclkrx, bfsrx, bclkxx, bfsxx, or bdxx when configured as a general-purpose output. figure 6 ? 18. mcbsp general-purpose i/o timings electrical specifications 65 december 2001 ? revised december 2002 sprs017b 6.11.3 mcbsp as spi master or slave timings low inactive state without delay; the mcbsp transmits data on the rising edge of bclkx and receives data on the falling edge of bclkr. table 6 ? 20 and table 6 ? 21 assume testing over recommended operating conditions, clkstp = 10b, clkxp = 0, and h = 0.5t c(co) (see figure 6 ? 19). note: for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. table 6 ? 20. mcbsp as spi master or slave timing requirements (clkstp = 10b and clkxp = 0) master slave unit min max min max unit t su(bdrv-bckxl) setup time, bdr valid before bclkx low 12 ? 12h ns t h(bckxl-bdrv) hold time, bdr valid after bclkx low 0 12h + 5 ns t su(bfxl-bckxh) setup time, bfsx low before bclkx high 10 ns t c(bckx) cycle time, bclkx 12h 32h ns table 6 ? 21. mcbsp as spi master or slave switching characteristics (clkstp = 10b and clkxp = 0) parameter master ? slave unit parameter min max min max unit t h(bckxl-bfxl) hold time, bfsx low after bclkx low ? t ? 6 t + 6 ns t d(bfxl-bckxh) delay time, bfsx low to bclkx high c ? 6 c + 6 ns t d(bckxh-bdxv) delay time, bclkx high to bdx valid ? 3 7 6h + 5 10h + 14 ns t dis(bckxl-bdxhz) disable time, bdx high impedance following last data bit from bclkx low c ? 2 c + 3 ns t dis(bfxh-bdxhz) disable time, bdx high impedance following last data bit from bfsx high 2h+ 3 6h + 17 ns t d(bfxl-bdxv) delay time, bfsx low to bdx valid 4h + 2 8h + 17 ns ? t = bclkx period = (1 + clkgdv) * 2h c = bclkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2h when clkgdv is even ? fsrp = fsxp = 1. as a spi master, bfsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on bfsx and bfsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp bfsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (bclkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) bclkx bfsx bdx bdr t su(bdrv-bclxl) t d(bckxh-bdxv) t h(bckxl-bdrv) t dis(bfxh-bdxhz) t dis(bckxl-bdxhz) t h(bckxl-bfxl) t d(bfxl-bdxv) t d(bfxl-bckxh) lsb msb t su(bfxl-bckxh) t c(bckx) figure 6 ? 19. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 0 electrical specifications 66 december 2001 ? revised december 2002 sprs017b low inactive state with delay; the mcbsp transmits data one-half cycle ahead of the rising edge of bclkx and receives data on the rising edge of bclkr. table 6 ? 22 and table 6 ? 23 assume testing over recommended operating conditions, clkstp = 11b, clkxp = 0, and h = 0.5t c(co) (see figure 6 ? 20). note: for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. table 6 ? 22. mcbsp as spi master or slave timing requirements (clkstp = 11b and clkxp = 0) master slave unit min max min max unit t su(bdrv-bckxl) setup time, bdr valid before bclkx low 12 ? 12h ns t h(bckxh-bdrv) hold time, bdr valid after bclkx high 0 12h + 5 ns t su(bfxl-bckxh) setup time, bfsx low before bclkx high 10 ns t c(bckx) cycle time, bclkx 12h 32h ns table 6 ? 23. mcbsp as spi master or slave switching characteristics (clkstp = 11b and clkxp = 0) parameter master ? slave unit parameter min max min max unit t h(bckxl-bfxl) hold time, bfsx low after bclkx low ? t ? 6 t + 6 ns t d(bfxl-bckxh) delay time, bfsx low to bclkx high c ? 6 c + 6 ns t d(bckxl-bdxv) delay time, bclkx low to bdx valid ? 3 7 6h + 5 10h + 14 ns t dis(bckxl-bdxhz) disable time, bdx high impedance following last data bit from bclkx low ? 2 4 6h + 3 10h + 17 ns t d(bfxl-bdxv) delay time, bfsx low to bdx valid c ? 6 c + 6 4h ? 2 8h + 17 ns ? t = bclkx period = (1 + clkgdv) * 2h c = bclkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2h when clkgdv is even d = bclkx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * 2h when clkgdv is even ? fsrp = fsxp = 1. as a spi master, bfsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on bfsx and bfsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp bfsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (bclkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) bclkx bfsx bdx bdr t d(bfxl-bckxh) t dis(bckxl-bdxhz) t d(bckxl-bdxv) t h(bckxh-bdrv) t su(bdrv-bckxl) t d(bfxl-bdxv) t h(bckxl-bfxl) lsb msb t su(bfxl-bckxh) t c(bckx) figure 6 ? 20. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 0 electrical specifications 67 december 2001 ? revised december 2002 sprs017b high inactive state without delay; the mcbsp transmits data on the falling edge of bclkx and receives data on the rising edge of bclkr. table 6 ? 24 and table 6 ? 25 assume testing over recommended operating conditions, clkstp = 10b, clkxp = 1, and h = 0.5t c(co) (see figure 6 ? 21). note: for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. table 6 ? 24. mcbsp as spi master or slave timing requirements (clkstp = 10b and clkxp = 1) master slave unit min max min max unit t su(bdrv-bckxh) setup time, bdr valid before bclkx high 12 ? 12h ns t h(bckxh-bdrv) hold time, bdr valid after bclkx high 0 12h + 5 ns t su(bfxl-bckxl) setup time, bfsx low before bclkx low 10 ns t c(bckx) cycle time, bclkx 12h 32h ns table 6 ? 25. mcbsp as spi master or slave switching characteristics (clkstp = 10b and clkxp = 1) parameter master ? slave unit parameter min max min max unit t h(bckxh-bfxl) hold time, bfsx low after bclkx high ? t ? 6 t + 6 ns t d(bfxl-bckxl) delay time, bfsx low to bclkx low c ? 6 c + 6 ns t d(bckxl-bdxv) delay time, bclkx low to bdx valid ? 3 7 6h + 5 10h + 14 ns t dis(bckxh-bdxhz) disable time, bdx high impedance following last data bit from bclkx high d ? 2 d + 3 ns t dis(bfxh-bdxhz) disable time, bdx high impedance following last data bit from bfsx high 2h + 3 6h + 17 ns t d(bfxl-bdxv) delay time, bfsx low to bdx valid 4h ? 2 8h + 17 ns ? t = bclkx period = (1 + clkgdv) * 2h c = bclkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2h when clkgdv is even ? fsrp = fsxp = 1. as a spi master, bfsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on bfsx and bfsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp bfsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (bclkx). t su(bfxl-bckxl) t h(bckxh-bdrv) t dis(bfxh-bdxhz) t dis(bckxh-bdxhz) bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) bclkx bfsx bdx bdr t d(bfxl-bckxl) t d(bfxl-bdxv) t d(bckxl-bdxv) t su(bdrv-bckxh) t h(bckxh-bfxl) lsb msb t c(bckx) figure 6 ? 21. mcbsp timing as spi master or slave: clkstp = 10b, clkxp = 1 electrical specifications 68 december 2001 ? revised december 2002 sprs017b high inactive state with delay; the mcbsp transmits data one-half cycle ahead of the falling edge of bclkx and receives data on the falling edge of bclkr. table 6 ? 26 and table 6 ? 27 assume testing over recommended operating conditions, clkstp = 11b, clkxp = 1, and h = 0.5t c(co) (see figure 6 ? 22). note: for all spi slave modes, clkg is programmed as 1/2 of the cpu clock by setting clksm = clkgdv = 1. table 6 ? 26. mcbsp as spi master or slave timing requirements (clkstp = 11b and clkxp = 1) master slave unit min max min max unit t su(bdrv-bckxl) setup time, bdr valid before bclkx low 12 ? 12h ns t h(bckxl-bdrv) hold time, bdr valid after bclkx low 0 12h + 5 ns t su(bfxl-bckxl) setup time, bfsx low before bclkx low 10 ns t c(bckx) cycle time, bclkx 12h 32h ns table 6 ? 27. mcbsp as spi master or slave switching characteristics (clkstp = 11b and clkxp = 1) parameter master ? slave unit parameter min max min max unit t h(bckxh-bfxl) hold time, bfsx low after bclkx high ? t ? 6 t + 6 ns t d(bfxl-bckxl) delay time, bfsx low to bclkx low c ? 6 c + 6 ns t d(bckxh-bdxv) delay time, bclkx high to bdx valid ? 3 7 6h + 5 10h + 14 ns t dis(bckxh-bdxhz) disable time, bdx high impedance following last data bit from bclkx high ? 2 4 6h + 3 10h + 17 ns t d(bfxl-bdxv) delay time, bfsx low to bdx valid c ? 6 c + 6 4h ? 2 8h + 17 ns ? t = bclkx period = (1 + clkgdv) * 2h c = bclkx low pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2) * 2h when clkgdv is even d = bclkx high pulse width = t/2 when clkgdv is odd or zero and = (clkgdv/2 + 1) * 2h when clkgdv is even ? fsrp = fsxp = 1. as a spi master, bfsx is inverted to provide active-low slave-enable output. as a slave, the active-low signal input on bfsx and bfsr is inverted before being used internally. clkxm = fsxm = 1, clkrm = fsrm = 0 for master mcbsp clkxm = clkrm = fsxm = fsrm = 0 for slave mcbsp bfsx should be low before the rising edge of clock to enable slave devices and then begin a spi transfer at the rising edge of the master clock (bclkx). bit 0 bit(n-1) (n-2) (n-3) (n-4) bit 0 bit(n-1) (n-2) (n-3) (n-4) bclkx bfsx bdx bdr t d(bfxl-bckxl) t su(bdrv-bckxl) t dis(bckxh-bdxhz) t h(bckxh-bfxl) t d(bckxh-bdxv) t h(bckxl-bdrv) t d(bfxl-bdxv) lsb msb t su(bfxl-bckxl) t c(bckx) figure 6 ? 22. mcbsp timing as spi master or slave: clkstp = 11b, clkxp = 1 electrical specifications 69 december 2001 ? revised december 2002 sprs017b 6.12 synchronous dram timings table 6 ? 28 and table 6 ? 29 assume testing over recommended operating conditions (see figure 6 ? 23 through figure 6 ? 29). table 6 ? 28. synchronous dram timing requirements no. min max unit 6 t su(dv-sclkh) setup time, read data valid before sdram_clk high 4.5 ns 7 t h(sclkh-dv) hold time, read data valid after sdram_clk high 2 ns table 6 ? 29. synchronous dram switching characteristics no. parameter min max unit 1 t d(sclkh-csv) delay time, sdram_clk high to chip select valid 0.5 11 ns 2 t d(sclkh-dqmv) delay time, sdram_clk high to byte enable valid 0.5 11 ns 3 t d(sclkh-dqmiv) delay time, sdram_clk high to byte enable invalid 0.5 11 ns 4 t d(sclkh-av) delay time, sdram_clk high to address valid 0.5 11 ns 5 t d(sclkh-aiv) delay time, sdram_clk high to address invalid 0.5 11 ns 8 t d(sclkh-casv) delay time, sdram_clk high to sdram_cas valid 0.5 11 ns 9 t d(sclkh-dv) delay time, sdram_clk high to data valid 0.5 11 ns 10 t d(sclkh-div) delay time, sdram_clk high to data invalid 0.5 11 ns 11 t d(sclkh-wev) delay time, sdram_clk high to sdram_we valid 0.5 11 ns 12 t d(sclkh-rasv) delay time, sdram_clk high to, sdram_ras valid 0.5 11 ns sdram_clk csn sdram_dqm[3:0] sdram_a[c:0] ? data[31:00] sdram_a[10] ? sdram_ras sdram_cas sdram_we sdram_a[r:0] ? be1 be2 be3 be4 bank column d1 d2 d3 d4 8 7 6 5 5 5 3 2 8 4 4 4 1 read ? the values for r and c depend on the particular size of the srams used. figure 6 ? 23. sdram read command (cas latency 3) electrical specifications 70 december 2001 ? revised december 2002 sprs017b sdram_clk csn sdram_dqm[3:0] sdram_a[c:0] ? data[31:00] sdram_ras sdram_cas sdram_we sdram_a[10] ? sdram_a[r:0] ? be1 be2 be3 be4 bank column d1 d2 d3 d4 11 8 9 5 5 5 3 11 8 9 4 4 2 1 10 3 4 write 1 ? the values for r and c depend on the particular size of the srams used. figure 6 ? 24. sdram write command bank activate row address row address 12 5 5 5 1 active 12 4 4 4 1 sdram_clk csn sdram_dqm[3:0] sdram_a[c:0] ? data[31:00] sdram_ras sdram_cas sdram_we sdram_a[r] ? sdram_a[r:0] ? ? the values for r and c depend on the particular size of the srams used. figure 6 ? 25. sdram active command electrical specifications 71 december 2001 ? revised december 2002 sprs017b 11 12 1 precharge 11 12 1 sdram_clk csn sdram_dqm[3:0] data[31:00] sdram_ras sdram_cas sdram_we sdram_a[r:0] ? ? the values for r and c depend on the particular size of the srams used. figure 6 ? 26. sdram precharge command bank 11 12 5 5 1 deactivate 11 12 4 4 1 sdram_clk csn sdram_dqm[3:0] sdram_a[c:0] ? data[31:00] sdram_ras sdram_cas sdram_we sdram_a[r] ? sdram_a[r:0] ? ? the values for r and c depend on the particular size of the srams used. figure 6 ? 27. sdram deactivate command electrical specifications 72 december 2001 ? revised december 2002 sprs017b 8 12 1 refr 8 12 1 sdram_clk csn sdram_a[c:0] ? data[31:00] sdram_ras sdram_cas sdram_we sdram_a[r] ? sdram_a[r:0] ? ? the values for r and c depend on the particular size of the srams used. figure 6 ? 28. sdram refresh command mrs value 11 8 12 5 1 mode register set 11 8 12 4 1 sdram_clk csn sdram_dqm[3:0] sdram_a[c:0] ? sdram_ras sdram_cas sdram_we sdram_a[r:0] ? ? the values for r and c depend on the particular size of the srams used. figure 6 ? 29. sdram mode register set command electrical specifications 73 december 2001 ? revised december 2002 sprs017b 6.13 i 2 c bus timings table 6 ? 30 through table 6 ? 32 assume testing over recommended operating conditions (see figure 6 ? 30 through figure 6 ? 32). table 6 ? 30. i 2 c bus device switching characteristics of the sda and scl bus lines parameter standard mode fast mode unit parameter min max min max unit t c(scl) cycle time, scl 10 2.5 s t w(sclh) pulse duration, scl high 4 0.6 s t w(scll) pulse duration, scl low 4.7 1.3 s t r(scl) rise time, scl 1000 300 ns t f(scl) fall time, scl 300 300 ns t r(sda) rise time, sda 1000 300 ns t f(sda) fall time, sda 300 300 ns t w(sp) pulse duration, spike suppression 0 50 ns t su(sda ? sclh) setup time, scl high after sda valid 250 100 ns t h(sda ? scll) hold time, scl low after sda invalid 0 3.45 0 0.9 s t c(scl) scl sda t su(sda ? sclh) t h(sda ? scll) t w(scll) t w(sclh) t r(scl) t f(scl) t f(sda) t r(sda) t w(sp) figure 6 ? 30. definition of timing on the i 2 c bus electrical specifications 74 december 2001 ? revised december 2002 sprs017b table 6 ? 31. i 2 c bus device timing requirements (stop and start conditions) standard mode fast mode unit min max min max unit t h(sdal ? scll1) hold time, scl low from sda low (start condition) 4 0.6 s t su(sclh-sdah) setup time, sda high from scl high (stop condition) 4 0.6 s t w(sdah) pulse duration, sda high. bus free time between a stop and start condition. 4.7 1.3 s scl sda t w(sdah) t h(sdal ? scll1) t h(sdal ? scll1) t su(sclh ? sdah) figure 6 ? 31. i 2 c bus timings (stop and start conditions) table 6 ? 32. i 2 c bus device timing requirements (repeated start condition) standard mode fast mode unit min max min max unit t su(sclh ? sdal) setup time, sda low after scl high 4.7 0.6 s t d(sdal ? scll2) hold time, scl low after sda low 4 0.6 s scl sda t su(sclh ? sdal) repeated start t h(sdal ? scll2) figure 6 ? 32. i 2 c bus timings (repeated start condition) electrical specifications 75 december 2001 ? revised december 2002 sprs017b 6.14 arm clock timings the arm sram timings are derived from the arm clock. the clock switching characteristics are defined in table 6 ? 33 for use in the arm sram timing definitions. table 6 ? 33. arm sram switching characteristics parameter min typ max unit a t c(arm) cycle time, arm clock 21.05 ns b t w(arm ? h) pulse duration, arm clock high a/2 ? 3 ? a/2 ? a/2 + 3 ? ns c t w(arm ? l) pulse duration, arm clock low a/2 ? 3 ? a/2 ? a/2 + 3 ? ns d t w(arm ? w) pulse duration, arm write cycle a/2 + na ?? ns e t w(arm ? r) pulse duration, arm read cycle a + na ?? ns ? a = t c(arm) ? n = the number of software wait states the arm sram write timing requirements listed in table 6 ? 34 represent back-to-back write operations to a zero-wait-state sram device. table 6 ? 34 through table 6 ? 35 assume testing over recommended operating conditions (see figure 6 ? 33 and figure 6 ? 34). table 6 ? 34. arm sram timing requirements (write) min nom max unit 1 t d(csl-av) delay time, address valid from cs low ? 3 4 ns 2 t d(csl-dv) delay time, data valid from cs low ? 2 5 ns 3 t d(csl-wel) delay time, write enable low from cs low 4 13 ns 4 t w(wel) pulse width, write enable low d ? 3.5 d d + 3.5 ns 5 t d(weh ? aiv) delay time, address invalid from write enable high 0 7 ns 6 t d(weh ? div) delay time, data invalid from write enable high 0 7 ns 7 t d(weh ? dv) delay time, data valid from write enable high 2 9 ns 8 t w(weh) pulse width, write enable high a/2 ? 3.5 ? a/2 ? a/2 + 3.5 ? ns 9 t d(weh ? csh) delay time, cs high from write enable high 0 7 ns 10 t d(csl ? bev) delay time, byte enable valid from cs low ? 3 4 ns 11 t d(weh ? beiv) delay time, byte enable invalid from write enable high 0 7 ns 12 t d(weh ? bev) delay time, byte enable valid from write enable high 2 9 ns 20 t d(csl-oeh) delay time, output enable high from cs low ? 3 4 ns 21 t d(weh ? oel) delay time, output enable low from write enable high 0 7 ns ? a = t c(arm) d = t w(arm-w) electrical specifications 76 december 2001 ? revised december 2002 sprs017b b 1 5 5 2 6 7 6 3 4 8 4 9 10 12 11 11 20 21 arm_mclk add[22:0] data[31:0] r/w cs n be [3:0] oe d ? c d ? a ? n = 0 wait states ? n = 1 or more wait states note: when performing a 32-bit access on a 16-bit-wide sram, two of the byte-enables will be active at the same time. the parti cular byte-enables active depend on the endiannism selected. figure 6 ? 33. arm sram write timing electrical specifications 77 december 2001 ? revised december 2002 sprs017b the arm sram read timing requirements listed in table 6 ? 35 represent back-to-back read operations to a zero-wait-state sram device. table 6 ? 35. arm sram timing requirements (read) min max unit 1 t d(csl-av) delay time, address valid from cs low ? 3 4 ns 2 t d(csl ? bhev1) delay time, byte enable high valid 1 from cs low ? 3 4 ns 3 t d(csl-oel) delay time, output enable low from cs low ? 3 4 ns 4 t d(csl-aiv1) delay time, address invalid 1 from cs low e ? 3 ? e + 4 ? ns 5 t w(csl) pulse duration, cs low 2e ? 3.5 ? 2e + 3.5 ? ns 6 t su(csl-dv1) setup time, data valid 1 from cs low e ? 12 ? ns 7 t d(csl ? aiv2) delay time, address invalid 2 from cs low 2e ? 3 ? 2e + 4 ? ns 8 t h(csl ? div1) hold time, data invalid 1 from cs low e ? 1 ? ns 9 t su(csl ? dv2) setup time, data valid 2 from cs low 2e ? 12 ? ns 10 t d(csl ? beiv1) delay time, byte enable invalid 1 from cs low e ? 4 ? e + 4 ? ns 11 t d(csl ? bev2) delay time, byte enable valid 2 from cs low e ? 2 ? e + 6 ? ns 12 t h(csl ? div2) hold time, data invalid 2 from cs low 2e ? 1 ? ns 13 t d(csl ? beiv2) delay time, byte enable invalid 2 from cs low 2e ? 4 ? 2e + 4 ? ns 14 t d(csl ? oeh) delay time, output enable high from cs low 2e ? 3 ? 2e + 4 ? ns ? e = t w(arm ? r) electrical specifications 78 december 2001 ? revised december 2002 sprs017b b c a 1 5 2 11 10 13 3 arm_mclk add[22:0] data[31:0] r/w cs n be [3:0] oe 6 8 9 12 7 4 14 e ? e ? ? n = 0 wait states ? n = 1 or more wait states note: when performing a 32-bit access on a 16-bit-wide sram, two of the byte-enables will be active at the same time. the parti cular byte-enables active depend on the endiannism selected. figure 6 ? 34. arm sram read timing electrical specifications 79 december 2001 ? revised december 2002 sprs017b 6.15 spi clock timings spi timings are derived from the internal spi clock. this clock is only available externally during a serial transfer. table 6 ? 36 through table 6 ? 38 assume testing over recommended operating conditions (see figure 6 ? 35 and figure 6 ? 36). table 6 ? 36. spi clock switching characteristics parameter min typ max unit t c(spi) cycle time, clkx_spi 168.4 a ? ns t w(spi ? h) pulse duration, clkx_spi high a/2 ? 3 ? a/2 ? a/2 + 3 ? ns t w(spi ? l) pulse duration, clkx_spi low a/2 ? 3 ? a/2 ? a/2 + 3 ? ns t r(spi) rise time, spi output signals. clkx_spi, mcudo, mcuen0, mcuen1, and mcuen2 1 4 ns t f(spi) fall time, spi output signals. clkx_spi, mcudo, mcuen0, mcuen1, and mcuen2 1 4 ns ? a = 4 x ptv x t c(arm) table 6 ? 37. spi falling edge timing requirements min nom max unit t d(enfs ? clkh) delay time, falling enable start active to first clock high a/2 ? 3 ? a/2 ? a/2 + 3 ? ns t d(clkl ? enfe) delay time, last clock low to falling enable end a ? 3 ? a ? a + 3 ? ns t w(enft) pulse duration, falling enable toggle a ? 3 ? a ? a + 3 ? ns t d(clkh ? dov) delay time, clock high to data out valid 2 8 ns t su(div ? clkl) setup time, data in valid to clock low 6 ns t h(clkl ? diiv) hold time, clock low to data in invalid 4 ns ? a = 4 x ptv x t c(arm) in this mode, all timing related activity for data in and enable is based on the falling edge of the spi clock. the timing activity for data out will be based on the rising edge of the spi clock. electrical specifications 80 december 2001 ? revised december 2002 sprs017b msb lsb bit=31 bit=32 ? total mcueno, 1 2, ( negative edge triggered) mcueno, 1 2, (positive edge triggered) triggered) mcueno, 1 2, mcueno, 1 2, triggered) (positive level clkx_spi mcudo mcudi msb lsb bit=total ? 1 bit=0 t c(spi) t w(spi ? h) t w(spi ? l) t r(spi) t f(spi) t d(clkl ? enfe) t d(enfs ? clkh) t d(clkl ? diiv) t w(enft) t su(div ? clkl) ( negative level a 13 figure 6 ? 35. spi falling edge timings electrical specifications 81 december 2001 ? revised december 2002 sprs017b table 6 ? 38. spi rising edge timing requirements min nom max unit t d(enrs ? clkh) delay time, rising enable start active to first clock high a ? 3 ? a ? a + 3 ? ns t d(clkl ? enre) delay time, last clock low to rising enable end a/2 ? 3 ? a/2 ? a/2 + 3 ? ns t w(enrt) pulse duration, rising enable toggle a ? 3 ? a ? a + 3 ? ns t d(clkl ? dov) delay time, clock low to data out valid 2 8 ns t su(div ? clkh) setup time, data in valid to clock high 6 ns t h(clkh ? diiv) hold time, clock high to data in invalid 4 ns ? a = 4 x ptv x t c(arm) in this mode, all timing related activity for data in and enable is based on the falling edge of the spi clock. the timing activity for data out will be based on the rising edge of the spi clock. msb lsb bit=31 bit=32 ? total mcueno, 1 2, ( negative edge triggered) mcueno, 1 2, (positive edge triggered) ( negative level triggered) mcueno, 1 2, mcueno, 1 2, triggered) (positive level clkx_spi mcudo mcudi msb lsb bit=total ? 1 bit=0 t d(enrs ? clkh) t d(clkl ? enre) t w(enrt) t h(clkh ? diiv) t su(div ? clkh) t d(clkl ? dov) t c(spi) t w(spi ? h) t w(spi ? l) t r(spi) t f(spi) figure 6 ? 36. spi rising edge timings mechanical data 82 december 2001 ? revised december 2002 sprs017b 7 mechanical data 7.1 ball grid array mechanical data ghk (s-pbga-n257) plastic ball grid array 0,08 0,12 1,40 max 0,85 0,45 0,55 0,35 0,45 0,95 15,90 sq 16,10 seating plane 7 j b a 1 d c e g f h 24 3 6 5 t k l m p n r w u v 12 8 9 10 11 15 14 13 16 17 14,40 typ 18 19 4145273-3/e 08/02 a1 corner 0,80 0,80 bottom view notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice c. microstar bga ? configuration figure 7 ? 1. tms320vc5470 257-ball microstar bga ? plastic ball grid array package microstar bga is a trademark of texas instruments. |
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