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| the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. mos integrated circuit pd30122 v r 4122 tm 64-/32-bit microprocessor document no. u15585ej3v0ds00 (3rd edition) date published december 2002 n cp(k) printed in japan data sheet ? the mark shows ma j or revised p oints. description the pd30122 (v r 4122) is one of nec electronics? v r series tm risc (reduced instruction set computer) microprocessors and is a high-performance 64-/32-bit microprocessor employing the mips tm risc architecture. the v r 4122 uses the high-performance, super power-saving v r 4120 tm as the cpu core, and has many peripheral functions such as a dma controller, serial interface, irda interface, and real-time clock. configured with these functions, the v r 4122 is suitable for high-speed battery-driven portable information systems. the external memory bus width can be selected from 32 bits and 16 bits, realizing high-speed data transfer. detailed function descriptions are provided in the following user?s manuals. be sure to read them before designing. ? v r 4122 user?s manual (u14327e) ? v r 4100 series tm architecture user?s manual (u15509e) features employs 64-bit mips architecture conforms to mips iii instruction set (deleting fpu, ll, lld, sc, and scd instructions) optimized 5-stage pipeline supports mips16 instruction set supports high-speed product-sum operation instructions supports four types of operating modes, enabling more effective power-consumption management internal maximum operating frequency: 180/150 mhz on-chip clock generator address space physical: 32 bits virtual: 40 bits integrates 32 double-entry tlbs high-capacity instruction/data separated cache memories instruction: 32 kb data: 16 kb memory controller (rom, synchronous dram (sdram), and flash memory supported) supports pci bus subset 4-channel dma controller serial interface (ns16550 compatible) on-chip clocked serial interface irda interface for infrared communication debug serial interface power supply voltage: v dd 1 = 1.8 to 2.0 v (150 mhz model), 1.9 to 2.0 v (180 mhz model) v dd 3 = 3.0 to 3.6 v package: 224-pin fine-pitch fbga applications ? battery-driven portable information systems ? embedded controllers, etc.
data sheet u15585ej3v0ds 2 pd30122 ordering information part number package internal maximum operating frequency pd30122f1-150-ga1 224-pin plastic fbga (16 16) 150 mhz pd30122f1-180-ga1 224-pin plastic fbga (16 16) 180 mhz pin configuration ? 224-pin plastic fbga (16 16) pd30122f1-150-ga1 pd30122f1-180-ga1 index mark vutrpnmlkjhgfedcba abcdefghjklmnprtuv 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bottom view top view data sheet u15585ej3v0ds 3 pd30122 (1/2) pin no. power supply note pin name pin no. power supply note pin name pin no. power supply note pin name a1 3.3 v clkout c14 3.3 v ad3 h3 3.3 v add13 a2 1.8 v v dd pd c15 3.3 v cbe2 h4 3.3 v data5 a3 1.8 v v dd p c16 3.3 v devsel# h15 3.3 v power a4 3.3 v clkx1 c17 3.3 v par h16 3.3 v gnd3 a5 3.3 v clkx2 c18 3.3 v frame# h17 3.3 v bktgio# a6 3.3 v pclk d1 3.3 v add17 h18 3.3 v firclk a7 3.3 v ad28 d2 3.3 v add21 j1 3.3 v data8 a8 3.3 v ad23 d3 3.3 v add22 j2 3.3 v data7 a9 3.3 v ad19 d4 1.8 v v dd 1 j3 3.3 v add11 a10 3.3 v ad16 d5 3.3 v gnd3 j4 3.3 v add12 a11 3.3 v ad13 d6 3.3 v cgnd j15 3.3 v poweron a12 3.3 v ad12 d7 3.3 v ad29 j16 3.3 v mpower a13 3.3 v ad10 d8 3.3 v ad24 j17 1.8 v gnd1 a14 3.3 v ad6 d9 3.3 v ad20 j18 3.3 v irdout# a15 3.3 v ad2 d10 3.3 v ad15 k1 3.3 v data10 a16 3.3 v rst# d11 1.8 v gnd1 k2 3.3 v data9 a17 3.3 v cbe1 d12 3.3 v ad8 k3 3.3 v add10 a18 3.3 v irdy# d13 3.3 v ad4 k4 3.3 v data11 b1 3.3 v add23 d14 3.3 v ad0 k15 3.3 v gnd3 b2 3.3 v v dd 3 d15 3.3 v gnd3 k16 1.8 v v dd 1 b3 1.8 v gndp d16 3.3 v gnd3 k17 3.3 v jtdi/rmode# b4 3.3 v cv dd d17 3.3 v perr# k18 3.3 v v dd 3 b5 3.3 v rtcx1 d18 3.3 v stop# l1 3.3 v data13 b6 3.3 v ad30 e1 3.3 v add15 l2 3.3 v data12 b7 3.3 v ad25 e2 3.3 v add18 l3 3.3 v gnd3 b8 3.3 v ad22 e3 3.3 v add16 l4 3.3 v add9 b9 3.3 v ad17 e4 3.3 v add19 l15 3.3 v rtcrst# b10 3.3 v ad14 e15 3.3 v gnd3 l16 3.3 v rstsw# b11 3.3 v v dd 3 e16 3.3 v gnd3 l17 3.3 v jtck b12 3.3 v ad9 e17 3.3 v req1# l18 3.3 v irdin b13 3.3 v ad5 e18 3.3 v clkrun m1 3.3 v data15 b14 3.3 v ad1 f1 3.3 v gnd3 m2 3.3 v data14 b15 3.3 v cbe3 f2 3.3 v data1 m3 3.3 v data17/gpio17 b16 3.3 v cbe0 f3 3.3 v data2 m4 3.3 v add8 b17 3.3 v v dd 3 f4 3.3 v data0 m15 3.3 v ddin/gpio34 b18 3.3 v trdy# f15 3.3 v req0# m16 3.3 v ledout# c1 3.3 v add20 f16 3.3 v req2# m17 3.3 v jtms c2 3.3 v add24 f17 3.3 v gnt0# m18 3.3 v firdin#/sel c3 1.8 v gndpd f18 3.3 v gnt2# n1 3.3 v add7 c4 3.3 v ad27 g1 1.8 v gnd1 n2 3.3 v data16/gpio16 c5 3.3 v gnd3 g2 3.3 v add14 n3 3.3 v add6 c6 3.3 v rtcx2 g3 3.3 v v dd 3 n4 3.3 v data18/gpio18 c7 3.3 v ad31 g4 3.3 v data3 n15 3.3 v drts#/mips16en/gpio33 c8 3.3 v ad26 g15 3.3 v serr# n16 3.3 v ddout/dbus32/gpio32 c9 3.3 v ad21 g16 3.3 v gnt1# n17 3.3 v jtdo c10 3.3 v ad18 g17 3.3 v jtrst# n18 3.3 v hldrq# c11 1.8 v v dd 1 g18 3.3 v lock# p1 3.3 v data20/gpio20 c12 3.3 v ad11 h1 3.3 v data6 p2 3.3 v data19/gpio19 c13 3.3 v ad7 h2 3.3 v data4 p3 3.3 v gnd3 note for the actual power supply voltage values, refer to 2. electrical specifications . remark # indicates active low. data sheet u15585ej3v0ds 4 pd30122 (2/2) pin no. power supply note pin name pin no. power supply note pin name pin no. power supply note pin name p4 3.3 v gnd3 t4 3.3 v data27/gpio27 u12 1.8 v gnd1 p15 3.3 v rts#/clksel1 t5 3.3 v data31/gpio31 u13 3.3 v sin p16 3.3 v dcts#/gpio35 t6 3.3 v cas u14 3.3 v gpio3 p17 3.3 v txd/clksel2 t7 3.3 v swr# u15 3.3 v gpio7 p18 3.3 v nwireen/hldak# t8 3.3 v cke0 u16 3.3 v gpio8 r1 3.3 v data21/gpio21 t9 3.3 v romcs0# u17 3.3 v v dd 3 r2 3.3 v add5 t10 3.3 v iocs0# u18 3.3 v dcd#/gpio15 r3 3.3 v v dd 3 t11 1.8 v v dd 1 v1 3.3 v data25/gpio25 r4 3.3 v dqm1 t12 3.3 v gpio0 v2 3.3 v data26/gpio26 r5 3.3 v data29/gpio29 t13 3.3 v gpio4 v3 3.3 v data28/gpio28 r6 3.3 v wr# t14 3.3 v gnd3 v4 3.3 v data30/gpio30 r7 3.3 v ras t15 3.3 v iordy v5 3.3 v sclk r8 3.3 v dqm3 t16 3.3 v gpio10 v6 3.3 v v dd 3 r9 3.3 v cs1# t17 3.3 v gpio13 v7 3.3 v dqm0 r10 3.3 v spower t18 3.3 v dtr#/clksel0 v8 3.3 v cke1 r11 3.3 v v dd 3 u1 3.3 v data24/gpio24 v9 3.3 v cs2#/romcs2# r12 3.3 v sout u2 3.3 v v dd 3 v10 3.3 v romcs1# r13 3.3 v gpio2 u3 3.3 v add3 v11 3.3 v gnd3 r14 3.3 v gnd3 u4 3.3 v add2 v12 3.3 v seclk r15 3.3 v battinh/battint# u5 3.3 v add1 v13 3.3 v gpio1 r16 3.3 v dsr# u6 3.3 v rd# v14 3.3 v gpio5 r17 3.3 v cts# u7 3.3 v gnd3 v15 3.3 v gpio6/sysdir r18 3.3 v rxd u8 3.3 v dqm2 v16 3.3 v gpio9 t1 3.3 v data23/gpio23 u9 3.3v cs0# v17 3.3 v gpio11 t2 3.3 v data22/gpio22 u10 3.3 v cs3#/romcs3# v18 3.3 v gpio12 t3 3.3 v add4 u11 3.3 v iocs1# note for the actual power supply voltage values, refer to 2. electrical specifications . remark # indicates active low. data sheet u15585ej3v0ds 5 pd30122 pin identification ad(31:0): address/data bus add(24:1): address bus battinh: battery inhibit battint#: battery interrupt request bktgio#: break trigger i/o cas: column address strobe cbe(3:0): command/byte enable cgnd: gnd for oscillator cke(1:0): clock enable clksel(2:0): clock select clkout: clock output clkrun: clock run clkx1: clock x1 clkx2: clock x2 cs(3:0)#: chip select cts#: clear to send cv dd : v dd for oscillator data(31:0): data bus dbus32: data bus 32 dcd#: data carrier detect dcts#: debug serial clear to send ddin: debug serial data input ddout: debug serial data output devsel#: device select dqm(3:0): data input/output drts#: debug serial request to send dsr#: data set ready dtr#: data terminal ready firclk: fir clock firdin#: fir data input frame#: cycle frame gnd1, gnd3: ground gndp, gndpd: gnd for pll gnt(2:0)#: grant gpio(13:0): general purpose i/o gpio(35:15): general purpose i/o hldak#: hold acknowledge hldrq#: hold request iocs(1:0)#: i/o chip select iordy: i/o ready irdin: irda data input irdout#: irda data output irdy#: initiator ready jtck: jtag clock jtdi: jtag data input jtdo: jtag data output jtms: jtag mode select jtrst#: jtag reset ledout#: led output lock#: lock mips16en: mips16 enable mpower: main power nwireen: n-wire enable par: parity pclk: pci clock perr#: parity error power: power switch poweron: power on state ras: row address strobe rd#: read req(2:0)#: request rmode#: reset mode romcs(3:0)#: rom chip select rst#: reset rstsw#: reset switch rtcrst#: real-time clock reset rtcx1: real-time clock x1 rtcx2: real-time clock x2 rts#: request to send rxd: receive data sclk: sdram clock seclk: clocked serial clock sel: irda module select serr#: system error sin: clocked serial input sout: clocked serial output spower: sdram power control stop#: target assert stop swr#: sdram write sysdir: system bus buffer direction trdy#: target ready txd: transmit data v dd 1, v dd 3: power supply voltage v dd p, v dd pd: v dd for pll wr#: write remark # indicates active low. data sheet u15585ej3v0ds 6 pd30122 internal block diagram and example of connection of external blocks v rc 4173 tm pc card lcdc lcd panel touch panel osb osb 32.768 khz 18.432 mhz pll rtc dsiu icu pmu cmu dcu dmaau giu led csi siu rs-232-c driver ir driver fir 48 mhz pciu scu bcu sdram sdramu v r 4122 v r 4120 cpu core rom/ flash memory cpu core internal block diagram virtual address bus internal data bus control (o) control (i) address/data (o) address/data (i) bus interface data cache (16 kb) instruction cache (32 kb) tlb cp0 cpu clock generator internal clock data sheet u15585ej3v0ds 7 pd30122 contents 1. pin functions ............................................................................................................... ...................8 1.1 pin functions ............................................................................................................... .............................. 8 1.2 pin status in specific states ............................................................................................... ................... 17 1.3 pin handling and i/o circuit types.......................................................................................... .............. 21 1.4 pin i/o circuits ............................................................................................................ ............................. 23 2. electrical specifications .................................................................................................... ...24 3. package drawing............................................................................................................. ...........56 4. recommended soldering conditions ................................................................................57 data sheet u15585ej3v0ds 8 pd30122 1. pin functions remark # indicates active low. 1.1 pin functions (1) memory interface signals (1/2) signal i/o function sclk output operation clock for sdram add(24:1) output higher 24 bits of the 25-bit address bus these signals are used to specify addresses for the v r 4122, sdram, rom, and i/o space. data(15:0) i/o 16-bit data bus these signals are used to transfer data between the v r 4122 and the sdram, rom, or i/o space. data(31:16)/ gpio(31:16) i/o functions may differ depending on the dbus32 pin setting. ? when dbus32 = 1 these signals function as the higher 16 bits of the 32-bit data bus. they are used to transfer data between the v r 4122 and the dram or rom. ? when dbus32 = 0 these signals function as general-purpose i/o ports. cke(1:0) output clock enable signals for sdram cke(1:0) supports the following banks. sdram bank cke(1:0) 32-bit data bus 16-bit data bus bank 3 cke 1 cs3#/romcs3# dqm3 bank 2 cke 0 cs2#/romcs2# dqm2 bank 1 cke 1 cs1# cs1# bank 0 cke 0 cs0# cs0# dqm3 output the function differs depending on the setting of the dbus32 pin and the connected device. ? when dbus32 = 1 and sdram is accessed: this is the byte enable signal for data(31:24) of the 32-bit data bus. a 32-bit external i/o device is accessed: this is the byte enable signal for data(31:24) of the 32-bit data bus. ? when dbus32 = 0 and sdram is accessed: this is the cs signal for sdram. this signal becomes active when a command is issued for the sdram connected to the highest address. dqm2 output the function differs depending on the setting of the dbus32 pin and the connected device. ? when dbus32 = 1 and sdram is accessed: this is the byte enable signal for data(23:16) of the 32-bit data bus. a 32-bit external i/o device is accessed: this is the byte enable signal for data(23:16) of the 32-bit data bus. ? when dbus32 = 0 and sdram is accessed: this is the cs signal for sdram. this signal becomes active when a command is issued for the sdram connected to the second highest address. dqm1 output the function differs depending on the connected device. when sdram is accessed: this is the byte enable signal for data(15:8). when a 32-bit external i/o device is accessed: this is the byte enable signal for data(15:8). when a 16-bit external i/o device is accessed: this is the add0 signal of the i/o device. data sheet u15585ej3v0ds 9 pd30122 (2/2) signal i/o function dqm0 output the function differs depending on the connected device. when sdram is accessed: this is the byte enable signal for data(7:0). when a 32-bit external i/o device is accessed: this is the byte enable signal for data(7:0). when a 16-bit external i/o device is accessed: this is the high-byte enable signal of the i/o bus. cs(1:0)# output chip select signal for sdram ras output ras signal for sdram cas output cas signal for sdram sysdir/gpio6 i/o direction signal for sdram if not used as the sysdir signal, this signal can be used as a gpio pin. spower output power supply control signal for sdram rd# output this signal becomes active when a read access is performed for data from the i/o space and rom. wr# output this signal becomes active when writing data to the i/o space. swr# output this signal becomes active when writing data to sdram. romcs(1:0)# output chip select signals for rom cs(3:2)#/ romcs(3:2)# output chip select signals for an expansion sdram or expansion rom ? when using expansion sdram these signals function as cs(3:2)#. ? when using expansion rom these signals function as romcs(3:2)#. hldrq# input the request signal for mastership of the system bus and dram bus from the external bus master. nwireen/ hldak# i/o refer to (13) debug interface signals . (2) i/o device interface signals signal i/o function iocs(1:0)# output device chip select signals these signals become active when the v r 4122 accesses the i/o device using the add bus or data bus. iordy input device ready signal make this signal active in a state in which the i/o device can be accessed from the v r 4122. (3) clock interface signals signal i/o function rtcx1 input this is the 32.768 khz oscillator?s input pin. it is connected to one side of a crystal resonator. rtcx2 output this is the 32.768 khz oscillator?s output pin. it is connected to one side of a crystal resonator. clkx1 input this is the 18.432 mhz oscillator?s input pin. it is connected to one side of a crystal resonator. clkx2 output this is the 18.432 mhz oscillator?s output pin. it is connected to one side of a crystal resonator. firclk input this is the 48 mhz clock input pin. this signal inputs a clock when fir is used. clkout output this is the clock output to supply an external device. a 9.216 mhz clock is output in the non- hibernate mode. the clock output stops at low level during hibernate. data sheet u15585ej3v0ds 10 pd30122 (4) battery monitor interface signals signal i/o function battinh/ battint# input the function differs depending on the setting of the mpower pin. ? when mpower = 0 battinh function this signal enables/disables activation at power-on. 1: activation enabled 0: activation disabled when mpower = 1 battint# function this is an interrupt signal that is output when the remaining power is low during normal operation. an external circuit che cks the remaining battery power. activate the si gnal at this pin if voltage sufficient for operation cannot be supplied. (5) initialization interface signals signal i/o function mpower output this signal indicates that the v r 4122 is operating. this signal is inactive in hibernate mode. poweron output this signal indicates that the v r 4122 is ready to operate. it becomes active when a power-on factor is detected and becomes inactive when the battinh/battint# signal check operation is completed. power input this is the v r 4122 activation signal. rstsw# input this is the v r 4122 reset signal. rtcrst# input this signal resets the rtc. when power is first supplied to a device, an external circuit must assert the signal at this pin for about 2 s. data sheet u15585ej3v0ds 11 pd30122 (6) rs-232-c interface signals signal i/o function rxd input this is a receive data signal. it is used when the rs-232-c controller sends serial data to the v r 4122. cts# input this is a transmit enable signal. assert this signal when the rs-232-c controller is ready to receive transmission of serial data. dcd#/gpio15 input this is a carrier detection signal. assert this signal when valid serial data is being received. it is also used as a power-on factor for the v r 4122. when this pin is not used for the dcd# signal, this pin can be used as an interrupt detection input for the giu. dsr# input this is the data set ready signal. assert this signal when the rs-232-c controller is ready to transfer serial data between the controller and the v r 4122. txd/clksel2, rts#/clksel1, dtr#/clksel0 i/o this function differs depending on the operating status. during normal operation (output) signals used for serial communication txd signal: this is a transmit data signal. it is used when the v r 4122 sends serial data to the rs-232-c controller. rts# signal: this is a transmit request signal. this signal is asserted when the v r 4122 is ready to receive serial data from the rs-232-c controller. dtr# signal: this is a terminal equipment ready signal. this signal is asserted when the v r 4122 is ready to transmit or receive serial data. ? ? ? ? during rtc reset (input) signals (clksel(2:0)) used to set the cpu core operation frequency, busclk frequency, and internal bus clock frequency. these signals are sampled when the rtcrst# signal changes from low level to high level. for the relationship between the clksel pin setting and each clock frequency, see table 1-1. setting of clksel and frequency of pclock, vtclock, tclock, and masterout (default value ). table 1-1. setting of clksel and frequency of pclock, vtclock, tclock, and masterout (default value) clksel(2:0) pclock (mhz) vtclock (mhz) tclock (mhz) masterout (mhz) 111 rfu rfu rfu rfu 110 180.6 30.1 15.1 3.8 101 164.2 32.8 16.4 4.1 100 150.5 30.1 15.1 3.8 011 129.0 32.3 16.1 4.0 010 100.4 33.5 16.7 4.2 001 90.3 30.1 15.1 3.8 000 78.5 26.2 13.1 3.3 remark rfu: reserved for future use data sheet u15585ej3v0ds 12 pd30122 (7) debug serial interface signals signal i/o function ddin/gpio34 i/o debug serial data input signal. it is used when serial data is transferred from the external serial controller to the v r 4122. this signal can be used as a general-purpose output port when not being used as the ddin signal. dcts#/gpio35 i/o transmit enable signal. assert this signal when the debug serial controller can receive the serial data transmission. this signal can be used as a general-purpose output port when not being used as the dcts# signal. ddout/ dbus32/gpio32 i/o the functions differs depending on the operating status. ? during normal operation (output) ddout: this signal functions as the debug serial transmit data signal. ? during rtc reset (input) dbus32: this signal functions as the data bus width switching signal. when the rtcrst# signal changes from low to high, this signal is sampled. 1: data bus is used with 32-bit width 0: data bus is used with 16-bit width this signal can be used as a general-purpose output port when not being used as the ddout or dbus32 signal. drts#/ mips16en/ gpio33 i/o the functions differs depending on the operating status. ? during normal operation (output) drts#: this signal functions as the debug serial transmit request signal. ? during rtc reset (input) mips16en: this signal functions as the mips16 instruction enable signal. when the rtcrst# signal changes from low to high, this signal is sampled. 1: mips16 instructions enabled 0: mips16 instructions disabled this signal can be used as a general-purpose output port when not being used as the drts# or mips16en signal. (8) irda interface signals signal i/o function irdin input this is an irda serial data input signal. it is used when the serial data is transferred from the irda controller to the v r 4122. both fir and sir can be used. if the irda controller used is a hewlett packard company product, however, this signal should be used only for sir. firdin#/sel i/o the function differs according to the irda controller to be used. ? ? ? ? hewlett packard controller or sharp semiconductor controller firdin#: it is an fir receive data input signal. ? ? ? ? temic semiconductor controller sel: it is a signal output for the fir/sir switching. irdout# output this is the irda serial data output signal. it is used when the serial data is transferred from the v r 4122 to the irda controller. data sheet u15585ej3v0ds 13 pd30122 (9) clocked serial signals signal i/o function sin input clocked serial input signal sout output clocked serial output signal seclk output synchronous clock output for the clocked serial interface (10) general-purpose i/o signals signal i/o function gpio(3:0) i/o maskable activation factor input signals. these signals can be used as general-purpose i/o ports after activation. gpio(5:4) i/o general-purpose i/o ports. sysdir/gpio6 i/o refer to (1) memory interface signals . gpio(8:7) i/o general-purpose i/o ports. gpio(12:9) i/o maskable activation factor input signals. these signals can be used as general-purpose i/o ports after activation. gpio13 i/o general-purpose i/o port. this signal is recommended to be used as a v rc 4173 interrupt. dcd#/gpio15 input refer to (6) rs-232-c interface signals . gpio(31:16)/ data(31:16) i/o refer to (1) memory interface signals . ddout/ dbus32/ gpio32 i/o refer to (7) debug serial interface signals . drts#/ mips16en/ gpio33 i/o refer to (7) debug serial interface signals . ddin/gpio34 i/o refer to (7) debug serial interface signals . dcts#/gpio35 i/o refer to (7) debug serial interface signals . (11) led interface signal signal i/o function ledout# output this is an output signal for lighting leds in normal operation mode. this pin has to be pulled up regardless of whether the led function is being used; otherwise the internal cache does not work correctly. data sheet u15585ej3v0ds 14 pd30122 (12) pci like bus interface signals signal i/o function ad(31:0) i/o this is a 32-bit address bus and data bus. in the address phase, addresses are output, and in the data phase, data is output. cbe(3:0) i/o these are the bus-command/byte-enable signals. in the address phase, bus commands are output, and in the data phase, they operate as the byte- enable signals. devsel# i/o this signal is asserted when the target is accessed and continues being asserted until the completion of the transaction. frame# i/o this signal is asserted when the initiator starts the transaction. it also remains asserted throughout burst transfer. req(2:0)# input these signals are asserted when the master sends a request to the v r 4122 for the bus mastership. gnt(2:0)# output these signals are asserted when the v r 4122 grants bus mastership to the device making the request with the req# signal. irdy# i/o this signal is asserted when the initiator is in the data transfer enabled state. lock# i/o this signal indicates a resource lock. par i/o this signal outputs a low level if the number of ?1? bits from the 36 ad(31:0) and cbe(3:0) signals is even, and a high level if the number is odd. perr# i/o this signal is asserted when a parity error occurs following a parity check by the data-read initiator in the read cycle or the data-write target in the write cycle. serr# i/o this signal is asserted when a fatal error for the system occurs. stop# i/o this signal is asserted when the target requires the initiator to abort the transaction. trdy# i/o this signal is asserted when the target is in the transfer-enabled state. pclk output this is the pci bus reference clock. clkrun i/o this signal controls the clock for power management. rst# output this is the pci bus reset signal. data sheet u15585ej3v0ds 15 pd30122 (13) debug interface signals (1/2) signal i/o function jtck input this is the n-wire clock input. jtms input this is the n-wire serial transfer mode selection signal. jtdi/rmode# input this is the rmode#/jtdi alternate function pin. when jtrst# is active, it functions as rmode#, and when jtrst# is inactive, it functions as jtdi. if a debugging tool is not connected externally, pull up to high level. ? rmode#: input when jtrst# is active, this becomes the reset mode pin. the debug reset initial value is determined according to the level of this signal. debug reset resets the processor with two kinds of resets: a debug cold reset and debug soft reset. these two resets function in the same way as a cold reset input and a soft reset input from the target system. 0: the debug reset is valid; the cpu core is reset. 1: the debug reset is invalid; the cpu core is not reset. ? jtdi: input when jtrst# is inactive this becomes the n-wire serial data input. jtdo output this is the n-wire serial data output. jtrst input this is the n-wire unit reset signal. bktgio# i/o ? bktgio#: in the input setting when jtrst# is inactive and bktgio# is in the input setting, bktgio# becomes the event trigger/break request input pin. when the event trigger input is valid and during a trace, if bktgio# is made low level, the match packet is output once. also, if bktgio# is made low level when the break request input is valid, the normal mode user program is aborted, and the processor is forcibly changed to debug mode. if bktgio# becomes low level in debug mode, the break request is held pending until the processor returns to normal mode. 0: the match packet is output. a break is requested and the processor is forcibly changed to debug mode. 1: the current status of the processor is maintained. ? bktgio#: in the output setting when jtrst# is inactive and bktgio# is in the output setting, bktgio# becomes the event trigger/break output pin. while the processor is operating in normal mode, if an event is detected upon a match with either of the conditions of the hardware breakpoints (instruction address breakpoint or data access breakpoint), a low level (1 pulse) is output from bktgio# as an event trigger, and report of the event detection is sent to the external debugging tool. all the events detected after the last event trigger has been output are sent as one event trigger. if the processor mode is changed to debug mode, the low-level output continues, and none of the as unreported events are sent. 0: detects a hardware breakpoint (= 1 cycle pulse) the processor is in debug mode (> 1 cycle pulse) 1: the processor is in normal mode data sheet u15585ej3v0ds 16 pd30122 (2/2) signal i/o function nwireen/ hldak# i/o the function differs depending on the operating status. ? during rtc reset (input) nwireen: this signal is sampled when the rtcrst# signal changes from low level to high level. products of version 3.1: this signal controls the mask function of haltimer shutdown. 1: haltimer shutdown is not executed even if haltimer is not cleared. 0: haltimer shutdown is executed if haltimer is not cleared. products other than version 3.1: pull the nwireen/hldak# pin up or down. however, the mask function of haltimer shutdown is not available (haltimer shutdown is executed if haltimer is not cleared). ? during normal operation (output) hldak#: bus mastership enable signal for system bus and dram sent to the external bus master. this signal becomes valid when the hlden bit of the bcucntreg1 register is 1 (when the hlden bit is 0, it is high impedance). (14) dedicated v dd and gnd signals signal name power supply note function v dd p 1.8 v dedicated v dd for the pll analog unit gndp 1.8 v dedicated gnd for the pll analog unit v dd pd 1.8 v dedicated v dd for the pll digital unit. its function is identical to v dd 1. gndpd 1.8 v dedicated gnd for the pll digital unit. its function is identical to gnd1. cv dd 3.3 v dedicated v dd for the oscillator cgnd 3.3 v dedicated gnd for the oscillator v dd 1 1.8 v normal 1.8 v v dd gnd1 1.8 v gnd for normal 1.8 v system v dd 3 3.3 v normal 3.3 v v dd gnd3 3.3 v gnd for normal 3.3 v system note for the actual power supply voltage values, refer to 2. electrical specifications . remark the v r 4122 has two power supplies, but there are no restrictions on the order of supply voltage application. data sheet u15585ej3v0ds 17 pd30122 1.2 pin status in specific states (1/4) pin name when reset by rtc in hibernate mode or during haltimer shutdown when reset by rstsw in suspend mode during bus hold ad(31:0) 0 0 0 hold note 1 add(24:1) 0 0 0 note 2 hi-z battinh/battint# hi-z hi-z hi-z hi-z hi-z bktgio# 1 1 1 hold hold cas 000 note 2 hi-z cbe(3:0) 0 0 0 hold note 1 cke(1:0) 0 0 0 note 2 hi-z clkout 0 0 clk clk clk clkrun hi-z hi-z hi-z hi-z hi-z cs(1:0)# hi-z 1 1 note 2 hi-z cs2#/romcs2# hi-z note 3 1 note 2 note 4 cs3#/romcs3# hi-z note 5 1 note 2 note 6 cts# hi-z hi-z hi-z hi-z hi-z data(15:0) 0 0 0 note 2 hi-z notes 1. normal operation. 2. maintains the previous status. for the pin status during the bus hold period, however, refer to the during bus hold column. 3. depends on the status of the bcucntreg3 register?s ext_romcs0 bit and the dbus32 pin. when the ext_romcs0 bit is 0 and the dbus32 pin = 1: high level if a combination other than above: high impedance 4. depends on the status of the bcucntreg3 register?s ext_romcs0 bit and the dbus32 pin. when the ext_romcs0 bit is 0 and the dbus32 pin = 1: high impedance if a combination other than above: high level 5. depends on the status of the bcucntreg3 register?s ext_romcs1 bit and the dbus32 pin. when the ext_romcs1 bit is 0 and dbus32 = 1: high level if a combination other than above: high impedance 6. depends on the status of the bcucntreg3 register?s ext_romcs1 bit and the dbus32 pin. when the ext_romcs1 bit is 0 and dbus32 = 1: high impedance if a combination other than above: high level remark 0: low level, 1: high level, hi-z: high impedance, hold: maintains the status of the preceding fullspeed mode data sheet u15585ej3v0ds 18 pd30122 (2/4) pin name when reset by rtc in hibernate mode or during haltimer shutdown when reset by rstsw in suspend mode during bus hold data(31:16)/gpio(31:16) note 1 note 1 note 1 note 2 note 3 dcd#/gpio15 hi-z hi-z hi-z hi-z hi-z dcts#/gpio35 hi-z note 4 note 4 hold hold ddin/gpio34 hi-z note 5 note 5 hold hold ddout/dbus32/gpio32 hi-z note 6 note 6 hold hold devsel# hi-z hi-z hi-z hold note 7 dqm(3:0) hi-z 0 0 note 2 hi-z drts#/mips16en/gpio33 hi-z note 8 note 8 hold hold dsr# hi-z hi-z hi-z hi-z hi-z dtr#/clksel0 hi-z 1 1 hold hold firclk hi-z note 9 hi-z note 9 hi-z note 9 hi-z note 9 hi-z note 9 firdin#/sel hi-z note 9 hi-z note 9 hi-z note 9 hold note 9 hold note 9 frame# hi-z hi-z hi-z hold note 7 notes 1. when the dbus32 bit is 1: low level when the dbus32 bit is 0: high impedance 2. maintain the previous status. for the pin status during the bus hold period, however, refer to the during bus hold column. 3. when the dbus32 bit is 1: high impedance when the dbus32 bit is 0: maintains the previous status 4. depends on the status of the giupodaten register?s pioen35 bit. when the pioen35 bit is 0: high impedance when the pioen35 bit is 1: maintains the status of the preceding fullspeed mode 5. depends on the status of the giupodaten register?s pioen34 bit. when the pioen34 bit is 0: high impedance when the pioen34 bit is 1: maintains the status of the preceding fullspeed mode 6. depends on the status of the giupodaten register?s pioen32 bit. when the pioen32 bit is 0: high level when the pioen32 bit is 1: maintains the status of the preceding fullspeed mode 7. normal operation 8. depends on the status of the giupodaten register?s pioen33 bit. when the pioen33 bit is 0: high level when the pioen33 bit is 1: maintains the status of the preceding fullspeed mode 9. pin status when nwireen = 0; the pin status is undefined when nwireen = 1. remark 0: low level, 1: high level, hi-z: high impedance, hold: maintains the status of the preceding fullspeed mode data sheet u15585ej3v0ds 19 pd30122 (3/4) pin name when reset by rtc in hibernate mode or during haltimer shutdown when reset by rstsw in suspend mode during bus hold gnt(2:0)# hi-z hi-z hi-z hold hold gpio(5:0) hi-z hi-z hi-z hold hold gpio6/sysdir 0 note 1 note 1 note 2 note 3 gpio(13:7) hi-z hi-z hi-z hold hold iocs(1:0)# hi-z hi-z 1 1 1 iordy hi-z hi-z hi-z hi-z hi-z irdin hi-z note 4 hi-z note 4 hi-z note 4 hi-z note 4 hi-z note 4 irdout# 0 note 4 0 note 4 0 note 4 0 note 4 0 note 4 irdy# hi-z hi-z hi-z hold note 5 jtck hi-z hi-z hi-z hi-z hi-z jtdi/rmode# hi-z hi-z hi-z hi-z hi-z jtdo hi-z hi-z hi-z hi-z hi-z jtms hi-z hi-z hi-z hi-z hi-z jtrst# hi-z hi-z hi-z hi-z hi-z ledout# hi-z 1 1 1 note 5 lock# hi-z hi-z hi-z hi-z note 5 mpower 00111 par 0 0 note 6 hold note 5 pclk 000hold note 5 perr# hi-z hi-z hi-z hi-z note 5 power hi-z hi-z hi-z hi-z hi-z poweron 00000 ras 000 note 2 hi-z rd# hi-z hi-z 1 note 2 hi-z notes 1. depends on the setting of the bcucntreg3 register?s sysdir_en bit when the sysdir_en bit is 1: low level when the sysdir_en bit is 0: high impedance 2. maintains the previous status. for the pin status during the bus hold period, however, refer to the during bus hold column. 3. depends on the setting of the bcucntreg3 register?s sysdir_en bit when the sysdir_en bit is 1: high impedance when the sysdir_en bit is 0: maintains the previous status 4. pin status when nwireen = 0; the pin status is undefined when nwireen = 1. 5. normal operation 6. undefined. drive either a low or high level. remark 0: low level, 1: high level, hi-z: high impedance, hold: maintains the status of the preceding fullspeed mode data sheet u15585ej3v0ds 20 pd30122 (4/4) pin name when reset by rtc in hibernate mode or during haltimer shutdown when reset by rstsw in suspend mode during bus hold req(2:0)# hi-z hi-z hi-z hi-z hi-z romcs(1:0)# hi-z hi-z 1 1 1 rst# 0 0 0 hold note 1 rstsw# hi-z hi-z hi-z hi-z hi-z rtcrst# hi-z hi-z hi-z hi-z hi-z rts#/clksel1 hi-z 1 1 1 hold rxd hi-z hi-z hi-z hi-z hi-z sclk 0 0 note 2 note 3 hi-z seclk 0 0 1 hold hold serr# hi-z hi-z hi-z hi-z note 4 sin hi-z hi-z hi-z hi-z hi-z sout 00000 spower 01111 stop# hi-z hi-z hi-z hi-z note 4 swr# hi-z 0 0 note 3 hi-z hldrq# hi-z hi-z hi-z hi-z hi-z nwireen/hldak# hi-z hi-z hi-z note 5 0 trdy# hi-z hi-z hi-z hold note 4 txd/clksel2 hi-z 1 1 1 hold wr# hi-z hi-z 1 note 3 hi-z notes 1. maintains the previous status. 2. outputs clock. 3. maintains the previous status. for the pin status during the bus hold period, however, refer to the during bus hold column. 4. normal operation 5. depends on the setting of the bcucntreg1 register?s hlden bit. when the hlden bit is 1: normal operation as hldak# pin when the hlden bit is 0: high impedance remark 0: low level, 1: high level, hi-z: high impedance, hold: maintains the status of the preceding fullspeed mode data sheet u15585ej3v0ds 21 pd30122 1.3 pin handling and i/o circuit types (1/2) pin name pin handling recommended connection of unused pins drive capability i/o circuit type ad(31:0) ? leave open ? a add(24:1) ?? note 1 a battinh/battint# ??? b bktgio# note 2 connect to v dd via a resistor ? a cas ??? a cbe(3:0) ? leave open ? a cke(1:0) ?? 120 pf a clkout ? leave open ? a clkrun pull up connect to v dd via a resistor ? a cs(1:0)# ?? 120 pf a cs2#/romcs2# ? leave open 120 pf a cs3#/romcs3# ? leave open 120 pf a cts# ? connect to v dd or gnd ? a data(15:0) ?? 120 pf a data(31:16)/gpio(31:16) ? connect to v dd or gnd via a resistor 120 pf a dcd#/gpio15 ??? b dcts#/gpio35 ? connect to v dd or gnd via a resistor ? a ddin/gpio34 ? connect to v dd or gnd via a resistor ? a ddout/dbus32/gpio32 pull up/pull down ?? a devsel# pull up connect to v dd via a resistor ? a dqm(3:0) ?? 120 pf a drts#/mips16en/gpio33 pull up/pull down ?? a dsr# ? connect to v dd or gnd ? a dtr#/clksel0 pull up/pull down ?? a firclk ? connect to v dd via a resistor ? a firdin#/sel ? connect to v dd or gnd via a resistor ? a frame# pull up connect to v dd via a resistor ? a gnt(2:0)# ? leave open ? a gpio(2:0) ? connect to v dd or gnd via a resistor ? b gpio3 ??? b gpio(5:4) ? connect to v dd or gnd via a resistor ? b gpio6/sysdir ? leave open ? b gpio(13:7) ? connect to v dd or gnd via a resistor ? b iocs(1:0)# ? leave open ? a iordy ? connect to v dd or gnd via a resistor ? a irdin ? connect to v dd or gnd via a resistor ? a irdout# ? leave open ? a notes 1. the drive capability of add(4:1) is 120 pf and that of the other signals is 40 pf. 2. pull-up processing is recommended for expansion to the next model. remarks 1. external handling is not required for the pins with no special directions in the pin handling column ( ? ). 2. for the pins with no special directions in the recommended connection of unused pins column, follow the directions in pin handling column. data sheet u15585ej3v0ds 22 pd30122 (2/2) pin name pin handling recommended connection of unused pins drive capability i/o circuit type irdy# pull up connect to v dd via a resistor ? a jtck note 1 connect to v dd ? b jtdi/rmode# ? connect to v dd ? a jtdo ? leave open ? a jtms note 1 connect to v dd ? a jtrst# pull down connect to gnd ? b ledout# pull up note 2 connect to v dd via a resistor note 2 ? a lock# pull up connect to v dd via a resistor ? a mpower ??? a par ? leave open ? a pclk ? leave open ? a perr# pull up connect to v dd via a resistor ? a power ??? b poweron ??? a ras ??? a rd# ??? a req(2:0)# ? connect to v dd ? a romcs(1:0)# ?? 120 pf a rst# ? leave open ? a rstsw# ??? b rtcrst# ??? b rts#/clksel1 pull up/pull down ?? a rxd ? connect to v dd or gnd ? a sclk ?? 120 pf a seclk ? leave open ? a serr# pull up connect to v dd via a resistor ? a sin ? connect to v dd or gnd ? a sout ? leave open ? a spower ??? a stop# pull up connect to v dd via a resistor ? a swr# ??? a hldrq# ? leave open ? a nwireen/hldak# pull down ?? a trdy# pull up connect to v dd via a resistor ? a txd/clksel2 pull up/pull down ?? a wr# ? leave open ? a notes 1. pull-up processing is recommended for expansion to the next model. 2. ledout# pin has to be pulled up regardless of whether the led function is being used. remarks 1. external handling is not required for the pins with no special directions in the pin handling column ( ? ). 2. for the pins with no special directions in the recommended connection of unused pins column, follow the directions in pin handling column. data sheet u15585ej3v0ds 23 pd30122 1.4 pin i/o circuits data output disable input enable v dd p-ch n-ch in/out type a type b output disable data open drain v dd p-ch n-ch in/out data sheet u15585ej3v0ds 24 pd30122 2. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol condition rating unit v dd1 applies to v dd p, v dd pd, and v dd 1 pins ? 0.5 to +2.5 v supply voltage v dd3 applies to cv dd and v dd 3 pins ? 0.5 to +4.0 v v dd3 3.7 v ? 0.5 to +4.0 v input voltage v i v dd3 < 3.7 v ? 0.5 to v dd3 + 0.3 v storage temperature t stg ? 65 to +150 c cautions 1. do not short-circuit two or more output pins simultaneously. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the specifications and conditions shown in dc characteristics and ac characteristics are the ranges for normal operation and quality assurance of the product. 3. v i can be ? 1.5 v if the input pulse is less than 10 ns. data sheet u15585ej3v0ds 25 pd30122 operating conditions (1) 150 mhz model parameter symbol condition min. max. unit v dd1 applies to v dd p, v dd pd, and v dd 1 pins 1.8 2.0 v supply voltage v dd3 applies to cv dd and v dd 3 pins 3.0 3.6 v ambient temperature t a ? 40 +85 c oscillation start voltage note 1 v dds 3.0 v oscillation hold voltage note 2 v ddh1 2.5 v oscillation hold voltage note 3 v ddh2 3.0 v notes 1. this is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 khz and 18.432 mhz. 2. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 khz. 3. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 mhz. (2) 180 mhz model parameter symbol condition min. max. unit v dd1 applies to v dd p, v dd pd, and v dd 1 pins 1.9 2.0 v supply voltage v dd3 applies to cv dd and v dd 3 pins 3.0 3.6 v ambient temperature t a ? 10 +70 c oscillation start voltage note 1 v dds 3.0 v oscillation start voltage note 2 v ddh1 2.5 v oscillation start voltage note 3 v ddh2 3.0 v notes 1. this is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 khz and 18.432 mhz. 2. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 khz. 3. this is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 mhz. capacitance (t a = 25 c, v dd = 0 v) parameter symbol condition min. max. unit input capacitance c i 10 pf i/o capacitance c io f c = 1 mhz unmeasured pins returned to 0 v. 10 pf data sheet u15585ej3v0ds 26 pd30122 dc characteristics (1) 150 mhz model (t a = ? ? ? ? 40 to +85 c, v dd1 = 1.8 to 2.0 v, v dd3 = 3.0 to 3.6 v) (1/2) parameter symbol condition min. typ. max. unit output voltage, high v oh1 i oh = ? 2 ma 0.8v dd3 v output voltage, low v ol1 i ol = 2 ma 0.4 v clock input voltage, high note 1 v ih1 0.8v dd3 v dd3 + 0.3 v ? 0.3 0.3v dd3 v clock input voltage, low note 1 v il1 pulse under 10 ns note 2 ? 1.5 0.3v dd3 v input voltage, high note 3 v ih2 2.0 v dd3 + 0.3 v ? 0.3 0.3v dd3 v input voltage, low note 3 v il2 pulse under 10 ns note 2 ? 1.5 0.3v dd3 v input voltage, high note 4 v ih3 0.85v dd3 v dd3 + 0.3 v ? 0.3 0.6 v input voltage, low note 4 v il3 pulse under 10 ns note 2 ? 1.5 0.3v dd3 v hysteresis voltage notes 4, 5 v h 0.17v dd3 v input leakage current i li v dd3 = 3.6 v, v i = v dd3 , 0 v 5 a output leakage current i lo v dd3 = 3.6 v, v i = v dd3 , 0 v 5 a notes 1. applies to firclk pin. 2. precision tests have not been performed. only guaranteed as design characteristics. 3. except rtcx1, clkx1, firclk, power, rstsw#, rtcrst#, dcd#/gpio15, gpio(13:0), and battinh/battint# pins. 4. applies to power, rstsw#, rtcrst#, dcd#/gpio15, gpio(13:0), and battinh/battint# pins. 5. hysteresis voltage: difference between the minimum voltage at which the high level of a schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. data sheet u15585ej3v0ds 27 pd30122 (2/2) parameter symbol condition min. typ. note 1 max. unit in fullspeed mode 135 250 ma in standby mode 52 100 ma in suspend mode 8 26 ma i dd1 note 2 in hibernate mode, v dd1 = 0.0 v, when led unit is off. 00 a in fullspeed mode 30 60 ma in standby mode 15 45 ma in suspend mode 3.5 10.5 ma supply current i dd3 note 3 in hibernate mode, when led unit is off. 50 350 a notes 1. unless otherwise specified, these are reference values at t a = 25 c, v dd1 = 1.9 v, v dd3 = 3.3 v. 2. total current flowing to the v dd p, v dd pd, and v dd 1 pins. 3. total current flowing to the cv dd and v dd 3 pins. remarks 1. in the fullspeed mode, the maximum values of i dd1 and i dd3 are not generated at the same time. 2. a current over the typ. value may flow depending on the usage conditions, so consider the max. value of the supply current when designing the power supplies. data sheet u15585ej3v0ds 28 pd30122 (2) 180 mhz model (t a = ? ? ? ? 10 to +70 c, v dd1 = 1.9 to 2.0 v, v dd3 = 3.0 to 3.6 v) (1/2) parameter symbol condition min. typ. max. unit output voltage, high v oh1 i oh = ? 2 ma 0.8v dd3 v output voltage, low v ol1 i ol = 2 ma 0.4 v clock input voltage, high note 1 v ih1 0.8v dd3 v dd3 + 0.3 v ? 0.3 0.3v dd3 v clock input voltage, low note 1 v il1 pulse under 10 ns note 2 ? 1.5 0.3v dd3 v input voltage, high note 3 v ih2 2.0 v dd3 + 0.3 v ? 0.3 0.3v dd3 v input voltage, low note 3 v il2 pulse under 10 ns note 2 ? 1.5 0.3v dd3 v input voltage, high note 4 v ih3 0.85v dd3 v dd3 + 0.3 v ? 0.3 0.6 v input voltage, low note 4 v il3 pulse under 10 ns note 2 ? 1.5 0.3v dd3 v hysteresis voltage notes 4, 5 v h 0.17v dd3 v input leakage current i li v dd3 = 3.6 v, v i = v dd3 , 0 v 5 a output leakage current i lo v dd3 = 3.6 v, v i = v dd3 , 0 v 5 a notes 1. applies to firclk pin. 2. precision tests have not been performed. only guaranteed as design characteristics. 3. except rtcx1, clkx1, firclk, power, rstsw#, rtcrst#, dcd#/gpio15, gpio(13:0), and battinh/battint# pins. 4. applies to power, rstsw#, rtcrst#, dcd#/gpio15, gpio(13:0), and battinh/battint# pins. 5. hysteresis voltage: difference between the minimum voltage at which the high level of a schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. data sheet u15585ej3v0ds 29 pd30122 (2/2) parameter symbol condition min. typ. note 1 max. unit in fullspeed mode 180 320 ma in standby mode 52 100 ma in suspend mode 10 30 ma i dd1 note 2 in hibernate mode, v dd1 = 0.0 v, when led unit is off. 00 a in fullspeed mode 30 60 ma in standby mode 15 45 ma in suspend mode 3.5 10.5 ma supply current i dd3 note 3 in hibernate mode, when led unit is off. 50 350 a notes 1. unless otherwise specified, these are reference values at t a = 25 c, v dd1 = 1.95 v, v dd3 = 3.3 v. 2. total current flowing to the v dd p, v dd pd, and v dd 1 pins. 3. total current flowing to the cv dd , and v dd 3 pins. remarks 1. in the fullspeed mode, the maximum values of i dd1 and i dd3 are not generated at the same time. 2. a current over the typ. value may flow depending on the usage conditions, so consider the max. value of the supply current when designing the power supplies. data sheet u15585ej3v0ds 30 pd30122 data retention characteristics (t a = 25 c) parameter symbol condition min. max. unit data retention voltage note v dddr3 hibernate mode 2.5 3.6 v data retention input voltage, high v ihdr applies to rtcrst# pin 0.9v dddr3 v note the data retention voltage is the voltage at which the operation of the elapsedtime counter and the data retention of the registers of the following peripheral units are guaranteed, and is not applied to the internal data of the cpu core. it is applied to the 3.3 v power supply (cv dd , v dd 3). bcu: bcucntreg3 pmu: pmucntreg(15:8), pmucnt2reg, pmuwaitreg, pmutclkdivreg, pmuintrclkdivreg rtc: etimelreg, etimemreg, etimehreg, ecmplreg, ecmpmreg, ecmphreg, rtcl1lreg, rtcl1hreg, rtcl1cntlreg, rtcl1cnthreg, rtcl2lreg, rtcl2hreg, rtcl2cntlreg, rtcl2cnthreg, rtcintreg(2:0) giu: giupodatl, giupodaten led: ledhtsreg, ledltsreg, ledcntreg data sheet u15585ej3v0ds 31 pd30122 ac characteristics (t a = ? ? ? ? 40 to +85 c) ac test input waveform (a) data(15:0), data(31:16)/gpio(31:16), iordy, rxd, cts#, dsr#, txd/clksel2, firclk, rts#/ clksel1, dtr#/clksel0, irdin, firdin#/sel, ddin/gpio34, dcts#/gpio35, ddout/dbus32/ gpio32, ad(31:0), cbe(3:0), devsel#, frame#, req(2:0)#, irdy#, lock#, par, perr#, serr#, stop#, trdy#, clkrun, drts#/mips16en/gpio33, sin, hldrq# 2.0 v 0.3 v 2.0 v 0.3 v measurement points v dd 0 v (b) battinh/battint#, dcd#/gpio15, gpio(13:7), sysdir/gpio6, gpio(5:0), power, rstsw#, rtcrst# 0.75v dd 0.2 v 0.75v dd 0.2 v measurement points v dd 0 v ac test output measurement points 0.5v dd 0.5v dd measurement points v dd 0 v data sheet u15585ej3v0ds 32 pd30122 load conditions (a) sclk, add(24:10) note , add(4:1), cke(1:0), dqm(3:0), romcs(1:0)#, cs(3:2)#/romcs(3:2)#, cs(1:0)#, data(31:16)/gpio(31:16), data(15:0), ras note , cas note , swr# note dut c l = 120 pf sclk, add(24:10) note , add(4:1), cke(1:0), dqm(3:0), romcs(1:0)#, cs(3:2)#/romcs(3:2)#, cs(1:0)#, data(31:16)/gpio(31:16), data(15:0), ras note , cas note , swr# note note the add(24:10), ras, cas, and swr# pins are low-drive-capacity pins. these pins are measurement using 120 pf, but designing with an external load of 40 pf or lower is recommended. (b) add(9:5), spower, iocs(1:0)#, rd#, wr#, mpower, poweron, txd/clksel2, rts#/clksel1, dtr#/clksel0, firdin#/sel, irdout#, ddout/dbus32/gpio32, ddin/gpio34, dcts#/gpio35, gpio(13:0), ledout#, clkout, ad(31:0), cbe(3:0), devsel#, frame#, gnt(2:0)#, irdy#, lock#, par, perr#, serr#, trdy#, stop#, pclk, clkrun, rst#, drts#/mips16en/gpio33, seclk, sout, nwireen/hldak# dut c l = 40 pf add(9:5), spower, iocs(1:0)#, rd#, wr#, mpower, poweron, txd/clksel2, rts#/clksel1, dtr#/clksel0, firdin#/sel, irdout#, ddout/dbus32/gpio32, ddin/gpio34, dcts#/gpio35, gpio(13:0), ledout#, clkout, ad(31:0), cbe(3:0), devsel#, frame#, gnt(2:0)#, irdy#, lock#, par, perr#, serr#, trdy#, stop#, pclk, clkrun, rst#, drts#/mips16en/gpio33, seclk, sout, nwireen/hldak# data sheet u15585ej3v0ds 33 pd30122 (1) clock parameter parameter symbol condition min. typ. max. unit f fircyc1 in fir 4 mbps 47.99520 48 48.00480 mhz firclk clock frequency note 1 f fircyc2 in fir 1.152/0.576 mbps 47.93800 48 48.02976 mhz firclk clock duty note 1 t firduty 10 90 % sclk high-level width note 2 t ch 3.5 ns sclk low-level width note 2 t cl 3.5 ns sclk jitter note 3 t jitter 3.5 % clksel(2:0) = 111 note 4 rfu mhz clksel(2:0) = 110 note 5 180.6 mhz clksel(2:0) = 101 note 5 164.2 mhz clksel(2:0) = 100 150.5 mhz clksel(2:0) = 011 129.0 mhz clksel(2:0) = 010 100.4 mhz clksel(2:0) = 001 90.3 mhz cpu core operating frequency f pcyc clksel(2:0) = 000 78.5 mhz notes 1. applies to the firclk pin. 2. applies to the sclk pin. 3. precision tests have not been performed. only guaranteed as design characteristics. 4. do not set clksel(2:0) = 111. 5. the settings clksel(2:0) = 110 and 101 are only guaranteed for the 180 mhz model. do not apply these settings to the 150 mhz model. remark clksel(2:0): value set to the txd/clksel2, rts#/clksel1, and dtr#/clksel0 pins after reset. t cl t ch sclk (output) data sheet u15585ej3v0ds 34 pd30122 (2) reset parameter parameter symbol condition min. max. unit reset input low-level width t wrsl applies to rtcrst# pin 305 s rtcrst# (input) t wrsl remark for the rtcrst# characteristics at power application, refer to v r 4122 user?s manual . (3) initialization parameter parameter symbol condition min. max. unit data sampling time (from rtcrst# ) t ss 61.04 s output delay time (from rtcrst# )t od 61.04 s rtc (internal clock) rtcrst# (input) txd/clksel2, rts#/clksel1, dtr#/clksel0, ddout/dbus32/gpio32, drts#/mips16en/gpio33 (i/o) t od t ss sampling hi-z remark set the input data level by using a pull-up or pull-down resistor with high resistance. data sheet u15585ej3v0ds 35 pd30122 (4) gpio interface parameter (1/2) parameter symbol condition min. max. unit input level width note 1 t inp1 note 2 163 nns t gpinr1 note 3 200 ns gpio input rise time t gpinr2 note 4 10 ns t gpinf1 note 3 200 ns gpio input fall time t gpinf2 note 4 10 ns output level width t outp note 5 30 ns notes 1. the n value is set using the idiv(1:0) bits of the pmuintrclkdivreg register. idiv(1:0) n 11 rfu 10 4 01 8 00 2 2. applies to the gpio(5:0), sysdir/gpio6, gpio(13:7), dcd#/gpio15, and data(31:16)/gpio(31:16) pins. 3. applies to the gpio(5:0), sysdir/gpio6, gpio(13:7), and dcd#/gpio15 pins. 4. applies to the data(31:16)/gpio(31:16) pins. 5. applies to the gpio(5:0), sysdir/gpio6, gpio(13:7), dcd#/gpio15, data(31:16)/gpio(31:16), ddout/dbus32/gpio32, drts#/mips16en/gpio33, ddin/gpio34, dcts#/gpio35 pins. caution these parameters apply when the sysdir/gpio6, data(31:16)/gpio(31:16), ddout/dbus32/gpio32, drts#/mips16en/gpio33, ddin/gpio34, or dcts#/gpio35 pin is used as a gpio signal. data sheet u15585ej3v0ds 36 pd30122 (4) gpio interface parameter (2/2) (a) input level width note gpio(5:0), sysdir/gpio6, gpio(13:7), data(31:16)/gpio(31:16) pins t inp1 note (b) gpio input rise/fall time notes 1. 2. gpio(5:0), sysdir/gpio6, gpio(13:7) pins data(31:16)/gpio(31:16) pins t gpinf1 t gpinf2 note 1 note 2 t gpinr1 t gpinr2 note 1 note 2 (c) output level width note gpio(5:0), sysdir/gpio6, gpio(13:7), data(31:16)/gpio(31:16), ddout/dbus32/gpio32, drts#/mips16en/gpio33, ddin/gpio34, dcts#/gpio35 pins t outp note data sheet u15585ej3v0ds 37 pd30122 (5) normal rom parameter (1/2) parameter symbol condition min. max. unit data access time (from address) note t acc t n ? 19 ns data access time (from romcs(3:0)# ) note t ce t n ? 19 ns data access time (from rd# ) note t oe t (n ? 1) ? 29 ns data input setup time t ds 0ns data input hold time t dh 5ns note the value of n is set by using the rom2_wait(3:0) bits of the romspeedreg register. the value of t is set by using the clksel(2:0) signals (txd/clksel2, rts#/clksel1, and dtr#/clksel0 pins) and the vtdiv(2:0) bits of the pmutclkdivreg register. rom2_wait(3:0) n rom2_wait(3:0) n 1111 18 0111 10 1110 17 0110 9 1101 16 0101 8 1100 15 0100 7 1011 14 0011 6 1010 13 0010 5 1001 12 0001 4 1000 11 0000 3 vtdiv(2:0) clksel(2:0) 000 001 010 (divided by 2) 011 (divided by 3) 100 (divided by 4) 101 (divided by 5) 110 (divided by 6) 111 111 rfu rfu rfu rfu rfu rfu rfu rfu 110 rfu rfu rfu 16.6 22.1 27.6 33.2 rfu 101 rfu rfu rfu 18.2 24.3 30.4 rfu rfu 100 33.2 rfu rfu 19.9 26.6 33.2 rfu rfu 011 31.0 rfu 15.5 23.3 31.0 rfu rfu rfu 010 29.9 rfu 19.9 29.9 rfu rfu rfu rfu 001 33.2 rfu 22.1 33.2 rfu rfu rfu rfu 000 38.2 rfu 25.5 38.2 rfu rfu rfu rfu data sheet u15585ej3v0ds 38 pd30122 (5) normal rom parameter (2/2) romcs(3:0)# (output) rd# (output) data (i/o) t acc t ce t oe invalid invalid t ds t dh add(24:1) (output) remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 39 pd30122 (6) page rom parameter (1/2) parameter symbol condition min. max. unit t acc1 t n ? 19 ns data access time (from address) note t acc2 t m ? 8ns data access time (from romcs(3:0)# ) note t ce t n ? 19 ns data access time (from rd# ) note t oe t (n ? 1) ? 29 ns data input setup time t ds 0ns data input hold time t dh 5ns note the value of n is set by using the rom2_wait(3:0) bits of the romspeedreg register. the value of m is set by using the rom4_wait(1:0) bits of the romspeedreg register. the value of t is set by using the clksel(2:0) signals (txd/clksel2, rts#/clksel1, and dtr#/clksel0 pins) and the vtdiv (2:0) bits of the pmutclkdivreg register. rom2_wait(3:0) n rom2_wait(3:0) n rom4_wait(1:0) m 1111 18 0111 10 11 5 1110 17 0110 9 10 4 1101 16 0101 8 01 3 1100 15 0100 7 00 2 1011 14 0011 6 1010 13 0010 5 1001 12 0001 4 1000 11 0000 3 vtdiv(2:0) clksel(2:0) 000 001 010 (divided by 2) 011 (divided by 3) 100 (divided by 4) 101 (divided by 5) 110 (divided by 6) 111 111 rfu rfu rfu rfu rfu rfu rfu rfu 110 rfu rfu rfu 16.6 22.1 27.6 33.2 rfu 101 rfu rfu rfu 18.2 24.3 30.4 rfu rfu 100 33.2 rfu rfu 19.9 26.6 33.2 rfu rfu 011 31.0 rfu 15.5 23.3 31.0 rfu rfu rfu 010 29.9 rfu 19.9 29.9 rfu rfu rfu rfu 001 33.2 rfu 22.1 33.2 rfu rfu rfu rfu 000 38.2 rfu 25.5 38.2 rfu rfu rfu rfu data sheet u15585ej3v0ds 40 pd30122 (6) page rom parameter (2/2) romcs(3:0)# (output) rd# (output) data (i/o) t acc1 invalid add(24:1) (output) invalid t acc2 t ce t oe t ds t dh t ds t dh remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 41 pd30122 (7) flash memory mode write parameter parameter symbol condition min. max. unit write cycle time t avav 150 ns address setup time (to wr# )t avwh 75 ns address setup time (to romcs(3:0)# )t avel 0ns romcs(3:0)# setup time (to wr# )t elwl 10 ns wr# low-level width t wlwh 75 ns romcs(3:0)# hold time (from wr# )t wheh 10 ns address hold time (from wr# )t whax 10 ns wr# high-level width t whwl 75 ns address setup time (to wr# )t avwl 25 ns data output setup time (to wr# )t dvwh 75 ns data output hold time (from wr# )t whdx 10 ns romcs(3:0)# (output) wr# (output) invalid add(24:1) (output) t avel t avwl t whwl t wlwh t avwh t avav t dvwh t whdx t wheh t whax data (i/o) t elwl data sheet u15585ej3v0ds 42 pd30122 (8) flash memory mode read parameter parameter symbol condition min. max. unit data output delay time from address t avqv 180 ns data output delay time from romcs(3:0)# t elqv 180 ns address setup time (to romcs(3:0)# )t avel 0ns data output delay time from rd# t glqv 80 ns address setup time (to rd# )t avgl 0ns romcs(3:0)# hold time (from rd# )t gheh 10 ns address hold time (from rd# )t ghax 10 ns rd# high-level width t ghgl 75 ns data input setup time t ds 0ns data input hold time t dh 5ns romcs(3:0)# setup time (to rd# )t elgl 10 ns romcs(3:0)# (output) rd# (output) invalid add(24:1) (output) invalid t avel t avgl t elgl t glqv t elqv t alqv t ghgl t gheh t ghax t ds t dh data (i/o) remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 43 pd30122 (9) i/o (lcd) interface parameter (1/2) parameter symbol condition min. max. unit address setup time (to command signal ) note 1, 2 t as t k ? 15 ns address hold time (from command signal ) note 1, 2 t ah t n ? 15 ns command signal recovery time note 1, 2 t ry t (n + 1) ? 15 ns iordy sampling start time note 2 t clr t l ? 15 ns command signal delay time from iordy notes 1, 2 t rhch t m ? 15 t (m + 2) + 15 ns iordy hold time (from command signal ) note 1 t ryz 0ns data output setup time (to command signal ) notes 1, 2 t dstc t (k ? 1) ? 15 ns data output setup time (to command signal ) notes 1, 2 t dvch t (k + l + m ? 1) ? 15 ns data output hold time (from command signal ) note 1, 2 t chdv t nns data input setup time (to command signal ) note 1 t ds 0ns data input hold time (from command signal ) note 1 t dh 5ns notes 1. with the v r 4122, the rd# and wr# signals are called the command signals for the lcd interface. 2. the values of k, l, m, and n are set by using the ion_1_wait(3:0) bits, ion_2_wait(3:0) bits, ion_3_wait(3:0) bits, and ion_5_wait(1:0) bits, respectively, of the ionspeedreg register. the value of t is set by using the clksel(2:0) bits (txd/clksel2, rts#/clksel1, and dtr#/clksel0 pins) and the vtdiv(2:0) bits of the pmutclkdivreg register (n = 0, 1). ion_1_wait(3:0) ion_2_wait(3:0) ion_3_wait(3:0) k (ion_1_wait(3:0)) l (ion_2_wait(3:0)) m (ion_3_wait(3:0)) ion_5_wait(1:0) n 1111 16 14 18 11 4 1110 15 13 17 10 3 1101 14 12 16 01 2 1100 13 11 15 00 1 1011 12 10 14 1010 11 9 13 1001 10 8 12 1000 9 7 11 0111 8 6 10 0110 7 5 9 0101 6 4 8 0100 5 3 7 0011 4 2 6 0010 3 1 5 0001 2 0 4 0000 1 ? 13 remark n = 0, 1 data sheet u15585ej3v0ds 44 pd30122 (9) i/o (lcd) interface parameter (2/2) vtdiv(2:0) clksel(2:0) 000 001 010 (divided by 2) 011 (divided by 3) 100 (divided by 4) 101 (divided by 5) 110 (divided by 6) 111 111 rfu rfu rfu rfu rfu rfu rfu rfu 110 rfu rfu rfu 16.6 22.1 27.6 33.2 rfu 101 rfu rfu rfu 18.2 24.3 30.4 rfu rfu 100 33.2 rfu rfu 19.9 26.6 33.2 rfu rfu 011 31.0 rfu 15.5 23.3 31.0 rfu rfu rfu 010 29.9 rfu 19.9 29.9 rfu rfu rfu rfu 001 33.2 rfu 22.1 33.2 rfu rfu rfu rfu 000 38.2 rfu 25.5 38.2 rfu rfu rfu rfu dqm(3:0) (output) iocs0#, iocs1# (output) rd#/wr# (output) add(24:1) (output) invalid t as iordy (input) data (output) data (input) invalid invalid t clr t rhch t dvch t chdv t ry t ds t dh t dstc t ah t ryz remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 45 pd30122 (10) bus hold parameter (1/3) parameter symbol condition min. max. unit hldrq# input pulse width note t hp in fullspeed/standby/suspend mode 271 ns data floating delay time t off in fullspeed/standby/suspend mode 0 ns data valid delay time t on in fullspeed/standby/suspend mode 0 ns note when the v r 4122 receives an input signal of less than 271 ns, the bus hold operation may malfunction. change the signal input to the hldrq# pin to one with a pulse width of 271 ns or more. (a) starting bus hold clkx1 (input) hldrq# (input) hldak# (output) note t off sampling note applies to the following pins. ? add(24:1), data(15:0), cke(1:0), dqm(3:0), cs(1:0)#, ras, cas, sclk, rd#, wr#, and swr# pins ? sysdir/gpio6 pin when the load-reducing buffer direction is controlled by setting the sysdir_en bit of the bcucntreg3 register ? data(31:16)/gpio(31:16) pins in 32-bit data bus mode ? cs(3:2)#/romcs(3:2)# pins when using the expansion memory space as sdram by setting the ext_romcs(1:0) bits of the bcucntreg3 register in the 32-bit data bus mode remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 46 pd30122 (10) bus hold parameter (2/3) (b) releasing bus hold (hldrq#) clkx1 (input) hldrq# (input) hldak# (output) note t on sampling note applies to the following pins. ? add(24:1), data(15:0), cke(1:0), dqm(3:0), cs(1:0)#, ras, cas, sclk, rd#, wr#, and swr# pins ? sysdir/gpio6 pin when the load-reducing buffer direction is controlled by setting the sysdir_en bit of the bcucntreg3 register ? data(31:16)/gpio(31:16) pins in 32-bit data bus mode ? cs(3:2)#/romcs(3:2)# pins when using the expansion memory space as sdram by setting the ext_romcs(1:0) bits of the bcucntreg3 register in the 32-bit data bus mode remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 47 pd30122 (10) bus hold parameter (3/3) (c) releasing bus hold (rstsw#) clkx1 (input) rtcx1 (input) rstsw# (input) hldrq# (input) hldak# (output) note t on sampling note applies to the following pins. ? add(24:1), data(15:0), cke(1:0), dqm(3:0), cs(1:0)#, ras, cas, sclk, rd#, wr#, and swr# pins ? sysdir/gpio6 pin when the load-reducing buffer direction is controlled by setting the sysdir_en bit of the bcucntreg3 register ? data(31:16)/gpio(31:16) pins in 32-bit data bus mode ? cs(3:2)#/romcs(3:2)# pins when using the expansion memory space as sdram by setting the ext_romcs(1:0) bits of the bcucntreg3 register in the 32-bit data bus mode remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 48 pd30122 (11) serial interface parameter (1/2) parameter symbol condition min. max. unit txd output pulse width note t txd n ? 0.1 n + 0.1 s rxd input pulse width note t rxd (9/16) n s irdout# high-level output pulse width note t irdout (3/16) n ? 1 (3/16) n + 1 s irdin input pulse width t irdin 1 s note n indicates the data transfer rate per bit, which is determined by the divisor of the baud-rate generator that is set with the siudll and siudlm registers. baud rate (bps) divisor (siudlm, siudll resister) n ( s) 50 23,040 20,000.00 75 15,360 13,333.33 110 10,473 9,090.91 134.5 8,565 7,434.94 150 7,680 6,666.67 300 3,840 3,333.33 600 1,920 1,666.67 1,200 960 833.33 1,800 640 555.56 2,000 576 500.00 2,400 480 416.67 3,600 320 277.78 4,800 240 208.33 7,200 160 138.89 9,600 120 104.17 19,200 60 52.08 38,400 30 26.04 57,600 20 17.36 115,200 10 8.68 128,000 9 7.81 144,000 8 6.94 192,000 6 5.21 230,400 5 4.34 288,000 4 3.47 384,000 3 2.60 576,000 2 1.74 1,152,000 1 0.868 remark baud rate = (18.432 mhz/16)/(value set in the siudlm and siudll registers) data sheet u15585ej3v0ds 49 pd30122 (11) serial interface parameter (2/2) txd (output) t txd rxd (input) irdout# (output) irdin (input) t rxd t irdout t irdin data sheet u15585ej3v0ds 50 pd30122 (12) debug serial interface parameter parameter symbol condition min. max. unit ddout output pulse width note t ddout n ? 0.1 n + 0.1 s ddin input pulse width note t ddin (9/16) n s note n indicates the data transfer rate per bit, which is determined by the divisor of the baud rate generator set with the dsiudll and dsiudlm registers. baud rate (bps) divisor (dsiudlm, dsiudll registers) n ( s) 50 23,040 20,000.00 75 15,360 13,333.33 110 10,473 9,090.91 134.5 8,565 7,434.94 150 7,680 6,666.67 300 3,840 3,333.33 600 1,920 1,666.67 1,200 960 833.33 1,800 640 555.56 2,000 576 500.00 2,400 480 416.67 3,600 320 277.78 4,800 240 208.33 7,200 160 138.89 9,600 120 104.17 19,200 60 52.08 38,400 30 26.04 57,600 20 17.36 115,200 10 8.68 128,000 9 7.81 144,000 8 6.94 192,000 6 5.21 230,400 5 4.34 288,000 4 3.47 384,000 3 2.60 576,000 2 1.74 1,152,000 1 0.868 remark baud rate = (18.432 mhz/16)/(value set in the dsiudlm and dsiudll registers) ddin (input) ddout (output) t ddin t ddout data sheet u15585ej3v0ds 51 pd30122 (13) sdram interface parameter (1/2) parameter symbol condition min. max. unit sclk jitter note t jitter 3.5 % sclk high-level width t ch 3.5 ns sclk low-level width t cl 3.5 ns output delay time (from sclk )t dsp 1.1 11.7 ns output delay time (from sclk )t dsn ? 5.8 18.6 ns data input setup time t sds 6.2 ns data input hold time t sdh 2.9 ns note precision tests have not been performed. only guaranteed as design characteristics. data sheet u15585ej3v0ds 52 pd30122 (13) sdram interface parameter (2/2) ras (output) add(24:10) (output) note 1 cke(1:0) (output) sclk (output) cas, swr# (output) dqm note 2 (output) data note 3 (output) data note 3 (input) t ch t dsp t cl t dsp t dsn t dsn t dsn t dsp t dsp t sdh t sds notes 1. the pins to which this signal applies differ depending on the state of the dbus32 pin and the ext_romcs(1:0) bits of the bcucntreg3 register. when dbus32 = 0: cs(1:0)#, dqm(3:2) when dbus32 = 1 and ext_romcs(1:0) = 11: cs(1:0)# when dbus32 = 1 and ext_romcs(1:0) = 10: cs(1:0)#, cs2#/romcs2# when dbus32 = 1 and ext_romcs(1:0) = 00: cs(1:0)#, cs(3:2)#/romcs(3:2)# 2. the pins to which this signal applies differ depending on the state of the dbus32 pin. when dbus32 = 0: dqm (1:0) when dbus32 = 1: dqm (3:0) 3. the pins to which this signal applies differ depending on the state of the dbus32 pin. when dbus32 = 0: data(15:0) when dbus32 = 1: data(15:0), data(31:16)/gpio(31:16) remark the broken lines indicate high impedance. data sheet u15585ej3v0ds 53 pd30122 (14) csi (clocked serial interface) parameter parameter symbol condition min. typ. max. unit operating frequency 9.216 mhz seclk clock cycle time t kcy1 108 ns seclk high-level width t kh1 t kcy1 /2 ? 10 ns seclk low-level width t kl1 t kcy1 /2 ? 10 ns seclk rise time t r1 10 ns seclk fall time t f1 10 ns sin input setup time (to seclk )t sik1 30 ns sin input hold time (from seclk )t ksi1 20 ns sout output delay time (from seclk )t kso1 20 ns seclk (output) sin (input) sout (output) t kso1 t sik1 t ksi1 t r1 t f1 output data input data hi-z hi-z t kcy1 t kh1 t kl1 data sheet u15585ej3v0ds 54 pd30122 (15) pci like bus interface parameter (1/2) parameter symbol condition min. max. unit pclk clock cycle notes 1, 2 t sclk t pns pclk high-level width notes 1, 2 t clkh (t p/2) ? 4ns pclk low-level width notes 1, 2 t clkl (t p/2) ? 4ns output valid delay time (from pclk ) note 3 t val 220ns delay time from floating to valid (from pclk ) note 4 t on 2ns output floating delay time (from pclk ) note 4 t off 28 ns data input setup time note 5 t su 7ns data input hold time note 5 t dh 0ns notes 1. applies to the pclk pin. 2. the value of p is set by using the sel_clk(1:0) bits of the pciclkselreg register, and the value of t is set by using the clksel(2:0) signals (txd/clksel2, rts#/clksel1, dtr#/clksel0) and the vtdiv(2:0) bits of the pmutclkdivreg register. sel_clk(1:0) p 11 rfu 10 1 01 4 00 2 vtdiv(2:0) clksel(2:0) 000 001 010 (divided by 2) 011 (divided by 3) 100 (divided by 4) 101 (divided by 5) 110 (divided by 6) 111 111 rfu rfu rfu rfu rfu rfu rfu rfu 110 rfu rfu rfu 16.6 22.1 27.6 33.2 rfu 101 rfu rfu rfu 18.2 24.3 30.4 rfu rfu 100 33.2 rfu rfu 19.9 26.6 33.2 rfu rfu 011 31.0 rfu 15.5 23.3 31.0 rfu rfu rfu 010 29.9 rfu 19.9 29.9 rfu rfu rfu rfu 001 33.2 rfu 22.1 33.2 rfu rfu rfu rfu 000 38.2 rfu 25.5 38.2 rfu rfu rfu rfu 3. applies to the ad(31:0), cbe(3:0), devsel#, frame#, irdy#, lock#, par, perr#, serr#, stop#, trdy#, gnt(2:0)#, and rst# pins. 4. applies to the ad(31:0), cbe(3:0), devsel#, frame#, irdy#, lock#, par, perr#, serr#, stop#, and trdy# pins. 5. applies to the ad(31:0), cbe(3:0), devsel#, frame#, irdy#, lock#, par, perr#, serr#, stop#, trdy#, and req(2:0)# pins. data sheet u15585ej3v0ds 55 pd30122 (15) pci like bus interface parameter (2/2) pclk (output) note 1 note 2 note 2 note 3 t clkh t clkl t sclk t off t val t dh t su t on notes 1. applies to the ad(31:0), cbe(3:0), devsel#, frame#, irdy#, lock#, par, perr#, serr#, stop#, trdy#, gnt(2:0)#, and rst# pins. 2. applies to the ad(31:0), cbe(3:0), devsel#, frame#, irdy#, lock#, par, perr#, serr#, stop#, and trdy# pins. 3. applies to the ad(31:0), cbe(3:0), devsel#, frame#, irdy#, lock#, par, perr#, serr#, stop#, trdy#, and req(2:0)# pins. remark the broken lines indicate high impedance. load coefficient (delay time per load capacitance) rating parameter symbol condition min. max. unit load coefficient cld 5 ns/20 pf caution precision tests have not been performed. only guaranteed as design characteristics. data sheet u15585ej3v0ds 56 pd30122 3. package drawing s item millimeters b c d e g h 15.4 1.20 15.4 l 0.08 0.36 0.35 0.1 m c1.0 16.00 0.10 p 224-pin plastic fbga (16x16) a 16.00 0.10 f 0.8 (t.p.) i 0.96 j k 0.10 1.31 0.15 q r25 r0.3 w 0.20 s sab s m b s a s c a b q h k m l p index mark j i g e f w d r w y1 s224s1-80-3c-2 y1 0.20 0.50 + 0.05 ? 0.10 a b vutrpnmlk jhgfedcba 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 data sheet u15585ej3v0ds 57 pd30122 4. recommended soldering conditions the pd30122 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. table 4-1. surface mounting type soldering conditions pd30122f1-150-ga1: 224-pin plastic fbga (16 16) pd30122f1-180-ga1: 224-pin plastic fbga (16 16) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 230 c, time: 30 seconds max. (at 210 c or higher), count: 2 times max., exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours.) ir30-103-2 vps package peak temperature: 215 c, time: 25 to 40 seconds (at 200 c or higher), count: 2 times max. , exposure limit: 3 days note (after that, prebake at 125 c for 10 to 72 hours.) vp15-103-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) ? note after opening the dry pack, store it at 25c or less and 65%rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). data sheet u15585ej3v0ds 58 pd30122 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. related documents v rc 4173 user ? s manual (u14579e) pd31173 (v rc 4173) data sheet (u15338e) reference document electrical characteristics for microcomputer (u15170j) note note this document number is that of the japanese version. the documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v r 4100 series, v r 4120, v r 4122, v rc 4173, and v r series are trademarks of nec electronics corporation. mips is a registered trademark of mips technologies, inc. in the united states. data sheet u15585ej3v0ds 59 pd30122 regional information ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics america, inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics shanghai, ltd. shanghai, p.r. china tel: 021-6841-1138 fax: 021-6841-1137 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec electronics singapore pte. ltd. novena square, singapore tel: 6253-8311 fax: 6250-3583 j02.11 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ?sucursal en espa?a madrid, spain tel: 091-504 27 87 fax: 091-504 28 60 v lizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 ?succursale fran?aise ?filiale italiana milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 ?branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ?tyskland filial taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 ?united kingdom branch milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 some information contained in this document may vary from country to country. before using any nec electronics product in your application, piease contact the nec electronics office in your country to obtain a list of authorized representatives and distributors. they will verify: pd30122 exporting this product or equipment that includes this product may require a governmental license from the u.s.a. for some countries because this product utilizes technologies limited by the export control regulations of the u.s.a. the information in this document is current as of november, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": com puters, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics's willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11 |
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