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ADC122S051 2 channel, 500 ksps 12-bit a/d converter general description the ADC122S051 is a low-power, two-channel cmos 12-bit analog-to-digital converter with a high-speed serial interface. unlike the conventional practice of specifying performance at a single sample rate only, the ADC122S051 is fully speci- fied over a sample rate range of 200 ksps to 500 ksps. the converter is based on a successive-approximation register architecture with an internal track-and-hold circuit. it can be configured to accept one or two input signals at inputs in1 and in2. the output serial data is straight binary, and is compatible with several standards, such as spi ? , qspi ? , microw- ire, and many common dsp serial interfaces. the ADC122S051 operates with a single supply that can range from +2.7v to +5.25v. normal power consumption using a +3v or +5v supply is 3.0 mw and 10 mw, respec- tively. the power-down feature reduces the power consump- tion to just 0.14 w using a +3v supply, or 0.32 w using a +5v supply. the ADC122S051 is packaged in an 8-lead msop package. operation over the industrial temperature range of ?40?c to +85?c is guaranteed. features n specified over a range of sample rates. n two input channels n variable power management n single power supply with 2.7v - 5.25v range key specifications n dnl +0.7 / ?0.4 lsb (typ) n inl 0.50 lsb (typ) n snr 72.5 db (typ) n power consumption ? 3v supply 3.0 mw (typ) ? 5v supply 10 mw (typ) applications n portable systems n remote data acquisition n instrumentation and control systems pin-compatible alternatives by resolution and speed all devices are fully pin and function compatible. resolution specified for sample rate range of: 50 to 200 ksps 200 to 500 ksps 500 ksps to 1 msps 12-bit adc122s021 ADC122S051 adc122s101 10-bit adc102s021 adc102s051 adc102s101 8-bit adc082s021 adc082s051 adc082s101 connection diagram 20106405 ordering information order code temperature range description top mark ADC122S051cimm ?40?c to +85?c 8-lead msop package x06c ADC122S051cimmx ?40?c to +85?c 8-lead msop package, tape & reel x06c ADC122S051eval evaluation board tri-state ? is a trademark of national semiconductor corporation qspi ? and spi ? are trademarks of motorola, inc. april 2005 ADC122S051 2 channel, 500 ksps 12-bit a/d converter ? 2005 national semiconductor corporation ds201064 www.national.com
block diagram 20106407 pin descriptions and equivalent circuits pin no. symbol description analog i/o 5,4 in1 and in2 analog inputs. these signals can range from 0v to v a . digital i/o 8 sclk digital clock input. this clock directly controls the conversion and readout processes. 7 dout digital data output. the output samples are clocked out of this pin on falling edges of the sclk pin. 6 din digital data input. the ADC122S051?s control register is loaded through this pin on rising edges of the sclk pin. 1cs chip select. on the falling edge of cs, a conversion process begins. conversions continue as long as cs is held low. power supply 2v a positive supply pin. this pin should be connected to a quiet +2.7v to +5.25v source and bypassed to gnd wit ha1f capacitor and a 0.1 f monolithic capacitor located within 1 cm of the power pin. 3 gnd the ground return for the analog supply and signals. ADC122S051 www.national.com 2
absolute maximum ratings (notes 1, 2) if military/aerospace specified devices are required, please contact the national semiconductor sales office/ distributors for availability and specifications. analog supply voltage v a ?0.3v to 6.5v voltage on any pin to gnd ?0.3v to v a +0.3v input current at any pin (note 3) 10 ma package input current (note 3) 20 ma power consumption at t a = 25?c see (note 4) esd susceptibility (note 5) human body model machine model 2500v 250v junction temperature +150?c storage temperature ?65?c to +150?c operating ratings (notes 1, 2) operating temperature range ?40?c t a +85?c v a supply voltage +2.7v to +5.25v digital input pins voltage range ?0.3v to v a clock frequency 0.8 mhz to 8 mhz analog input voltage 0v to v a package thermal resistance package ja 8-lead msop 250?c / w soldering process must comply with national semiconduc- tor?s reflow temperature profile specifications. refer to www.national.com/packaging. (note 6) ADC122S051 converter electrical characteristics (note 9) the following specifications apply for v a = +2.7v to 5.25v, gnd = 0v, f sclk = 3.2 mhz to 8 mhz, f sample = 200 ksps to 500 ksps, c l = 35 pf unless otherwise noted. boldface limits apply for t a =t min to t max : all other limits t a = 25?c. symbol parameter conditions typical limits (note 7) units static converter characteristics resolution with no missing codes 12 bits inl integral non-linearity 0.5 1.1 lsb (max) dnl differential non-linearity +0.7 1.3 lsb (max) ?0.4 ?1.0 lsb (min) v off offset error +0.3 1.3 lsb (max) oem channel to channel offset error match 0.1 1.0 lsb (max) fse full scale error ?0.5 1.5 lsb (max) fsem channel to channel full-scale error match +0.01 1.0 lsb (max) dynamic converter characteristics sinad signal-to-noise plus distortion ratio v a = +2.7 to 5.25v f in = 40.2 khz, ?0.02 dbfs 72 69.2 db (min) snr signal-to-noise ratio v a = +2.7 to 5.25v f in = 40.2 khz, ?0.02 dbfs 72.5 70.6 db (min) thd total harmonic distortion v a = +2.7 to 5.25v f in = 40.2 khz, ?0.02 dbfs ?84 ?75 db (max) sfdr spurious-free dynamic range v a = +2.7 to 5.25v f in = 40.2 khz, ?0.02 dbfs 86 76 db (min) enob effective number of bits v a = +2.7 to 5.25v 11.7 11.2 bits (min) channel-to-channel crosstalk v a = +5.25v f in = 40.2 khz ?86 db imd intermodulation distortion, second order terms v a = +5.25v, f a = 40.161 khz, f b = 41.015 khz ?87 db intermodulation distortion, third order terms v a = +5.25v f a = 40.161 khz, f b = 41.015 khz ?88 db fpbw -3 db full power bandwidth v a = +5v 11 mhz v a = +3v 8 mhz ADC122S051 www.national.com 3
ADC122S051 converter electrical characteristics (note 9) (continued) the following specifications apply for v a = +2.7v to 5.25v, gnd = 0v, f sclk = 3.2 mhz to 8 mhz, f sample = 200 ksps to 500 ksps, c l = 35 pf unless otherwise noted. boldface limits apply for t a =t min to t max : all other limits t a = 25?c. symbol parameter conditions typical limits (note 7) units analog input characteristics v in input range 0 to v a v i dcl dc leakage current 0.02 1 a (max) c ina input capacitance track mode 33 pf hold mode 3 pf digital input characteristics v ih input high voltage v a = +5.25v 2.4 v (min) v a = +3.6v 2.1 v (min) v il input low voltage 0.8 v (max) i in input current v in =0vorv in =v a 0.02 10 a (max) c ind digital input capacitance 2 4 pf (max) digital output characteristics v oh output high voltage i source = 200 a v a ? 0.03 v a ? 0.5 v (min) i source =1ma v a ? 0.10 v v ol output low voltage i sink = 200 a 0.02 0.4 v (max) i sink = 1 ma 0.1 v i ozh , i ozl tri-state ? leakage current 0.005 1 a (max) c out tri-state ? output capacitance 2 4 pf (max) output coding straight (natural) binary power supply characteristics (c l =10pf) v a analog supply voltage 2.7 v (min) 5.25 v (max) i a supply current, normal mode (operational, cs low) v a = +5.25v, f sample = 500 ksps, f in =40khz 1.9 2.4 ma (max) v a = +3.6v, f sample = 500 ksps, f in =40khz 0.84 1.2 ma (max) supply current, shutdown (cs high) v a = +5.25v, f sample = 0 ksps 60 na v a = +3.6v, f sample = 0 ksps 38 na p d power consumption, normal mode (operational, cs low) v a = +5.25v 10 12.6 mw (max) v a = +3.6v 3.0 4.3 mw (max) power consumption, shutdown (cs high) v a = +5.25v 0.32 w v a = +3.6v 0.14 w ac electrical characteristics f sclk maximum clock frequency (note 8) 3.2 mhz (min) 8 mhz (max) f s sample rate (note 8) 200 ksps (min) 500 ksps (max) t conv conversion time 13 sclk cycles dc sclk duty cycle f sclk = 8 mhz 50 30 % (min) 70 % (max) t acq track/hold acquisition time full-scale step input 3 sclk cycles throughput time acquisition time + conversion time 16 sclk cycles ADC122S051 www.national.com 4
ADC122S051 timing specifications the following specifications apply for v a = +2.7v to 5.25v, gnd = 0v, f sclk = 3.2 mhz to 8 mhz, f sample = 200 ksps to 500 ksps, c l =35pf, boldface limits apply for t a =t min to t max : all other limits t a = 25?c. symbol parameter conditions typical limits (note 7) units t csu setup time sclk high to cs falling edge (note 10) v a = +3.0v ?3.5 10 ns (min) v a = +5.0v ?0.5 t clh hold time sclk low to cs falling edge (note 10) v a = +3.0v +4.5 10 ns (min) v a = +5.0v +1.5 t en delay from cs until dout active v a = +3.0v +4 30 ns (max) v a = +5.0v +2 t acc data access time after sclk falling edge v a = +3.0v +14.5 30 ns (max) v a = +5.0v +13 t su data setup time prior to sclk rising edge +3 10 ns (min) t h data valid sclk hold time +3 10 ns (min) t ch sclk high pulse width 0.5 x t sclk 0.3 x t sclk ns (min) t cl sclk low pulse width 0.5 x t sclk 0.3 x t sclk ns (min) t dis cs rising edge to dout high-impedance output falling v a = +3.0v 1.8 20 ns (max) v a = +5.0v 1.3 output rising v a = +3.0v 1.0 v a = +5.0v 1.0 note 1: absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. for guaranteed specifications and test conditions, see the electrical characterist ics. the guaranteed specifications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the lis ted test conditions. note 2: all voltages are measured with respect to gnd = 0v, unless otherwise specified. note 3: when the input voltage at any pin exceeds the power supply (that is, v in < gnd or v in > v a ), the current at that pin should be limited to 10 ma. the 20 ma maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 ma to two. the abso lute maximum rating specification does not apply to the v a pin. the current into the v a pin is limited by the analog supply voltage specification. note 4: the absolute maximum junction temperature (t j max) for this device is 150?c. the maximum allowable power dissipation is dictated by t j max, the junction-to-ambient thermal resistance ( ja ), and the ambient temperature (t a ), and can be calculated using the formula p d max=(t j max ? t a )/ ja . the values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins a re driven beyond the power supply voltages, or the power supply polarity is reversed). obviously, such conditions should always be avoided. note 5: human body model is 100 pf capacitor discharged through a 1.5 k ? resistor. machine model is 220 pf discharged through zero ohms note 6: reflow temperature profiles are different for lead-free and non-lead-free packages. note 7: tested limits are guaranteed to national?s aoql (average outgoing quality level). note 8: this is the frequency range over which the electrical performance is guaranteed. the device is functional over a wider range which is specified under operating ratings. note 9: datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. note 10: clock may be in any state (high or low) when cs is asserted, with the restrictions on setup and hold time given by t csu and t clh . ADC122S051 www.national.com 5
timing diagrams 20106451 ADC122S051 operational timing diagram 20106408 timing test circuit 20106406 ADC122S051 serial timing diagram 20106450 sclk and cs timing parameters ADC122S051 www.national.com 6
specification definitions acquisition time is the time required to acquire the input voltage. that is, it is time required for the hold capacitor to charge up to the input voltage. aperture delay is the time between the fourth falling sclk edge of a conversion and the time when the input signal is acquired or held for conversion. conversion time is the time required, after the input voltage is acquired, for the adc to convert the input voltage to a digital word. crosstalk is the coupling of energy from one channel into the other channel, or the amount of signal energy from one analog input that appears at the measured analog input. differential non-linearity (dnl) is the measure of the maximum deviation from the ideal step size of 1 lsb. duty cycle is the ratio of the time that a repetitive digital waveform is high to the total time of one period. the speci- fication here refers to the sclk. effective number of bits (enob, or effective bits) is another method of specifying signal-to-noise and distortion or sinad. enob is defined as (sinad ? 1.76) / 6.02 and says that the converter is equivalent to a perfect adc of this (enob) number of bits. full power bandwidth is a measure of the frequency at which the reconstructed output fundamental drops 3 db below its low frequency value for a full scale input. gain error is the deviation of the last code transition (111...110) to (111...111) from the ideal (v ref ? 1.5 lsb), after adjusting for offset error. integral non-linearity (inl) is a measure of the deviation of each individual code from a line drawn from negative full scale ( 1 M 2 lsb below the first code transition) through positive full scale ( 1 M 2 lsb above the last code transition). the deviation of any given code from this straight line is measured from the center of that code value. intermodulation distortion (imd) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the adc input at the same time. it is defined as the ratio of the power in the second and third order intermodulation products to the sum of the power in both of the original frequencies. imd is usually expressed in db. missing codes are those output codes that will never appear at the adc outputs. the ADC122S051 is guaranteed not to have any missing codes. offset error is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. gnd + 0.5 lsb). signal to noise ratio (snr) is the ratio, expressed in db, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c. signal to noise plus distortion (s/n+d or sinad) is the ratio, expressed in db, of the rms value of the input signal to the rms value of all of the other spectral compo- nents below half the clock frequency, including harmonics but excluding d.c. spurious free dynamic range (sfdr) is the differ- ence, expressed in db, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, excluding d.c. total harmonic distortion (thd) is the ratio, ex- pressed in db or dbc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. thd is calcu- lated as where a f1 is the rms power of the input frequency at the output and a f2 through a f6 are the rms power in the first 5 harmonic frequencies. throughput time is the minimum time required between the start of two successive conversion. it is the acquisition time plus the conversion time. in the case of the ADC122S051, this is 16 sclk periods. ADC122S051 www.national.com 7
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. dnl-v a = 3.0v inl - v a = 3.0v 20106420 20106421 dnl-v a = 5.0v inl - v a = 5.0v 20106462 20106463 dnl vs. supply inl vs. supply 20106422 20106423 ADC122S051 www.national.com 8
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. (continued) dnl vs. clock frequency inl vs. clock frequency 20106424 20106425 dnl vs. clock duty cycle inl vs. clock duty cycle 20106426 20106427 dnl vs. temperature inl vs. temperature 20106428 20106429 ADC122S051 www.national.com 9
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. (continued) snr vs. supply thd vs. supply 20106430 20106435 snr vs. clock frequency thd vs. clock frequency 20106431 20106436 snr vs. clock duty cycle thd vs. clock duty cycle 20106432 20106437 ADC122S051 www.national.com 10
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. (continued) snr vs. input frequency thd vs. input frequency 20106433 20106438 snr vs. temperature thd vs. temperature 20106434 20106439 sfdr vs. supply sinad vs. supply 20106440 20106445 ADC122S051 www.national.com 11
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. (continued) sfdr vs. clock frequency sinad vs. clock frequency 20106441 20106446 sfdr vs. clock duty cycle sinad vs. clock duty cycle 20106442 20106447 sfdr vs. input frequency sinad vs. input frequency 20106443 20106448 ADC122S051 www.national.com 12
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. (continued) sfdr vs. temperature sinad vs. temperature 20106444 20106449 enob vs. supply enob vs. clock frequency 20106452 20106453 enob vs. clock duty cycle enob vs. input frequency 20106454 20106455 ADC122S051 www.national.com 13
typical performance characteristics t a = +25?c, f sample = 200 ksps to 500 ksps, f sclk = 3.2 mhz to 8 mhz, f in = 40.2 khz unless otherwise stated. (continued) enob vs. temperature spectral response - 3v, 200 ksps 20106456 20106459 spectral response - 5v, 200 ksps spectral response - 3v, 500 ksps 20106460 20106464 spectral response - 5v, 500 ksps power consumption vs. throughput 20106465 20106461 ADC122S051 www.national.com 14
applications information 1.0 ADC122S051 operation the ADC122S051 is a successive-approximation analog-to- digital converter designed around a charge-redistribution digital-to-analog converter. simplified schematics of the ADC122S051 in both track and hold modes are shown in figures 1, 2 , respectively. in figure 1 , the ADC122S051 is in track mode: switch sw1 connects the sampling capacitor to one of two analog input channels through the multiplexer, and sw2 balances the comparator inputs. the ADC122S051 is in this state for the first three sclk cycles after cs is brought low. figure 2 shows the ADC122S051 in hold mode: switch sw1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch sw2 unbalances the compara- tor. the control logic then instructs the charge-redistribution dac to add fixed amounts of charge to the sampling capaci- tor until the comparator is balanced. when the comparator is balanced, the digital word supplied to the dac is the digital representation of the analog input voltage. the ADC122S051 is in this state for the fourth through sixteenth sclk cycles after cs is brought low. the time when cs is low is considered a serial frame. each of these frames should contain an integer multiple of 16 sclk cycles, during which time a conversion is performed and clocked out at the dout pin and data is clocked into the din pin to indicate the multiplexer address for the next conversion. 2.0 using the ADC122S051 an ADC122S051 timing diagram and a serial interface timing diagram for the ADC122S051 are shown in the timing dia- grams section. cs is chip select, which initiates conversions and frames the serial data transfers. sclk (serial clock) controls both the conversion process and the timing of serial data. dout is the serial data output pin, where a conversion result is sent as a serial data stream, msb first. data to be written to the ADC122S051?s control register is placed on din, the serial data input pin. new data is written to din with each conversion. a serial frame is initiated on the falling edge of cs and ends on the rising edge of cs. each frame must contain an integer multiple of 16 rising sclk edges. the adc output data (dout) is in a high impedance state when cs is high and is active when cs is low. thus, cs acts as an output enable. additionally, the device goes into a power down state when cs is high and also between continuous conversion cycles. during the first 3 cycles of sclk, the adc is in the track mode, acquiring the input voltage. for the next 13 sclk cycles the conversion is accomplished and the data is clocked out, msb first, starting on the 5th clock. if there are more than one conversion in a frame, the adc will re-enter the track mode on the falling edge of sclk after the n*16th rising edge of sclk, and re-enter the hold/convert mode on the n*16+4th falling edge of sclk, where "n" is an integer. when cs is brought high, sclk is internally gated off. if sclk is stopped in the low state while cs is high, the subsequent fall of cs will generate a falling edge of the internal version of sclk, putting the adc into the track mode. this is seen by the adc as the first falling edge of sclk. if sclk is stopped with sclk high, the adc enters the track mode on the first falling edge of sclk after the falling edge of cs. during each conversion, data is clocked into the din pin on the first 8 rising edges of sclk after the fall of cs. for each 20106409 figure 1. ADC122S051 in track mode 20106410 figure 2. ADC122S051 in hold mode ADC122S051 www.national.com 15
applications information (continued) conversion, it is necessary to clock in the data indicating the input that is selected for the conversion after the current one. see tables 1, 2 and table 3 . if cs and sclk go low simultaneously, it is the following rising edge of sclk that is considered the first rising edge for clocking data into din. there are no power-up delays or dummy conversions re- quired with the ADC122S051. the adc is able to sample and convert an input to full conversion immediately following power up. the first conversion result after power-up will be that of in1. table 1. control register bits bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dontc dontc add2 add1 add0 dontc dontc dontc table 2. control register bit descriptions bit #: symbol: description 7-6,2-0 dontc don?t care. the value of these bits do not affect the device. 3 add0 these three bits determine which input channel will be sampled and converted in the next track/hold cycle. the mapping between codes and channels is shown in table 3 . 4 add1 5 add2 table 3. input channel selection add2 add1 add0 input channel x 0 0 in1 (default) x 0 1 in2 x 1 x not allowed. the output signal at the d out pin is indeterminate if add1 is high. ADC122S051 www.national.com 16
applications information (continued) 3.0 ADC122S051 transfer function the output format of the ADC122S051 is straight binary. code transitions occur midway between successive integer lsb values. the lsb width for the ADC122S051 is v a /4096. the ideal transfer characteristic is shown in figure 3 . the transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 lsb, or a voltage of v a /8192. other code transitions occur at steps of one lsb. 4.0 typical application circuit a typical application of the ADC122S051 is shown in figure 4 . power is provided in this example by the national semi- conductor lp2950 low-dropout voltage regulator, available in a variety of fixed and adjustable output voltages. the power supply pin is bypassed with a capacitor network located close to the ADC122S051. because the reference for the ADC122S051 is the supply voltage, any noise on the supply will degrade device noise performance. to keep noise off the supply, use a dedicated linear regulator for this device, or provide sufficient decoupling from other circuitry to keep noise off the ADC122S051 supply pin. because of the ADC122S051?s low power requirements, it is also possible to use a precision reference as a power supply to maximize performance. the four-wire interface is also shown con- nected to a microprocessor or dsp. 20106411 figure 3. ideal transfer characteristic 20106413 figure 4. typical application circuit ADC122S051 www.national.com 17
applications information (continued) 5.0 analog inputs an equivalent circuit for one of the ADC122S051?s input channels is shown in figure 5 . diodes d1 and d2 provide esd protection for the analog inputs. at no time should any input go beyond (v a + 300 mv) or (gnd ? 300 mv), as these esd diodes will begin conducting, which could result in erratic operation. the capacitor c1 in figure 5 has a typical value of 3 pf, and is mainly the package pin capacitance. resistor r1 is the on resistance of the multiplexer and track / hold switch, and is typically 500 ohms. capacitor c2 is the ADC122S051 sam- pling capacitor and is typically 30 pf. the ADC122S051 will deliver best performance when driven by a low-impedance source to eliminate distortion caused by the charging of the sampling capacitance. this is especially important when using the ADC122S051 to sample ac signals. also important when sampling dynamic signals is a band-pass or low-pass filter to reduce harmonics and noise, improving dynamic performance. 6.0 digital inputs and outputs the ADC122S051?s digital output dout is limited by, and cannot exceed, the supply voltage, v a . the digital input pins are not prone to latch-up and, and although not recom- mended, sclk, cs and din may be asserted before v a without any latch-up risk. 7.0 power supply considerations the ADC122S051 is fully powered-up whenever cs is low, and fully powered-down whenever cs is high, with one exception: the ADC122S051 automatically enters power- down mode between the 16th falling edge of a conversion and the 1st falling edge of the subsequent conversion (see timing diagrams). the ADC122S051 can perform multiple conversions back to back; each conversion requires 16 sclk cycles. the ADC122S051 will perform conversions continuously as long as cs is held low. the user may trade off throughput for power consumption by simply performing fewer conversions per unit time. the power consumption vs. sample rate curve in the typical performance curves section shows the typical power con- sumption of the ADC122S051 versus throughput. to calcu- late the power consumption, simply multiply the fraction of time spent in the normal mode by the normal mode power consumption , and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power dissipation. 7.1 power management when the ADC122S051 is operated continuously in normal mode, the maximum throughput is f sclk /16. throughput may be traded for power consumption by running f sclk at its maximum 8 mhz and performing fewer conversions per unit time, putting the ADC122S051 into shutdown mode between conversions. a plot of typical power consumption versus throughput is shown in the typical performance curves section. to calculate the power consumption for a given throughput, multiply the fraction of time spent in the normal mode by the normal mode power consumption and add the fraction of time spent in shutdown mode multiplied by the shutdown mode power consumption. generally, the user will put the part into normal mode and then put the part back into shutdown mode. note that the curve of power consumption vs. throughput is nearly linear. this is because the power consumption in the shutdown mode is so small that it can be ignored for all practical purposes. 7.2 power supply noise considerations the charging of any output load capacitance requires cur- rent from the power supply, v a . the current pulses required from the supply to charge the output capacitance will cause voltage variations on the supply. if these variations are large enough, they could degrade snr and sinad performance of the adc. furthermore, discharging the output capaci- tance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resis- tive. load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. the larger is the output capaci- tance, the more current flows through the die substrate and the greater is the noise coupled into the analog channel, degrading noise performance. to keep noise out of the power supply, keep the output load capacitance as small as practical. if the load capacitance is greater than 35 pf, use a 100 ? series resistor at the adc output, located as close to the adc output pin as practical. this will limit the charge and discharge current of the output capacitance and improve noise performance. 20106414 figure 5. equivalent input circuit ADC122S051 www.national.com 18
physical dimensions inches (millimeters) unless otherwise noted 8-lead msop order number ADC122S051cimm, ADC122S051cimmx ns package number p0mua08a national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications. for the most current product information visit us at www.national.com. life support policy national?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president and general counsel of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. banned substance compliance national semiconductor manufactures products and uses packing materials that meet the provisions of the customer products stewardship specification (csp-9-111c2) and the banned substances and materials of interest specification (csp-9-111s2) and contain no ??banned substances?? as defined in csp-9-111s2. national semiconductor americas customer support center email: new.feedback@nsc.com tel: 1-800-272-9959 national semiconductor europe customer support center fax: +49 (0) 180-530 85 86 email: europe.support@nsc.com deutsch tel: +49 (0) 69 9508 6208 english tel: +44 (0) 870 24 0 2171 fran?ais tel: +33 (0) 1 41 91 8790 national semiconductor asia pacific customer support center email: ap.support@nsc.com national semiconductor japan customer support center fax: 81-3-5639-7507 email: jpn.feedback@nsc.com tel: 81-3-5639-7560 www.national.com ADC122S051 2 channel, 500 ksps 12-bit a/d converter

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