600 n-channel logic level enhancement mode field effect transistor features 600v,1.3a,r ds(on) =7.5 @v gs =10v. super high dense cell design for extremely low r ds(on) . high power and current handling capability. to-251 & to-252 package. absolute maximum ratings (tc=25 c unless otherwise noted) parameter symbol limit unit drain-source voltage v ds v gate-source voltage v gs 30 v drain current-pulsed 1.3 a i dm a drain-source diode forward current i s 1.3 a maximum power dissipation p d w operating and storage temperautre range t j ,t stg -55 to 150 c thermal characteristics thermal resistance, junction-to-case thermal resistance, junction-to-ambient r / jc r / ja 3.5 50 /w c /w c ? @tc=25 c derate above 25 c 0.29 w/ c drain current-continuous (tc=25 c) s g d 1 preliminary 3.9 ced01n6/CEU01N6 ceu series to-252aa(d-pak) ced series to-251(l-pak) g g s s d d -continuous (tc=100 c) 0.85 a 35 i d
electrical characteristics (t c =25 c unless otherwise noted) parameter symbol condition min typ max unit drain-source avalanche rating a off characteristics drain-source breakdown voltage bv dss v gs = 0v,i d = 250 a 600 v zero gate voltage drain current i dss v ds =600v,v gs =0v 25 a gate-body leakage i gss v gs =30v,v ds =0v 100 na on characteristics a gate threshold voltage v gs(th) v ds =v gs ,i d = 250 a 24 v drain-source on-state resistance r ds(on) v gs =10v, i d = 0.65a 7.5 ? g 2 single pulse drain-source avalanche energy maximum drain-source avalanche current e as i as v dd =50v, l=95mh a mj ced01n6/CEU01N6 r g =25 ? 1.3 90 5.5 0.9 s forward transconductance fs v ds = 50v, i d = 0.65a switching characteristics b turn-on delay time rise time turn-off delay time t d(on) t r t d(off) t f v dd = 300v, i d =1a, v gs =10v r gen =25 6 18 ns ns ns ns 25 50 10 30 20 50 total gate charge gate-source charge gate-drain charge q g q gs q gd v ds =480v, i d = 1a, v gs =10v 8 12 nc nc nc fall time ? 1.3 3
parameter symbol condition min typ max unit electrical characteristics (t c =25 c unless otherwise noted) drain-source diode characteristics diode forward voltage v sd v gs = 0v, is =1.3a 1.5 v a notes b.guaranteed by design, not subject to production testing. a.pulse test:pulse width 300 3 s, duty cycle 2%. [ [ 3 figure 1. output characteristics v ds , drain-to-source voltage (v) i d , drain current(a) i d , drain current (a) b dynamic characteristics input capacitance c iss c rss c oss output capacitance reverse transfer capacitance v ds =25v, v gs =0v f =1.0mh z 200 p f 30 p f p f 10 ced01n6/CEU01N6 figure 2. transfer characteristics v gs , gate-to-source voltage (v) 1.2 1.0 0.8 0.6 0.4 0.2 0 0123 4 5 6 v gs =10,9,8,7v v g s =5 v v gs =6v 0.01 0.1 2 4 6 10 8 25 c 150 c -55 c 1.v ds =40v 2.pulse test
4 with temperature figure 6. breakdown voltage variation with temperature vth, normalized gate-source threshold voltage g fs , transconductance (s) bv dss , normalized drain-source breakdown voltage is, source-drain current (a) with drain current i ds , drain-source current (a) figure 8. body diode forward voltage variation with source current v sd , body diode forward voltage (v) tj, junction temperature ( c) tj, junction temperature ( c) figure 5. gate threshold variation figure 7. transconductance variation figure 3. capacitance v ds , drain-to source voltage (v) c, capacitance (pf) 1.30 1.20 1.10 1.0 0.90 0.80 0.70 0.60 -50 -25 0 25 50 75 100 125 150 v ds =v gs i d =250 k a figure 4. on-resistance variation with temperature t j , junction temperature( c) on-resistance(ohms) r ds(on) , r ds(on) , normalized -100 -50 0 50 100 200 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v gs =10v i d =0.65a 150 0.75 1 0 0.25 0.5 0 0.25 0.5 0.75 1.0 v ds =50v ciss coss crss 300 250 200 150 100 50 0 0 5 10 15 20 25 2 0.1 1 0.4 0.6 0.8 1.2 1.0 v gs =0v -50 -25 0 25 50 75 100 125 150 1.15 1.10 1.05 1.00 0.95 0.90 0.85 i d =250 k a ced01n6/CEU01N6
5 figure 11. switching test circuit figure 12. switching waveforms t v v t t d(on) out in on r 10% t d(off) 90% 10% 10% 50% 50% 90% t off t f 90% pulse width inverted transient thermal impedance square wave pulse duration (msec) figure 13. normalized thermal transient impedance curve r(t),normalized effective v dd r d v v r s v g gs in gen out l v gs , gate to source voltage (v) figure 9. gate charge qg, total gate charge (nc) figure 10. maximum safe operating area v ds , drain-source voltage (v) i d , drain current (a) ced01n6/CEU01N6 2 1 0.1 0.01 0.01 0.1 1 10 100 1000 10000 p dm t 1 t 2 1. r / jc (t)=r (t) * r / jc 2. r / jc =see datasheet 3. t jm- t c =p*r / jc (t) 4. duty cycle, d=t1/t2 15 12 9 6 3 0 03 6 9 12 v ds =480v i d =1a r ds (on) l i m it 10 1 0.01 1 10 100 1000 t c =25c single pulse tj=150 c 0.1 500 dc 10ms 1ms 100 s single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5
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