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1 the ddc112s test mode by jim todsen ? 1998 burr-brown corporation AB-135 printed in u.s.a. july, 1998 this application bulletin covers the ddc112s test mode. it elaborates on the explanation given in the data sheet and is written with the purpose of helping you use the test mode to its fullest capability. it does assume a basic understanding of the ddc112s operation. for a good introduction to the ddc112, see the ddc112s data sheet. the organization of this application bulletin is as follows: first, an overview presents the basic operation of the test mode. next are explanations of single packet and multiple packet test signals. noise and linearity performance of the test mode are then covered followed by some special consid- erations for using the test mode. finally, a program for investigating test mode performance is discussed with the listing for the program given afterwards. overview during normal operation, a sensor connected to each ddc112 input supplies signal current which is measured by ddc112 and converted to a 20-bit digital word. to help with debug during system development and to provide a good system- level diagnostic check, the ddc112 has a test mode which is enabled by the test pin. while in test mode, the inputs are disconnected and a test signal is measured instead. figure 1 shows a simplified block diagram of the front end of the ddc112 including test mode circuitry. you enter test mode by holding test high while conv toggles. likewise, you exit test mode by holding test low while conv toggles. the integration timing control for test mode is identical to that of normal operation: conv still sets the side (a or b) and length of integration. as in normal operation, there is a continuous and non-continuous mode in test mode determined by the length of t int (see application bulletin ab-131 for more information on the continuous and non-continuous modes). c test in figure 1 supplies the test signal to the front-end integrators. switches s a and s b , which in normal operation steer the sensors current to the a or b integrator, are opened and s at , s bt and s vt are used instead (these switches are only used in test mode). c test , previously charged to v ref by s vt , is dumped to the appropriate side by either s at or s bt depending on conv. after the dumped charge from c test is integrated by c int , s at (or s bt ) opens and c test recharges to v ref via s vt . c test is now ready for another charge dump. when the integration period is over, the adc measures the signal integrated onto c int (the total test signal dumped by c test ) just as in normal operation. s gnd shorts the ddc112s inputs to ground during test mode to prevent any current from the sensor building a charge on the ddcs inputs. c test can be dumped once or multiple times onto the integrator during an integration period. the next two sec- tions explain the timing necessary to control the number of dumps. note that the magnitude of the test signal is not a direct function of the integration time t int , but rather the number of charge packet dumps. if the number of charge packets dumped remains constant, changing t int will not affect the test mode data. figure 1. simplified block diagram of the ddc112s front end. 1b 1a s at s vt c test c test s a s gnd s b s bt c int c int in1 2b 2a s at s vt v ref s a s gnd s b s bt c int c int in2 v ref to adc
2 single packet when test is held high, a single packet of charge from c test is dumped onto the integrator at the beginning of every test mode integration. figure 2 shows the timing diagram and specifications for this case. the integrator status trace highlights the fact that the test mode functions the same as normal operation with respect to integration, measurement, auto-zero, reset, etc. the bottom trace of figure 2 shows the output voltage on the side a integrator. conv triggers the sequence that controls s at , s bt and s vt . a short time after conv toggles, s vt opens and switch s at (or s bt ) dumps c test s charge onto the appropriate integra- tor side. after the charge transfers from c test to c int , switch s at (or s bt ) opens and c test recharges to v ref using s vt . the test circuitry then waits until the next integration begins before dumping c test to the other side. this cycle continues until test is held low while conv toggles. at that point, the test mode is over and normal operation resumes. the size of each charge packet is (v ref )(c test ), approxi- mately 13pc. if, for example, the range is set to 250pc, a single packet test signal equals approximately 5.2% of full scale. the absolute value of the charge packet can vary by 20% or more due to fabrication process variations. as previously mentioned, the readings during single packet test mode are independent of t int since the test mode supplies a fixed amount of charge ( ? 13pc) each integration. the a and b sides of a channel use the same c test . due to the nature of the switching arrangement, there is a small imbalance in the charge injection between sides a and b during test mode. this imbalance results in slightly different effective sizes for the side a and b test packets. typical mismatch between side a and b charge packets is ? 0.2pc. symbol description min typ max units t 1 setup time for test mode enable 100 ns t 2 setup time for test mode disable 100 ns figure 2. single packet test mode timing. the information provided herein is believed to be reliable; however, burr-brown assumes no responsibility for inaccuracies or o missions. burr-brown assumes no responsibility for the use of this information, and all use of such information shall be entirely at the users own risk. pr ices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. burr-brown does not authorize or warrant any burr-brown product for use in life support devices and/or systems. normal operation test mode int b m/r/az a int a m/r/az b int b m/r/az a int a m/r/az b int b m/r/az a int a m/r/az b normal operation conv test test mode status integrator status s ta s tb s vt s gnd v out v ref ??side integrator t 1 t 2 dv dt i sensor c int = 1 packet 1 packet d v = ? c test v ref c int 13pc c int
3 multiple packet as described above, a packet of charge is dumped onto the integrator at the beginning of every integration during the test mode. additional packets can be dumped creating a larger test signal. multiple packets are dumped onto the integrator by toggling test during the integration as illus- trated in figure 3. the rising edge of test during a test mode integration triggers the dumping of an additional packet. multiple toggles on test result in multiple packets being dumped. in order to stay in test mode, test must be high when conv toggles at the end of the integration. figure 3 shows the relevant timing specifications for mul- tiple packet dumps. the specifications limit the maximum number of multiple packet dumps for a given t int . since the rising edges of test must be at least 5.4 m s apart, the maximum number of dumps is t int /5.4 m s (round down when this number is a non-integer). this limitation is not a concern during the continuous mode. even for t int = 500 m s, over 90 dumps are allowed which corresponds to more than 1200pc of test signaleasily enough to reach full scale on any range. it is only for the short t int s of the noncontinous mode where you need to watch the limit. noise the noise of the test mode signal is very low. in fact, the noise performance in the test mode is usually better than what can be achieved in normal operation, even with very low sensor capacitance. since the ddc112s inputs are disconnected during test mode, any coupling or interference on them (e.g., 60hz pickup) will not affect the readings. this feature can be helpful in isolating the source of interference during system evaluation. table i lists typical noise perfor- mance for the different internal ranges while in test mode with a single packet dump. the noise increases slightly for multiple packet dumps, particularly at the lower ranges. figure 3. multiple packet test mode timing. range (full-scale charge) typical noise (rms) 1 (50pc) 4.7ppm 2 (100pc) 3.6ppm 3 (150pc) 3.2ppm 4 (200pc) 3.1ppm 5 (250pc) 3.0ppm 6 (300pc) 3.0ppm 7 (350pc) 2.9ppm table i. typical noise performance in test mode. symbol description min typ max units t 1 setup time for test mode enable 100 ns t 2 setup time for test mode disable 100 ns t 3 hold time for test mode enable 100 ns t 4 from rising edge of test to the 5.4 m s edge of conv while test mode enabled t 5 rising edge to rising edge of test 5.4 m s normal operation test mode int b m/r/az a int b m/r/az a int a m/r/az b int b m/r/az a int a m/r/az b normal operation conv test test mode status integrator status s ta s tb s vt s gnd v out v ref ??side integrator t 1 t 5 t 4 t 4 t 3 t 2 dv dt i sensor c int = 2 packets 3 packets d v = ? c test v ref c int 13pc c int
4 linearity as with the noise performance, the linearity of the test signal is very good. measurements made in the test mode show that the linearity of the test mode is usually limited by the performance of the ddc112 itself. that is, the linearity of the test mode is typically only slightly worse than the linearity measured in normal operation with a linear input signal. figure 4 shows a comparison of integral non-linear- ity (inl) for normal operation of the ddc112 with a very linear input signal and for the test mode. inl is defined here as the deviation of the data from a line connected between the datas end points. notice in figure 4 how the test mode inl is only slightly worse than that of the ddc112 in normal operation. this indicates that the test mode signal is very linear and the linearity of the test mode is limited by the ddc112s inherent linearity. special considerations for the very best performance in test mode, t int might need to be an integer multiple of 3 clk periods, depending on your pc board layout. for example, if clk = 10mhz, t int might need to be a integer multiple of 300ns. if t int is not an integer multiple of 3 clk periods, there can be excessive noise in the test mode. the reason for this is explained in application bulletin, ab-131. basically, the internal slow clock (discussed in ab-131) is always left running while in test mode, even when t int > 4794 clk periods. to prevent requiring t int to be an integer multiple of 3 clk periods, pay close attention to the pc board layout. place the bypass capacitors for v ref and the power supplies as close to the pins as possible. use a good analog ground plane with the analog pins on the ddc112 connecting directly to it. see the evaluation fixture layout for an example. in this layout, the test mode noise shows no need for t int to be an integer multiple of 3 clk periods. that is, the same noise perfor- mance is achieved with t int = 500 m s, 501 m s, 502 m s, etc. example program to help investigate the test mode, a pascal program similar to the one in application bulletin, ab-125 is given in listing 1. this program runs under dos and controls the evaluation fixture hardware. using the program, you can change the number of data points averaged per reading, full- scale range, t int , and the number of test mode packets. with these variables set, you can then retrieve a reading. the displayed average for the retrieved reading is normalized to full scale = 1.0 and the rms noise is given in ppm. a routine to measure the linearity of the test mode signal is also included in the program. the program determines the size of each packet by making an initial measurement with a single packet test signal. it then calculates the number of packets needed to reach full scale. a loop increments the packets up to this number while taking data at each step. afterwards, an end-point line is connected between the first point and the final point. the program stores the linearity data in a file and reports the maximum difference between the data points and the end-point line as the inl. figure 4. normal mode and test mode inl (end-point line fit). output reading (% of full scale) inl (ppm) 0 _5 ?0 ?5 ?0 ?5 ?0 10 20 0 30405060708090100 normal mode test mode
5 listing 1 (*******************************************************************************) (* *) (* burr-brown corporation *) (* *) (* application bulletin AB-135 *) (* *) (*******************************************************************************) (* *) (* ddc112 test mode program *) (* written in turbo pascal 7.0 *) (* *) (* this program is designed to illustrate use of the ddc112s *) (* test mode. this program requires the ddc112 to be connected to the *) (* ddc112 evaluation fixture dem-ddc112u-c. see ab-125 for more info *) (* on the evaluation fixture. *) (* *) (* the user can program the # of averages/reading, range, *) (* tint and # of test packets from the menu. a single reading can be *) (* retrieved or a complete measurement of the ddc112s linearity can be *) (* taken. the results of the linearity measurement are saved to a file *) (* *) (* created by jim todsen 5/20/98 *) (* *) (*******************************************************************************) (*{$r-,s-} *) {$a+,b-,e+,f+,g-,i+,l-,n+,o+,r+,s+,v-,x+} program ddc112testmode; uses dos,crt,strings; type real4by1 = array[1..4] of real; {used to store 1a,1b,2a,2b data} {1>1a, 2>2a, 3>1b, 4>2b} var range : longint; tint : real; nt : longint; tpck : longint; pcport : longint; pprintport : ^word; readdr, wraddr, strbaddr : word; datackcode : word; sysckcode : word; ctrl1code, ctrl2code : word; dxmitdelaycode : word; userddccode : word; yave, yrms : real4by1; {*******************************************************************************} procedure badbeep; {*******************************************************************************} begin sound(100); delay(200); nosound; end; {*******************************************************************************} procedure goodbeep; {*******************************************************************************} begin sound(300); delay(50); nosound; end;
6 {*******************************************************************************} procedure xilinxwrite(xilinxaddr, xilinxdata : byte); {*******************************************************************************} {write data to a specified address on the ddc112 evaluation fixture} begin port[wraddr] := $7f and xilinxaddr; delay(2); port[strbaddr] := 1; delay(1); port[strbaddr] := 0; delay(1); port[wraddr] := $80 or xilinxdata; delay(2); port[strbaddr] := 1; delay(1); port[strbaddr] := 0; delay(1); end; {*******************************************************************************} procedure setrange(newrange: word); {*******************************************************************************} {set the ddc112 range} begin writeln( setting range = ,newrange); ctrl1code := ctrl1code and $78; ctrl1code := ctrl1code or newrange; xilinxwrite(6,ctrl1code); delay(1000); {wait for settling after change} end; {*******************************************************************************} procedure settint(var newtint: real) ; {*******************************************************************************} {set the ddc112 integration time} var intcountcode: longint; begin if newtint > 1500000 then newtint:= 1500000; intcountcode := round(newtint*10)-1; {10 mhz clk} writeln( setting tint = ,newtint:7:1); xilinxwrite(7,(ctrl2code and $7e)); {hold conv} delay(1000); {wait to insure conv is stopped} xilinxwrite(5,(intcountcode and $7f)); xilinxwrite(4,((intcountcode shr 7) and $7f)); xilinxwrite(3,((intcountcode shr 14) and $7f)); xilinxwrite(2,((intcountcode shr 21) and $07)); xilinxwrite(7,(ctrl2code or $1)); {release conv} end; {*******************************************************************************} procedure settstpckts(numpckt: longint); {*******************************************************************************} {set the # of test packets dumped to the ddc112 each integration} begin if numpckt > 0 then begin ctrl1code := ctrl1code or $8; {test on} xilinxwrite(6,ctrl1code); if numpckt = 1 then xilinxwrite(11,127) {all 1s = 1 packet} else xilinxwrite(11,(numpckt-2)); end else begin ctrl1code:= ctrl1code and $f7; {test off} xilinxwrite(6, (ctrl1code)); end; delay(1000) ;{settling time after change} end;
7 {*******************************************************************************} procedure setpcport(pcport: word); {*******************************************************************************} {set the address of the pcs parallel port used for the evaluation fixture} begin if pcport = 1 then pprintport := ptr($40,$08) else pprintport := ptr($40,$0a); wraddr:= pprintport^; readdr:= wraddr + 1; strbaddr:= wraddr + 2; port[strbaddr]:= 0; p{init strobe at 0 (really, 1 out)} end; {*******************************************************************************} procedure xilinxrefresh; {*******************************************************************************} {refresh the xilinx fpgas on the evaluation fixture} begin port[strbaddr] := 0; {init port strobe high} delay(1); xilinxwrite(0, datackcode); xilinxwrite(1, sysckcode); xilinxwrite(6, ctrl1code); xilinxwrite(7, ctrl2code); xilinxwrite(8, ((dxmitdelaycode and $180) shr 7)); xilinxwrite(9, ((dxmitdelaycode and $7f))); xilinxwrite(10, (userddccode shl 1)); setrange(range); settint(tint); settstpckts(tpck); goodbeep; end; {*******************************************************************************} procedure getint(descrip: string; min, max: longint; var value: longint; var err: boolean); {*******************************************************************************} {get an integer value from the user} var userinput : string[25]; check : integer; temp : longint; begin err:= true; clrscr; writeln; writeln( the current ,descrip, is: ,value); writeln; writeln( enter the new ,descrip,:); readln(userinput); if userinput = x then exit; if userinput = x then exit; if userinput = then exit; val(userinput,temp,check); if check <> 0 then begin badbeep; writeln( *** invalid ,descrip); writeln; delay(1000); exit; end else begin if (temp < min) or (temp > max) then begin badbeep; writeln; writeln( *** invalid ,descrip); writeln; delay(500); exit; end else begin value := temp; err := false; end; end; end;
8 {*******************************************************************************} procedure getreal(descrip: string; min, max: longint; var value: real; var err: boolean); {*******************************************************************************} {get a real value from the user} var userinput : string[25]; check : integer; temp : real; begin err := true; clrscr; writeln; writeln( the current ,descrip, is: ,value:9:3); writeln; writeln( enter the new ,descrip,:); readln(userinput); if userinput = x then exit; if userinput = x then exit; if userinput = then exit; val(userinput,temp,check); if check <> 0 then begin badbeep; writeln( *** invalid ,descrip); writeln; delay(500); exit; end else begin if (temp < min) or (temp > max) then begin badbeep; writeln; writeln( *** invalid ,descrip); writeln; delay(1000); exit; end else begin value := temp; err := false; end; end; end; {*******************************************************************************} procedure readdata(var drderror: boolean); {*******************************************************************************} {readback nt points from evaluation fixture; find yave, yrms, return status} var fnum, n : longint; { final number } busybit3, loop : integer; { data ready bit } nib, d, siderd : byte; portdatard : byte; ysum, ysumsq : array[1..4] of extended; temp : extended; ird, trd, k, count, datatime, i, j : word; fscale,deltime : real; firsttime : boolean; timereq, sampletime : real; numtints : word; begin write( filling demo board memory... ); firsttime := true; {flag to check for side a or b on first data point} if tint < 479.4 then {ncont mode} begin timereq := 1501*6*1/10 - tint; {1501=min # of slowclks to finish ncont meas} numtints := trunc(timereq / tint)+1; {# of tints skipped} if ((numtints mod 2) <> 0) then numtints := numtints+1; {numtints must be even} sampletime := tint*(2+numtints); end {cont} else sampletime := tint*2;
9 i := 0; while i < round(nt*1.4 + 50) do {extra margin for safety} begin delay(round(sampletime/1e3)); if keypressed and (readkey = chr(27)) then begin goodbeep; i := round(nt*1.4 + 50); end; i := i + 1; end; xilinxwrite(6, ctrl1code and $5f); {enable readback} {wait for pc interface board data valid} k := 0; drderror := false; busybit3 := (port[readdr] and $08) shr 3; {initialize bit 3} while (busybit3 <> 1) and (k <= 20000) do begin busybit3 := (port[readdr] and $08) shr 3; inc(k); if (k mod 40) = 0 then delay(1); if k = 20000 then drderror := true; end; if drderror = true then begin badbeep; clrscr; writeln; writeln( **** data retrieval error ****); writeln; writeln( check the following:); writeln; writeln( ddc112 securely in socket); writeln( power supplies at 5v); writeln( cables properly connected); writeln( demo board refreshed); writeln( pc port set correctly); writeln; writeln( ******************************); writeln; writeln( hit enter to continue ); readln; exit; end else begin fscale := $fffff-$1000; {fullscale range = all ones - offset} for d := 1 to 4 do begin ysum[d] := 0; ysumsq[d] := 0; end; writeln(retrieving data...); for n := nt-1 downto 0 do begin for d := 1 to 4 do begin trd := n + nt*(d-1); fnum := 0; portdatard := $6f; {decrement xilinx ram memory address} port[wraddr] := portdatard; port[strbaddr] := 1; port[strbaddr] := 0; port[strbaddr] := 1; port[strbaddr] := 0; {prepare for ram memory address (portdatard := $6f;)} for ird := 1 to 6 do {get 6 nibbles} begin portdatard := portdatard - $10; {msb, msb-1,...,lsb nibble} port[wraddr] := portdatard; port[strbaddr] := 1; port[strbaddr] := 0; {wait for pc interface board data valid} k := 0; busybit3 := (port[readdr] and $08) shr 3; {init bit 3}
10 while (busybit3 <> 1) and (k <= 20000) do begin busybit3 := (port[readdr] and $08) shr 3; inc(k); if (k mod 40) = 0 then delay(1); if k = 20000 then begin drderror := true; n := 0; end; end; nib := ((port[readdr] xor $80) and $f0) shr 4; {xor inverts bit 7 (-busy), and f0 gets rid of 4 lower bits, shift right puts the data bits in lower nibble} if ird = 1 then siderd := ((nib and $4) xor $4) shr 2; {bit3 lo ==> sidea} fnum := fnum shl 4; fnum := fnum or nib; {add nibble to final number} end; if firsttime then begin if siderd = 0 then firsttime := false {first point is correct side} else begin firsttime := false; for count := 1 to ((userddccode-1)*2 + 1) do {read & throw away pts} begin portdatard := $6f; {decrement xilinx ram memory address} port[wraddr] := portdatard; port[strbaddr] := 1; port[strbaddr] := 0; port[strbaddr] := 1; port[strbaddr] := 0; {prepare for ram memory address (portdatard := $6f;)} for ird := 1 to 6 do {get 6 nibbles} begin portdatard := portdatard - $10; {msb, msb-1,...,lsb nibble} port[wraddr] := portdatard; port[strbaddr] := 1; port[strbaddr] := 0; {wait for pc interface board dvalid} k := 0; busybit3 := (port[readdr] and $08) shr 3; {init bit 3} while (busybit3 <> 1) and (k <= 20000) do begin busybit3 := (port[readdr] and $08) shr 3; inc(k); if (k mod 40) = 0 then delay(1); if k = 20000 then begin drderror := true; n := 0; end; end; end; end; fnum := 0; portdatard := $6f; {decrement xilinx ram memory address} port[wraddr] := portdatard; port[strbaddr] := 1; port[strbaddr] := 0; port[strbaddr] := 1; port[strbaddr] := 0; {prepare for ram memory address (portdatard := $6f;)} for ird := 1 to 6 do {get 6 nibbles} begin portdatard := portdatard - $10; {msb, msb-1,...,lsb nibble} port[wraddr] := portdatard; port[strbaddr] := 1; port[strbaddr] := 0; {wait for pc interface board data valid} k := 0; busybit3 := (port[readdr] and $08) shr 3; {init bit 3}
11 while (busybit3 <> 1) and (k <= 20000) do begin busybit3 := (port[readdr] and $08) shr 3; inc(k); if (k mod 40) = 0 then delay(1); if k = 20000 then begin drderror := true; n := 0; end; end; nib := ((port[readdr] xor $80) and $f0) shr 4; {xor inverts bit 7 (-busy), and f0 gets rid of 4 lower bits, shift right puts the data bits in lower nibble} if ird = 1 then siderd := ((nib and $4) xor $4) shr 2; {bit3 lo ==> sidea} fnum := fnum shl 4; fnum := fnum or nib; {add nibble to final number} end; end; end; fnum := (fnum and $000fffff); {set bits 31-21 := 0} fnum := fnum - $1000; {subtract offset} ysum[d] := ysum[d] + fnum; temp := fnum; temp := temp * fnum; ysumsq[d] := ysumsq[d] + temp; end; end; for d := 1 to 4 do begin yave[d] := ysum[d]/(nt*fscale); temp := nt*ysumsq[d]-(ysum[d]*ysum[d]); yrms[d] := sqrt(abs(temp)/(nt*(nt-1)))/fscale; yrms[d] := yrms[d] * 1e6; {convert to ppm} end; end; xilinxwrite(6,ctrl1code or $20); {enable write to ram} end; {*****************************************************************************} procedure retrievedata(var err: boolean); {*****************************************************************************} {call readdata then display results} begin readdata(err); if err = false then begin clrscr; writeln; writeln( # of pts = ,nt, range = ,range, tint = ,tint:8:1, test pkts = ,tpck); writeln; writeln( average rms noise); writeln( 1a: ,yave[1]:11:7, ,yrms[1]:6:2, ppm); writeln( 2a: ,yave[2]:11:7, ,yrms[2]:6:2, ppm); writeln( 1b: ,yave[3]:11:7, ,yrms[3]:6:2, ppm); writeln( 2b: ,yave[4]:11:7, ,yrms[4]:6:2, ppm); end; end; {*****************************************************************************} procedure testmodelinearity; {*****************************************************************************} {measure linearity of the ddc112s test mode} {1st take 1 reading. use results to determine # of steps to fullscale.} {fit data with endpoint line and report max deviation from that line.} var n,i : integer; err : boolean; username : string[8]; filename : string[12]; f1 : text; tpacket : real; steps : word; tdat : array[1..4,0..100] of real; {holds data for lin fit} m,b : real; inlpt, inlmax : real; inl : array[1..4] of real;
12 begin clrscr; if nt < 10 then begin writeln; writeln(*** the number of points / reading is low ***); writeln; writeln( increase the number for better results ); badbeep; getint(# of points,1,10000,nt,err); end; writeln; writeln(enter a file name for test mode linearity data (max 8 characters)); readln(username); writeln; filename := username + .dat; assign(f1,filename); delay(1); {$i-} rewrite(f1); {$i+} if ioresult <> 0 then begin writeln(); writeln( *** file i/o problem, try a new name...); delay(400); badbeep; exit; end; settstpckts(1); {set test pckts = 1 & collect 1st data} writeln( collecting test data 1); readdata(err); if err = false then begin {use 1st data pt to calc # steps required} for n := 1 to 4 do tdat[n,1] := yave[n]; tpacket := (yave[1])*100; {calc packet size} writeln; writeln(*** each test packet is ,tpacket:4:1, % of full scale ***); steps := trunc(1/yave[1]); {calc # of steps for fullscale} if steps > (trunc(tint/5.4)) then begin steps := trunc(tint/5.4); writeln; writeln(***********************************************); writeln(test mode will not be able to reach full scale); writeln(with current tint. increasing tint will allow); writeln(more test packets dumps during the integration.); writeln(***********************************************); badbeep; end; end else exit; for i := 2 to steps do {collect rest of data} begin writeln; writeln( collecting test data ,i, out of ,steps); settstpckts(i); readdata(err); if err = true then exit; for n := 1 to 4 do tdat[n,i] := yave[n]; end; settstpckts(tpck); {restore user test package setting} clrscr; writeln; writeln( linearity results: endpoint fit); writeln( (max deviation from endpoint line)); writeln;
13 for n := 1 to 4 do {fit linearity} begin b := tdat[n,1]; {y = mx + b} m := (tdat[n,steps] - tdat[n,1])/(steps-1); inlmax := 0; for i := 2 to (steps-1) do {inl for i=1 & steps =0 for endpoint fit} begin inlpt := abs(tdat[n,i] - (m*(i-1) + b)); if inlpt > inlmax then inlmax := inlpt; end; inl[n] := 1e6* inlmax ; {convert to ppm} case n of 1: writeln( inl for 1a = ,inl[1]:6:1, ppm); 2: writeln( inl for 2a = ,inl[2]:6:1, ppm); 3: writeln( inl for 1b = ,inl[3]:6:1, ppm); 4: writeln( inl for 2b = ,inl[4]:6:1, ppm); end; end; writeln(f1, burr-brown corporation ); writeln(f1, application bulletin AB-135 ); writeln(f1,ddc112 test mode linearity measurement); writeln(f1); writeln(f1,# of averages/readings = ,nt); writeln(f1,range = ,range); writeln(f1,tint = ,tint:7:1); writeln(f1); writeln(f1,# test); writeln(f1,packets 1a ave 2a ave 1b ave 2b ave); for i := 1 to steps do writeln(f1,i:3, ,tdat[1,i]:11:6, ,tdat[2,i]:11:6, ,tdat[3,i]:11:6, ,tdat[4,i]:11:6); writeln(f1); writeln(f1, endpoint fit); writeln(f1, inl(ppm): ,inl[1]:8:1, inl[2]:12:1, inl[3]:12:1, inl[4]:12:1); close(f1); goodbeep; writeln; writeln( hit enter to continue...); readln; end; {***************************************************************************} {***************************************************************************} {main} {***************************************************************************} {***************************************************************************} var userinput : string[10]; goodbye,done : boolean; err : boolean; choice : word; check : integer; mintint : real; begin range := 5; tint := 500; nt := 500; tpck := 1; pcport := 1; datackcode := 2; sysckcode := 0; dxmitdelaycode := 0; userddccode := 1; ctrl1code := $20; {initially read, internal dclk} ctrl2code := 1; {demo bd conv} pprintport := ptr($40,$08); {default: pc port=1} wraddr := pprintport^; readdr := wraddr + 1; strbaddr := wraddr + 2; port[strbaddr] := 0; {init strobe at 0 (really, 1 out)}
14 xilinxrefresh; clrscr; goodbye := false; while (goodbye <> true) do begin clrscr; writeln; writeln(----------------------------------------- - ); writeln( | burr-brown corporation |); writeln( | application bulletin ab1xx |); writeln( | |); writeln( | ddc112 test mode evaluation program |); writeln( ); writeln; writeln( # points/reading = ,nt); writeln( range = ,range); writeln( tint = ,tint:7:1); writeln( # test packets = ,tpck); writeln; writeln; writeln( =========================== ); writeln( choose one of the following ); writeln( =========================== ); writeln; writeln( 1) refresh demo board); writeln; writeln( 2) set # points averaged/reading); writeln( 3) set range); writeln( 4) set tint); writeln( 5) set # of test mode packets); writeln( 6) set pc port); writeln; writeln( 7) take single reading); writeln( 8) measure linearity of test mode); writeln; writeln( 9) exit program); writeln; readln(userinput); val(userinput,choice,check); if check <> 0 then badbeep else begin if (choice < 0) or (choice > 9) then badbeep else case choice of 1: begin writeln; writeln(refreshing demo board...); xilinxrefresh; end; 2: getint(# of points,1,10000,nt,err); 3: begin getint(range,0,7,range,err); if err = false then setrange(range); end; 4: begin getreal(tint,0,1500000,tint,err); if err = false then settint(tint); end;
15 5: begin getint(test mode packets,0,128,tpck,err); if err = false then begin if tpck > trunc(tint/5.4) then {allow 5.4us per packet} begin writeln; writeln(*****************************************************); writeln( # of test packets is too high for current tint . ); mintint := tpck*5.4; writeln( tint must be > ,mintint:7:1, us for ,tpck, packets.); tpck := trunc(tint/5.4); writeln( setting # of test packets to ,tpck); writeln(*************************************************); writeln; writeln( hit enter to continue...); badbeep; readln; end; settstpckts(tpck); end; end; 6: begin getint(pc port,1,2,pcport,err); setpcport(pcport); end; 7: begin done := false; while done = false do begin retrievedata(err); if err = true then done := true else begin writeln; writeln( enter r to repeat measurement); readln(userinput); if (userinput <> r) and (userinput <> r) then done := true; end; end; end; 8: testmodelinearity; 9: goodbye := true; end; end; end; end.

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