may 2001 advance information copyright ? alliance semiconductor. all rights reserved. ? as7c1026a as7c31026a 5v/3.3v 64k x 16 cmos sram 5/17/01; v.0.9.4 alliance semiconductor p. 1 of 9 features ? as7c1026a (5v version) as7c31026a (3.3v version) industrial and commercial versions organization: 65,536 words 16 bits center power and ground pins for low noise high speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time low power consumption: active - 660 mw (as7c1026a) / max @ 10 ns - 324 mw (as7c31026a) / max @ 10 ns low power consumption: standby - 55 mw (as7c1026a) / max cmos i/o - 36 mw (as7c31026a) / max cmos i/o latest 6t 0.25u cmos technology easy memory expansion with ce , oe inputs ttl-compatible, three-state i/o jedec standard packaging - 44-pin 400 mil soj - 44-pin tsop 2 - 48-ball 6 8 mm csp/mbga esd protection 2000 volts latch-up current 200 ma logic block diagram 64k 16 array oe ce we column decoder row decoder a0 a1 a2 a3 a4 a5 a7 v cc gnd a8 a9 a10 a11 a12 a13 a14 a15 control circuit i/o0?i/o7 i/o8?i/o15 ub lb i/o buffer a6 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 i/o13 i/o12 gnd v cc i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 nc a0 ce i/o0 i/o1 i/o2 i/o3 v cc gnd i/o4 i/o5 i/o6 i/o7 we a15 a14 a13 44-pin soj (400 mil), tsop 2 21 22 a12 nc ub lb i/o15 i/o14 2 a3 3 a2 4 a1 1 a4 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 43 42 41 44 a6 a7 oe a5 as7c1026a as7c31026a selection guide as7c1026a-10 as7c31026a-10 as7c1026a-12 as7c31026a-12 as7c1026a-15 as7c31026a-15 as7c1026a-20 as7c31026a-20 unit maximum address access time 10 12 15 20 ns maximum output enable access time 5678ns maximum operating current as7c1026a 120 110 100 100 ma as7c31026a 90 80 80 80 ma maximum cmos standby current as7c1026a 10 10 10 15 ma as7c31026a 10 10 10 15 ma 00000 48-csp/mini ball-grid-array package 123456 alb oe a 0 a 1 a 2 nc bi/o8 ub a3 a4 ce i/o0 ci/o9 i/o10 a5 a6 i/o1 i/o2 dv ss i/o11 nc a7 i/o3 v dd ev dd i/o12 nc nc i/o4 v ss fi/o14 i/o13 a14 a15 i/o5 i/o6 gi/o15 nc a12 a13 we i/o7 hnc a8 a9a10a11nc pin arrangement
? as7c1026a as7c31026a 5/17/01; v.0.9.4 alliance semiconductor p. 2 of 9 functional description the as7c1026a and as7c31026a are high-performance cmos 1,048,576-bit static random access memory (sram) devices organized as 65,536 words 16 bits. they are designed for memory applications where fast data access, low power, and simple interfacing are desired. equal address access and cycle times (t aa , t rc , t wc ) of 10/12/15/20 ns with output enable access times (t oe ) of 5, 6, 7, 8 ns are ideal for high-performance applications. when ce is high the devices enter standby mode. the as7c1026a is guaranteed not to exceed 55 mw power consumption in cmos standby mode. a write cycle is accomplished by asserting write enable (we ) and chip enable (ce ). data on the input pins i/o0?i/o15 is written on the rising edge of we (write cycle 1) or ce (write cycle 2). to avoid bus contention, external devices should drive i/o pins only after outputs have been disabled with output enable (oe ) or write enable (we ). a read cycle is accomplished by asserting output enable (oe ) and chip enable (ce ), with write enable (we ) high. the chips drive i/o pins with the data word referenced by the input address. when either chip enable or output enable is inactive, or write enable is ac tive, output drivers stay in high-impedance mode. the devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be w ritten and read. lb controls the lower bits, i/o0?i/o7, and ub controls the higher bits, i/o8?i/o15. all chip inputs and outputs are ttl-compatible, and operation is from a single 5v supply (as7c1026a) or 3.3v supply (as7c31026a ). the device is packaged in common industry standard packages. chip scale bga packaging, easy to use in manufacturing, provides the s mallest possible footprint. this 48-ball jedec-registered package has a ball pitch of 0.75 mm and external dimensions of 8 mm 6 mm. absolute maximum ratings note: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a str ess rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificat ion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table key: h = high, l = low, x = don?t care. parameter symbol min max unit vo l t ag e o n v cc relative to gnd as7c1026a v t1 ?0.50 +7.0 v as7c31026a v t1 ?0.50 +5.0 v voltage on any pin relative to gnd both v t2 ?0.50 v cc +0.50 v power dissipation both p d ?1.0w storage temperature (plastic) both t stg ?65 +150 c ambient temperature with vcc applied both t bias ?55 +125 c dc current into outputs (low) both i out ?20ma ce we oe lb ub i/o0?i/o7 i/o8?i/o15 mode h x x x x high z high z standby (i sb ), i sbi ) lhl lhd out high z read i/o0?i/o7 (i cc ) lhlhlhigh zd out read i/o8?i/o15 (i cc) lhl l ld out d out read i/o0?i/o15 (i cc ) llxll d in d in write i/o0?i/o15 (i cc ) llxlhd in high z write i/o0?i/o7 (i cc ) llxhlhigh zd in write i/o8?i/o15 (i cc ) l l h x h x x h x h high z high z output disable (i cc )
? as7c1026a as7c31026a 5/17/01; v.0.9.4 alliance semiconductor p. 3 of 9 recommended operating conditions ? v il min. = ?3.0v for pulse width less than t rc /2. dc operating characteristics (over the operating range) 1 capacitance (f = 1mhz, t a = 25 c, v cc = nominal) 2 parameter device symbol min nominal max unit supply voltage as7c1026a v cc 4.5 5.0 5.5 v as7c31026a v cc 3.0 3.3 3.6 v input voltage as7c1026a v ih 2.2 ? v cc + 0.5 v as7c31026a v ih 2.0 ? v cc + 0.5 v both v il ? ?0.5 ? 0.8 v ambient operating temperature commercial t a 0? 70 o c industrial t a ?40 ? 85 o c parameter sym test conditions device -10 -12 -15 -20 unit min max min max min max min max input leakage current | i li | v cc = max v in = gnd to v cc both ? 1 ? 1 ? 1 ? 1 a output leakage current | i lo | v cc = max ce = v ih , v out = gnd to v cc both ? 1 ? 1 ? 1 ? 1 a operating power supply current i cc v cc = max, ce v il outputs open, f = f max = 1/t rc as7c1026a ? 120 ? 110 ? 100 ? 100 ma as7c31026a ? 90 ? 80 ? 80 ? 80 ma standby power supply current i sb v cc = max, ce v il , outputs open, f = f max = 1/t rc as7c1026a ? 30 ? 25 ? 20 ? 20 ma as7c31026a ? 30 ? 25 ? 20 ? 20 i sb1 v cc = max, ce v cc ?0.2v, v in gnd + 0.2v or v in v cc ?0.2v, f = 0 as7c1026a ? 10 ? 10 ? 10 ? 15 ma as7c31026a ? 10 ? 10 ? 10 ? 15 output voltage v ol i ol = 8 ma, v cc = min both ? 0.4 ? 0.4 ? 0.4 ? 0.4 v v oh i oh = ?4 ma, v cc = min 2.4 ? 2.4 ? 2.4 ? 2.4 ? v parameter symbol signals test conditions max unit input capacitance c in a, ce , we , oe , lb , ub v in = 0v 5 pf i/o capacitance c i/o i/o v in = v out = 0v 7 pf
? as7c1026a as7c31026a 5/17/01; v.0.9.4 alliance semiconductor p. 4 of 9 read cycle (over the operating range) 3,9 key to switching waveforms read waveform 1 (address controlled) 3,6,7,9 read waveform 2 (oe , ce , ub , lb controlled) 3,6,8,9 parameter symbol -10 -12 -15 -20 unit notes minmaxminmaxminmaxminmax read cycle time t rc 10 ? 12 ? 15 ? 20 ? ns address access time t aa ?10?12?15?20ns 3 chip enable (ce ) access time t ace ?10?12?15?20ns 3 output enable (oe ) access time t oe ?5?6?7?8ns output hold from address change t oh 2?3?3?3?ns 5 ce low to output in low z t clz 0?0?0?0?ns4, 5 ce high to output in high z t chz ?3?3?4?5ns4, 5 oe low to output in low z t olz 0?0?0?0?ns4, 5 byte select access time t ba ?5?6?7?8ns byte select low to low z t blz 0?0?0?0?ns4, 5 byte select high to high z t bhz ?5?6?6?8ns4, 5 oe high to output in high z t ohz ?3?3?4?5ns4, 5 power up time t pu 0?0?0?0?ns4, 5 power down time t pd ?10?12?15?20ns4, 5 undefined output/don?t care falling input rising input t oh t aa t rc t oh data out address data valid previous data valid data valid t rc t aa t blz t ba t oe t olz t oh t ohz t hz t bhz t ace t lz address oe ce lb , ub data in
? as7c1026a as7c31026a 5/17/01; v.0.9.4 alliance semiconductor p. 5 of 9 write cycle (over the operating range) 11 write waveform 1 (we controlled) 10,11 write waveform 2 (ce controlled) 10,11 parameter symbol -10 -12 -15 -20 unit notes min max min max min max min max write cycle time t wc 10 ? 12 ? 15 ? 20 ? ns chip enable ( ce ) to write end t cw 8 ? 10 ? 12 ? 12 ? ns address setup to write end t aw 8 ? 9 ? 10 ? 12 ? ns address setup time t as 0?0?0 ? 0? ns write pulse width t wp 7?8?9?12? ns address hold from end of write t ah 0?0?0 ? 0? ns data valid to write end t dw 5?6?8?10? ns data hold time t dh 0?0?0 ? 0? ns 5 write enable to output in high z t wz ? 6 ? 6 ? 6 ? 8 ns 4, 5 output active from write end t ow 1?1?1 ? 2? ns 4, 5 byte select low to end of write t bw 8 ? 10 ? 12 ? 12 ? ns address ce lb , ub we data in data out t wc t cw t bw t aw t as t wp t dw t dh t ow t wz t wr data undefined high z data valid address ce lb , ub we data in t wc t cw t bw t wp t dw t dh t ow t wz t wr data out data undefined high z high z t as t aw data valid t clz
as7c1026a as7c31026a ? 5/17/01; v.0.9.4 alliance semiconductor p. 6 of 9 ac test conditions notes 1during v cc power-up, a pull-up resistor to v cc on ce is required to meet i sb specification. 2 this parameter is sampled, but not 100% tested. 3 for test conditions, see ac test conditions , figures a, b, and c. 4 these parameters are specified with c l = 5pf, as in figures b or c. transition is measured 500 mv from steady-state voltage. 5 this parameter is guaranteed, but not tested. 6we is high for read cycle. 7ce and oe are low for read cycle. 8 address valid prior to or coincident with ce transition low. 9 all read cycle timings are referenced from the last valid address to the first transitioning address. 10 ce or we must be high during address transitions. either ce or we asserting high terminates a write cycle. 11 all write cycle timings are referenced from the last valid address to the first transitioning address. 12 not applicable. 13 c=30pf, except all high z and low z parameters where c=5pf. 255w c(14) 320w gnd +3.3v figure c: 3.3v output load 168w thevenin equivalent: d out +1.728v (5v and 3.3v) 255w c(14) 480w gnd +5v figure b: 5v output load 10% 90% 10% 90% gnd +3.0v figure a: input pulse 2 ns d out d out ? output load: see figure b or figure c. ? input pulse level: gnd to 3.0v. see figure a. ? input rise and fall times: 2 ns. see figure a. ? input and output timing reference levels: 1.5v.
? as7c1026a as7c31026a 5/17/01; v.0.9.4 alliance semiconductor p. 7 of 9 package dimensions 44-pin tsop 2 min (mm) max (mm) a1.2 a1 0.05 a2 0.95 1.05 b 0.30 0.45 c 0.127 (typical) d 18.28 18.54 e 10.03 10.29 he 11.56 11.96 e 0.80 (typical) l0.400.60 d he 1234567891011121314 44 43 42 41 40 39 38 37 36 35 34 33 32 31 15 16 30 29 17 18 19 20 28 27 26 25 c l a1 a2 e 44-pin tsop 2 0?5 21 24 22 23 e a b seating plane 44-pin soj 44-pin soj 400 mil min (in) max (in) a 0.128 0.148 a 1 0.025 ? a 2 0.105 1.115 b 0.026 0.032 b 0.015 0.020 c 0.007 0.013 d 1.120 1.130 e 0.370 nom e 1 0.395 0.405 e 2 0.435 0.445 e 0.050 nom e pin 1 a 1 b b a a 2 e 2 e 1 e 2 d c
as7c1026a as7c31026a ? 5/17/01; v.0.9.4 alliance semiconductor p. 8 of 9 notes 1 bump counts: 48 (8 row x 6 column). 2 pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3 units: millimeters. 4 all tolerance are +/- 0.050 unless otherwise specified. 5 typ: typical. 6 y is coplanarity: 0.08 (max). (in mils) minimum typical maximum a?0.75? b 5.90 8.00 8.10 b1 ? 3.75 ? c 7.90 8.00 8.10 c1 ? 5.25 ? d?0.35? e??1.20 e1 ? 0.68 ? e2 0.22 0.25 0.27 y??0.08 48-ball fbga bottom view 6 543 2 1 ball a1 c1 a b c d f g h j a b1 side view to p vi ew ball #a1 index c sram die elastomer b detail view a y die 0.3/t p e2 e die d e1 e2 e *pin 1 indicator will show as engraved circle and/or inc. trade mark *
? as7c1026a as7c31026a ? copyright a lliance semic onductor corporation. all rights reserved. our three-point logo, our name and inte lliwatt are trademarks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. a lliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsib ility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/or estimat es at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant chan ges to these specifications are possible. the information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liability arising out of the application or use of any pr oduct described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchan tability, or infringement of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available from alliance). all sales of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from a lliance does not c onvey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its pr oducts for use as cr itical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in such life-s upporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify a lliance against all claims arising from such use. 5/17/01; v.0.9.4 alliance semiconductor p. 9 of 9 ordering codes part numbering system package \ access time volt/temp 10 ns 12 ns 15 ns 20 ns plastic soj, 400 mil 5v commercial as7c1026a-10jc as7c1026a-12jc as7c1026a-15jc as7c1026a-20jc 5v industrial as7c1026a-10ji as7c1026a-12ji as7c1026a-15ji as7c1026a-20ji 3.3v commercial as7c31026a-10jc as7c31026a-12jc as7c31026a-15jc as7c31026a-20jc tsop 2, 10.2 x 18.4 mm 5v commercial as7c1026a-10tc as7c1026a-12tc as7c1026a-15tc as7c1026a-20tc 3.3v commercial as7c31026a-10tc AS7C31026A-12TC as7c31026a-15tc as7c31026a-20tc 3.3v industrial as7c31026a-10ti as7c31026a-12ti as7c31026a-15ti as7c31026a-20ti csp/bga, 6 x 8 mm 5v commercial as7c1026a-10bc as7c1026a-12bc as7c1026a-15bc as7c1026a-20bc 3.3v commercial as7c31026a-10bc as7c31026a-12bc as7c31026a-15bc as7c31026a-20bc 3.3v industrial as7c31026a-10bi as7c31026a-12bi as7c31026a-15bi as7c31026a-20bi as7c x 1026 ?xx x c sram prefix vo l t ag e : blank=5v cmos 3=3.3v cmos device numbe r access time package: j=soj 400 mil t=tsop 2, 10.2 x 18.4 mm b=csp/bga, 6 x 8 mm temperature range: c= commercial: 0 c to 70 c i= industrial: -40 c to 85 c
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