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16-bit, dual voltage output digital-to-analog converter description the dac7632 is a 16-bit, dual channel, voltage output, digital-to-analog converter (dac) which provides 15-bit monotonic performance over the specified temperature range. the device accepts 24-bit serial input data, has double- buffered dac input logic (allowing simultaneous update of both dacs), and provides a serial data output for daisy- chaining multiple devices. a programmable asynchronous reset clears all registers to a mid-scale code of 8000 h or to a zero-scale code of 0000 h . the dac7632 can operate from a single +5v supply or from +5v and ?v supplies, providing an output range of 0v to +2.5v or ?.5v to +2.5v, respec- tively. low power and small size per dac make the dac7632 ideal for industrial process control, data acquisition sys- tems, and closed-loop servo-control. the dac7632 is avail- able in an lqfp-32 package and specified over a ?0 c to +85 c temperature range. features low power: 4mw unipolar or bipolar operation settling time: 10 s to 0.003% fsr 15-bit linearity and monotonicity: C40 c to +85 c programmable reset to mid-scale or zero-scale double-buffered data inputs applications process control closed-loop servo-control motor control data acquisition systems dac-per-pin programmers dac7632 sbas234 ?february 2002 www.ti.com copyright ?2002, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. dac a dac register a input register a shift register dac b dac register b input register b v ref l v ref h v ref h sense v ref l sense v out b v out a v out b sense sdi sdo control logic cs clk rst rstsel ldac load agnd dgnd v out a sense v cc v ss v dd dac7632 d a c763 2 production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
dac7632 2 sbas234 www.ti.com absolute maximum ratings (1) v cc and v dd to v ss .............................................................. 0.3v to 11v v cc and v dd to gnd ........................................................... 0.3v to 5.5v v ref l to v ss ............................................................. 0.3v to (v cc v ss ) v cc to v ref h ............................................................ 0.3v to (v cc v ss ) v ref h to v ref l ......................................................... 0.3v to (v cc v ss ) digital input voltage to gnd ................................... 0.3v to v dd + 0.3v digital output voltage to gnd ................................. 0.3v to v dd + 0.3v maximum junction temperature ................................................... +150 c operating temperature range ........................................ 40 c to +85 c storage temperature range ......................................... 65 c to +125 c lead temperature (soldering, 10s) ............................................... +300 c note: (1) stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum conditions for extended periods may affect device reliability. electrostatic discharge sensitivity this integrated circuit can be damaged by esd. texas instru- ments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. specified package temperature package ordering transport product monotonicity package-lead designator (1) range marking number media, quantity dac7632vf 14 bits lqfp-32 vf 40 c to +85 c dac7632 dac7632vft tape and reel, 250 " """"" dac7632vfr tape and reel, 1000 dac7632vfb 15 bits lqfp-32 vf 40 c to +85 c dac7632b dac7632vfb t tape and reel, 250 " """"" dac7632vfb r tape and reel, 1000 note: (1) for the most current specifications and package information, refer to our web site at www.ti.com. package/ordering information
dac7632 3 sbas234 www.ti.com dac7632vf dac7632vfb parameter conditions min typ max min typ max units accuracy linearity error 3 4 2 3 lsb linearity match 4 2 lsb differential linearity error 2 3 1 2 lsb monotonicity, t min to t max 14 15 bits bipolar zero error 1 3 ?? mv bipolar zero error drift 5 10 ?? ppm/ c full-scale error 1 3 ?? mv full-scale error drift 5 10 ?? ppm/ c bipolar zero matching channel-to-channel matching 1 3 ?? mv full-scale matching channel-to-channel matching 1 3 ?? mv power-supply rejection ratio (psrr) at full scale 10 100 ?? ppm/v analog output voltage output r l = 10k ? v ref lv ref h ?? v output current 1.25 +1.25 ?? ma maximum load capacitance no oscillation 500 ? pf short-circuit current 10, +30 ? ma short-circuit duration gnd or v cc or v ss indefinite ? reference input ref high input voltage range v ref l + 1.25 +2.5 ?? v ref low input voltage range 2.5 v ref h 1.25 ?? v ref high input current 500 ? a ref low input current 500 ? a dynamic performance settling time to 0.003%, 5v output step 8 10 ?? s channel-to-channel crosstalk 0.5 ? lsb digital feedthrough 2 ? nv-s output noise voltage f = 10khz 60 ? nv/ hz dac glitch 7fff h to 8000 h or 8000 h to 7fff h 40 ? nv-s digital input v ih 0.7 v dd ? v v il 0.3 v dd ? v i ih 10 ? a i il 10 ? a digital output v oh i oh = 0.8ma 3.6 4.5 ?? v v ol i ol = 1.6ma 0.3 0.4 ?? v power supply v dd +4.75 +5.0 +5.25 ??? v v cc +4.75 +5.0 +5.25 ??? v v ss 5.25 5.0 4.75 ??? v i cc 0.7 1.1 ?? ma i dd 50 ? a i ss 1.2 0.8 ?? ma power 7.5 11.5 ?? mw temperature range specified performance 40 +85 ?? c ? specifications same as dac7632vf. electrical characteristics (dual supply) at t a = t min to t max , v dd = v cc = +5v, v ss = 5v, v ref h = +2.5v, and v ref l = 2.5v, unless otherwise noted.
dac7632 4 sbas234 www.ti.com dac7632vf dac7632vfb parameter conditions min typ max min typ max units accuracy linearity error (1) 3 4 2 3lsb linearity match 4 2lsb differential linearity error 2 3 1 2lsb monotonicity, t min to t max 14 15 bits zero scale error 1 3 ?? mv zero scale error drift 5 10 ?? ppm/ c full-scale error 1 3 ?? mv full-scale error drift 5 10 ?? ppm/ c zero scale matching channel-to-channel matching 1 3 ?? mv full-scale matching channel-to-channel matching 1 3 ?? mv power supply rejection ratio (psrr) at full scale 10 100 ?? ppm/v analog output voltage output r l = 10k ? 0v ref h ?? v output current 1.25 +1.25 ?? ma maximum load capacitance no oscillation 500 ? pf short-circuit current 10, +30 ? ma short-circuit duration gnd or v cc indefinite ? reference input ref high input voltage range v ref l + 1.25 +2.5 ?? v ref low input voltage range 2.5 v ref h 1.25 ?? v ref high input current 250 ? a ref low input current 250 ? a dynamic performance settling time to 0.003%, 5v output step 8 10 ?? s channel-to-channel crosstalk 0.5 ? lsb digital feedthrough 2 ? nv-s output noise voltage, f = 10khz 60 ? nv/ hz dac glitch 7fff h to 8000 h or 8000 h to 7fff h 40 ? nv-s digital input v ih 0.7 v dd ? v v il 0.3 v dd ? v i ih 10 ? a i il 10 ? a digital output v oh i oh = 0.8ma 3.6 4.5 ?? v v ol i ol = 1.6ma 0.3 0.4 ?? v power supply v dd +4.75 +5.0 +5.25 ??? v v cc +4.75 +5.0 +5.25 ??? v v ss 000 ??? v i cc 0.5 0.9 ?? ma i dd 50 ? a power 2.5 4.5 ?? mw temperature range specified performance 40 +85 ?? c ? specifications same as dac7632vf. note: (1) if v ss = 0v, the specification applies to code 0040 h and above due to possible negative zero-scale error. specifications (dual supply) at t a = t min to t max , v dd = v cc = +5v, v ss = 0v, v ref h = +2.5v, and v ref l = 0v, unless otherwise noted.
dac7632 5 sbas234 www.ti.com pin name description 1v cc analog +5v power supply 2, 3 agnd analog ground 4 nc no connection 5, 6 dgnd digital ground 7v dd digital +5v power supply 8 sdo serial data output 9-16 nc no connection 17 clk data clock input 18 sdi serial data input 19 cs chip select, active low 20 rstsel reset select. determines the action of rst. if high, a rst common will set the dac registers to mid-scale code (8000 h ). if low, a rst command will set the dac registers to zero-scale code (0000 h ). 21 rst reset, rising edge triggered. depending on the state of rstsel, the dac registers are set to either mid-scale code or zero-scale code. pin descriptions pin name description 22 ldac dac register load control, rising edge triggered 23 load dac input register load control, active low 24 v ss analog 5v power supply (or 0v for single supply) 25 v out b dac b output voltage 26 v out b sense dac b output amplifier inverting input. used to close the feedback loop at the load. 27 v ref h sense dac a and b reference high sense input 28 v ref h dac a and b reference high input 29 v ref l dac a and b reference low input 30 v ref l sense dac a and b reference low sense input 31 v ref a sense dac a output amplifier inverting input. used to close the feedback loop at the load. 32 v out a dac a output voltage top view ssop pin configuration v cc agnd agnd nc dgnd dgnd v dd sdo v ss load ldac rst rstsel cs sdi clk 1 2 3 4 5 6 7 8 nc = no connection 24 23 22 21 20 19 18 17 dac7632 v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 nc nc nc nc nc nc nc nc 9 10 11 12 13 14 15 16
dac7632 6 sbas234 www.ti.com C 40 c typical characteristics: v ss = 0v at t a = +25 c, v dd = v cc = +5v, v ss = 0v, v refh = +2.5v, v refl = 0v, representative unit, unless otherwise specified. +25 c +85 c 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, C 40 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, C 40 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h
dac7632 7 sbas234 www.ti.com typical characteristics: v ss = 0v (cont.) at t a = +25 c, v dd = v cc = +5v, v ss = 0v, v refh = +2.5v, v refl = 0v, representative unit, unless otherwise specified. 0.30 0.25 0.20 0.15 0.10 0.05 0.00 v ref h current vs code (all dacs sent to indicated code) v ref current (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 0.00 0.05 0.10 0.15 0.20 0.25 0.30 v ref l current vs code (all dacs sent to indicated code) v ref current (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 1 0.8 0.6 0.4 0.2 0 analog supply current vs temperature i cc (ma) temperature ( c) 40 15 10 35 60 85 data = ffff h (all dacs) no load 1.0 0.8 0.6 0.4 0.2 0.0 digital input code 0000 h 2000 h 4000 h 6000 h 8000 h a000 h c000 h e000 h ffff h analog supply current vs digital input code i cc (ma) all dacs no load dac b dac a 3 2 1 0 1 2 3 temperature ( c) 40 15 85 10 35 60 zero-scale error vs temperature zero-scale error (mv) code (0040 h ) full-scale error vs temperature full-scale error (mv) dac b dac a 3 2 1 0 1 2 3 temperature ( c) 40 15 85 10 35 60 code (ffff h )
dac7632 8 sbas234 www.ti.com broadband noise time (10 s/div) noise voltage (50 v/div) bw = 10khz code = 8000 h typical characteristics: v ss = 0v (cont.) at t a = +25 c, v dd = v cc = +5v, v ss = 0v, v refh = +2.5v, v refl = 0v, representative unit, unless otherwise specified. 1000 100 10 frequency (hz) 10 100 1000 10000 100000 1000000 output noise voltage vs frequency noise (nv/ hz) time (1 s/div) output voltage vs mid-scale glitch performance output voltage (20mv/div) +5v ldac 0 7fff h to 8000 h time (1 s/div) output voltage vs mid-scale glitch performance output voltage (20mv/div) +5v ldac 0 8000 h to 7fff h +5v ldac 0 time (2 s/div) output voltage vs settling time (0v to +2.5v) output voltage large-signal settling time: 1v/div small-signal settling time: 500 v/div time (2 s/div) output voltage vs settling time (+2.5v to 2mv) output voltage +5v ldac 0 large-signal settling time: 1v/div small-signal settling time: 500 v/div
dac7632 9 sbas234 www.ti.com typical characteristics: v ss = 0v (cont.) at t a = +25 c, v dd = v cc = +5v, v ss = 0v, v refh = +2.5v, v refl = 0v, representative unit, unless otherwise specified. v ss = C 5v at t a = +25 c, v dd = v cc = +5v, v ss = 5v, v refh = +2.5v, v refl = 2.5v, representative unit, unless otherwise specified. +85 c +25 c 0.50 0.40 0.30 0.20 0.10 0.00 logic input level for digital inputs (v) 0 1 23 4 5 logic supply current vs logic input level for digital inputs logic supply current (ma) typical of one digital input 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 5 4 3 2 1 0 r load (k ? ) 0.01 0.1 1 10 100 v out vs r load v out (v) source sink 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, +85 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h
dac7632 10 sbas234 www.ti.com C 40 c typical characteristics: v ss = C 5v (cont.) at t a = +25 c, v dd = v cc = +5v, v ss = 5v, v refh = +2.5v, v refl = 2.5v, representative unit, unless otherwise specified. 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, C 40 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac b, C 40 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 0.0 v ref h current vs code (all dacs sent to indicated code) v ref current (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 0.0 0.1 0.2 0.3 0.4 0.5 0.6 v ref l current vs code (all dacs sent to indicated code) v ref current (ma) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h bipolar zero error vs temperature bipolar zero error (mv) dac b dac a 3 2 1 0 1 2 3 temperature ( c) 40 15 85 10 35 60 code (8000 h ) positive full-scale error vs temperature positive full-scale error (mv) dac b dac a 3 2 1 0 1 2 3 temperature ( c) 40 15 85 10 35 60 code (ffff h )
dac7632 11 sbas234 www.ti.com typical characteristics: v ss = C 5v (cont.) at t a = +25 c, v dd = v cc = +5v, v ss = 5v, v refh = +2.5v, v refl = 2.5v, representative unit, unless otherwise specified. negative full-scale error vs temperature negative full-scale error (mv) dac a dac b 3 2 1 0 1 2 3 temperature ( c) 40 15 85 10 35 60 code (0000 h ) 5 4 3 2 1 0 1 2 3 4 5 r load (k ? ) 0.01 0.1 1 10 100 v out vs r load v out (v) source sink time (2 s/div) output voltage vs settling time ( 2.5v to +2.5v) output voltage +5v ldac 0 large-signal settling time: 2v/div small-signal settling time: 500 v/div time (2 s/div) output voltage vs settling time (+2.5v to 2.5v) output voltage +5v ldac 0 large-signal settling time: 2v/div small-signal settling time: 500 v/div 1.00 0.75 0.50 0.25 0.00 0.25 0.50 0.75 1.00 analog supply current vs digital input code analog supply current (ma) 0000 h 2000 h 4000 h i cc i ss 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h no load 1 0.5 0 0.5 1 1.5 analog supply current vs temperature analog supply current (ma) i ss i cc data = ffff h (all dacs) no load temperature ( c) 40 15 10 35 60 85
dac7632 12 sbas234 www.ti.com figure 1. dac7632 architecture. r 2r 2r 2r 2r 2r 2r 2r 2r 2r v ref h v out v out sense v ref h sense v ref l v ref l sense r f typical characteristics: v ss = C 5v (cont.) at t a = +25 c, v dd = v cc = +5v, v ss = 5v, v refh = +2.5v, v refl = 2.5v, representative unit, unless otherwise specified. time (1 s/div) output voltage vs mid-scale glitch performance output voltage (50mv/div) +5v ldac 0 7fff h to 8000 h time (1 s/div) output voltage vs mid-scale glitch performance output voltage (50mv/div) +5v ldac 0 8000 h to 7fff h theory of operation the dac7632 is a dual channel, voltage output, 16-bit dac. the architecture is an r-2r ladder configuration with the three msb s segmented, followed by an operational amplifier that serves as a buffer. each dac has its own r-2r ladder network, segmented msbs, and output op amp, as shown in figure 1. the minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references v ref l and v ref h, respectively. the digital input is a 24-bit serial word that contains an address bit for selecting one of two dacs, a quick load bit, six unused bits, and the 16-bit dac code (msb first). the converters can be powered from either a single +5v supply or a dual 5v supply. the device offers a reset function which immediately sets all dac output voltages, dac regis- ters and input registers to mid-scale (code 8000 h ) or to zero- scale (code 0000 h ), depending on the state of rstsel. see figures 2 and 3 for the basic configurations of the dac7632.
dac7632 13 sbas234 www.ti.com figure 2. basic single-supply operation of the dac7632. v cc agnd agnd nc dgnd dgnd v dd sdo v ss load ldac rst rstsel cs sdi clk 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 dac7632 9 10 11 12 13 14 15 16 nc nc = no connection nc nc nc nc nc nc nc clock 32 0.1 f 31 30 29 28 +2.5v 27 26 25 v outa v outa sense v refl sense v refl v refh v refh sense v outb sense v outb serial data in chip select reset input and dac registers load dac registers load input register(s) 0v to +2.5v 0v to +2.5v +5v 1 f 0.1 f +5v 1 f figure 3. basic dual-supply operation of the dac7632. 24 23 22 21 20 19 18 17 0.1 f 1 f 5v +5v v cc agnd agnd nc dgnd dgnd v dd sdo v ss load ldac rst rstsel cs sdi clk 1 2 3 4 5 6 7 8 dac7632 9 10 11 12 13 14 15 16 nc nc = no connection. nc nc nc nc nc nc nc clock 32 0.1 f 31 30 29 28 +2.5v 27 26 25 v outa v outa sense v refl sense v refl v refh v refh sense v outb sense v outb serial data in chip select reset input and dac registers load dac registers load input register(s) 2.5v to +2.5v 2.5v 2.5v to +2.5v +5v 1 f 0.1 f +5v 1 f
dac7632 14 sbas234 www.ti.com figure 5. dual supply configuration-buffered references, used for dual-supply performance. v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 1000pf v out v out 100 ? 100 ? +2.5v +v 2.5v v v +v opa2234 2200pf 1000pf 2200pf v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 r w2 r w1 +2.5v +v v out r w1 r w2 v out figure 4. analog output closed-loop configuration r w represents wiring resistances. analog outputs when v ss = 5v (dual-supply operation), the output amplifier can swing to within 2.25v of the supply rails over the 40 c to +85 c temperature range. when v ss = 0v (single-supply operation), and with r load also connected to ground, the output can swing to ground. care must also be taken when measuring the zero-scale error when v ss = 0v. since the output cannot swing below ground, the output voltage may not change for the first few digital input codes (0000 h , 0001 h , 0002 h , etc.) if the output amplifier has a negative offset. at the negative limit of 2mv, the first specified output starts at code 0040 h . due to the high accuracy of these dacs, system design problems such as grounding and contact resistance become very important. a 16-bit converter with a 2.5v full-scale range has a 1lsb value of 38 v. with a load current of 1ma, series wiring and connector resistance of only 40m ? (r w2 ) will cause a voltage drop of 40 v, as shown in figure 4. to understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copper-clad printed circuit board is 1/2m ? per square. for a 1ma load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30 v. the dac7632 offers a force and sense output configuration for the high open-loop gain output amplifier. this feature allows the loop around the output amplifier to be closed at the load, as shown in figure 4, thus ensuring an accurate output voltage. reference inputs the reference inputs, v ref l and v ref h, can be any voltage between v ss + 2.5v and v cc 2.5v, provided that v ref h is at least 1.25v greater than v ref l. the minimum output of each dac is equal to v ref l plus a small offset voltage (essentially, the offset of the output op amp). the maximum output is equal to v ref h plus a similar offset voltage. note that v ss (the negative power supply) must either be connected to ground or must be in the range of 4.75v to 5.25v. the voltage on v ss sets several bias points within the converter. if v ss is not in one of these two configurations, the bias values may be in error and proper operation of the device may be affected. the current into the v ref h input and out of v ref l depends on the dac output voltages, and can vary from a few microamps to approximately 0.5ma. the reference input appears as a varying load to the reference supply. if the reference applied can sink or source the required current, a reference buffer is not required. the dac7632 features reference drive and sense connections such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. figures 5 through 13 show different reference configurations and the effect on the integral linearity and differential linearity, for each case.
dac7632 15 sbas234 www.ti.com figure 6. single-supply buffered reference with a reference low of 50mv. v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 1000pf v out v out 100 ? +2.5v 2k ? 98k ? +0.050v +v +v opa2350 2200pf 1000pf 2200pf 100 ? figure 9. single-supply buffered reference with v ref l = +1.25v and v ref h = +2.5v. figure 7. integral linearity and differential linearity error characteristic curves for figure 6. figure 8. integral linearity and differential linearity error characteristic curves for figure 9. v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 1000pf v out v out 100 ? +v opa2350 2200pf 1000pf 2200pf +2.5v +v +v +1.25v 100 ? 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h
dac7632 16 sbas234 www.ti.com figure 11. linearity and differential linearity error charac- teristic curves for figure 10. figure 12. low-cost single-supply configuration. figure 13. linearity and differential linearity error charac- teristic curves for figure 12. v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 v out v out +2.5v +v 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 le (lsb) dle (lsb) linearity error and differential linearity error vs code (dac a, +25 c) 0000 h 2000 h 4000 h 6000 h 8000 h digital input code a000 h c000 h e000 h ffff h figure 10. single-supply buffered v ref h. v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 v out v out +v opa2350 +2.5v +v 1000pf 100 ? 2200pf digital interface see table i for the basic control logic for the dac7632. the interface consists of a serial data clock (clk) input, serial data input (sdi), input register load control signal ( load ), and dac register load control signal (ldac). in addition, a chip select ( cs ) input is available to enable serial communi- cation when there are multiple serial devices attached to a single serial bus. an asynchronous reset (rst) input (rising edge triggered) is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, de- pending on the status of the reset select (rstsel) signal. the dac code, quick load control, and address are provided via a 24-bit serial interface (see figure 15). the first bit (dacsel) selects the input register that will be updated when load goes low. the third bit is a quick load bit such that if high, the code in the shift register is loaded into both input registers when the load signal goes low. if the quick load bit is low when an active load signal is issued, the content of the shift register is loaded only to the input register that is addressed by dacsel. the quick load bit is followed by five unused bits. the last 16 bits (msb first) make up the dac code.
dac7632 17 sbas234 www.ti.com input dac dacsel cs rst rstsel ldac load register register mode dac 0 l h x x l write hold write input a 1 l h x x l write hold write input b xhhx h hold write update all x h h x h h hold hold hold all xx l x x reset to 0000 h reset to 0000 h reset to zero-scale all xx h x x reset to 8000 h reset to 8000 h reset to mid-scale all table i. dac7632 logic truth table. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 dacsel x x x x x x d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 quick load serial data input cs (1) clk (1) load rst serial shift register h (2) x (3) h h no change l (4) l h h no change l (5) h h advanced one bit l h h advanced one bit h (6) xl (7) h no change h (6) xh (8) no change notes: (1) cs and clk are interchangeable. (2) h = logic high. (3) x = don t care. (4) l = logic low. (5) = positive logic transition. (6) a high value is suggested in order to avoid a false clock from advancing the shift register and changing the shift register. (7) if data is clocked into the serial register while load is low, the input registers will change as data flows through the shift register. this will corrupt the data in each dac register that has been erroneously selected. (8) rising edge of rst causes no change in the contents of the serial shift register. table ii. serial shift register truth table. figure 14. daisy-chaining multiple dac7632s. dac7632 clk sdi cs sck din cs sdo dac7632 clk sdi cs sdo dac7632 clk sdi cs sdo to other serial devices data presented to sdi is clocked into the shift register on each rising clk edge. this data is latched into the input register(s) via a logic-low level on load . the data is directed from the shift register to the desired input register(s) specified by data bits 21 and 23. the internal dac registers are edge triggered and not level triggered. when the ldac signal is transitioned from low to high, the digital word currently in the input registers are latched. this double-buffered architec- ture has been designed so that new data can be entered for each dac without disturbing the analog outputs. when the new data has been entered into the device, both dac outputs can be updated simultaneously by the rising edge of ldac. additionally, it allows the input registers to be written to at any point, then the dac output voltages can be synchronously changed via a trigger signal (ldac). note that cs and clk are combined with an or gate, which controls the serial-to-parallel shift register. these two inputs are completely interchangeable. in addition, care must be taken with the state of clk when cs rises at the end of a serial transfer. if clk is low when cs rises, the or gate will provide a rising edge to the shift register, shifting the internal data one additional bit. the result will be incorrect data and possible selection of the wrong input register(s). if both cs and clk are used, cs should rise only when clk is high. if not, then either cs or clk can be used to operate the shift register (the remaining pin should be tied to dgnd). please refer to table ii for more information. serial-data output the serial-data output pin (sdo) is the internal shift register s output. for the dac7632, sdo is a driven output and does not require an external pull-up. any number of dac7632s can be daisy-chained by connecting the sdo pin of one device to the sdi pin of the following device in the chain, as shown in figure 14.
dac7632 18 sbas234 www.ti.com figure 15. digital input and output timing. dacsel (lsb) sdi clk cs load x d15 d1 d0 sdi clk ldac rst v out t css t ld1 t cl t ch t ds t dh t ld2 t ldrw t s t rsth t rstl t rsss t rssh t csh t s 0.003% fsr error band 0.003% fsr error band rstsel x x xx x quick load (msb) t lddd ldac t lddh t lddl t sdo sdo digital timing figure 15 and table iii provide detailed timing for the digital interface of the dac7632. digital input coding the dac7632 input data is in straight binary format. the output voltage is given by equation 1. vvl vhvln out ref ref ref =+ ( ) , 65 536 where n is the digital input code. this equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. digitally-programmable current source the dac7632 offers a unique set of features that allows a wide range of flexibility in designing application circuits such as programmable current sources. the dac7632 offers both a differential reference input, as well as an open-loop con- figuration around the output amplifier. the open-loop con- figuration around the output amplifier allows a transistor to be placed within the loop to implement a digitally-program- mable, unidirectional current source. the availability of a differential reference allows programmability for both the full- scale and zero-scale currents. the output current is calcu- lated as: i vhvl r vlr out ref ref sense ref sense = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ( ) , / n 65 536
dac7632 19 sbas234 www.ti.com symbol description min max units t ds data valid to clk rising 10 ns t dh data held valid after clk rises 20 ns t ch clk high 25 ns t cl clk low 25 ns t css cs low to clk rising 15 ns t csh clk high to cs rising 0 ns t ld1 load high to clk rising 10 ns t ld2 clk rising to load low 30 ns t ldrw load low time 30 ns t lddl ldac low time 100 ns t lddh ldac high time 100 ns t lddd load low to ldac rising 40 ns t rsss resetsel valid to reset high 0 ns t rssh reset high to resetsel not valid 100 ns t rstl reset low time 10 ns t rsth reset high time 10 ns t sdo sdo propogation delay 10 30 ns t s settling time 10 s table iii. timing specifications (t a = 40 c to +85 c). figure 16. 4-20ma digitally-controlled current source. v out a v out a sense v ref l sense v ref l v ref h v ref h sense v out b sense v out b 32 31 30 29 28 27 26 25 dac7632 1000pf i out 100 ? +2.5v 20k ? 80k ? +v +v opa2350 100 ? 2200pf 1000pf 2200pf v programmed 125 ? i out v programmed 125 ? figure 16 shows a dac7632 in a 4-20ma current output configuration. the output current can be determined by equation 3: i vv n v out = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? 25 05 125 65 536 05 125 . . , . ?? at full-scale, the output current is 16ma, plus the 4ma, for the zero current. at zero scale the output current is the offset current of 4ma (0.5v/125 ? ).
dac7632 20 sbas234 www.ti.com package drawing mtqf002b january 1995 revised may 2000 vf (s-pqfp-g32) plastic quad flatpack 4040172/d 04/00 gage plane seating plane 1,60 max 1,45 1,35 8,80 9,20 sq 0,05 min 0,45 0,75 0,25 0,13 nom 5,60 typ 1 32 7,20 6,80 24 25 sq 8 9 17 16 0,25 0,45 0,10 0 C 7 m 0,20 0,80 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice.
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third?party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2002, texas instruments incorporated

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