elm road, west chirton industrial estate, north shields, ne29 8se, england. tel +44 (0191) 2930500. fax +44 (0191) 2590997 1m x 32 sram module puma 84s32000 - 012/015/020 plastic 84 j-leaded jedec plcc issue 2.0 : march 2002 description features the puma 84s32000 is a 32mbit cmos high speed static ram organised as 1m x 32 in a jedec 84 pin surface mount j-leaded plcc, available with access times of 12, 15, and 20ns. the output width is user configurable as 8, 16 or 32 bits using eight chip selects (cs1~8). the device features low power standby, multiple ground pins for maximum noise immunity and ttl compatible inputs and outputs. the puma 84s32000 offers a dramatic space saving advantage over eight standard 512kx8 devices. ? very fast access times of 12/15/20 ns . jedec 84 'j' leaded plastic surface mount package. single 5v 10% power supply. user configurable as 8 / 16 / 32 bit wide output. operating power (32-bit) 5.28 w (max) low power standby cmos 550 mw (max) fully static operation. multiple ground pins for maximum noise immunity. package details address inputs a0 ~ a18 data input/output d0 ~ d31 chip select cs1 ~ 8 write enable we output enable oe no connect nc power (+5v) v cc ground gnd pin functions 512k x 8 cs1 cs2 cs3 cs4 we oe sram a0 - a18 d0 - d7 d8 - d15 d16 - d23 d24 - d31 512k x 8 sram 512k x 8 sram 512k x 8 sram 512k x 8 sram d0 - d7 d8 - d15 d16 - d2 3 d24 - d31 512k x 8 sram 512k x 8 sram 512k x 8 sram cs5 cs6 cs7 cs8 pin definition block diagram d17 d18 d19 gnd d20 d21 d22 d23 vcc d24 d25 d26 d27 gnd d28 d29 d30 d14 d13 d12 gnd d11 d10 d9 d8 vcc d7 d6 d5 d4 gnd d3 d2 d1 d16 a18 a17 cs4 cs3 cs2 cs1 vcc oe we a16 a15 a14 d15 nc cs6 cs5 987654321 8281807978777675 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 10 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vcc a13 a11 a10 a9 a8 a7 d31 a6 a5 a4 a3 a2 a1 a0 d0 a12 puma 84s32000 view from above nc nc 11 cs8 cs7 84 83 nc nc 73 74 nc nc 54 55 52 53 nc nc 33 34 nc nc nc nc 29 30 nc 31 nc 32 12 13
puma 84s32000 - 012/015/020 issue 2.0 : march 2002 2 voltage on any pin relative to v ss v t (2) -0.5 - 7.0 v power dissipation p t - - 5.0 w storage temperature t stg -65 - 150 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) v t can be -2.0v pulse of less than 8ns. dc operating conditions parameter symbol min typ max unit absolute maximum ratings (1) recommended operating conditions parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - v cc +0.5 v input low voltage v il -0.3 - 0.8 v operating temperature (commercial) t a 0 - 70 o c (industrial) t ai -40 - 85 o c (suffix i) parameter symbol test condition min typ max unit i/p leakage current address,oe,we i li 0v < v in < v cc -20 - 20 a output leakage current i lo cs = v ih, v i/o = gnd to v cc -20 - 20 a operating supply current 32-bit mode i cc32 min. cycle, cs = v il , f=f max , i out = 0ma - - 960 ma 16-bit mode i cc16 as above. - - 640 ma 8-bit mode i cc8 as above. - - 480 ma standby supply current ttl levels i sb1 cs = v ih , f=f max - - 320 ma cmos levels i sb2 cs > v cc -0.2v, 0.2 puma 84s32000 - 012/015/020 issue 2.0 : march 2002 3 capacitance (v cc =5v10%,t a =25 o c) note: capacitance calculated, not measured. parameter symbol test condition max unit input capacitance (address,oe,we) c in1 v in = 0v 70 pf i/p capacitance (other) c in2 v in = 0v 12 pf i/o capacitance worst case (8-bit) c i/o v i/o = 0v 62 pf operation truth table * input pulse levels: 0v to 3.0v * input rise and fall times: 3ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc =5v10% ac test conditions output load cs oe we data pins supply current mode h x x high impedance i sb1 , i sb2 standby l l h data out i cc32 , i cc16 , i cc8 read l h l data in i cc32 , i cc16 , i cc8 write l l l data in i cc32 , i cc16 , i cc8 write l h h high-impedance i sb1 , i sb2 high-z notes : h = v ih : l =v il : x = v ih or v il the above table reflects the operation of each of the ram's on the module. care should be taken to avoid bus contention on data lines using chip select signals. 166? 30pf i/o pin 1.76v
puma 84s32000 - 012/015/020 issue 2.0 : march 2002 4 012 015 020 parameter symbol min max min max min max unit write cycle time t wc 12 - 15 - 20 - ns chip selection to end of write t cw 10 - 12 - 15 - ns address valid to end of write t aw 10 - 12 - 15 - ns address setup time t as 0-0-0- ns write pulse width t wp 10 - 12 - 12 - ns write recovery time t wr 0-0-0- ns write to output in high z t whz 060709 ns data to write time overlap t dw 6-7-9- ns data hold from write time t dh 0-0-0- ns output active from end of write t ow 3-3-3- ns read cycle 012 015 020 parameter symbol min max min max min max unit read cycle time t rc 12 - 15 - 20 - ns address access time t aa -12-15-20 ns chip select access time t acs -12-15-20 ns output enable to output valid t oe -6-7-9 ns output hold from address change t oh 3-3-3- ns chip selection to output in low z t clz 3-3-3- ns output enable to output in low z t olz 0-0-0- ns chip deselection to o/p in high z t chz 060709 ns output disable to output in high z t ohz 060709 ns ac operating conditions write cycle
puma 84s32000 - 012/015/020 issue 2.0 : march 2002 5 read cycle timing waveform (1,2) write cycle no.1 timing waveform (1,4) ac read characteristics notes (1) we is high for read cycle. (2) all read cycle timing is referenced from the last valid address to the first transition address. (3) t chz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) at any given temperature and voltage condition, t chz (max) is less than t clz (min) both for a given module and from module to module. (5) these parameters are sampled and not 100% tested. oe t acs t clz (4,5) t ohz (3) t t olz aa oh chz (3,4,5) data valid t t t t rc address cs dout oe don't care. t wr(7) as(6) t cw t wp(2) t dw dh aw don't care t t t t t wc ohz(3,9) address oe cs we dout din hi g h-z hi g h-z ow t (8) data valid
puma 84s32000 - 012/015/020 issue 2.0 : march 2002 6 write cycle no.2 timing waveform (1,5) ac write characteristics notes (1) all write cycle timing is referenced from the last valid address to the first transition address. (2) all writes occur during the overlap of cs and we low. (3) if oe, cs, and we are in the read mode during this period, the i/o pins are low impedance state. inputs of opposite phase to the output must not be applied because bus contention can occur. (4) dout is the read data of the new address. (5) oe is continuously low. (6) address is valid prior to or coincident with cs and we low, too avoid inadvertant writes. (7) cs or we must be high during address transitions. (8) when cs are low : i/o pins are in the output state. input signals of opposite phase leading to the output should not be applied. (9) defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. these parameters are sampled and not 100% tested. t aw t cw wr(7) wc as(6) dw dh oh ow whz(3,9) wp(2) don't t t t t t address cs we dout din t t t t care hi g h-z hi g h-z (4) (8) data valid
puma 84s32000 - 012/015/020 issue 2.0 : march 2002 7 package information dimensions in mm(inches) plastic 84 pin jedec surface mount plcc 30.10 (1.185) 0.90 (0.035) typ 29.20 (1.150) 5.08 (0.200) max 28.20 (1.110) 30.35 (1.195) xxxxxx-x xxxxxxxx-xx xxxxx-xx xxxx
puma 84s32000 - 012/015/020 issue 2.0 : march 2002 8 speed 012 = 12 ns 015 = 15 ns 020 = 20 ns temperature range blank = commercial temperature i = industrial temperature power consumption blank = standard l = low power organisation 32000 = 1m x 32 sram configurable as 2m x 16 and 4m x 8 memory type s = asynchronous sram 5v + 10% v cc package puma 84 = memory stack 84 pin 'j' leaded ordering information note : although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express written approval of a company director. puma84s32000li-012
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