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2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 3-77-62 tmp88cp77/s77/u77 2007-10-23 2.6.2 control the timer / counter 1 is controlled by a timer / counter 1 control register (tc1cr) and two 16-bit timer registers (treg1a and treg1b). reset does not affect treg1a and treg1b. note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz] note 2: writing to the lower byte of the timer registers (treg1al, treg1bl), the comparison is inhibited until the upper byte(treg1ah, treg1bh) is written. only the lower byte of the timer registers can not be changed. after writing to the upper byte, any match during 1 machine cycle (instruction execution cycle) is ignored. note 3: set the mode, source clock, edge (including int2es) when tc1 stops (tc1s=00). note 4: software capture can be used in only timer and event counter modes. scap1 is automatically cleared to 0 after capturing. note 5: values to be loaded to timer registers must satisfy the following condition. treg1a>0 note 6: tc1cr and treg1a are write-only registers and must not be used with any of the read-modify-write instructions such as set, clr, etc. note 7: please use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. please read the capture value in a capture enabled condition. note 8: since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr 2007-10-23 2007-10-23 2007-10-23 3-77-66 tmp88cp77/s77/u77 2007-10-23 (4) window mode counting up is performed on the rising edge of the pulse that is the logical and-ed product of the tc1 pin input (window pulse) and an internal clock. the contents of treg1a are compared with the contents of up-counter. if a match is found, an inttc1 interrupt is generated, and the counter is cleared. positive or negative logic for the tc1 pin input can be selected. edge selection is the same as for int2 pin. setting scap1 to 1 transfers the current contents of up-counter to treg1b. it is necessary that the maximum applied frequency be such that the counter value can be analyzed by the program. that is; the frequency must be considerably slower than the selected internal clock. figure 2-23. window mode timing chart (5) pulse width measurement mode counting is started by the external trigger (set to external trigger start by tc1s). the trigger can be selected either the rising or falling edge of the tc1 pin input. the source clock is used an internal clock. on the next falling (rising) edge, the counter contents are transferred to treg1b and an inttc1 interrupt is generated. the counter is cleared when the single edge capture mode is set. when double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred to treg1b. if a falling (rising) edge capture value is required, it is necessary to read out treg1b contents until a rising (falling) edge is detected. falling or rising edge is selected with int2es, and single edge or double edge is selected with mcap1 (bit 6 in tc1cr). note: the first captured value af ter the timer starts may be read incorrectively, therefore, ignore the first captured value. match detect treg1a inttc1 interrupt internal clock up-counter treg1a tc1 pin input internal clock up-counter tc1 pin input inttc1 interrupt (a) positive logic (at int2es=0) (b) negative logic (at int2es=1) ? ? match detect 1 0 7 47 5 46 31 2 1 0 7 5 3 6 2 0 2 3 counter clear command start 890 1 9 command start counter clear 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 3-77-93 tmp88cp77/s77/u77 2007-10-23 2.10.4 i 2 c bus mode control the following registers ar e used to control the serial bus interf ace (sbi-ver.c) and m onitor the operation status in the i 2 c bus mode. note 1: fc ; high-frequency clock [hz] note 2: set the bc to 000 before switching to 8-bit sio bus mode. note 3: sbicr1 is write-only registers, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. note 4: this i 2 c bus circuit does not support the fast mode. it supports the standard mode only. although the i 2 c bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the i 2 c specification is not guaranteed in that case. note 1: for writing transmitted data, start from the msb (bit 7). note 2: cannot read the data which was written into sbidbr, since a write data buffer and a read data buffer are independent in sbidbr. therefore, sbidbr cannot be used with any of read-modify-write instructions such as bit manipulation, etc. note 3: the data which was written into sbidbr is cleared to 0 when intsbi is generated. note: i2car is write-only register, which cannot be used with any of read-modify-write instruction such as bit manipulation, etc. figure 2-41.serial bus inter face control regi ster 1, serial bus interface data buf fer register and i 2 c bus address register in the i 2 c bus mode serial bus interface control register 1 sbicr176543210 (00020h) bc ack swrst sck (initial value: 0000 0000) bc number of transferred bits bc ack = 0 ack = 1 write only number of clock bits number of clock bits 000 8 8 9 8 001 1 1 2 1 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 1117787 ack acknowledge mode specification 0: acknowledge not returned to transmitter. 1: acknowledge returned to transmitter. read/ write swrst initiate a internal of sbi 0: - 1: initialized (clearing 0 after initialized) read/ write sck serial clock selection 000:reserved (note4) 001:reserved (note4) 010: 58.8 khz 011: 30.3 khz at fc = 8 mhz (output on scl pin) 100: 15.4 khz 101: 7.75 khz 110: 3.89 khz 111:reserved write only serial bus interface data buffer register sbidbr76543210 (00021h) read / write i 2 c bus address register i2car 76543210 slave address als (00022h) sa6 sa5 sa4 sa3 sa2 sa1 sa0 (initial value: 0000 0000) sa 88cp77/s77/u77 slave address selection write only als address recognition mode specification 0: slave address recognition 1: non slave address recognition 2007-10-23 3-77-95 tmp88cp77/s77/u77 2007-10-23 (1) acknowledge mode specification set the ack (bit 4 in sbicr1) to 1 for o peration in the acknowledge mode. the 88cp77/s77/u77 generates an additional clock pulse for an acknowledge signal when operating in the master mode. in the transmitter mode during the clock pulse cycle, the sda pin is released in order to receive the acknowledge signal from the receiver. in the receiver mode during the clock pulse cycle, the sda pin is set to the low level in order to generate the acknowledge signal. reset the ack for operation in the non-acknowledge mode. the 88cp77/s77/u77 do not generate a clock pulse for the acknowledge signal when operating in the master mode. in the acknowledge mode, the 88cp77/s77/u77 counts a clock pulse for the acknowledge signal when operating in the slave mode. during the clock pulse, when the received slave address is the same as the value set at the i2car or when a general call is received, the sda pin is set to the low level in order to gener ate the acknowledge signal. in the transmitter mode during the clock pulse cycle after matching the slave addresses or receiving a general call, the sda pin is released in order to receive the acknowledge signal from the receiver. in the receiver mode during the clock pulse cycle, the sda pin is set to the low level in order to generate the acknowledge signal. in non-acknowledge mode, the 88cp77/s77/u77 does not count a clock pulse for the acknowledge signal when operating in the slave mode. (2) number of transfer bits the bc (bits 7 to 5 in sbicr1) is used to select a number of bits for transmitting and receiving data. since the bc is cleared to 000 as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. other than these, the bc retains a specified value. (3) serial clock a. clock source the sck (bits 2 to 0 in sbicr1) is used to select a maximum transfer frequency output from the scl pin in the master mode. set a communication baud rate that meets the i 2 c bus specification, such as the shortest pulse width of tlow, based on the equations shown below.in both master mode and slave mode, a pulse width of at least 4 machine cycles is required for both high and low levels. figure 2-43. clock source 1/fscl t low t high t low = 2 /fc t high = 2 /fc + 8/fc fscl = 1/( t low + t high) n n note: fc ; high-frequency clock (bits 2 to 0 in the sbicr1) 000 001 010 011 100 101 110 4 5 6 7 8 9 10 n sck 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 2007-10-23 |
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