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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9853 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 programmable digital qpsk /16-qam modulator functional block diagram 10-bit dac sine cosine interpolation filter inv sync filter dds preamble insertion randomizer clock control functions 6 3 fir filter fir filter interpolation filter encoder: fsk qpsk dqpsk 16-qam d16-qam data delay & mux xor r-s fec ad9853 10 10 a out gain control to driver amp reset t x enable fec enable/ disable ref clock in serial data in serial control bus: 32-bit output frequency tuning word input data rate/modulation format fec/randomizer/preamble enable/configuration fir filter coefficients ref clock multiplier enable i/q phase invert sleep mode to lp filter and ad8320 cable driver amplifer features universal low cost solution for hfc network return-channel t x function: 5 mhzC42 mhz/ 5 mhzC65 mhz 165 mhz internal reference clock capability includes programmable pulse-shaping fir filters and programmable interpolating filters fsk/qpsk/dqpsk/16-qam/d16-qam modulation formats 6 3 internal reference clock multiplier integrated reed-solomon fec function programmable randomizer/preamble function supports interoperable cable modem standards internal sinx/x compensation >50 db sfdr @ 42 mhz output frequency (single tone) controlled burst mode operation +3.3 v to +5 v single supply operation low power: 750 mw @ full clock speed (3.3 v supply) space saving surface mount packaging applications hfc data, telephony and video modems wireless lan general description the ad9853 integrates a high speed direct-digital synthesizer (dds), a high performance, high speed digital-to-analog con- verter (dac), digital filters and other dsp functions onto a single chip, to form a complete and flexible digital modulator device. the ad9853 is intended to function as a modulator in network applications such as interactive hfc, wlan and mmds, where cost, size, power dissipation, functional integra- tion and dynamic performance are critical attributes. the ad9853 is fabricated on an advanced cmos process and it sets a new standard for cmos digital modulator performance. the device is loaded with programmable functionality and provides a direct interface port to the ad8320, digitally- programmable cable driver amplifier. the ad9853/ad8320 chipset forms a highly integrated, low power, small footprint and cost-effective solution for the hfc return-path requirement and other more general purpose modulator applications. the ad9853 is available in a space saving surface mount pack- age and is specified to operate over the extended industrial temperature range of C40 c to +85 c.
C2C rev. c ad9853Cspecifications parameter temp test level min typ max units ref clock input characteristics frequency range 6 refclk disabled (+3.3 v supply) full iv 42 126 mhz 6 refclk enabled (+3.3 v supply) full iv 7 21 mhz 6 refclk disabled (+5 v supply) full iv 108 168 mhz 6 refclk enabled (+5 v supply) full iv 18 28 mhz duty cycle +25 civ 40 60 % input capacitance +25 cv 3 pf input impedance +25 c v 100 m w dac output characteristics resolution 10 bits full-scale output current +25 c iv 5 10 20 ma gain error +25 c i C10 +10 % fs output offset +25 ci 10 m a output offset temperature coefficient full v 50 na/ c differential nonlinearity +25 c i 0.5 0.75 lsb integral nonlinearity +25 c i 0.5 1.5 lsb output capacitance +25 cv 5 pf phase noise @ 1 khz offset, 40 mhz a out 6 refclk enabled +25 c v C100 dbc 6 refclk disabled +25 c v C110 dbc voltage compliance range +25 c i C0.5 +1.5 v wideband sfdr (single tone): 1 mhz a out +25 c iv 62 68 dbc 20 mhz a out +25 c iv 52 54 dbc 42 mhz a out +25 c iv 48 50 dbc 65 mhz a out 1 +25 c iv 42 44 dbc modulator characteristics i/q offset +25 civ 48 db adjacent channel power +25 c iv 44 dbm error vector magnitude +25 civ 1 2 % in-band spurious emission 5 mhzC42 mhz a out +25 c iv 42 dbc 5 mhzC65 mhz a out 1 +25 c iv 40 dbc passband amplitude ripple +25 cv 0.3 db timing characteristics serial control bus maximum frequency full iv 25 mhz minimum clock pulsewidth low (t pwl ) full iv 10 ns minimum clock pulsewidth high (t pwh ) full iv 10 ns maximum clock rise/fall time full iv 100 ns minimum data setup time (t ds ) full iv 10 ns minimum data hold time (t dh ) full iv 10 ns minimum clock setupstop condition (t cs ) full iv 10 ns minimum clock holdstart condition (t ch ) full iv 10 ns reset minimum t x enable low to reset low (t tr ) full iv 10 ns minimum reset high to start condition (t rh ) full iv 10 ns fec enable minimum fec enable/disable to t x enable high (t fh ) full iv 0 ns minimum fec enable/disable to t x enable low (t fl ) full iv 0 ns (v s = +3.3 v 6 5%, r set = 3.9 k v , reference clock frequency = 20.48 mhz with 6 3 refclk enabled, symbol rate = 2.56 ms/s, a = 0.25, unless otherwise noted)
C3C rev. c ad9853 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9853 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. parameter temp test level min typ max units timing characteristics (continued) wake-up timeCpll power-down +25 civ 1 ms wake-up timeCdac power-down +25 c iv 200 m s wake-up timeCdigital power-down +25 civ 5 m s data latency (t dl ) +25 c iv 6 symbols minimum reset pulsewidth low (t rl ) +25 civ 10 ns cmos logic inputs logic 1 voltage, +5 v supply +25 c i +3.5 v logic 1 voltage, +3.3 v supply +25 c i +3.0 v logic 0 voltage +25 c i +0.4 v logic 1 current +25 ci 12 m a logic 0 current +25 ci 12 m a input capacitance +25 cv 3 pf power supply 2 +v s current (+3.3 v + 5%) full operating conditions +25 c i 184 230 ma with pll power-down enabled +25 c i 178 224 ma with dac power-down enabled +25 c i 170 216 ma with digital power-down enabled +25 c i 36 54 ma with all power-down enabled +25 c i 16 20 ma +v s current (+5 v + 5%) +25 c i 400 595 ma notes 1 reference clock = 28 mhz with clock multiplier enabled; supply voltage = +5 v. 2 maximum values are obtained under worst case operating modes. typical values are valid for most applications. specifications subject to change without notice. explanation of test levels test level i C 100% production tested. iii C sample tested only. iv C parameter is guaranteed by design and characterization testing. v C parameter is a typical value only. vi C devices are 100% production tested at +25 c and guaranteed by design and characterization testing for industrial operating temperature range. absolute maximum ratings* maximum junction temperature . . . . . . . . . . . . . . . +150 c v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 v digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . C0.7 v to +v s digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 5 ma storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature . . . . . . . . . . . . . . . . . C40 c to +85 c lead temperature (10 sec soldering) . . . . . . . . . . . . +300 c mqfp q ja thermal impedance . . . . . . . . . . . . . . . . . 36 c/w *absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability under any of these conditions is not necessarily implied. exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. warning! esd sensitive device ordering guide temperature package package model range description option ad9853as C40 c to +85 c metric quad flatpack s-44a (mqfp)
ad9853 C4C rev. c pin function descriptions pin # pin name pin function 1, 7, 9, 10, 36, 39, 44 dgnd digital ground 2, 8, 37, 40, 43 dvdd digital supply voltage 3 control bus clock bit clock for control bus data 4 control bus data in c ontrol bus data in 5 fec enable enables/disables fec 6 address bit address bit for control bus 11, 26, 31 test data out factory useserial test data out 12, 13 pll gnd pll ground 14 pll vcc supply voltage for pll 15 pll filter pll loop filter connection 16, 19, 23 agnd analog ground 17 nc no connect 18 dac rset rset resistor connection 20, 22 avdd analog supply voltage 21 dac baseline dac baseline voltage 24 iout analog current output of the dac 25 ioutb complementary analog cur- rent output of the dac 27 test clk factory usescan clock 28 test latch factory usescan latch 29 test data in factory useserial test data in 30 test data enable factory useserial test data enable, grounded for normal operation 32 reset master device reset function 33 ca enable cable amplifier e nable 34 ca clock cable amplifier serial control clock 35 ca data cable amplifier serial control data 38 ref clk in reference clock input 41 data in input serial data stream 42 t x enable pulse that frames the valid input data stream pin configuration 44-lead metric quad flatpack (s-44a) 3 4 5 6 7 1 2 10 11 8 9 40 39 38 41 42 43 44 36 35 34 37 29 30 31 32 33 27 28 25 26 23 24 pin 1 identifier top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 avdd dac baseline avdd nc pll gnd pll gnd agnd ca enable pll vcc reset test data out pll filter test data enable dac rset dvdd test data in agnd test latch dgnd test clk ioutb ad9853 iout dvdd agnd dgnd dgnd dgnd dvdd control bus clock dvdd control bus data in fec enable address bit dgnd nc = no connect dvdd dgnd dgnd test data out test data out t x enable data in ref clk in ca clock ca data address bit
ad9853 C5C rev. c table i. modulator function description modulation encoding format fsk*, qpsk, dqpsk, 16-qam, d16-qam, selectable via control bus output carrier frequency range dc C 63 mhz with +3.3 v supply voltage dc C 84 mhz with +5 v supply voltage serial input data rate evenly divisible fraction of reference clock pulse-shaping fir filter 41 tap, linear phase, 10-bit coefficients fully programmable via control bus interpolation range interpolation rate = (4/ m ) ( icic 1) ( icic 2) where: m = 2 for qpsk, m = 4 for 16-qam minimum and maximum rates minimum interpolation rateqpsk = 2 3 2 = 12 16-qam = 1 4 3 = 12 maximum interpolation rateqpsk = 2 31 63 = 3906 16-qam = 1 31 63 = 1953 these are the minimum and maximum interpolation ratios from the input data rate to the system clock. the interpolation range is a function of the fixed interpolation factor of four in the fir filters, the programmed cic filter interpolation rates (icic1, icic2), as well as system timing constraints. maximum reference clock frequency +3.3 v supply: 21 mhz with 6 refclk enabled, 126 mhz with 6 refclk disabled +5 v supply: 28 mhz with 6 refclk enabled, 168 mhz with 6 refclk disabled 6 refclk fixed 6 reference clock multiplier, enable/disable control via control bus r-s fec enable/disable via control bus and dedicated control pin. control pin enable/disable function: logic 1 = enable logic 0 = disable primitive polynomial: p(x) = x 8 + x 4 + x 3 + x 2 + 1 code generator polynomial: g(x) = (x + a 0 )(x + a 1 )(x + a 2 ) . . . (x + a 2t C1 ) selectable via control bus t = 0C10 (programmable) codeword length (n) = 255 max (programmable) n = k + 2 t (k range = 16 k 255 C 2 t) fec/randomizer can be transposed in signal chain via control bus. i/q channel spectrum i cos + q sin (default) or i cos C q sin, selectable via control bus. preamble insertion 0C96 bits, programmable length and content randomizer enable/disable control via control bus generating polynomial: x 6 + x 5 + 1, programmable seed (davic/dvb-compliant) or x 15 + x 14 + 1, programmable seed (docsis-compliant) randomizer and fec blocks can be transposed in signal chain, via control bus. *in fsk mode, f0:f1 are direct dds cosine output. the two interpolator stages of the ad9853 are not used in the fsk mode and sh ould be programmed for maximum interpolation rates to reduce unnecessary current consumption. this means that interpolator #1 should be set to a decim al value of 31, and interpolator #2 should be set to decimal value of 63. this is easily accomplished by programming registers 12 and 13 (hex) with the values o f ff (hex).
ad9853 C6C rev. c table ii. control register functional assignment register address data (note 1) d7 d6 d5 d4 d3 d2 d1 d0 00h msb value of k (message length in bytes) for reed-solomon encoder, where 16 10 k 255 10 (note 2) lsb 01h msb the number of correctable byte lsb randomizer randomizer length (note 3) errors (t) for the reed-solomon insertion 00 2 = 6 bit encoder , where 0 t 10 10 .01 2 = 15 bit for t = 0, the rs encoder is 0 = after rs 10 2 = randomizer off effectively disabled. 1 = before rs 11 2 = randomizer off 02h msb lower eight bits of seed value for 15-bit randomizer (not used for 6-bit randomizer) lsb 03h msb upper seven bits of seed value for 15-bit randomizer lsb C or C seed value for 6-bit randomizer (d1 not used in this case). 04h msb preamble length (l) where 0 l 96 bits (note 4) lsb 05h modulation mode 000 2 = qpsk , 001 2 = dqpsk, 010 2 = 16-qam 011 2 = d16-qam , 100 2 = fsk 06h the msb of the preamble always resides in d7 of address 11h and is the first preamble bit to be clocked out of the device du ring transmission of : a packet. up to 96 bits of preamble are available as specified in register 04h. unused bits are dont care for l < 96. 11h msb preamble data. (note 5) 12h msb interpolator #1: rate lsb rate change factor ( r ) where 3 10 r 31 10 13h msb interpolator #2: rate lsb rate change factor ( r ) where 2 10 r 63 10 14h msb interpolator #1: scale lsb 2 multiplier 0 = off 1 = on 15h 6 msb interpolator #2: scale lsb 16h frequency tuning word #1 lsb : fsk mode : specifies the space frequency (f0). 19h msb all other modes : specifies the carrier frequency. 1ah frequency tuning word #2 lsb : fsk mode : specifies the mark frequency (f1). 1dh msb (addresses 1ahC1dh are only valid for fsk mode.) 1eh 5 msb-2 msb-3 10-bit fir end tap coefficient, a 0 lsb 0 1fh msb 0 msb-1 < unused bits > : : fir intermediate tap coefficients, a 1 C a 19 : 46h msb-2 msb-3 10-bit fir center tap coefficient, a 20 lsb 20 47h msb 20 msb-1 < unused bits > spectrum digital power 6 refclk pll mode dac mode 48h 0 = i cos + q sin 0 = normal 0 = off 0 = awake 0 = awake (note 7) 1 = i cos C q sin 1 = shutdown 1 = on 1 = sleep 1 = sleep 49h ad8320 cable driver gain control byte (gcb) (note 8) msb the absolute gain, a v , of the ad8320 is given by: a v = 0.316 + 0.077 gcb (where 0 gcb 255 10 ) lsb notes 1 the 8-bit register address is preceded by an 8-bit device address, which is given by 000001xy, where the value of bits x and y are determined as follows: x voltage applied to pin 6 y desired register function 0 gnd 0 write 1+v s 1 read 2 this register must be loaded with a nonzero value even if the rs encoder has been disabled by setting t = 0 in register 01h. 3 unused regions are dont care bit locations. 4 if a preamble is not used this register must be initialized to a value of 0 by the user. 5 addresses 06hC011h and 1ehC47h are write only. 6 readback of register 15h results in a value that is 2 the actual programmed value. this is a design error in the readback function. 7 assertion of reset (pin 32) sets the contents of this register to 0. 8 registers 0hC48h may be written to using a single register address followed by a contiguous data sequence (see figure 27). register 49h, however, must be written to individually; i.e., a separately addressed 8-bit data sequence.
modulated output spectrum with 3.3 v supply, a = 0.25, 20.48 mhz refclk typical performance characteristicsCad9853 C7C rev. c 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 10db ref lvl = C20dbm figure 1. qpsk, 320 kb/s, a out = 10 mhz 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 10db ref lvl = C20dbm figure 2. qpsk, 640 kb/s, a out = 20 mhz 0 C10 C100 start 0hz stop60 mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 10db ref lvl = C20dbm figure 3. qpsk, 1.28 mb/s, a out = 42 mhz 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 10db ref lvl = C20dbm figure 4. qpsk, 1.28 mb/s, a out = 10 mhz 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 10db ref lvl = C20dbm figure 5. qpsk, 2.56 mb/s, a out = 20 mhz 0 C10 C100 start 0hz stop60 mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 10db ref lvl = C20dbm figure 6. qpsk, 5.12 mb/s, a out = 42 mhz
ad9853 C8C rev. c 0 0 0 0 0 0 0 0 0 0 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 30db ref lvl = 0dbm figure 8. a out = 1 mhz 0 0 0 0 0 0 0 0 0 0 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 30db ref lvl = 0dbm figure 9. a out = 42 mhz modulated output spectrum with 5 v supply, a = 0.25, 27.5 mhz refclk 0 C10 C10 0 start 0hz stop 80mhz 8mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 22.5s rf att = 10db ref lvl = C20dbm figure 7. qpsk, 1.375 mb/s, a out = 65 mhz single tone output spectrum with +3.3 v supply, 20.48 mhz refclk 0 0 0 0 0 0 0 0 0 0 0 C10 C100 start 0hz stop 60mhz 6mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 17s rf att = 30db ref lvl = 0dbm figure 11. a out = 20 mhz 0 0 0 0 0 0 0 0 0 0 0 C10 C100 center 40hz span 80mhz 8mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 5khz vbw = 5khz swt = 8s rf att = 30db ref lvl = 0dbm figure 12. a out = 65 mhz (+5 v supply, 27.5 mhz refclk) 0 C10 C100 start 0 hz stop 80 mhz 8 mhz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 3khz vbw = 3khz swt = 22.5s rf att = 10db ref lvl = C20dbm figure 10. qpsk, 5.5 mb/s, a out = 65 mhz
ad9853 C9C rev. c output phase noise plots, a out = 40 mhz 0 C10 C100 center 40hz span 10mhz 1khz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 30hz vbw = 30hz swt = 56s rf att = 20db ref lvl = C1dbm figure 13. 6 3 refclk enabled ch pwr = C6.98dbm acp up = C44.95dbm acp low = C44.66dbm alt1 up = C65.96dbm alt1 low = C65.99dbm figure 15. adjacent channel power, a out = 30 mhz, 2.56 ms/s, channel bw = 3.2 mhz ( a = 0.25) 0 C10 C100 center 40hz span 10khz 1khz/ C40 C70 C80 C90 C20 C30 C60 C50 rbw = 30hz vbw = 30hz swt = 56s rf att = 20db ref lvl = C1dbm figure 14. 6 3 refclk disabled
ad9853 C10C rev. c symbols 1.2 C1.2 0 t1 3 ref lvl C8dbm cf 42mhz meas signal sr 1.28mhz eye [1] demod 16qam figure 18. 16-qam modulation 1.2 C1.2 C1.5 1.5 real t1 ref lvl C8dbm cf 42mhz meas signal sr 1.28mhz constellation demod 16qam figure 19. 16-qam modulation symbols 1.2 C1.2 0 t1 3 ref lvl C7dbm cf 42mhz meas signal sr 1.28mhz eye [1] demod qpsk figure 16. qpsk modulation 1.2 C1.2 C1.5 1.5 real t1 ref lvl C7dbm cf 42mhz meas signal sr 1.28mhz constellation demod qpsk figure 17. qpsk modulation typical plots of eye diagrams and constellations
ad9853 C11C rev. c max clock rate C mhz ambient temp C 8 c 95 85 45 110 115 170 120 125 130 135 140 145 150 155 160 165 75 65 55 bit rate >2mb/s vcc = +5v continuous mode figure 20. max clk rate vs. ambient temperature (to ensure max junction temp is not exceeded) bit rate C mb/s power C watts 2.6 1.2 0 0.5 3.5 1.0 1.5 2.0 2.5 3.0 2.4 2.0 1.8 1.6 1.4 2.2 vcc = +5.0v clk = 165mhz continuous mode vcc = +4.0v figure 21. power consumption vs. bit rate bit rate C mb/s spurious in-band emission C dbc C45 C60 5.12 2.56 0.64 1.28 C50 C55 clk = 122.88 mhz vcc = +3.3v C40 a out = 42mhz a out = 32mhz a out = 22mhz a out = 12mhz figure 22. spurious emission vs. bit rate vs. a out bit rate C mb/s power C watts 0.80 0.75 0.55 01 6 2345 0.70 0.65 0.60 clk = 122.88 mhz vcc = +3.3v continuous mode figure 23. pwr consumption vs. bit rate burst mode duty cycle C % power C watts 2.4 1.9 0 20 100 40 60 80 2.3 2.2 2.1 2.0 2.5 clk = 165mhz vcc = +5.0v bit rate = 3.4mb/s figure 24. power consumption vs. burst duty cycle C40 C42 C52 3.5 1.75 0.44 0.88 C44 C46 C50 C48 bit rate C mb/s spurious in-band emission C dbc a out = 65mhz a out = 40mhz a out = 20mhz clk = 165mhz vcc = +4.0v to +5.0v figure 25. spurious emission vs. bit rate vs. a out
ad9853 C12C rev. c notes on burst transmission operation: 1. packet length = number of information bytes, k 2. in fec mode t x enable must be kept high for n 3 (k+2t) bytes where n is the number of codewords 3. if necessary, zero fill the last codeword to reach assigned k data bytes per codeword 4. the input data is sampled at the bit rate frequency (f b ) with the first sample taken at seconds after the rising edge of t x enable 5. preamble delay = 6. data rate must be exact sub-multiple of reference clock. 1 2 3 (f b ) (# of preamble bits) (bit rate frequency) frame structure: min t x enable low time = preamble + 8 symbols. (equates to 8 symbols minimum spacing between bursts with no change in profile) t x enable note: data rate must be precisely synchronized with rising edge of t x enable d1 d2 d3 d4 d5 d6 d7 dn don't care d1 d2 d3 d4 d5 d6 d7 dn don't care data packet = k bytes fec parity (2t bytes) fec parity (2t bytes) data packet = k bytes t x enable to a out latency data in internal code- word structure at r-s output frame structure for multiple code words or continous transmission: d1 d2 d3 d4 d5 d6 d7 dn don't care d1 d2 d3 d4 d5 d6 d7 dn don't care data packet = k bytes fec parity (2t bytes) data packet = k bytes fec parity (2t bytes) t x enable data in input data processing: t x enable d1 d59 dn d60 d61 d62 d63 d64 d65 d1 d2 d2 d3 d4 d5 data packet and fec parity codeword(s) preamble complete frame as presented to modulator encoder: internal bit clock data in encoder input preamble length = 96 bits maximum during this interval the data is r-s encoded, randomized, and delayed to synchronize with the end of the preamble data. one codeword one codeword preamble insertion figure 26. data framing and processing
ad9853 C13C rev. c s device address a(s) register address a(s) data a(s) write data a(s) p s device address a(s) register address a(s) read data a (m) p device address a(s) data s a(m) lsb = 0 lsb = 1 a(s) = acknowledge by slave a(m) = acknowledge by master s = start condition p = stop condition a (m) = no acknowledge by master figure 27. serial control busread and write sequences r/w msb a 1 0 0 0 0 0 lsb 0 = write / 1 = read address control (set via device pin 6) figure 28. serial control bus8-bit device address detail t fh t fl fec disable/ enable control t x enable t fh = fec to t x enable setup time = 0ns t fl = fec to t x enable hold time = 0ns figure 29. fec enable/disable timing diagram t tr t rl t x enable reset control clock control data t rh t pwh t pwl t ch t ds t dh t cs t tr = minimum t x enable low to reset low = 10ns t rl = minimum reset pulsewidth = 10ns t rh = minimum reset to start condition = 10ns t ch = minimum clock hold time start condition = 10ns t cs = minimum clock setup time stop condition = 10ns t ds = minimum data setup time = 10ns t dh = minimum data hold time = 10ns t pwh = t pwl = minimum clock pulsewidth high/low = 10ns t mp = minimum clock period = 40ns = 25mhz t mp figure 30. serial control interface timing diagram
ad9853 C14C rev. c digital qpsk/16Cqam modulator control processor serial control bus gain control bus coupling circuit and lp filter power down ad9853 direct control lines data in ref clock in programmable cable driver amplifier ad8320 to diplexer control processor figure 32. basic implementation of ad9853 digital modulator and ad8320 programmable cable driver amplifier in return-path application t rl reset note 1 note 2 note 2 control bus t x enable dac out t dl t rl : minimum reset low time = 10ns t dl : data latency = 6 symbols note 1. during this interval all control bus registers must be programmed. note 2. during this interval the control register (48h) may need to be reprogrammed due to being cleared by the preceding reset pulse. note 3. three resets are required to ensure that the data path is zero'd. start up sequence figure 31. recommended start-up sequence notes on the reset function: 1. reset is active low 2. reset zeros the control register at address 48 hex which causes the following default condition to exist: a. 6 3 refclk is disabled b. output spectrum is set to i 3 cos+q 3 sin c. digital pll power-down is disabled d. pll power-down is disabled e. dac pll power-down is disabled 3. serial control bus is reset and initialized. 4. outputs of modulation encoders are set to zero. this allows the fir filters and subsequent interpolation filters to be flushed with zeros as long as t x enable is held low. 5. the preamble is cleared upon execution of the reset function.
ad9853 C15C rev. c theory of operation the ad9853 is a highly integrated modulator function that has been specifically designed to meet the requirements of the hfc upstream function for both interoperable and proprietary system implementations. the ad8320 is a companion cable driver amplifier with a digitally-programmable gain function, that interfaces to the ad9853 modulator and directly drives the cable plant with the modulated carrier. together, the ad9853 and ad8320 provide an easily implementable transmitter solu- tion for the hfc return-path requirement. control and data interface as shown in the devices block diagram on the front page, the various transmit parameters, which include the input data rate, modulation format, fec and randomizer configurations, as well as all the other modulator functions, are programmed into the ad9853 via a serial control bus. the ad8320 cable driver amp gain can be programmed directly from the ad9853 via a 3-wire bus by writing to the appropriate ad9853 r egister. the ad 9853 also contains dedicated pins for fec e nable/disable and a reset function. note: t x enable pin must be held low for the duration of all serial control bus operations. the ad9853s serial control bus consists of a bidirectional data line and a clock line. communication is initiated upon a start condition, which is defined as a high-to-low transition of the data line while the clock is held high. communication terminates upon a stop condition, which is defined as a low-to-high transi- tion in the data line while the clock is held high. ordinarily, the data line transitions only while the clock line is low to avoid a start or s top condition. data is alw ays written or read back in 8-bit bytes followed by a single acknowledge bit. the micro- controller or asic (i.e., the bus master) transfers eight data bits and the ad9853 (i.e., the slave) issues the acknowledge bit. the acknowledge bit is active low and is clocked out on every ninth clock pulse. the bus master must three-state the data line dur- ing the ninth clock pulse and allow the ad9853 to pull it low. a valid write sequence consists of a minimum of three bytes. this means 27 clock pulses (three bytes with nine clock pulses each) must be provided by the bus master. the first byte is a chip address byte that is predefined except for bit positions 1 and 0. bit positions 7, 6, 5, 4 and 3 must be zero. bit position 2 must be a one. bit 1 is set according to the external address pin on the ad9853 (1 if the pin is connected to +v s ; 0 if the pin is grounded). bit 0 is set to 1 if a read operation is desired, 0 if a write operation is desired. the second byte is a register address with valid addresses between 00h and 49h. an address which is outside of this range will not be acknowledged. the third byte is data for the address register. multiple data bytes are allowed and loaded sequentially. that is, the first data byte is written to the addressed register and any subsequent data bytes are written to subsequent register addresses. it is permissible to write all registers by issuing a valid chip address byte, then an address byte of 00h and then 72 (48h) data bytes. address 49h must be written independently, that is, not in conjunction with any other address. a valid read sequence consists of a minimum of four bytes (refer to figure 27). this means the bus master must provide 36 clock pulses (four bytes with nine cl ock pulses each). like the write sequence, the first two bytes are the chip address byte, with the read/write bit set to 0, and the readback register address. after the slave provides an acknowledge at the end of the register address, the master must present a start condition on the bus, followed by the chip address byte with the read/write bit set to a 1. the slave proceeds to provide an acknowledge. dur- ing the next eight clocks the slave will write to the bus from the register address. the master must provide an acknowledge on the ninth clock of this byte. any subsequent clocks from the master will force the slave to read back from subsequent regis- ters. at the end of the read-back cycle, the master must force a no-acknowledge and then a stop condition. this will take the slave out of read-back mode. not all of the serial control bus registers can be read back. registers (06hC11h) and (1ehC 47h) are write only. also, like the writing procedure, register 49h must be read from independently. input data synchronization the serial input data interface consists of two pins, the serial data input pin and a t x enable pin. the input data arrives at the bit rate and is framed by the t x enable signal as shown in figure 26. a high frequency sampling clock continuously samples the t x enable signal to detect the rising edge. once the rising edge of t x enable is detected, an internal sampler strobes the serial data at the correct point in time relative to the positive t x enable transition and then continues to sample at the correct interval based on the programmed input data rate. for proper synchronization of the ad9853, 1) the input burst data must be accurately framed by t x enable and 2) the input data rate must be an exact even submultiple of the system clock. typically this will require that the input data rate clock be synchronized with reference clock. reed-solomon encoder the ad9853 contains a programmable reed-solomon (r-s) encoder capable of generating an (n, k) code where n is the code word length and k is the message length. error correction becomes vital to reliable communications when the transmission channel conditions are less than ideal. the original message can be precisely reconstructed from a cor- rupted transmission as long as the number of message errors is within the encoders limits. when forward error correction (fec) is engaged, either through the serial control interface bus or hardware (logic high at pin 5), it is implemented using the following mcns-compatible field generator and primitive polynomials: primitive polynomial: p ( x ) = x 8 + x 4 + x 3 + x 2 + 1 code generator polynomial: g ( x ) = ( x + a 0 )( x + a 1 )( x + a 2 ) . . . ( x + a 2t C 1 ) the code-word structure is defined as follows: n = k + 2 t ( bytes ) where: n = code-word length k = message length (in bytes), programmable from 16C255 t = number of byte errors that can be corrected p rogrammable from 0C10. a code word is the sum of the message length (in bytes) and number of check bytes required to correct byte errors at the
ad9853 C16C rev. c receive end. the values actually programmed on the serial con- trol bus are k and t, which will define n as shown in the above code-word structure equation. as can be seen from the code-word structure equation, two check bytes are required to correct each byte error. setting t = 0 and k > 0 will bypass the reed-solomon encoding process. since reed-solomon works on bytes of information and not bits, a single byte error can be as small as one inverted bit out of a byte, or as large as eight inverted bits of one byte; in either instance the result is one byte error. for example, if the value t is specified as 5, the r-s fec could be correcting as many as 40, or as few as 05, erroneous bits, but those errors must be contained in 5 message bytes. if the errors are spr ead among more than five bytes, the message will not be fully error corrected. when using the r-s encoder, the message data needs to be partitioned or gapped with dont care data for the time duration of the check bytes as shown in the timing diagram of figure 26. during the intervals between message data, the de- vice ignores data at the input. the position of the r-s encoder in the coding data path can be switched with the randomizer by exercising register 1, bit d3, via the serial control bus. randomizer function the next stage in the modulation chain is the randomizing or scrambling stage. randomizing is necessary due to the fact that impairments in digital transmission can be a function of the statistics of the digital source. receiver symbol synchronization is more easily maintained if the input sequence appears random or equiprobable. long strings of 0s or 1s can cause a bit or symbol synchronizer to lose synchronization. if there are repeti- tive patterns in the data, discrete spurs can be produced, caus- ing interchannel interference. in modulation schemes relying on suppressed carrier transmission, nonrandom data can increase the carrier feedthrough. us ing a randomizer effectively whitens the data. the technique used in the ad9853 to randomize the data is to perform a modulo 2 logic addition of the data with a pseudo- random sequence. the pseudorandom sequence is generated by a shift register of length m with an exclusive or combination of the nth bit and the last (mth) bit of the shift register that is fed back to the shift register input. by choosing the appropriate feedback point, a maximal length sequence is generated. the maximal length sequence will repeat after every 2 m clock cycles, but appears effectively random at the output. the criterion for maximal length is that the polynomial 1 + x n + x m be irre- ducible and prime over the galois field. the ad9853 contains the following two polynomial configurations in hardware: x 15 + x 14 +1 :mcns (docsis) compatible. x 6 + x 5 +1 :davic/dvb compatible. the seed value is fully programmable for both configurations. the seed value is reset prior to each burst and is used to calcu- late the randomizer bit, which is combined in an exclusive xor with the first bit of data from each burst. the first bit of data in a burst is the msb of the first symbol following the last symbol of the internally generated preamble. preamble insertion block as shown in the block diagram of the ad9853, the circuit in- cludes a programmable preamble insertion register. this register is 96 bits long and is transmitted upon receiving the t x enable signal. it is transmitted without being reed-solomon encoded or scrambled. ramp-up data, to allow for receiver synchroniza- tion, is included as the first bits in the preamble, followed by user burst profile or channel equalization information. the first bit of r-s encoded and scrambled information data is timed to immediately follow the last bit of preamble data. for most modulation modes, a minimum preamble is required. this minimum is one symbol, two bits for dqpsk or four bits for either 16-qam or d16-qam. no preamble is required for either fsk or qpsk. in conformance with davic/dvb standards, the preamble is not differentially coded in dqpsk mode. however the pre- amble data can be differentially precoded when loaded into the preamble register. the last symbol of the preamble is used as the reference point for the first internal differentially coded symbol so the preamble and data will effectively be coded differ- entially. in the d16-qam mode, the preamble is always differ- entially coded internally. modulation encoder the preamble, followed by the encoded and scrambled data is then modulation encoded according to the selected modulation format. the available modulation formats are fsk, qpsk, dqpsk, 16-qam and d16-qam. the corresponding symbol constellations support the interactive hfc cable specifications called out by mcns (docsis), 802.14 and davic/dvb. the data arrives at the modulation encoder at the input bit rate and is demultiplexed as modulation encoded symbols into sepa- rate i and q paths. for qpsk and dqpsk, the symbol rate is one-half of the bit rate and each symbol is comprised of two bits. for 16-qam and d16-qam, the symbol rate is one- fourth the bit rate and each symbol is comprised of four bits. in the fsk mode, although the 1 and 0 data is entered into the serial data input, it effectively bypasses the encoding, scrambling and modulation paths. the fsk data is directly routed to the direct digital synthesizer (dds) where it is used to switch the dds between two stored tuning words (f0:f1) to achieve fsk modulation in a phase-continuous manner. by holding the input at either 1 or 0, a single frequency continuous wave can be output for system test or cw transmission purposes. differential encoding of data is frequently used to overcome phase ambiguity error or a false lock condition that can be introduced in carrier-recovery circuits used to demodulate the signal. in straight qpsk and 16-qam, the phase of the re- ceived signal is compared to that of a recovered carrier of known phase to demodulate the signal in a coherent manner. if the phase of the recovered carrier is in error, then demodulation will be in error. differential encoding of data at the transmit end eliminates the need for absolute phase coherency of the recov- ered carrier at the receive end. if a coherent reference generated by a phase lock loop experiences a phase inversion while de- modulating in a differentially coded format, the errors would be limited to the symbol during which the inversion occurred and the following symbol. differential coding uses the phase of the previously transmitted symbol as a reference point to compare to the current symbol. the change in phase from one symbol to
ad9853 C17C rev. c the next contains the message information and is used to de- modulate the signal instead of the absolute phase of the signal. the transmitter and receiver must use the same symbol deriva- tion scheme. differential encoding in the ad9853 occurs while data still exists as a serial data stream. when in straight qpsk or 16-qam, the serial data stream p asses to the symbol mapper/format en- coder stage without modification. when differential encoding is engaged, the serial data stream is modified prior to the symbol mapper/format stage according to table vi. only i1 and q1 are modified, even in the d16-qam mode whose symbols are com- posed of q1, i1, q0, i0. in d16-qam, only the two msbs of the 4-bit symbol are modified; furthermore, the previously transmitted symbol referred to in table vi are the two msbs of the previous 4-bit symbol. symbol mapping for qpsk and dqpsk are identical. symbol mapping for 16-qam and d16-qam are slightly different (see figure 37) in accordance with mcns (docsis) specifications. special note: for most modulation modes, a minimum pre- amble is required. for dqpsk the minimum preamble is one symbol (2 bits) and for either 16-qam or d16-qam the mini- mum preamble is one symbol (4 bits). for fsk or qpsk, no preamble is required. user should be additionally aware that in the dqpsk mode, the preamble is not differentially encoded in accordance with mcns (docsis) specifications. if the preamble must be dif- ferentially encoded, it can pre-encoded using the derivation in table vi. in d16-qam, the preamble is always differentially encoded as is the payload data. when initiating a new differentially encoded transmission, the previously transmitted symbol is always the last symbol of the preamble. programmable pulse-shaping fir filters the i and q data paths of the modulator each contain a pulse shaping filter. each is a 41-tap, linear phase fir . they are used to provide bandwidth containment and pulse shaping of the data in order to minimize intersymbol interference. the filter coeffi- cients are programmable, so any realizable linear phase response characteristic may be implemented. the linear phase restriction is due to the fact that the user may only define the center coeffi- cient and the lower 20 coefficients. the hardware fills in the upper 20 coefficients as a mirror image of the lower 20. this forces a linear phase response. it should also be noted that the pulse shaping filter upsamples the symbol rate by a factor of four. normally, a square-root raised cosine (srrc) response is desired. in fact, the ad9853 evaluation board softw are driver implements an srrc response. when using the srrc response, an excess bandwidth factor ( a ) is defined that affects the low pass roll-off characteristic of the filter (where 0 a 1). when a = 0, the srrc is an ideal low-pass filter with a brick wall at one-half of the symbol rate ( the nyquist bandwidth of the data). although this provides maximum bandwidth containment, it has the ad- verse affect of causing the tails of the time domain response to be large, which increases intersymbol interference (isi). on the other hand, when a = 1, the srrc yields a smooth roll-off characteristic that significantly reduces the time domain tails, which improves isi. unfortunately, the cost of this benefit is a doubling of the bandwidth of the data signal. val ues of a between 0 and 1 yield a tradeoff between excess bandwidth in the fre- quency domain and tail suppression in the time domain. the fir filter coefficients for the srrc response may be calcu- lated using a variety of methods. one such method uses the inverse fourier transform integral to calculate the impulse re- sponse (time domain) from the srrc frequency response (fre- quency domain). an example of this method is shown in figure 33. of course, this method requires that the srrc frequency response be known beforehand. the fir filters in the ad9853 are implemented in hardware using a fixed point architecture of 10-bit, twos complement integers. thus, each of the filter coefficients, a i , is an integer such that: C512 a i 511 [i = 0, 1, , 40] programmable interpolation filters the ad9853 employs two stages of interpolation filters in each of the i and q channels of the modulator. these filters are implemented as cascaded integrator-comb (cic) filters. cic filters are unique in that they not only provide a low-pass fre- quency response characteristic, but also provide the ability to have one sampling rate at the input and another sampling rate at the output. in general, a cic filter may either be used as an interpolator (low-to-high sample rate conversion) or as a decimator (high-to-low sample rate conversion). in the case of the ad9853, the cic filters are configured as interpolators, only. furthermore, the interpolation is done in two separate stages with each stage designed so that the rate change is pro- grammable. the first interpolator stage offers rate change ratios of 3 to 31, while the second stage offers rate change ratios of 2 to 63. as stated in the previous section, the data coming out of the fir filters is oversampled by four. spectral images appear at their output (a direct result of the sampling pro cess). these images are replicas of the baseband spectrum w hich are re- peated at intervals of four times the symbol rate (the rate at which the fir filters sample the data). the images are an un- wanted byproduct of the sampling process and effectively repre- sent a source of noise. normally, the output of the fir filters would be fed directly to the input of the i and q modulator. this means that the spectral images produced by the firs would become part of the modu- lated signaldefinitely not a desirable consequence. this is where the cic filters play their role. since they have a low-pass characteristic, they can be used to eliminate the spectral images produced by the firs. frequency response of the cic filters the frequency response of a cic filter is predictable. it can be shown that the system function of a cic filter is: hz z k k rm n () = ? ? ? ? - = - ? 0 1 where n is the number of cascaded integrator (or comb) sec- tions, r is the rate change ratio, and m is the number of unit delays in each integrator/comb stage. for the ad9853, two of these variables are fixed as a result of the hardware implementa- tion; specifically, n = 4 and m = 1. as mentioned earlier, r (the rate change ratio) is programmable.
ad9853 C18C rev. c square-root raised cosine (srrc) fir filter compute and plot srrc filter coefficients: ...map the filter tap index to time domain (centered at t=0) ...inverse fourier integral compute srrc impulse response (time domain) from the srrc frequency response (frequency domain). the cos() function replaces the normal complex exponential because we are restricted to real filter coefficients. ...srrc filter coefficients integerized and scaled ...fir filter coefficients compute and plot srrc frequency response: ...define number of frequency points and frequency step size (for plotting purposes) ...create vector of uniformly spaced frequency points {f max = 0.5; a requirement of the gain() function}, ...normalized frequency response ...excess bandwidth factor for srrc frequency response ...bandwidth of srrc filter (relative to symbol rate) ...processing gain of cic filters (used to correlate results with ad9853 eval. bd.) ...sets max value of srrc filter based on finite word size ...number of fir pulse shaping filter taps ...upsampling ratio of fir pulse shaping filter (relative to the symbol rate) ...returns 1 if a <= x <= b, 0 otherwise ...returns nearest integer to x ...ratio to decibel conversion function ...srrc frequency response function (f is relative to the symbol rate) 500 0 10 5 0 152025303540 h tap tap srrc impulse response frequency scale C f n h n C db 0 0 C20 C40 C60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 frequency scaled to symbol rate srrc normalized frequency response 0 1 2 3 4 5 6 7 8 9 101112131415 16 17 18 19 20 h t = 0 0 3 2 C2 C5 C2 5 7 1 C7 C7 7 19 7 C34 C71 C48 71 260 438 511 tap := 0..taps C 1 t tap := 1 freqscale tap C taps C 1 2 . bw 0 h(t) := h tap := h(t tap ) h := int h scaleproc gain max(h) . 0.5 freq_pts C 1 d f := freq_pts := 250 n := 0..freq_pts C 1 f n := d f n . k := (| gain(h,0) |) C1 h n := k | gain (h,f n ) | . global declarations constants: a 0.5 proc_gain 1 bw 0.5 (1 + a ) . scale 511 taps 41 freqscale 4 functions: inrange (x,a,b) (x a) . (x b) int(x) floor (x + 0.5) db(x) if (| x | = 0, 200, 20 log (| x |)) . srrc(f) passband 0.5 (1 C a ) . stopband 0.5 (1 + a ) if inrange (f, 0, stopband) 1 if inrange (f, 0, passband) cos p 4 a . . . (2 f + a C 1) if inrange (f, passband, stopband) 0 otherwise srrc(f) cos(2 p f t)df .... figure 33. mathcad simulation of a 41-tap srrc filter
ad9853 C19C rev. c the frequency response, h(f), of a cic filter is found by evalu- ating h(z) at z = e j(2 p f/r) : hf e jfrk k rm n () / = ? ? ? ? ? - () = - ? 2 0 1 p where f is relative to the input sample rate of the cic filter. with this formula, we can accurately predict the frequency response of the cic filters. compensating for cic roll-off as discussed previously, the cic filters offer a low-pass charac- teristic that can be used to eliminate the spectral images pro- duced by the fir filters. unfortunately, the cic response is not flat over the frequency range of the baseband signal. thus, the inherent attenuation (or roll-off) of the cic filters distorts the baseband data signal. so even though the cic filters help to eliminate the images described earlier, they introduce another form of error to the baseband signalfrequency-dependent amplitude distortion. this ultimately manifests itself as a higher level of error vector magnitude (evm) at the output of the i and q modulator. also, the larger the bandwidth of the baseband signal, the more pronounced the cic roll-off, the greater the amplitude distortion and the worse the evm perfor- mance. this is a serious problem because if a value of a =1 is used for the srrc response of the fir filters, a doubling of the bandwidth of the baseband signal results and hence, a degrada- tion in evm performance. fortunately, there is a way to compensate for the effects of cic roll-off. since the frequency response of the cic filters is pre- dictable, it is possible to compensate for the cic roll-off charac- teristic by adjusting the response of the fir filters accordingly. the adjustment is accomplished by modifying the fir filter response with a response that is the inverse of that of the cic filters. this is done by precompensating the fir filters. to perform cic compensation, we simply define a function (h comp ) that has a response which is the inverse of the cic response. specifically, hf hf comp () = () 1 by multiplying the original fir filter frequency response by h comp , we obtain the necessary compensation. unfortunately, its not quite this simple. recall that the coeffi- cients of the baseband filter were computed using an inverse fourier transform integral w hich included the srrc function. in order to compensate for the cic filter response, the srrc function must be multiplied by the h comp function. but the frequency scale of the srrc response is computed based on frequencies relative to the symbol rate, while the h comp func- tion is computed relative to the input sampling rate of the cic filter. the input cic sampling rate happens to be the same as the sample rate of the fir filter (see figure 36), or four times the symbol rate. thus, we have a frequency scaling problem. this problem is easily corrected by introducing a frequency scaling factor (freqscale = 4) into the h comp function so that the frequency scales of the two functions match. thus, the actual h comp function required is given by: h h f freqscale comp = ? ? ? ? 1 it should be noted that in compensating for the cic roll-off, only the first stage cic filter need be considered. this is due to the fact that at the output of the first stage cic filter the bandwidth of the signal is reduced to the point that the roll-off introduced by the second stage is negligible in the region of the baseband signal. the cic compensation method is demonstrated by example (using mathcad) in figures 34 and 35. an interpolation rate (r) of 6 is used in the example. the improvement obtained by compensating for the cic response is graphically demonstrated in figure 35 which shows: the srrc filter response (which is the desired overall response) the composite response of the srrc in series with the cic filter (distorted response) the composite response of the compensated srrc in series with the cic (corrected response) note that the ideal srrc response and the compensated com- posite response are virtually identical in the region of the pass- band. thus, the goal of correcting for the cic filter response has been accomplished. there is one subtlety to be noted in the example. the cic compensation is only applied to the first 90% of the bandwidth of the baseband signal (note the variable b inside the integral). it was found that compensation over the full 100% of the band- width produced a reduction in the suppression of signals in the stopband region of the srrc. this resulted in creating more distortion than by not correcting for the cic roll-off in the first place. however, by slightly reducing the bandwidth over which correction is applied, the stopband suppression is once again restored and a significant improvement in evm performance is obtained. determining the necessary interpolator rate change ratio the ad9853 contains three stages of digital interpolation: 1) fixed 4 pulse shaping fir filter. 2) programmable 3 to 31 first interpolation filter. 3) programmable 2 to 63 second interpolation filter. after the serial input data stream has been encoded into qpsk or 16-qam symbols, the symbol interpolation rate of the ad 9853 is determined by the product of the three interpolating stages listed above. in qpsk m ode, the minimum symbol interpolation rate that will work is 4 3 2 = 24; for 16-qam the minimum is 4 4 3 = 48. the maximum symbol interpolation rate is 4 31 63 = 7812. the symbol rate at the encoder output for qpsk is equal to 1/2 the bit rate of the data and for 16-qam it is 1/4 the bit rate. figure 36 is a partial block diagram of the ad9853 and follows the path of the data stream from the input of the i and q encoder block to the output of the dac.
ad9853 C20C rev. c cos(2 p f t)df ... . bw 0 h1(t) := r := 6 f b bw, . srrc (f) if . h(0,r) h f freqscale ,r ,1 modification of square-root raised cosine (srrc) fir filter response to compensate for cascaded integrator-comb (cic) filter response compute srrc filter coefficients: ...map the filter tap index to time domain (centered at t = 0) ...inverse fourier integral computes srrc impulse response (time domain) from the srrc frequency response (frequency domain). the cos() function replaces the normal complex exponential because we are resticted to real filter coefficients. ...srrc filter coefficients integerized and scaled compute srrc filter coefficients modified for correction of cic response: ...cic interpolation ratio (user programmable) ...inverse fourier intergral modifies the srrc response by the reciprocal of the normalized cic frequency response. the modification is only performed over the fraction of the srrc bandwidth as specified by b . ...modified srrc filter coefficients integerized and scaled to 10-bit range srrc and modified srrc impulse response ...fir filter coefficients for srrc response ...fir filter coefficients for srrc response with cic compensation display frequency response plots: f:= 0,0.001.. 0.5 ...normalized frequency range [a requirement of mathcad's gain() function] ...scale factors to adjust srrc, compensated srrc, and cic frequency responses to unity at f = 0 ...function to compute normalized, uncompensated fir response (srrc) in db ...function to compute normalized cic response in db ...function to compute normalized, compensated fir response (srrc + cic C1 ) in db ...function to compute overall system response of srrc and cic together in db ...function to compute overall system response of compensated srrc and cic together srrc, cic, and corrected srrc response 10 5 0 15 20 25 30 35 40 tap 500 0 h tap h1 tap frequency scale C f n 0 0 C20 C40 C60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fir(f) cic(f) comp(f) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 0 3 2 C2 C5 C2 5 7 1 C7 C7 7 19 7 C34 C71 C48 71 260 438 511 h t = h1 t = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 14 2 C3 C6 C1 7 9 1 C10 C9 8 24 12 C34 C78 C61 56 251 435 511 tap := 0..taps C 1 t tap := 1 freqscale tap C taps C 1 2 . bw 0 h(t) := srrc(f) cos(2 p f t)df .... h tap := h(t tap ) h := int h proc_gainscale max(h) . scalesrrc := (| gain(h,0) |) C1 h1 tap := h1(t tap ) h1 := int h1 proc_gainscale max(h1) . scalecompsrrc := (| gain(h1,0) |) C1 scalecic := (| h(0,r) |) C1 scalesrrc := 5.559 10 C4 . scalecompsrrc := 5.79 10 C4 . scalecic := 7.716 10 C4 . fir(f) := db(scalesrrc | gain(h,f) |) . cic(f) := db(scalecic | h(f,r) |) . comp(f) := db(scalecompsrrc | gain(h1,f) |) . sysuncomp(f) := fir(f) + cic(f) syscomp(f) := comp(f) + cic(f) figure 34. mathcad simulation of 41-tap srrc filter with cic compensation
ad9853 C21C rev. c frequency scale C f frequency scaled to symbol rate 2 0 C10 C22 C34 0.1 0.2 0.3 0.4 0.5 0.6 0.7 passband detail frequency scale C f frequency scaled to symbol rate 0 0 C20 C40 C60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fir(f) sysuncomp(f) syscomp(f) response of normal srrc, normal srrc + cic, and compensated srrc + cic fir(f) sysuncomp(f) syscomp(f) ...excess bandwidth factor for srrc frequency response ...portion of srrc bandwidth over which apply cic correction (0< b <= 1) ...bandwidth of srrc filter (relative to symbolrate) ...number of fir pulse shaping filter taps ...sets max value of fir pulse shaping filter based on finite word size ...upsampling ratio of fir pulse shaping filter (relative to the symbol rate) ...processing gain of cic filters (used to correlate results with ad9853 eval. bd.) ...number of comb/integrator stages in cic filter ...unit delays per stage of cic filter ...returns 1 if a<= x <= b, 0 otherwise ...returns nearest integer to x ...ratio to decibel conversion function ...srrc frequency response function (f is relative to the symbol rate) ...z transform ...cic filter time index frequency response function Ck f r z h(f,r) r m C 1 . k = 0 n s global declarations constants: a 0.5 proc_gain 1 bw 0.5 (1+ a ) . scale 511 taps 41 freqscale 4 functions: inrange (x,a,b) (x a) . (x b) int(x) floor(x + 0.5) db(x) if (| x | = 0, C200, 20 log (| x |)) . . . srrc(f) passband 0.5 (1 C a ) stopband 0.5 (1 + a ) 1 if inrange (f, 0, stopband) if inrange (f, 0, passband) cos p 4 a . . . (2 f + a C 1) if inrange (f, passband, stopband) 0 otherwise b 0.9 n 4 m 1 z(f) e 2 j p f .. figure 35. mathcad simulation (continued)
ad9853 C22C rev. c the goal of interpolation is to up-sample the baseband informa- tion to the system clock rate and to suppress aliases in the pass- band. the system clock rate is the sample rate of the sine and cosine signal carriers generated by the dds in the quadrature modulator stage. alias suppression is accomplished by the cic filters as described previously. for timing synchronization, the overall interpolation rate must be set such that the bit rate of the baseband signal be an even integer factor of the system clock rate. the importance of the relationship between the data and system clock rates can not be overstressed. it is restated here for clarity: the system clock rate must be an even integer multiple of the data bit rate. following is a design example that demonstrates the principles outlined above. system requirements: ? baseband bit rate 1.024 mb/s ? carrier frequency 49 mhz ? modulation scheme 16-qam ? system power 3.3 v it should be noted that with a 3.3 v power supply, the maxi- mum system clock rate of the ad9853 is 126 mhz. this sets an upper bound on the system clock. the first consideration is to make sure that the required carrier frequency is within the ad9853s output frequency range. the carrier frequency should be 40% of the system clock rate. the given carrier frequency requirement of 49 mhz means that a minimum system clock rate of 122.5 mhz is required; a value within the range of the ad9853s 126 mhz capability. we must next ensure that the system clock rate is an even inte- ger multiple of the input bit rate. dividing the system clock rate (122.5 mhz) by the data rate (1.024 mbps) yields 119.63. obviously this is not an integer, so we must select the nearest even integer value (in this case, 120) as the data rate multiplier. thus, a system clock rate of 122.88 mhz is required (120 1.024 mbps). with 6 refclk engaged, the reference clock input will be 1/6th of the system clock rate, or 20.48 mhz. finally, the two interpolator rates must be determined. since the fir filter and interpolator stages will be operating on 16-qam symbols, the data rate must be converted from bits/second to symbols/second (baud). each 16-qam symbol is composed of four serial data bits. therefore, the baud rate at the input to the fir filter is 1.024 mbps/4 = 256k baud. the fir pulse shaping filters up-sample by a factor of 4. this fixes the fir sample clock at 256k baud 4, or 1.024 msps. with the fir sampling at a 1.024 msps rate, and a previously determined system clock rate of 122.88 mhz, the interpolators must up- sample by a factor of 120 (122.88/1.024 = 120). rule of thumb: divide the interpolating burden as equally as possible among the two interpolators. since the required rate change ratio is 120, select a value of 10 for interpolator #1 and 12 for interpolator #2 (10 12 = 120). this satisfies the requirements for the two programmable inter- polator stages. thus far we have established the rate change ratios for the inter- polators. however, there is an additional consideration. by default, the interpolators have an intrinsic gain (or loss) that is dependent on the selected interpolation rate. since there is the potential to have overall cic gains of greater than unity, care must be taken to avoid the occurrence of overflow in the interpolators. interpolator scaling proper signal processing in the ad9853 depends on data propa- gating through the pulse-shaping filter and interpolator stages with as flat a baseband response as possible. in addition to the frequency response issue, it is also necessary to ensure that the numerical data propagating through the interpolators does not result in an overflow condition. as mentioned earlier, the interpolators are implemented using a cic filter. in the ad9853, the cic filter is designed using fixed-point processing and two cascaded cic filter sections (interpolator #1 and interpolator #2). it is important to under- stand that in a cic filter, the integration portion of the circuit will require the accumulation of values based on the rate change factor, r . this means that the size of the data word grows in a manner dependent on the choice of r. in the case of interpola- tor #1, the circuit is designed around a maximum r of 32 and this results in an output register width of 28 bits. the design of interpolator #2 requires an output register width of 25 bits. i & q encoder i q 3 symbol clock 4 4 41 - tap fir 12 41 - tap fir 12 mux 2 3 2 3 13 inter- polator #1 scaler 28 13 inter- polator #2 scaler 25 10 system clock m = 3...31 n = 2...63 13 28 13 25 10 scaler inter- polator #2 scaler inter- polator #1 mux 10 20 dds inverse sinc filter dac 20 10 1 3 sin( v c ) cos( v c ) 10 4 m 4 n figure 36. block diagram of ad9853 data path and clock stages
ad9853 C23C rev. c these register widths have been chosen to accommodate the highest values of r for each interpolator. when values of r are chosen that are less than the maximum value, then data will accumulate only in the lesser significant bits of the output regis- ter. this is an important point to consider since only 13 bits of 28 are passed on from interpolator #1 to interpolator #2, and only 10 bits of 25 are passed on from interpolator #2 to the i and q modulator (see figure 36). if only the most significant bits were to be passed on, then low r values would result in most (possibly all) of the bits being 0s because data would have accumulated only in the less significant bits of the output regis- ter. obviously, it is necessary to have a mechanism that allows one to select which group of bits to pass on to the next stage in order to prevent the loss of data by truncation. in the ad9853 this mechanism is handled by means of the interpolator #1 and #2 scaling registers (control bus addresses 14h and 15h). the scaling word w ritten into each register selects a group of bits at the output of the appropriate interpolator. in the case of interpolator #1 this is a 13-bit group, while in the case of interpolator #2 it is a 10-bit group. inspection of the scaling registers indicates that interpolator #1 uses a 5-bit scaling word while interpolator #2 uses a 6-bit scaling word. at first inspection it would seem as though there are 32 and 64 scaling steps for interpolator #1 and #2, respectively. this is not the case, however. the scaling word is actually decoded in a nonlinear manner and there is considerable overlap; i.e., several different register values may actually select the same group of bits at the interpolator output. table iii lists the relationship between the scaling word value and the highest bit of the inter- polator output register which becomes the most significant bit (msb) of the group selected. table iii. interpolator scale bit selection interpolator #1 interpolator #2 highest bit highest bit scaling selected scaling selected register from register from value output value output (decimal) register (decimal) register 012 012 115 114 216 215 3C4 18 3C4 16 5 19 5C6 17 6 20 7C10 18 7C9 21 11C14 19 10C11 22 15C21 20 12C14 23 22C30 21 15C19 24 31C44 22 20C24 25 45C62 23 25C30 26 63 24 31 27 selection of the proper scaling value is dependent on the selec- tion of r for the interpolator. it is desirable to choose a scale value that ensures that the msb of the selected group of bits coincides with the highest useful bit in the output register. to accomplish this condition, use the following rule: scaling rule : for a particular interpolator, choose a nominal scaling register value that is one less than the interpolation rate (r) for the same interpolator. for example, if interpolator #1 is set for an interpolation rate of 6, then choose a scaling register value of 5 for interpolator #1. it has already been mentioned that the required number of bits at the output of the cic filter is a function of r. it turns out that for values of r that are a power of 2, the number of bits required to handle the growth of the output register is an inte- ger. this results in a processing gain of unity for the cic filter. for values of r that are not a power of 2, the required number of output bits is not an integer. this results in a processing gain that is not unity. tables iv and v detail the relationship be- tween the scaling register values and the processing gain for interpolator #1 and interpolator #2. note that certain scale register values for a particular r yield a processing gain greater than unity. thus, it is possible that the nominal scaling register values will result in a total cic processing gain of > 1. warning: it is of utmost importance the user make certain that the total processing gain of the data path be 1. that is, the product of the fir gain, interpolator #1 gain, and interpolator #2 gain must be 1. this is because total process- ing gains of > 1 may result in an overflow condition within the cic filters, which puts the hardware in a nonrecoverable state (short of resetting the device). the contents of tables iv and v offer the user some flexibility in the choice of processing gains for a particular interpolation rate. for example, let us assume that an overall interpolation rate of 25 is required. a value of r = 5 for both interpolators satisfies this requirement, which leads to a scale register value of 4 for each interpolator. note, however, that under these conditions the processing gain for the cic filters alone is 3.053 (1.953 1.563). there are two ways in which we can handle this situation. the first is to scale the coefficients of the fir filter by 0.3275 (1/3.053), which reduces the total processing gain to 1. the disadvantage here is that the fir coefficients are 10-bit signed integers and scaling by 0.3275 may result in an unacceptable level of trunca- tion caused by the finite resolution. the second method makes use of tables iv and v. we can choose the alternate scale value of 5 (instead of 4) for interpolator #2. this results in a processing gain of 1.525 (1.953 0.781). we can now scale the fir coefficients by a more modest value of 0.6557 (1/1.525) and net an overall gain of unity through the three stages. of course, we could just as easily have chosen the alternate scale value for interpolator #1 and modified the fir coefficients accordingly. typically, the choice of interpolator scale values that results in an overall gain closest to (but not less than) one is selected. then the fir coefficients are scaled downward to yield unity gain.
ad9853 C24C rev. c table iv. interpolator #1 rate nominal change scale alternate factor value nominal scale resulting (r) (r-1) gain value gain 03 02 1.688 03 0.844 04 03 1.000 05 0.500 05 04 1.953 05 0.977 06 05 1.688 06 0.844 07 06 1.340 07 0.670 08 07 1.000 10 0.500 09 08 1.424 10 0.712 10 09 1.953 10 0.977 11 10 1.300 12 0.650 12 11 1.688 12 0.844 13 12 1.073 15 0.536 14 13 1.340 15 0.670 15 14 1.648 15 0.824 16 15 1.000 20 0.500 17 16 1.199 20 0.600 18 17 1.424 20 0.712 19 18 1.675 20 0.837 20 19 1.953 20 0.977 21 20 1.130 25 0.565 22 21 1.300 25 0.650 23 22 1.485 25 0.743 24 23 1.688 25 0.844 25 24 1.907 25 0.954 26 25 1.073 31 0.536 27 26 1.201 31 0.601 28 27 1.340 31 0.670 29 28 1.489 31 0.744 30 29 1.648 31 0.824 31 30 1.818 31 0.909 table v. interpolator #2 rate nominal change scale alternate factor value nominal scale resulting (r) (r-1) gain value gain 02 01 1.000 02 0.500 03 02 1.125 03 0.563 04 03 1.000 05 0.500 05 04 1.563 05 0.781 06 05 1.125 07 0.563 07 06 1.531 07 0.766 08 07 1.000 11 0.500 09 08 1.266 11 0.633 10 09 1.563 11 0.781 11 10 1.891 11 0.945 12 11 1.125 15 0.563 13 12 1.320 15 0.660 14 13 1.531 15 0.766 15 14 1.758 15 0.879 16 15 1.000 22 0.500 17 16 1.129 22 0.564 18 17 1.266 22 0.633 19 18 1.410 22 0.705 20 19 1.563 22 0.781 21 20 1.723 22 0.861 22 21 1.891 22 0.945 23 22 1.033 31 0.517 24 23 1.125 31 0.563 25 24 1.221 31 0.610 26 25 1.320 31 0.660 27 26 1.424 31 0.712 28 27 1.531 31 0.766 29 28 1.643 31 0.821 30 29 1.758 31 0.879 31 30 1.877 31 0.938 32 31 1.000 45 0.500 33 32 1.063 45 0.532 34 33 1.129 45 0.564 35 34 1.196 45 0.598 36 35 1.266 45 0.633 37 36 1.337 45 0.668 38 37 1.410 45 0.705 39 38 1.485 45 0.743 40 39 1.563 45 0.781 41 40 1.642 45 0.821 42 41 1.723 45 0.861 43 42 1.806 45 0.903 44 43 1.891 45 0.945 45 44 1.978 45 0.989 46 45 1.033 63 0.517 47 46 1.079 63 0.539 48 47 1.125 63 0.563 49 48 1.172 63 0.586 50 49 1.221 63 0.610 51 50 1.270 63 0.635 52 51 1.320 63 0.660 53 52 1.372 63 0.686 54 53 1.424 63 0.712 55 54 1.477 63 0.739 56 55 1.531 63 0.766 57 56 1.586 63 0.793 58 57 1.643 63 0.821 59 58 1.700 63 0.850 60 59 1.758 63 0.879 61 60 1.817 63 0.908 62 61 1.877 63 0.938 63 62 1.938 63 0.969
ad9853 C25C rev. c 10 (01) 00 (00) 01 (10) 11 (11) q i a. qpsk symbol mapping 1011 (0111) 1010 (0101) 1000 (0100) 1001 (0110) q i 0001 (0010) 0011 (0011) 0010 (0001) 0000 (0000) 0100 (1000) 0101 (1010) 0111 (1011) 0110 (1001) 1110 (1101) 1100 (1100) 1101 (1110) 1111 (1111) b. d16-qam symbol mapping 1011 (0111) 1001 (0110) 1000 (0100) 1010 (0101) q i 0001 (0010) 0011 (0011) 0010 (0001) 0000 (0000) 0100 (1000) 0110 (1001) 0111 (1011) 0101 (1010) 1110 (1101) 1100 (1100) 1101 (1110) 1111 (1111) c. 16-qam gray-coded symbol mapping figure 37. symbol mapping for qpsk, 16-qam, and dqam, spectrum = i cos + q sin (spectrum = i cos C q sin) mixers, adder, inverse sinc functions at the output of the interpolation filters, the pulse-shaped, up- sampled i and q baseband data is multiplied with digitized quadrature versions of the carrier, cos( w c t) and sin( w c t) respec- tively, which are provided by a direct digital synthesizer (dds) block. the dds block has a 32-bit tuning word that results in an extremely fine frequency tuning resolution of f clock /2 n , as well as extremely fast output frequency switching. the multiplier outputs are then summed to form the qpsk/qam-modulated signal. this signal is then filtered by an inverse sinc filter to compensate for the sinx/x roll-off function inherent in the digital-to-analog conversion process. the inverse sinc filter flattens the gain response across the nyquist bandwidth. this is most critical for higher data rate signals that are placed on carri- ers at the high end of the spectrum where the uncompensated sinx/x roll-off would be getting progressively steeper. gain attenuation across a channel will result in modulation quality impairments, such as degraded error vector magnitude (evm). the spectral inversion bit, when enabled, inverts the q data at the input to the adder circuit in the quadrature amplitude modulator section. this has the effect of reversing the direction of the phase rotation around the constellation map. positive phase rotation on the i/q constellation plane corresponds to counterclockwise movement. for example, the symbols in parentheses on the qpsk constellation in figure 37 corresponds to a spectral mapping of i cos C q sin. the phase rotation from symbol value 11 to 01 is a positive 90 degree rotation. traversing around the constellation in a positive direction, there are also positive 90 degree rotations from 01 to 00, 00 to 10, and 10 back to 11. if the spectral invert bit is disabled, providing the spectral map i cos + q sin as shown in figure 37, a phase rotation from symbol value 11 to 01 now corresponds to a nega- tive 90 degrees of phase rotation. similarly, there are now nega- tive 90 degree phase rotations from 01 to 00, 00 to 10 and 10 back to 11. in other words, the direction of phase rotation
ad9853 C26C rev. c around the constellation has simply been reversed. this effect also holds true for the 16-qam and d16-qam constellations shown in the respective i cos C q sin and i cos + q sin mappings shown in figure 37. direct digital synthesizer function the direct digital synthesizer (dds) block delivers the sine/cosine carriers that are digitally modulated by the i/q data paths. the dds function is frequency tuned via the control bus with a 32-bit tuning word. this allows the ad9853s output carrier frequency to be very precisely tuned while still providing output frequency agility. the equation relating output frequency of the ad9853 digital modulator to the frequency tuning word (ftword) and the reference clock (refclk) is given as: f out = ( ftword refclk )/2 32 where: f out and refclk frequencies are in hz and ftword is a decimal number from 0 to (2 32 )/2 example: find the ftword for f out = 41 mhz and refclk = 122.88 mhz if f out = 41 mhz and refclk = 122.88 mhz, then: ftword = 556aaaaa hex loading 556aaaaah into control bus registers 16hC19h programs the ad9853 for f out = 41 mhz, given a refclk frequency of 122.88 mhz. d/a converter up to this point all the processing has been in the digital domain. in order to pass the modulated signal onto the cable driver for amplification to the levels required to drive the 75 ohm cable, a digital-to-analog converter (dac) is implemented. the dac needs to have good enough transient characteristics so as not to add significant spurious in the spectrum. typically the worst spurs from the dac are due to harmonics of the fundamental signal and their aliases (please see the ad9850 complete-dds data sheet for a detailed explanation of aliased images). these harmonics are worst case for the higher carrier frequencies. the ad9853 contains a wideband 10-bit dac which maintains spurious-free dynamic range (sfdr) performance of C50 dbc up to 42 mhz a out and C44 dbc up to 65 mhz a out . the conversion process will produce aliased components at the dac output at n f clock f carrier (n = 1, 2, 3, ...). these are typically filtered with an external rlc filter between the dac and the line driver amplifier. again, it is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest so as to avoid the aforementioned modulation impairments. a relatively inexpen- sive seventh order elliptical low-pass filter is sufficient to sup- press the aliased components for hfc network applications. the ad9853 provides true and complement outputs, pins 24 and 25, which are current outputs. the full-scale output current is set by the r set resistor at pin 18. the value of r set for a particular i out is determined using the following equation: r set = 32 (1.248 v / i out ) for example, if a full-scale output current of 20 ma is desired, then r set = 32(1.248/0.02), or approximately 2 k w . every doubling of the r set value will halve the output current. maxi- mum output current is specified as 20 ma. the full-scale output current range of the ad9853 is 5 maC20 ma, with 10 ma being the optimal value for best spurious-free dynamic range (sfdr). full-scale output currents outside of this range will degrade sfdr performance. sfdr is also slightly affected by output matching, that is, for best sfdr, the two outputs should be equally terminated. the output load should be located as close as possible to the ad9853 package to minimize stray capacitance and inductance. the load may be a simple resistor to ground, an op amp cur- rent-to-voltage converter, or a transformer-coupled circuit. it is best not to attempt to directly drive highly reactive loads (such as an lc filter). driving an lc filter without a transformer requires that the filter be doubly terminated for best performance, that is, the filter input and output should both be resistively terminated with the appropriate values. the parallel combina- tion of the two terminations will determine the load that the ad9853 will see for signals within the filter passband. for ex- ample, a 50 w terminated input/output low-pass filter will look like a 25 w load to the ad9853. the resistor at the filter input will mask the reactive components of the lc filter and provide a termination for signals outside the filter pass band. the output compliance voltage of the ad9853 is C0.5 v to +1.5 v. any signal developed at the dac output should not exceed +1.5 v, otherwise, signal distortion will result. further- more, the signal may extend below ground as much as 0.5 v without damage or signal distortion. the use of a transformer with a grounded center-tap for common-mode rejection results in signals at the ad9853 dac output pins that are symmetrical about ground. as previously mentioned, by differentially combining the two signals the user can provide some degree of common-mode signal rejection. the amount of rejection is dependent upon how closely the common-mode signals of each output are matched in amplitude and phase. if the signals are exactly alike, then ideally, there would be 100 percent rejection in a perfect differential amplifier or combiner. a differential combiner might consist of a transformer or an op amp. the object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 hz hum or clock feed through that is present on both input sig- nals. the ad9853 true and complement outputs can be differ- entially combined and, in fact, are configured as such on the ad9853-xxpcb evaluation board. this evaluation board utilizes a broadband 1:1 transformer with a grounded, center- tapped primary to perform differential combining of the two dac outputs.
ad9853 C27C rev. c reference clock multiplier due to the fact that the ad9853 is a dds-based modulator, a relatively high frequency system clock is required. for dds applications the carrier is typically limited to about 40% of f clock . for a 65 mhz carrier, the system clock required is above 150 mhz. to avoid the cost associated with these high frequency references, and the aggravating noise coupling issues associated with operating a high frequency clock on a pc board, the ad9853 provides an on-chip 6 clock multiplier. with the 6 on-chip multiplier, the input reference clock required for the ad9853 can be kept in the 20 mhz to 30 mhz range, which results in cost and system implementation savings. the 6 refclk multiplier maintains clock integrity as evidenced by the ad9853s system phase noise characteristics of C100 dbc/hz and virtually no clock related spurious in the output spectrum. external loop filter components consisting of a series resistor (1.3 k w ) and capacitor (0.01 m f) provide the compensation zero for the 6 refclk pll loop. the overall loop perfor- mance has been optimized for these component values. table vi. derivation of currently transmitted symbol quadrant current msbs of msbs for input quadrant previously currently bits phase transmitted transmitted i q change symbol symbol 00 0 11 11 00 0 01 01 00 0 00 00 00 0 10 10 01 90 11 01 01 90 01 00 01 90 00 10 01 90 10 11 11 180 11 00 11 180 01 10 11 180 00 11 11 180 10 01 10 270 11 10 10 270 01 11 10 270 00 01 10 270 10 00 note: this table applies to both dqpsk and d16-qam formats. in dqpsk a symbol is comprised of two bits that are denoted as i(1) q(1). in this case, i(1) and q(1) are the msbs and the table can be interpreted directly. in d16-qam a symbol is defined as comprised of four bits denoted as i(1) q(1) i(0) q(0). i(1), q(1) are the msbs and i(0), q(0) are the lsbs. as indi- cated in the table, only the msbs i(1) and q(1) are altered as a function of the differential coding; i(0) and q(0) are not altered. device thermal considerations the ad9853 is specified to operate at an ambient temperature of up to +85 c. the maximum junction temperature (t j ) is specified at +150 c, which provides a worst case junction-to-air differential of +65 c. thus, with the specified q ja of +36 c/w, a maximum device dissipation of 1.8 w is achievable under the worst case conditions. it is important to understand that a sig- nificant portion of the heat generated by the device is trans- ferred to the environment via the package leads. the specified q ja value assumes that the device is soldered to a multilayer printed circuit board (pcb) with the device power and ground pins connected directly to power and ground planes of the pcb. the amount of power internally generated by the device is pri- marily dependent on four factors: ? power supply voltage ? system clock rate ? input data rate ?t x enable duty cycle (assuming the device is operated in the burst data mode) the power generated by the device increases with an increase in any one of the four factors. it turns out that the contribution of generated power due to the system clock rate, input data rate and t x enable duty cycle may be ignored at power supply voltages of less than 4 v (as the total power generated by the device will not exceed 1.8 w). however, for supply voltages greater than 4 v, operation at +85 c ambient temperature will require a tradeoff among the other three factors; i.e., a reduced system clock rate, a reduced data rate, a reduced t x enable duty cycle, or some combination of the three. it should be men- tioned, that operation at a power supply voltage of 4 v yields the same level of performance as specified at 5 v operation. for example, the user may still take advantage of the 165 mhz maximum system clock rate specified for 5 v operation. v dd i out i outb digital out v dd (b) v dd digital in (a) (c) figure 38. equivalent i/o circuits ad9853-xxpcb evaluation board two versions of evaluation boards are available for the ad9853 digital qpsk/16-qam modulator: the AD9853-45PCB and the ad9853-65pcb. the C 45 contains a 45 mhz low-pass filter to support a 5 mhzC42 mhz output bandwidth and the C65 has a 65 mhz low-pass filter to support a 5 mhzC65 mhz output bandwidth. both versions of the evaluation board contain the ad9853 device, a refclock oscillator, a seventh order elliptic low- pass filter of the designated frequency, an ad8320 program- mable cable driver amplifier, operating software for windows ? 3.1 or windows 95, and a booklet of complete operating in- structions and performance graphs. the evaluation board pro- vides an optimal environment for menu-driven programming of the devices and analysis of output spectral performance. part number on-board low-pass filter AD9853-45PCB 45 mhz ad9853-65pcb 65 mhz windows is a registered trademark of microsoft, corporation.
ad9853 C28C rev. c c33 10 m f +10v fec (sw2) functions jumper function 1-2 soft fec enable/disable 2-3 hard fec disable open hard fec enable or external fec control via j11 when using transformer t1a, remove r3 and r6 when not using t1a, connect e13 to e14 and leave r3 and r6 in place tst1 hi 4dm j9 2 4 6 8 10 12 14 1 3 5 7 9 11 13 rest e13 t1a t1 C 1t sig r6 25 v 4 2 6 1 : 1 e14 gnd ca en agnd iout ioutb test out2 test clk test latch tstdata in tstdata en tstdata out reset avdd dac bl avdd agnd dac rset nc agnd pll filter pll vcc pll gnd gnd ca clk ca data dgnd dvdd ref clk in dgnd dvdd data in tx enable dvdd dgnd dgnd dvdd bus clk fec en address bit dgnd dvdd dgnd dgnd testout1 busdat in ad9853 u1 34 cac cad dut+v clk dut+v sdi txe dut+v 44 tst1 smb j10 external fec enable r7 3.9k v +5v fecc 1 2 3 sw2 h3m digital modulator 22 12 21 20 19 18 17 16 15 14 13 c31 0.1 m f r4 3.9k v dut+v c10 0.01 m f 33 23 32 31 30 29 28 27 26 25 24 cae dut+v bdat bclk gnd 1 3 dut+v dut+v dut+v gnd gnd r5 1300 v dut+v note: c31 normally not populated 35 36 37 38 39 40 41 42 43 1 11 2345678910 c25 0.1 m f dut+v c24 0.1 m f dut+v c23 0.1 m f dut+v c30 0.1 m f dut+v c29 0.1 m f dut+v dac out/ filter in smb j6 e9 e1 e10 sig e2 sig r3 50 v c6 68pf (33pf) c3 7pf (6.8pf) 1 2 c9 56pf (39pf) e3 e4 e11 e12 amp smb j7 filter out/ amp in c7 100pf (82pf) c4 33pf (33pf) c5 22pf (27pf) c8 82pf (82pf) l1 120nh (180nh) l2 100nh (100nh) l3 100nh (150nh) 1 2 12 7th order eliptic 50 v low pass filter values in parentheses C 45 mhz filter values not in parentheses C 65 mhz filter t x enable jumper configuration jumper function e5-e6 header connector from dg2020, data generator e7-e8 software control of t x enable open hard enable or ext. control via j4 t x enable e7 e5 e8 e6 smb j4 r11 3.9k v +5v txe txee gnd +5v c17 0.1 m f y1 14 vcc out 8 gnd sw41 clk smb j2 r1 50 v external clk 7 crystal osc. if clock remove source is y1 j2 (external) r1 y1 (xtal) jumper function 1-2 hard power-down 2-3 hard power-down or external control via j3 no jumper powered up ad8320 power-down sw1 functions 8ppt+5v rz1 2 3 4 5 6 7 8 latch busclk busdat reset txen bdat tstate 2.2k pull-up network to +5v three-state buffer u4 74ac244 2a4 2y4 2a3 2y3 2a2 2y3 2a1 2y2 1a4 1y4 1a3 1y3 1a2 1y2 1a1 1y1 17 15 13 11 8 6 4 2 gnd gnd gnd bdat dat 3 5 7 9 12 14 16 18 rbak bdat 1g 2g tstat 19 1 +5v c22 0.1 m f latch +5v r8 3.9k v fec u3 74act573 9 8 7 6 5 4 3 2 txen tstate reset busdat busclk 12 13 14 15 16 17 18 19 fecc txee tsat rest dat bclk 11 1 latch c34 0.001 m f 8d 8q 7d 7q 6d 6q 5d 5q 4d 4q 3d 3q 2d 2q 1d 1q en oe +5v c21 0.1 m f "centronics" print port conn. c36crpx latch busclk busdat reset fec txen tstate rbak 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 j1 c20 10 m f +10v tb1 power input connector dut+v gnd +5v gnd +10v 1 2 3 4 5 75 v output smb 75 j8 c12 0.1 m f c2 0.1 m f vccl vin vref vcc gnd gnd byp gnd gnd gnd 20 19 18 17 16 15 14 13 12 11 +10v +10v cad cac cae gnd pdn +10v +10v +10v c32 0.1 m f programmable gain amplifier c1 0.1 m f c11 0.1 m f r2 62 v amp sdata clk daten gnd vocm pd vcc vcc vcc vout ad8320 u2 1 2 3 4 5 6 7 8 9 10 c16 0.1 m f +10v serial data in smb j5 r12 3.9k v +5v sdi sdi smb j3 podn r10 3.9k v ad8320 external powerdown 1 2 3 gnd pdn podn h3m sw1 ad8320 powerdown source switch c26 0.1 m f dut+v c27 0.1 m f dut+v c28 0.1 m f dut+v c15 0.1 m f +10v c19 10 m f dut+v c13 10 m f +10v c14 0.1 m f +10v c18 10 m f +5v figure 39. electrical schematic of ad9853-xxpcb evaluation board
ad9853 C29C rev. c a. layer 1 (top) C signal routing and ground plane b. layer 2 C ground plane figure 40. pcb layout patterns for the four-layer ad9853-xxpcb evaluation board c. layer 3 C dut +v, +5 v, and +12 v power plane d. layer 4 (bottom) C signal routing
ad9853 C30C rev. c plots of typical output spectrum from the AD9853-45PCB evaluation board (conditions: dut supply voltage = +3.3 v, qpsk modulation, 2.048 mb/s, 20.48 mhz ext. refclk, 6 refclk enabled, srrc filter function, a out = 40 mhz, a = 0.25, 50 mhz low-pass filter). C25 C35 ref 50.0mhz inc 10mhz res bw 60mhz vid bw 5.4khz 10.0mhz/div 500ms/div C65 C95 C105 C45 C55 C85 C75 atten 30db 50 v tg off figure 41. direct dac output C25 C35 ref 50.0mhz inc 10mhz res bw 10mhz vid bw 5.4khz 10.0mhz/div 500ms/div C65 C95 C105 C45 C55 C85 C75 atten 30db 50 v tg off 2nd harmonic figure 42. output of ad8320 programmable line driver amplifier driven by ad9853 modulator plots of typical output spectrum from the ad9853-65pcb evaluation board (conditions: dut supply voltage = +4.0 v, qpsk modulation, 2.7792 mb/s, 27.792 mhz ext. refclk, 6 refclk enabled, srrc filter function, a out = 60 mhz, a = 0.25, 70 mhz low-pass filter). C25 C35 ref 100.0mhz inc 20mhz res bw 10mhz vid bw 5.4khz 20.0mhz/div 1s/div C65 C95 C105 C45 C55 C85 C75 atten 10db 50 v tg off figure 43. direct dac output C2.0 12.0 ref 100.0mhz inc 20mhz res bw 10mhz vid bw 5.4khz 20.0mhz/div 1s/div 42.0 72.0 82.0 22.0 32.0 62.0 52.0 atten 30db 50 v tg off 2nd harmonic 3rd harmonic figure 44. output of ad8320 programmable line driver amplifier driven by ad9853 modulator
ad9853 C31C rev. c outline dimensions dimensions shown in inches and (mm). 44-lead metric quad flatpack (mqfp) (s-44a) top view (pins down) 1 33 34 44 11 12 23 22 0.530 (13.45) 0.510 (12.95) sq 0.031 (0.80) bsc 0.018 (0.45) 0.012 (0.30) 0.398 (10.10) 0.390 (9.90) sq 0.315 (8.00) ref 0.083 (2.10) 0.077 (1.95) 0.010 (0.25) max 0.009 (0.23) 0.005 (0.13) seating plane 0.096 (2.45) max 0.041 (1.03) 0.029 (0.73) c3361cC0C2/99 printed in u.s.a.

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