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features description applications ads8509 slas324a ? october 2004 ? revised june 2005 16-bit 250-ksps serial cmos sampling analog-to-digital converter 250-khz sampling rate the ads8509 is a complete 16-bit sampling analog-to-digital (a/d) converter using state-of-the-art 4-v, 5-v, 10 v, 3.33-v, 5-v, and 10-v input cmos structures. it contains a complete 16-bit, ranges capacitor-based, successive approximation register 2.0 lsb max inl (sar) a/d converter with sample-and-hold, refer- 1 lsb max dnl, 16-bit no missing codes ence, clock, and a serial data interface. data can be output using the internal clock or can be spi compatible serial output with synchronized to an external data clock. the ads8509 daisy-chain (tag) feature also provides an output synchronization pulse for single 5-v supply ease of use with standard dsp processors. pin-compatible with ads7809 (low speed) the ads8509 is specified at a 250-khz sampling rate and 12-bit ads8508/7808 over the full temperature range. precision resistors uses internal or external reference provide various input ranges including 10 v and 0 v 70-mw typ power dissipation at 250 ksps to 5 v, while the innovative design allows operation from a single +5-v supply with power dissipation 20-pin so and 28-pin ssop packages under 100 mw. simple dsp interface the ads8509 is available in 20-pin so and 28-pin ssop packages, both fully specified for operation over the industrial -40 c to 85 c temperature range. industrial process control data acquisition systems digital signal processing medical equipment instrumentation please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2004?2005, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
successive approximation register clock comparator cs cdac buffer ref cap r1 i n 10 k w 4.9 k w internal +2.5 v ref 4 k w serial data out & control busy da t aclk da t a 2.5 k w 9.8 k w r2 i n r3 i n ext/int r/c sb/btc pwrd
absolute maximum ratings ads8509 slas324a ? october 2004 ? revised june 2005 package/ordering information (1) minimum no minimum specification relative package package ordering transport product missing sinad temperature accuracy lead designator number media, qty code (db) range (lsb) ads8509ibdw tube, 25 so-20 dw ads8509ibdwr tape and reel, 2000 ads8509ib 2 16 85 -40 c to 85 c ads8509ibdb tube, 50 ssop-28 db ads8509ibdbr tape and reel, 2000 ads8509idw tube, 25 so-20 dw ads8509idwr tape and reel, 2000 ads8509i 3 15 83 -40 c to 85 c ads8509idb tube, 50 ssop-28 db ads8509idbr tape and reel, 2000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com. over operating free-air temperature range (unless otherwise noted) (1) unit r1 in 25 v r2 in 25 v analog inputs r3 in 25 v ref +v ana + 0.3 v to agnd2 - 0.3 v dgnd, agnd2 0.3 v v ana 6 v ground voltage differences v dig to v ana 0.3 v v dig 6 v digital inputs -0.3 v to +v dig + 0.3 v maximum junction temperature 165 c storage temperature range ?65 c to 150 c internal power dissipation 700 mw lead temperature (soldering, 1.6 mm from case 10 seconds) 260 c (1) all voltage values are with respect to network ground terminal. 2 www .ti.com
electrical characteristics ads8509 slas324a ? october 2004 ? revised june 2005 at t a = -40 c to 85 c, f s = 250 khz, v dig = v ana = 5 v, using internal reference and 0.1%, 0.25 w fixed resistors (see figure 29 and figure 30 ) (unless otherwise specified) ads8509i ads8509ib parameter test conditions unit min typ max min typ max resolution 16 16 bits analog input voltage ranges (1) impedance (1) capacitance 50 50 pf throughput speed conversion cycle acquire and convert 4 4 s throughput rate 250 250 khz dc accuracy inl integral linearity error -3 3 -2 2 lsb (2) dnl differential linearity error -2 2 -1 1 lsb no missing codes 15 16 bits transition noise (3) 1 1 lsb 10 v range int. ref. with 0.1% external -0.5 0.5 -0.5 0.5 full-scale %fsr fixed resistors error (4) (5) all other ranges -0.5 0.5 -0.5 0.5 full-scale error drift int. ref. 7 7 ppm/ c 10 v range ext. ref. with 0.1% external -0.5 0.5 -0.5 0.5 full-scale %fsr fixed resistors error (4) (5) all other ranges -0.5 0.5 -0.5 0.5 full-scale error drift ext. ref. 2 2 ppm/ c bipolar zero error (4) -10 10 -5 5 mv bipolar zero error drift 0.4 0.4 ppm/ c 10 v range -5 5 -5 5 unipolar zero mv 4 v and 5 v -3 3 -3 3 error (4) range unipolar zero error drift 2 2 ppm/ c recovery to rated accuracy after 1- f capacitor to cap 1 1 ms power down power supply sensitivity -8 8 -8 8 +4.75 v < v d < +5.25 v lsb (v dig = v ana = v d ) ac accuracy sfdr spurious-free dynamic range f i = 20 khz 90 99 95 99 db (6) thd total harmonic distortion f i = 20 khz -98 -90 -98 -93 db sinad f i = 20 khz 83 88 85 88 db signal-to-(noise+distortion) ?60-db input 30 32 db snr signal-to-noise ratio f i = 20 khz 83 88 86 88 db full-power bandwidth (7) 500 500 khz sampling dynamics aperture delay 5 5 ns transient response fs step 2 2 s overvoltage recovery (8) 150 150 ns (1) 10 v, 0 v to 5 v, etc. (see table 3 ) (2) lsb means least significant bit. for the 10-v input range, one lsb is 305 v. (3) typical rms noise at worst case transitions and temperatures. (4) as measured with fixed resistors shown in figure 29 and figure 30 . adjustable to zero with external potentiometer. factory calibrated with 0.1%, 0.25 w resistors. (5) for bipolar input ranges, full-scale error is the worst case of -full-scale or +full-scale uncalibrated deviation from ideal first and last code transitions, divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. for unipolar input ranges, full-scale error is the deviation of the last code transition divided by the transition voltage. it also includes the effect of offset error. (6) all specifications in db are referred to a full-scale 10-v input. (7) full-power bandwidth is defined as the full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 db. (8) recovers to specified performance after 2 x fs input overvoltage. 3 www .ti.com
ads8509 slas324a ? october 2004 ? revised june 2005 electrical characteristics (continued) at t a = -40 c to 85 c, f s = 250 khz, v dig = v ana = 5 v, using internal reference and 0.1%, 0.25 w fixed resistors (see figure 29 and figure 30 ) (unless otherwise specified) ads8509i ads8509ib parameter test conditions unit min typ max min typ max reference internal reference voltage no load 2.48 2.5 2.52 2.48 2.5 2.52 v internal reference source current 1 1 a (must use external buffer) internal reference drift 8 8 ppm/ c external reference voltage range 2.3 2.5 2.7 2.3 2.5 2.7 v for specified linearity external reference current drain ext. 2.5-v ref. 100 100 a digital inputs logic levels v il low-level input voltage -0.3 0.8 -0.3 0.8 v v ih high-level input voltage 2.0 v dig +0.3 v 2.0 v dig +0.3 v v i il low-level input current v il = 0 v 10 10 a i ih high-level input current v ih = 5 v 10 10 a digital outputs data format (serial 16-bits) data coding (binary 2's comp- lement or straight binary) pipeline delay (conversion re- sults only available after com- pleted conversion.) data clock (selectable for internal or external data clock) internal clock (output only when ext/ int low 9 9 mhz transmitting data) external clock (can run continu- ext/ int high 0.1 26 0.1 26 ally but not recommended for mhz optimum performance) v ol low-level output voltage i sink = 1.6 ma 0.4 0.4 v v oh high-level output voltage i source = 500 a 4 4 v leakage current hi-z state, 5 5 a v out = 0 v to v dig output capacitance hi-z state 15 15 pf power supplies v dig digital input voltage 4.75 5 5.25 4.75 5 5.25 v v ana analog input voltage 4.75 5 5.25 4.75 5 5.25 v must be v ana i dig digital input current 4 4 ma i ana analog input current 10 10 ma power dissipation pwrd low f s = 250 khz 70 100 70 100 mw pwrd high 50 50 w temperature range specified performance -40 85 -40 85 c derated performance (9) -55 125 -55 125 c storage -65 150 -65 150 c thermal resistance ( q ja ) ssop 62 62 c/w so 46 46 c/w (9) the internal reference may not be started correctly beyond the industrial temperature range (-40c to 85c), therefore use of an external reference is recommended. 4 www .ti.com
timing requirements, t a = ?40 c to 85 c ads8509 slas324a ? october 2004 ? revised june 2005 parameter min typ max unit t w1 pulse duration, convert 40 ns t d1 delay time, busy from r/ c low 6 20 ns t w2 pulse duration, busy low 2.2 s t d2 delay time, busy, after end of conversion 5 ns t d3 delay time, aperture 5 ns t conv conversion time 2.2 s t acq acquisition time 1.8 s t conv + t acq cycle time 4 s t d4 delay time, r/ c low to internal dataclk output 270 ns t c1 cycle time, internal dataclk 110 ns t d5 delay time, data valid to internal dataclk high 15 35 ns t d6 delay time, data valid after internal dataclk low 20 35 ns t c2 cycle time, external dataclk 35 ns t w3 pulse duration, external dataclk high 15 ns t w4 pulse duration, external dataclk low 15 ns t su1 setup time, r/ c rise/fall to external dataclk high 15 t c2 + 5 ns t su2 setup time, r/ c transition to cs transition 10 ns t d7 delay time, sync, after external dataclk high 3 35 ns t d8 delay time, data valid 2 20 ns t d9 delay time, cs to rising edge 10 ns t d10 delay time, previous data available after cs, r/ c low 2 s t su3 setup time, busy transition to first external dataclk 5 ns t d11 delay time, final external dataclk to busy falling edge 1 s t su3 setup time, tag valid 0 ns t h1 hold time, tag valid 2 ns 5 www .ti.com v dig v ana busycs r/c t ag da t a da t aclk sync r1 in agnd1 ref cap agnd2 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 1 1 dw p ackage r2 in r3 in sb/btc ext/int dgnd pwrd v dig v ana busycs r/c nct ag ncda t a da t aclk sync r1 in agnd1 nc cap agnd2 ncnc nc ref dgnd 12 3 4 5 6 7 8 9 101 1 1213 14 2827 26 25 24 23 22 21 20 19 18 17 16 15 db p ackage r2 in sb/btc ext/int pwrdnc (t op view) (t op view) nc r3 in
ads8509 slas324a ? october 2004 ? revised june 2005 terminal functions terminal description name db no. dw no. i/o agnd1 2 2 ? analog ground. used internally as ground reference point. minimal current flow. agnd2 9 7 ? analog ground busy 25 17 o busy output. falls when a conversion is started, and remains low until the conversion is completed and the data is latched into the output shift register. cap 6 5 ? reference buffer capacitor. 2.2-f tantalum to ground. cs 24 16 ? chip select. internally ored with r/ c. data 17 13 o serial data output. data is synchronized to dataclk, with the format determined by the level of sb/ btc. in the external clock mode, after 16 bits of data, the ads8509 outputs the level input on tag as long as cs is low and r/ c is high (see figure 8 and figure 9 ). if ext/ int is low, data is valid on both the rising and falling edges of dataclk, and between conversions data stays at the level of the tag input when the conversion was started. dataclk 16 12 i/o either an input or an output depending on the ext/ int level. output data is synchronized to this clock. if ext/ int is low, dataclk transmits 16 pulses after each conversion, and then remains low between conversions. dgnd 14 10 ? digital ground ext/ int 13 9 ? selects external or internal clock for transmitting data. if high, data is output synchronized to the clock input on dataclk. if low, a convert command initiates the transmission of the data from the previous conversion, along with 16-clock pulses output on dataclk. nc 5, 8, 10, ? ? no connect 11, 18, 20, 22, 23 pwrd 26 18 i power down input. if high, conversions are inhibited and power consumption is significantly reduced. results from the previous conversion are maintained in the output shift register. r/ c 21 15 i read/convert input. with cs low, a falling edge on r/ c puts the internal sample-and-hold into the hold state and starts a conversion. when ext/ int is low, this also initiates the transmission of the data results from the previous conversion. if ext/ int is high, a rising edge on r/ c with cs low, or a falling edge on cs with r/ c high, transmits a pulse on sync and initiates the transmission of data from the previous conversion. ref 7 6 i/o reference input/output. outputs internal 2.5-v reference. can also be driven by external system reference. in both cases, bypass to ground with a 2.2-f tantalum capacitor. r1 in 1 1 i analog input. see table 3 for input range connections. r2 in 3 3 i analog input. see table 3 for input range connections. r3 in 4 4 i analog input. see table 3 for input range connections. sb/ btc 12 8 o select straight binary or binary 2's complement data output format. if high, data is output in a straight binary format. if low, data is output in a binary 2's complement format. sync 15 11 o sync output. this pin is used to supply a data synchronization pulse when the ext level is high and at least one external clock pulse has occured when not in the read mode. see the external clock modes desciptions. tag 19 14 i tag input for use in the external clock mode. if ext is high, digital data input from tag is output on data with a delay that is dependent on the external clock mode. see figure 8 and figure 9 . v ana 27 19 i analog supply input. nominally +5 v. connect directly to pin 20, and decouple to ground with 0.1-f ceramic and 10-f tantalum capacitors. v dig 28 20 i digital supply input. nominally +5 v. connect directly to pin 19. must be v ana . 6 www .ti.com
parameter measurement information ads8509 slas324a ? october 2004 ? revised june 2005 figure 1. critical timing figure 2. basic conversion timing - internal dataclk (read previous data during conversion) 7 www .ti.com 1 2 t s u 1 t s u 1 cs r/c external da t aclk cs set low , discontinuous ext da t aclk t s u 1 t s u 1 r/c cs external da t aclk r/c set low , discontinuous ext da t aclk t s u 2 t s u 2 cs r/c t s u 3 busy external da t aclk cs set low , discontinuous ext da t aclk r/c busy st a tus ( n + 1 ) th accquisition ( n + 1 ) th conversion errorcorrection nth conversion errorcorrection internal da t aclk ( n ? 1 ) th conversion data da t a nth conversion data ( n + 2 ) th accquisition 1 2 16 2 16 d 15 d 0 d 15 d 0 t ag = 0 t ag = 0 t ag = 0 8 starts read cs , ext/int , and t ag are tied low t w 1 t d 1 t w 2 t d 3 t d 1 1 t d 2 t d 3 t w 1 t d 1 t w 2 t d 1 1 t d 2 t c o n v t a c q t c o n v t a c q t d 4 t d 4 t c 1 t d 5 t d 6 1
ads8509 slas324a ? october 2004 ? revised june 2005 parameter measurement information (continued) figure 3. basic conversion timing - external dataclk figure 4. read after conversion (discontinuous external dataclk) 8 www .ti.com busy st a tus (n+1)th accquisition (n+1)th conversion errorcorrection nth conversion errorcorrection external da t aclk da t a nth data (n+1)th data (n+2)th accquisition t ag = 0 no moredata to shift out no moredata to shift out t ag = 0 t ag = 0 t ag = 0 t ag = 0 r/c ext/int tied high, cs and t ag are tied low t w 1 + t s u 1 starts read t w 1 t w 1 t d 1 t w 2 t d 1 t w 2 t d 3 t d 1 1 t d 2 t d 3 t d 1 1 t d 2 t s u 1 t c o n v t a c q t c o n v t a c q t s u 3 t s u 1 t s u 3 1 16 1 2 16 1 16 1 2 16 busy st a tus ( n + 1 ) th accquisition error correction nth conversion external da t aclk da t a nth conversion data sync = 0 d 15 0 1 2 3 15 14 16 t ag t01 d 05 d 10 d 12 d 13 d 14 t00 t04 t03 t02 t13 t12 t1 1 t06 t16 t15 t14 t yy 5 4 1 1 12 13 10 d 1 1 t05 d 04 d 03 d 02 d 01 txx t00 d 00 null t17 null r/c ext/int tied high, cs tied low t w 1 + t s u 1 starts read t w 1 t d 1 t w 2 t s u 1 t d 3 t d 1 1 t d 2 t c o n v t a c q t d 3 t d 1 t s u 3 t w 3 t c 2 t w 4 t s u 1 t d 8 t d 8 t s u 3 t h 1
ads8509 slas324a ? october 2004 ? revised june 2005 parameter measurement information (continued) figure 5. read during conversion (discontinuous external dataclk) figure 6. read after conversion with sync (discontinuous external dataclk) 9 www .ti.com busy st a tus errorcorrection nth conversion external da t aclk da t a nth conversion data sync = 0 d15 0 1 2 3 15 14 16 d05 d10 d12 d13 d14 5 4 1 1 12 13 10 d1 1 d00 d04 d03 d02 d01 r/c ext/int tied high, cs and t ag tied low rising da t aclk change da t a, t w 1 + t s u 1 starts read t ag is not recommended for this mode. there is not enough time to do so without violating t d 1 1 . t w 1 t d 1 t w 2 t d 1 0 t d 3 t s u 3 t c o n v t d 2 t s u 1 t w 3 t c 2 t w 4 t d 1 1 t d 8 t d 8 busy st a tus (n+1)th accquisition error correction nth conversion external da t aclk da t a nth conversion data sync d15 2 3 4 5 17 16 18 t ag t01 d05 d10 d12 d13 d14 t00 t04 t03 t02 t13 t12 t1 1 t06 t16 t15 t14 t yy t17 7 6 13 14 15 12 d1 1 t05 d00 d04 d03 d02 d01 txx =0 0 1 t00 null r/c ext/int tied high, cs tied low t w 1 + t s u 1 starts read t w 1 t s u 1 t s u 1 t d 1 t d 1 t d 3 t d 1 1 t d 2 t w 2 t d 3 t c o n v t a c q t s u 1 t s u 3 t c 2 t w 4 t w 3 t c 2 t d 7 t d 8 t s u 3 t h 1 t d 8 t s u 1
ads8509 slas324a ? october 2004 ? revised june 2005 parameter measurement information (continued) figure 7. read during conversion with sync (discontinuous external dataclk) 10 www .ti.com busy st a tus errorcorrection nth conversion external da t aclk da t a nth conversion data sync = 0 d15 2 3 4 5 17 16 18 d05 d10 d12 d13 d14 7 6 13 14 15 12 d1 1 d00 d04 d03 d02 d01 0 1 r/c ext/int tied high, cs and t ag tied low t w 1 + t s u 1 starts read t ag is not recommended for this mode. there is not enough time to do so without violating t d 1 1 . t w 1 t w 2 t d 1 t d 3 t d 1 0 t s u 3 t s u 1 t s u 1 t w 3 t d 7 t c 2 t d 8 t c 2 t w 4 t s u 1 t d 8 t d 1 1 t c o n v t d 2
ads8509 slas324a ? october 2004 ? revised june 2005 parameter measurement information (continued) figure 8. conversion and read timing with continuous external dataclk (ext/ int tied high) read after conversions (not recommended) 11 www .ti.com 0 1 2 3 4 17 18 bit 15 (msb) bit 14 bit 1 bit 0 (lsb) t ag 0 t ag 1 t ag 0 t ag 1 t ag 2 t ag 15 t ag 16 t ag 17 t ag 18 t ag 19 t c2 t w4 t w3 t w1 t su1 t su2 t d1 t su2 t c2 t d7 t d8 t d9 external da t aclk cs r/c busy sync da t a t ag
ads8509 slas324a ? october 2004 ? revised june 2005 parameter measurement information (continued) figure 9. conversion and read timing with continous external dataclk (ext/ int tied high) read previous conversion results during conversion (not recommended) 12 www .ti.com t c2 t w4 t w3 t w1 t su2 t su1 t d10 t d8 t d1 t su1 t c2 t d8 external da t aclk cs r/c busy sync da t a t ag bit 15 (msb) bit 0 (lsb) t ag 0 t ag 1 t ag 0 t ag 1 t ag 16 t ag 17 t ag 18 t ag 19
typical characteristics ads8509 slas324a ? october 2004 ? revised june 2005 spurious free dynamic range total harmonic distortion vs vs free-air temperature free-air temperature figure 10. figure 11. signal-to-noise ratio signal-to-noise and distortion vs vs free-air temperature free-air temperature figure 12. figure 13. signal-to-noise ratio signal-to-noise and distortion vs vs input frequency input frequency figure 14. figure 15. 13 www .ti.com 75 80 85 90 95 100 105 ?40 25 85 sfdr ? spurious free dynamic range ? db t a ? free-air t emperature ? c f s = 250 ksps, f i = 20 khz ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?40 25 85 thd ? t otal harmonic distortion ? db t a ? free-air t emperature ? c f s = 250 ksps, f i = 20 khz snr ? signal-to-noise ratio ? db 70 75 80 85 90 95 100 ?40 25 85 t a ? free-air t emperature ? c f s = 250 ksps, f i = 20 khz 70 75 80 85 90 95 100 ?40 25 85 sinad ? signal-t o-noise and distortion ? db t a ? free-air t emperature ? c f s = 250 ksps, f i = 20 khz sinad ? signal-t o-noise and distortion ? db 65 70 75 80 85 90 1 10 100 f i ? input frequency ? khz 65 70 75 80 85 90 1 10 100 snr ? signal-to-noise ratio ? db f i ? input frequency ? khz
ads8509 slas324a ? october 2004 ? revised june 2005 typical characteristics (continued) spurious free dynamic range total harmonic distortion vs vs input frequency input frequency figure 16. figure 17. internal reference voltage bipolar zero scale error vs vs free-air temperature free-air temperature figure 18. figure 19. full scale error supply current vs vs free-air temperature free-air temperature figure 20. figure 21. 14 www .ti.com 70 75 80 85 90 95 100 105 1 10 100 sfdr ? spurious free dynamic range ? db f i ? input frequency ? khz ?70 ?75 ?80 ?85 ?90 ?95 ?100 ?105 1 10 100 thd ? t otal harmonic distortion ? db f i ? input frequency ? khz 2.490 2.492 2.494 2.496 2.498 2.500 2.502 2.504 2.506 2.508 2.510 ?55 ?35 ?15 5 25 45 65 85 105 internal reference v oltage ? v t a ? free-air t emperature ? c ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 ?40 ?25 ?10 5 20 35 50 65 80 bipolar zero scale error ? mv t a ? free-air t emperature ? c external reference, 10-v range ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 ?40 ?25 ?10 5 20 35 50 65 80 t a ? free-air t emperature ? c external reference, 10 v range for 5 representativeparts full scale error ? %fsr 10 1 1 12 13 14 15 16 17 18 19 20 ?40 ?25 ?10 5 20 35 50 65 80 supply current ? ma t a ? free-air t emperature ? c
ads8509 slas324a ? october 2004 ? revised june 2005 typical characteristics (continued) histogram performance vs cap pin capacitor esr figure 22. figure 23. integral nonlinearity figure 24. differential nonlinearity figure 25. 15 www .ti.com 50 55 60 65 70 75 80 85 90 95 100 0 1 2 3 4 5 6 7 8 9 10 1 1 performance esr ? resistance ? 2.2 m f capacitor on cap pin (pin 6) |thd| sinad 0 500 1000 1500 2000 2500 3000 3500 4000 4500 ?3 ?2 ?1 0 1 2 3 4 149 2082 4224 4224 1484 238 1 1 hits code 8192conversions of a dc input ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 0 16384 32768 49152 65536 inl ? lsbs code f s = 250 ksps ?2.5 ?2 ?1.5 ?1 ?0.5 0 0.5 1 1.5 2 2.5 0 16384 32768 49152 65536 dnl ? lsbs code f s = 250 ksps
basic operation reading data internal dataclk external dataclk ads8509 slas324a ? october 2004 ? revised june 2005 typical characteristics (continued) fft (20 khz input) figure 26. two signals control conversion in the ads8509: cs and r/ c. these two signals are internally ored together. to start a conversion the chip must be selected, cs low, and the conversion signal must be active, r/ c low. either signal can be brought low first. conversion starts on the falling edge of the second signal. busy goes low when conversion starts and returns high after the data from that conversion is shifted into the internal storage register. sampling begins when busy goes high. to reduce the number of control pins cs can be tied low permanently. the r/ c pin now controls conversion and data reading exclusively. in the external clock mode this means that the ads8509 will clock out data whenever r/ c is brought high and the external clock is active. in the internal clock mode data is clocked out every convert cycle regardless of the states of cs and r/ c. the ads8509 provides a tag input for cascading multiple converters together. the conversion result is available as soon as busy returns to high therefore, data always represents the conversion previously completed even when it is read during a conversion. the ads8509 outputs serial data in either straight binary or binary two?s compliment format. the sb/ btc pin controls the format. data is shifted out msb first. the first conversion immediately following a power-up will not produce a valid conversion result. data can be clocked out with either the internally generated clock or with an external clock. the ext/ int pin controls this function. if external clock is used the tag input can be used to daisy-chain multiple ads8509 data pins together. in the internal clock mode data for the previous conversion is clocked out during each conversion period. the internal data clock is synchronized to the internal conversion clock so that is does not interfere with the conversion process. the dataclk pin becomes an output when ext/ int is low. 16 clock pulses are generated at the beginning of each conversion after timing t 8 is satisfied, i.e. you can only read previous conversion result during conversion. dataclk returns to low when it is inactive. the 16 bits of serial data are shifted out the data pin synchronous to this clock with each bit available on a rising and then a falling edge. data pin returns to the state of tag pin input sensed at the start of transmission. the external clock mode offers several ways to retrieve conversion results. however, since the external clock cannot be synchronized to the internal conversion clock care must be taken to avoid corrupting the data. 16 www .ti.com ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 20 0 25 50 75 100 125 8192 points,f s = 250 ksps, f i = 20 khz, 0 db sinad = 86.0 db,thd = ?98.7 db amplitude ? db f ? frequency ? khz
tag feature ads8509 slas324a ? october 2004 ? revised june 2005 when ext/ int is set high, the r/ c and cs signals control the read state. when the read state is initiated the result from the previously completed conversion is shifted out the data pin synchronous to the external clock that is connected to the dataclk pin. each bit is available on a falling and then a rising edge. the maximum external clock speed of 28.5 mhz allows data shifted out quickly either at the beginning of conversion or the beginning of sampling. there are several modes of operation available when using an external clock. it is recommended that the external clock run only while reading data. this is the discontinuous clock mode. since the external clock is not synchronized to the internal clock that controls conversion slight changes in the external clock can cause conflicts that can corrupt the conversion process. specifications with a continuously running external clock cannot be guaranteed. it is especially important that the external clock does not run during the second half of the conversion cycle (approximately the time period specified by t d11 , see timing table). in the discontinuous clock mode data can be read during conversion or during sampling, with or without a sync pulse. data read during a conversion must meet the t d11 timing specification. data read during sampling must be complete before starting a conversion. whether reading during sampling or during conversion a sync pulse is generated whenever at least one rising edge of the external clock occurs while the part is not in the read state. in the discontinuous external clock with sync mode a sync pulse follows the first rising edge after the read command. the data is shifted out after the sync pulse. the first rising clock edge after the read command generates a sync pulse. the sync pulse can be detected on the next falling edge and then the next rising edge. successively, each bit can be read first on the falling edge and then on the next rising edge. thus 17 clock pulses after the read command are required to read on the falling edge. 18 clock pulses are necessary to read on the rising edge. table 2. dataclk pulses dataclk pulses required description with sync without sync read on falling edge of dataclk 17 16 read on rising edge of dataclk 18 17 if the clock is entirely inactive when not in the read state no sync pulse is generated. in this case the first rising clock edge shifts out the msb. the msb can be read on the first falling edge or on the next rising edge. in this discontinuous external clock mode with no sync, 16 clocks are necessary to read the data on the falling edge and 17 clocks for reading on the rising edge. data always represents the conversion already completed. the tag feature allows the data from multiple ads8509 converters to be read on a single serial line. the converters are cascaded together using the data pins as outputs and the tag pins as inputs as illustrated in figure 27 . the data pin of the last converter drives the processor's serial data input. data is then shifted through each converter, synchronous to the externally supplied data clock, onto the serial data line. the internal clock cannot be used for this configuration. the preferred timing uses the discontinuous, external, data clock during the sampling period. data must be read during the sampling period because there is not sufficient time to read data from multiple converters during a conversion period without violating the t d11 constraint (see the external dataclock section). the sampling period must be sufficiently long to allow all data words to be read before starting a new conversion. note, in figure 27 , that a null bit separates the data word from each converter. the state of the data pin at the end of a read cycle reflects the state of the tag pin at the start of the cycle. this is true in all read modes, including the internal clock mode. for example, when a single converter is used in the internal clock mode the state of the tag pin determines the state of the data pin after all 16 bits have shifted out. when multiple converters are cascaded together this state forms the null bit that separates the words. thus, with the tag pin of the first converter grounded as shown in figure 27 the null bit becomes a zero between each data word. 17 www .ti.com
analog inputs ads8509 slas324a ? october 2004 ? revised june 2005 figure 27. timing of tag feature with single conversion (using external dataclk) the ads8509 has six analog input ranges as shown in table 3 . the offset and gain specifications are factory calibrated with 0.1%, ?-w, external resistors as shown in figure 29 and figure 30 . the external resistors can be omitted if larger gain and offset errors are acceptable or if using software calibration. the hardware trim circuitry shown in figure 29 and figure 30 can reduce the errors to zero. the analog input pins r1 in , r2 in , and r3 in have 25-v overvoltage protection. the input signal must be referenced to agnd1. this will minimized the ground loop problem typical to analog designs. the analog input should be driven by a low impedance source. a typical driving circuit using opa627 or opa132 is shown in figure 28 . the ads8509 can operate with its internal 2.5-v reference or an external reference. an external reference connected to pin 6 (ref) bypasses the internal reference. the external reference must drive the 4-k w resistor that separates pin 6 from the internal reference (see the illustration on page 1). the load will vary with the difference between the internal and external reference voltages. the external reference voltage can vary from 2.3 v to 2.7 v. the internal reference will be approximately 2.5 v. the reference, whether internal or external, is buffered internally with a buffer with its output on pin 5 (cap). the ads8509 is factory tested with 2.2-f capacitors connected to pins 5 and 6 (cap and ref). each capacitor should be placed as close as possible to its pin. the capacitor on pin 6 band limits the internal reference noise. a smaller capacitor can be used but it may degrade snr and sinad. the capacitor on pin 5 stabilizes the reference buffer and provides switching charge to the cdac during conversion. capacitors smaller than 1 f can cause the buffer to become unstable may not hold sufficient charge for the cdac. the parts are tested to specifications with 2.2 f so larger capacitors are not necessary. the equivalent series resistor (esr) of these compensation capacitors is also critical. keep the total esr under 3 w . see the typical characteristics section concerning how esr affects performance. neither the internal reference nor the buffer should be used to drive an external load. such loading can degrade performance. any load on the internal reference causes a voltage drop across the 4-k w resistor and will affect gain. the internal buffer is capable of driving 2-ma loads but any load can cause perturbations of the reference at the cdac, degrading performance. it should be pointed out that, unlike other competitor?s parts with similar input structure, the ads8509 does not require a second high speed amplifier used as buffer to isolate the cap pin from the signal dependent current in the r3 in pin but can tolerate it if one do exist. 18 www .ti.com external da t aclk . 2 3 4 35 34 36 17 16 20 21 19 1 null d q a 00 d q null d q b 00 d q a 15 d q a 16 d q b 15 d q b 16 d q t ag ( a ) t ag ( b ) da t a ( a ) da t a ( b ) da t aclk ( both a & b ) sync ( both a & b ) ( both a & b ) da t a ( b ) nth conversion data b 15 a 15 b 00 b 13 b 14 b 01 a 00 a 14 a 13 a 01 da t a ( a ) a 15 a 00 a 13 a 14 a 01 18 nulla nullb nulla ads 8509 a t ag da t a da t aclk ads 8509 b t ag da t a da t aclk processor sclk gpiogpio sdi t ag(a) = 0 t ag(a) = 0 r/c cs r/c cs r/c busy ext/int tied high, cs of both converter a and b, t ag input of converter a are tied low .
ads8509 slas324a ? october 2004 ? revised june 2005 the external reference voltage can vary from 2.3 v to 2.7 v. the reference voltage determines the size of the least significant bit (lsb). the larger reference voltages produce a larger lsb, which can improve snr. smaller reference voltages can degrade snr. figure 28. typical driving circuitry (10 v, no trim) 19 www .ti.com op a 627 gnd gnd gnd gnd gnd pin 1 pin 7 ? pin 2 + pin 3 pin 4 pin 6 ? 15 v + 15 v v in 2.2 f 100 nf 2 k 22 pf 2 k 22 pf 200 100 33.2 k 2.2 f 2.2 f 100 nf 2.2 f r1 i n agnd1r2 i n r3 i n capref ads8509 op a 132 or agnd2 dgnd gnd
ads8509 slas324a ? october 2004 ? revised june 2005 table 3. input range connections (see figure 29 and figure 30 for complete information) analog connect r1 in via connect r2 in via connect impedance input range 200 w to 100 w to r3 to 10 v v in agnd cap 11.5 k w 5 v agnd v in cap 6.7 k w 3.33 v v in v in cap 5.4 k w 0 v to 10 v agnd v in agnd 6.7 k w 0 v to 5 v agnd agnd v in 5.0 k w 0 v to 4 v v in agnd v in 5.4 k w table 4. control truth table specific function cs r/ c busy ext/ int dataclk pwrd sb/ btc operation initiate conversion and out- 1 > 0 0 1 0 output 0 x initiates conversion n. data from conversion n - 1 put data using internal clock clocked out on data synchronized to 16 clock 0 1 > 0 1 0 output 0 x pulses output on dataclk. initiate conversion and out- 1 > 0 0 1 1 input 0 x initiates conversion n. put data using external clock 0 1 > 0 1 1 input 0 x initiates conversion n. 1 > 0 1 1 1 input x x outputs data with or without sync pulse. see section reading data. 1 > 0 1 0 1 input 0 x outputs data with or without sync pulse. see section reading data. 0 0 > 1 0 1 input 0 x no actions 0 0 0 > 1 x x 0 x this is an acceptable condition. power down x x x x x 0 x analog circuitry powered. conversion can pro- ceed.. x x x x x 1 x analog circuitry disabled. data from previous conversion maintained in output registers. selecting output format x x x x x x 0 serial data is output in binary 2s complement format. x x x x x x 1 serial data is output in straight binary format. table 5. output codes and ideal input voltages digital output binary 2's straight descrip- analog input complements binary tion (sb/btc low) (sb/btc high) binary code hex code binary code hex code full-scale 10 5 3.33 v 0 v to 10 v 0 v to 5 v 0 v to 4 v range least signifi- cant bit 305 v 153 v 102 v 153 v 76 v 61 v (lsb) full scale 9.999695 v 4.999847 v 3.333231 v 9.999847 v 4.999924 v 3.999939 v 0111 1111 1111 1111 7fff 1111 1111 1111 1111 ffff (fs - 1lsb) midscale 0 v 0 v 0 v 5 v 2.5 v 2 v 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000 one lsb below -305 v 153 v 102 v 4.999847 v 2.499924 v 1.999939 v 1111 1111 1111 1111 ffff 0111 1111 1111 1111 7fff midscale -full scale -10 v -5 v -3.333333 v 0 v 0 v 0 v 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000 20 www .ti.com
ads8509 slas324a ? october 2004 ? revised june 2005 figure 29. offset/gain circuits for unipolar input ranges 21 www .ti.com + + + 5 v + + 200 w 100 w v i n 33.2 k w 2.2 m f 2.2 m f r1 i n agnd1r2 i n r3 i n capref agnd2 200 w 33.2 k w 50 k w v i n 100 w r1 i n agnd1r2 i n r3 i n capref agnd2 2.2 m f + 5 v 50 k w 2.2 m f 576 k w + + + + r1 i n agnd1r2 i n r3 i n capref agnd2 200 w 100 w v i n 2.2 m f 2.2 m f 33.2 k w 200 w 33.2 k w +5 v 50 k w 2.2 m f 100 w v i n 50 k w 2.2 m f 576 k w r1 i n agnd1r2 i n r3 i n capref agnd2 + + ++ r1 i n agnd1r2 i n r3 i n capref agnd2 v i n 200 w 100 w 33.2 k w 2.2 m f 2.2 m f v i n 200 w 100 w 33.2 k w +5 v +5 v +5 v 50 k w 50 k w 2.2 m f 576 k w 2.2 m f r1 i n agnd1r2 i n r3 i n capref agnd2 input range 0 v ? 10 v 0 v ? 5 v0 v ? 4 v without t rim with t rim (adjust offset first at 0 v , then adjust gain)
ads8509 slas324a ? october 2004 ? revised june 2005 figure 30. offset/gain circuits for bipolar input ranges 22 www .ti.com input range 10 v 5 v 3.3 v without t rim with t rim (adjust offset first at 0 v , then adjust gain) + + + + r1 i n agnd1r2 i n r3 i n capref agnd2 r1 i n agnd1r2 i n r3 i n capref agnd2 200 w 100 w v i n 33.2 k w 2.2 m f 2.2 m f 33.2 k w 200 w 100 w 2.2 m f +5 v 50 k w 576 k w 2.2 m f 50 k w +5 v 2.2 f 2.2 f + + v i n 200 w v i n 200 w r1 i n agnd1r2 i n r3 i n capref agnd2 r1 i n agnd1r2 i n r3 i n capref agnd2 100 w 100 w 33.2 k w 33.2 k w +5 v +5 v ++ 2.2 m f 2.2 m f 576 k w 50 k w 50 k w 2.2 f 2.2 f + + v i n r1 i n agnd1r2 i n r3 i n capref agnd2 r1 i n agnd1r2 i n r3 i n capref agnd2 v i n 200 w 200 w 100 w 100 w 33.2 k w 33.2 k w + + 2.2 m f 2.2 m f 576 k w +5 v 50 k w 50 k w +5 v v i n
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) ads8509ibdb active ssop db 28 50 tbd call ti call ti ads8509ibdbr active ssop db 28 2000 tbd call ti call ti ADS8509IBDBRG4 active ssop db 28 2000 tbd call ti call ti ads8509ibdw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509ibdwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509ibdwrg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509idb active ssop db 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509idbr active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509idbrg4 active ssop db 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509idw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509idwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads8509idwrg4 active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 3-oct-2005 addendum-page 1

mechanical data msso002e ? january 1995 ? revised december 2001 post office box 655303 ? dallas, texas 75265 db (r-pdso-g**) plastic small-outline 4040065 /e 12/01 28 pins shown gage plane 8,20 7,40 0,55 0,95 0,25 38 12,90 12,30 28 10,50 24 8,50 seating plane 9,90 7,90 30 10,50 9,90 0,38 5,60 5,00 15 0,22 14 a 28 1 20 16 6,50 6,50 14 0,05 min 5,90 5,90 dim a max a min pins ** 2,00 max 6,90 7,50 0,65 m 0,15 0 ? 8 0,10 0,09 0,25 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-150
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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