View NJU6433B_3265228.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJU6433B ver.2005-07-08 -1- 1/4 duty lcd driver general description the NJU6433B is a 1/4 duty lcd driver for segment type lcd panel. the lcd driver consists of 4-common and 50-segment drives up to 200 segments. the NJU6433B is useful for the digital tuning system or others segment type display driver. features 50 segment drivers duty ratio 1/4 (up to 200-segments) serial data transmission (shift clock 2mhz max.) oscillation circuit on-chip (external resistance required) display off function (inhb terminal) operating voltage 2.4 to 5.5v lcd driving voltage 6.5v max. package outline bump chip, chip, qfp 64-g1, qfp64-h1 c-mos technology block diagram package outline NJU6433Bc/bch preliminary NJU6433Bfg1 NJU6433Bfh1
NJU6433B ver.2005-07-08 - 2 - pad location chip center : x=0 m, y=0 m chip size : x=3.20 mm, y=3.20 mm chip thickness : 400 m pad size : x=99.2 m, y=99.2 m pad pitch : 171.2 m bump height : 25 m pad coordinates chip size 3.20 x 3.20 mm(chip center x=0 m, y=0 m) pad no. terminal x= m y= m pad no. terminal x= my= m pad no. terminal x= my= m 1 seg 1 -1279 -1437 25 seg 25 1437 81 49 seg 49 -1437 1280 2 seg 2 -1107 -1437 26 seg 26 1437 253 50 seg 50 -1437 1109 3 seg 3 -936 -1437 27 seg 27 1437 424 51 osc 1 -1437 937 4 seg 4 -765 -1437 28 seg 28 1437 595 52 osc 2 -1437 766 5 seg 5 -594 -1437 29 seg 29 1437 766 53 v dd -1437 595 6 seg 6 -423 -1437 30 seg 30 1437 937 54 v ss -1437 424 7 seg 7 -251 -1437 31 seg 31 1437 1109 55 v lcd -1437 253 8 seg 8 -80 -1437 32 seg 32 1437 1280 56 ce -1437 81 9 seg 9 91 -1437 33 seg 33 1280 1437 57 scl -1437 -90 10 seg 10 262 -1437 34 seg 34 1109 1437 58 data -1437 -261 11 seg 11 433 -1437 35 seg 35 937 1437 59 mode -1437 -432 12 seg 12 605 -1437 36 seg 36 766 1437 60 inhx -1437 -603 13 seg 13 776 -1437 37 seg 37 595 1437 61 com 4 -1437 -775 14 seg 14 947 -1437 38 seg 38 424 1437 62 com 3 -1437 -946 15 seg 15 1118 -1437 39 seg 39 253 1437 63 com 2 -1437 -1117 16 seg 16 1289 -1437 40 seg 40 81 1437 64 com 1 -1437 -1288 17 seg 17 1437 -1288 41 seg 41 -90 1437 18 seg 18 1437 -1117 42 seg 42 -261 1437 19 seg 19 1437 -946 43 seg 43 -432 1437 20 seg 20 1437 -775 44 seg 44 -603 1437 21 seg 21 1437 -603 45 seg 45 -775 1437 22 seg 22 1437 -432 46 seg 46 -946 1437 23 seg 23 1437 -261 47 seg 47 -1117 1437 24 seg 24 1437 -90 48 seg 48 -1288 1437 1 16 48 33 17 32 49 64 y x
NJU6433B ver.2005-07-08 -3- pin configuration terminal description no. symbol function 1~50 seg 1 ~seg 50 lcd segment output terminals 51 52 osc 1 osc 2 oscillation terminals : external resistance is connected to these terminals. 53 v dd power supply (+5v) 54 v ss power supply (0v) 55 v lcd power supply for lcd driving the relation : 1.3v dd |v dd - v lcd |, v ss v lcd must be maintained. 56 ce chip enable signal input terminal : "h" : lcd display data and mode setting data input "l" : disable fall edge : lcd display data latch 57 scl serial data transmission clock input terminal : lcd display and mode setting data are input synchronized scl clock signal rise edge. 58 data serial data input terminal data input timing : scl clock rise edge 59 mode data or mode select terminal "h" : data input mode "l" : lcd display data input mode (refer the mode setting table for mode setting contents) 60 inhb display-off control terminal : when display goes to off, the display data in the shift-register is retained. "h" : display-on "l" : display-off 61~64 com 4 ~com 1 lcd common output terminals b
NJU6433B ver.2005-07-08 - 4 - functional description (1) operation of each block (1-1) oscillation circuit the oscillation circuit operate by connecting external resistance (capacitance is incorporated). this circuit provides the clock signal to both common and segment drivers. (1-2) divider circuit this circuit divides the oscillating signal to generate the common and segment timing. (1-3) shift-register when the ce terminal is "h" (enable mode), the display data is transferred to the shift-register synchronized by the shift clock on the scl terminal. (1-4) latch circuit and segment driver when the ce signal falling, the display data is latched, and the data controls the segment signal of display-on/off. (2) data input format (2-1) input data correspond to segment status the "h" input data correspond to segment "on" and "l" correspond to "off". data dxxx segment status ?h? on ?l? off
NJU6433B ver.2005-07-08 -5- (2-2) write to shift-register write to shift-register performes mode setting data writing and lcd display data writing.
NJU6433B ver.2005-07-08 - 6 - (2-3) mode setting transferd register selection and all clear of the shift register are performed by writing 4-bit code shown below to the decoder in ce ="h" and mode ="h" state. ce terminal mode terminal data terminal mode # data d 3 d 2 d 1 d 0 (hex) mode set up 0 0 0 1 (01 h ) select the shift-register 1 0 0 1 0 (02 h ) select the shift-register 2 0 0 1 1 (03 h ) select the shift-register 3 0 1 0 0 (04 h ) select the shift-register 4 0 1 0 1 (05 h ) select the all shift-register (1 to 4) ?h? ?h? 1 1 1 1 (0f h ) all shift-register is "l" note) the internal decoder is data through type. therefore, the 8 bits data also can write though only 4 bits data from the ce falling are validated.
NJU6433B ver.2005-07-08 -7- (2-4) block data and whole data transfer a. block data (50-bit) transfer in this mode, each 50 bits data block send to the each register. b. whole data (200-bit) transfer
NJU6433B ver.2005-07-08 - 8 - (2-5) display data correspond to segment and common terminals
NJU6433B ver.2005-07-08 -9- absolute maximum ratings parameter symbol ratings unit note operating voltage (1) v dd -0.3~+7.0 v operating voltage (2) v lcd v dd -6.5~v ss v 1 input voltage (1) v 1(1) -0.3~+7.0 v 2 input voltage (2) v 1(2) -0.3~v dd +0.3 v 3 output voltage v 0 -0.3~v dd +0.3 v 3 output current (1) i o(1) 100 ua 4 output current (2) i o(2) 1.0 ma 5 power dissipation p d 300 mw operating temperature t opr -30~+85 c storage temperature t stg -40~+125 c note 1) v dd x 1.3 |v dd -v lcd |, v ss v lcd note 2) ce, scl, data, mode, inhb terminals note 3) osc 1 , osc 2 terminals note 4) seg 1 ~seg 50 terminals note 5) com 1 ~com 4 terminals electrical characteristics ? dc characteristics parameter symbol conditions min typ max unit no te operating voltage (1) v dd v dd te r m i n a l 2.4 5.0 5.5 v operating voltage (2) v lcd v lcd te r m i n a l v ss v dd -6.5 v 1 "h" input voltage v ih 0.7v dd v dd v "l? input voltage v il ce, scl, data, mode, inhb v ss 0.3v dd v "h" input current v ih v 1 =v dd 5 ua "l" input current v il ce,scl, data,mode, inhb v 1 =v ss 5 ua "h" output voltage (1) v oh(1) i o =-10ua v dd -1.0 v "l? output voltage (1) v ol(1) seg 1 ~seg 50 i o =+10ua v lcd +1.0 v middle level voltage 1/3(1) v ms1/3 i o = 10ua v 1 -1.0 v 1 v 1 +1.0 v middle level voltage 2/3(1) v ms2/3 seg 1 ~seg 50 i o = 10ua v 2 -1.0 v 2 v 2 +1.0 v 2 "h" output voltage (2) v oh(2) i o =-100ua v dd -0.6 v "l" output voltage (2) v ol(2) com 1 ~com 4 i o =+100ua v lcd +0.6 v middle level voltage 1/3(2) v mc1/3 i o = 100ua v 1 -0.6 v 1 v 1 +0.6 v middle level voltage 2/3(2) v mc2/3 com 1 ~com 4 i o = 100ua v 2 -0.6 v 2 v 2 +0.6 v 2 oscillating frequency range f osc osc 1 , osc 2 te r m i n a l s 25 200 khz oscillating frequency f osc osc 1 , osc 2 , r=140k ? 115 130 145 khz operating current (1) i dd v dd te r m i n a l 50 80 ua operating current (2) i lcd v lcd te r m i n a l 15 25 ua hysteresis voltage v h ce, scl, data, mode, inhb 0.3 v note 1) the relation : v dd x 1.3 |v dd -v lcd |, v ss v lcd must be maintained. note 2) v 1 =1/3|v dd -v lcd |, v 2 =2/3|v dd -v lcd | (ta= 25 c , v dd =5.0v, v ss =0v, v lcd =v dd -6.5v) v 2 v 1 1/3|v dd -v lcd | 2/3|v dd -v lcd | v dd v lcd
NJU6433B ver.2005-07-08 - 10 - ? ac characteristics parameter symbol conditions min typ max unit "l" clock pulse width t wcll scl 0.25 us "h" clock pulse width t wclh scl 0.25 us data set-up time t ds scl, data 0.25 us data hold time t dh scl, data 0.25 us ce set-up time t sce ce, data 1.0 us ce hold time (1) t hdce ce, data 1.0 us ce hold time (2) t hcle ce, scl t 1.25 us mode set-up time t smd mode, ce 0.25 us mode hold time t hmd mode, ce 0.25 us "l" chip enable pulse width t wcel ce 4.0 us power supply rise time t rdd v dd 0.1 10 ms power supply off time t off v dd 1 ms ? input timing characteristics (ta= 25 c , v dd =5.0v, v ss =0v, v lcd =v dd -6.5v) v dd 4.5v 0.2v t rdd t off 0.2v 0.2v 5.0v
NJU6433B ver.2005-07-08 -11- ? lcd driving waveform(1/4duty ? 1/3bias)
NJU6433B ver.2005-07-08 - 12 - application circuit note) the internal display data is undefined when v dd is just turned on. to avoid the meaningless display, please keep the inhb terminal at "l" until proper display data has been transferred. in order to set the initial condition, 200-bit blank data or the first 200-bit data to be displayed should be transferred. b [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

▲Up To Search▲

Price & Availability of NJU6433B

	To Download NJU6433B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .