View TDF8599TH_3294294.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1. general description the tdf8599 is a dual bridge-tied load (btl) car audio ampli?er comprising an ndmost-ndmost output stage based on soi bcdmos technology. low dissipation enables the tdf8599 high-ef?ciency, class-d ampli?er to be used with a smaller heat sink than those normally used with standard class-ab ampli?ers. the tdf8599 can operate in either non-i 2 c-bus mode or i 2 c-bus mode. when in i 2 c-bus mode, dc load detection results and fault conditions can be easily read back from the device. up to ?ve i 2 c-bus addresses can be selected when an external resistor is connected to pin ads. when pin ads is short circuited to ground, the tdf8599 operates in non-i 2 c-bus mode. switching between operating mode and mute mode in non-i 2 c-bus mode is only possible using pins en and sel_mute. 2. features n high-ef?ciency n low quiescent current n operating voltage from 8 v to 18 v n two 4 w /2 w capable btl channels or one 1 w capable btl channel n differential inputs n supports i 2 c-bus mode with ?ve i 2 c-bus addresses or non-i 2 c-bus mode operation n clip detect n independent short circuit protection for each channel n advanced short circuit protection for load, gnd and supply n load dump protection n thermal foldback and thermal protection n dc offset protection n selectable ad or bd modulation n parallel channel mode for high current drive capability n advanced clocking: u switchable oscillator clock source: internal (master) or external (slave) u spread spectrum mode u phase staggering u frequency hopping n no pop noise caused by dc output offset voltage tdf8599 i 2 c-bus controlled dual channel 43 w/2 w single channel 85 w/1 w class-d power ampli?er with load diagnostics rev. 01 13 november 2008 product data sheet
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 2 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics n i 2 c-bus mode: u dc load detection u ac load detection u thermal pre-warning diagnostic level setting u identi?cation of activated protections or warnings u selectable diagnostic information available using pin diag n quali?ed in accordance with aec-q100 3. applications n car audio applications 4. quick reference data [1] output power is measured indirectly based on r dson measurement. 5. ordering information table 1. quick reference data symbol parameter conditions min typ max unit general; v p = 14.4 v v p supply voltage 8 14.4 18 v i stb standby current voltage on pin en < 0.8 v - - 10 m a i q(tot) total quiescent current operating mode; no load, snubbers and ?lter connected - 90 120 ma dual btl channel; v p = 14.4 v p o output power stereo mode; thd = 1 %; r l =4 w [1] 18 20 - w thd = 10 %; r l =4 w 24 26 - w square wave (eiaj); r l =4 w -40-w thd = 1 %; r l =2 w 29 32 - w thd = 10 %; r l =2 w 39 43 - w square wave (eiaj); r l =2 w -70-w parallel mode thd = 10 %; r l =1 w [1] -85-w table 2. ordering information type number package name description version TDF8599TH hsop36 plastic, heatsink small outline package; 36 leads; low stand-off height sot851-2 tdf8599td hsop36 plastic, heatsink small outline package; 36 leads; low stand-off height sot938-1
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 3 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 6. block diagram fig 1. block diagram 001aai766 pwm ctrl tdf8599 driver high stabi1 5 v stabi stabi2 vp1 out1n boot1p out1p out2n boot2p out2p vstab2 33 vstab1 34 24 31 10 9 1 2 5 3 4 8 agnd svrr in1p in1n acgnd in2p in2n vp2 vp1 v dda 32 29 28 23 22 26 27 pgnd1 vp1 pgnd1 + driver low pwm ctrl driver high driver low boot1n boot2n pwm ctrl driver high vp2 pgnd2 vp2 pgnd2 driver low pwm ctrl driver high driver low oscillator 18 oscset 19 oscio 17 ssm 12 mod mode select + i 2 c-bus diagnostics protections ovp, ocp, otp uvp, tf, wp,dcp gndd/hw clip dcp 6 en 7 sel_mute 16 scl 15 sda 11 36 diag 14 13 20 ads pgnd1 30 pgnd2 25 35 v ddd 21
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 4 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 7. pinning information 7.1 pinning fig 2. heatsink up (top view) pin con?guration TDF8599TH TDF8599TH out1n in1p boot1n in1n vp1 in2p pgnd1 gndd/hw v ddd vstab1 in2n boot1p acgnd out1p en out2p sel_mute boot2p svrr pgnd2 agnd vp2 v dda ads mod 001aai767 36 35 34 33 32 31 30 29 28 27 26 25 11 12 9 10 7 8 clip boot2n diag out2n sda vstab2 scl 24 23 22 21 15 16 13 14 dcp ssm oscio oscset 20 19 17 18 5 6 3 4 1 2
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 5 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 7.2 pin description fig 3. heatsink down (top view) pin con?guration tdf8599td tdf8599td in1p gndd/hw in1n v ddd in2p vstab1 in2n out1n acgnd boot1n en vp1 sel_mute pgnd1 svrr boot1p agnd out1p v dda out2p 001aai768 1 2 3 4 5 6 7 8 9 10 ads mod clip diag sda scl ssm oscset 11 12 13 14 15 16 17 18 28 27 30 29 32 31 34 33 boot2p pgnd2 vp2 boot2n out2n vstab2 dcp oscio 20 19 22 21 24 23 26 25 36 35 table 3. pin description symbol pin type [1] description in1p 1 i channel 1 positive audio input in1n 2 i channel 1 negative audio input in2p 3 i channel 2 positive audio input in2n 4 i channel 2 negative audio input acgnd 5 i decoupling for input reference voltage en 6 i enable input: non-i 2 c-bus mode: switch between off and mute mode i 2 c-bus mode: off and standby mode sel_mute 7 i select mute or on (unmute) svrr 8 i decoupling for internal half supply reference voltage agnd 9 g analog supply ground v dda 10 p analog supply voltage ads 11 i non-i 2 c-bus mode: connected to ground i 2 c-bus mode: selection and address selection pin mod 12 i modulation mode, phase shift and parallel mode select
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 6 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics [1] i = input, o = output, i/o = input/output, g = ground and p = power supply. 8. functional description 8.1 general the tdf8599 is a dual full bridge (btl) audio power ampli?er utilizing class-d technology. the audio input signal is converted into a pulse-width modulated (pwm) signal using the analog input and pwm control stages. a pwm signal is applied to driver circuits for both high-side and low-side enabling the dmos power output transistors to be driven. an external 2 nd order low-pass ?lter converts the pwm signal into an analog audio signal across the loudspeakers. clip 13 o clip output; open-drain diag 14 o diagnostic output; open-drain sda 15 i/o i 2 c-bus data input and output scl 16 i i 2 c-bus clock input ssm 17 master setting: spread spectrum mode frequency slave setting: phase lock operation oscset 18 master/slave setting oscillator master only setting: set internal oscillator frequency oscio 19 i/o external oscillator slave setting: input internal oscillator master setting: output dcp 20 i dc protection input for the ?ltered output voltages vstab2 21 decoupling internal stabilizer 2 for dmost drivers out2n 22 o channel 2 negative pwm output boot2n 23 boot 2 negative bootstrap capacitor vp2 24 p channel 2 power supply voltage pgnd2 25 g channel 2 power ground boot2p 26 boot 2 positive bootstrap capacitor out2p 27 o channel 2 positive pwm output out1p 28 o channel 1 positive pwm output boot1p 29 boot 1 positive bootstrap capacitor pgnd1 30 g channel 1 power ground vp1 31 p channel 1 power supply voltage boot1n 32 boot 1 negative bootstrap capacitor out1n 33 o channel 1 negative pwm output vstab1 34 decoupling internal stabilizer 1 for dmost drivers v ddd 35 decoupling of the internal 5 v logic supply gndd/hw 36 g ground digital supply voltage handle wafer connection table 3. pin description continued symbol pin type [1] description
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 7 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics the tdf8599 includes integrated common circuits for all channels such as the oscillator, all reference sources, mode functionality and a digital timing manager. in addition, the built-in protection includes thermal foldback, temperature, overcurrent and overvoltage (load dump). the tdf8599 operates in either i 2 c-bus mode or non-i 2 c-bus mode. in i 2 c-bus mode, dc load detection, frequency hopping and extended con?gurability are provided together with enhanced diagnostic information. 8.2 mode selection the mode pins en and sel_mute enable mute state, i 2 c-bus mode and operating mode switching. pin sel_mute is used to mute and demute the device and must be connected to an external capacitor. this capacitor generates a time constant which is used to ensure smooth fade-in and fade-out of the input signal. when pin en is low, the tdf8599 is off and the supply current is at its lowest value (typically 2 m a). when off, the tdf8599 is completely deactivated and will not react to i 2 c-bus commands. the tdf8599 is enabled when pin en is high. a resistor connected between pin ads and ground determines if the tdf8599 is in i 2 c-bus mode or in non-i 2 c-bus mode (see section 9 ). i 2 c-bus mode is selected by leaving the connection between pin ads and pin gnd open. in i 2 c-bus mode with pin en high, the tdf8599 is in standby mode and will wait for further commands. non-i 2 c-bus mode is selected by connecting pin ads to pin gnd. in non-i 2 c-bus mode, the default tdf8599 state is mute mode. the ampli?ers switch idle (50 % duty cycle) and the audio signal is suppressed at the output. in addition, the capacitor (c svrr ) is charged to half the supply voltage. to enter operating mode, pin sel_mute must be released (see figure 4 ) and capacitor (c on ) charged by an internal pull-up. i 2 c-bus mode and non-i 2 c-bus mode control are described in t ab le 4 and t ab le 5 . switches s1 and s2 are illustrated in figure 4 . a. non-i 2 c-bus mode b. i 2 c-bus mode fig 4. mode selection 001aai769 sel_mute en 3.3 v c on s1 s2 tdf8599 001aai770 sel_mute en 3.3 v c on s2 tdf8599
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 8 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics [1] x = do not care 8.3 pulse-width modulation frequency the output signal from the ampli?er is a pwm signal with a switching frequency of f osc . this frequency is set by connecting a resistor (r osc ) between pins oscset and agnd. the optimal clock frequency setting is between 300 khz and 400 khz. connecting a resistor with a value of 39 k w , for example, sets the clock frequency to 320 khz. the external capacitor (c osc ) has no in?uence on the oscillator frequency. it does however, reduce jitter and sensitivity to disturbance. using a 2 nd order lc demodulation ?lter in the application generates an analog audio signal across the loudspeaker. 8.3.1 master and slave mode selection in a master and slave con?guration, multiple tdf8599 devices are daisy-chained together in one audio application with a single device providing the clock frequency signal for the other devices. in this situation, it is recommended that the oscillators of all devices are synchronized for optimum emi behavior as follows: all oscio pins are connected together and one tdf8599 in the application is con?gured as the clock-master. all other tdf8599 devices are con?gured as clock-slaves (see figure 6 ). ? the clock-master pin oscio is con?gured as the oscillator output. when a resistor (r osc ) is connected between pins oscset and agnd, the tdf8599 is in master mode. ? the clock-slave pins oscio are con?gured as the oscillator inputs. when pin oscset is directly connected to pin agnd (see t ab le 6 ), the tdf8599 is in slave mode. table 4. i 2 c-bus mode operation pin en bit ib1[d0] bit ib2[d0] mode s2 closed 1 0 operating mode 1 1 mute mode 0x [1] standby mode s2 open x [1] x [1] off table 5. non-i 2 c-bus mode operation pin en bit ib2[d0] mode s2 closed s1 open operating mode s2 closed mute mode s2 open do not care off table 6. mode setting oscio mode settings pin oscset pin oscio master r osc > 26 k w output slave r osc =0k w ; shorted to agnd input
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 9 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics the value of the resistor r osc sets the carrier frequency based on the following formula: (1) in master mode, spread spectrum mode and frequency hopping can be enabled. in slave mode, phase staggering and phase lock operation can be selected. an external clock can be used as the master-clock on pin oscio of the slave devices. when using an external clock it must remain active during the shutdown sequence to ensure that all devices are switched off and able to enter the off state as described in section 8.2 . 8.3.2 spread spectrum mode (master mode) spread spectrum mode is a technique of modulating the oscillator frequency with a slow varying signal to broaden the switching spectrum, thereby reducing the spectral density of the emi. connecting a capacitor (c ssm ) to pin ssm enables spread spectrum mode (see figure 7 ). when pin ssm is connected to pin agnd, spread spectrum mode is disabled. the capacitor on pin ssm (c ssm ) sets the spreading frequency when spread spectrum mode is active. the current (i ssm ) ?owing in and out of pin ssm is typically 5 m a. this gives a triangular voltage on pin ssm that sweeps around the voltage set by pin oscset 5 %. the voltage on pin ssm is used to modulate the oscillator frequency. fig 5. oscillator frequency as function of r osc fig 6. master and slave con?guration f osc 12.45 10 9 r osc --------------------------- - hz [] = f osc (khz) 300 500 450 350 400 001aai771 20 30 10 40 50 r osc (k w ) 0 001aai772 oscset oscio master c osc r f osc r osc tdf8599 oscset oscio slave 1 tdf8599 oscset oscio slave 2 tdf8599
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 10 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics the spread spectrum frequency can be calculated using: (2) where the voltage on pin oscset = v 1 and is calculated as 100 m a r osc (v) with i ssm =5 m a. the frequency swings between 0.95 f osc and 1.05 f osc , see figure 8 . 8.3.3 frequency hopping (master mode) frequency hopping is a technique used to change the oscillator frequency for am tuner compatibility. in master mode, the resistor connected between pin oscset and pin agnd sets the oscillator frequency. in i 2 c-bus mode, this frequency can be varied by 10 % to 0.9 f osc or 1.1 f osc using bit ib1[d3:d4]. see figure 8 . 8.3.4 phase lock operation (slave mode) in slave mode, phase lock operation can be used to reduce the jitter effects of the external oscillator signal connected to pin oscio. phase lock operation is also needed to enable phase staggering, see section 8.4.2 . phase lock operation is enabled when the oscillator is in slave mode by connecting two capacitors (c pll_s and c pll_p ) and a resistor (r pll ) between pin ssm and pin agnd (see figure 9 ). connecting pin ssm to pin agnd disables phase lock operation and causes the slave to use the external oscillator signal f ssm i ssm 2c ssm v 1 10 % ------------------------------------------------------ hz [] = a. off b. on fig 7. spread spectrum mode 001aai773 100 m a r osc ssm c osc oscset 001aai774 100 m a 5 m a i ssm r osc ssm c osc c ssm oscset fig 8. spread spectrum operation in master mode 001aai775 t (ms) oscio max(v) min(v) ssm
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 11 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics directly. values for c pll_s , c pll_p and r pll depend on the desired loop bandwidth (bw pll ) of the pll. r pll is given by: r pll = 8.4 bw pll w . the corresponding values for c pll_s and c pll_p are given by: (3) remark: c pll_p is only needed when p /4 phase shift is selected. see section 8.4.2 for more detailed information. (4) when pin oscio is connected to a clock-master with spread spectrum mode enabled, the pll loop bandwidth bw pll should be 100 f ssm . see t ab le 7 for all oscillator modes. 8.4 operation mode selection pin mod is used to select speci?c operation modes. the resistor (r mod ) connected between pins mod and agnd determines the operation mode. the mode of operation depends on whether non-i 2 c-bus mode or i 2 c-bus mode is active. this is in turn determined by the resistor value connected between pins ads and agnd. a. off b. on fig 9. phase lock operation table 7. oscillator modes oscset pin oscio pin ssm pin oscillator modes r osc > 26 k w output c ssm master, spread spectrum r osc > 26 k w output shorted to agnd master, no spread spectrum r osc =0 w input c pll + r pll slave, pll enabled r osc =0 w input shorted to agnd slave, pll disabled c pll_p 0.032 r pll bw pll ------------------------------------ f [] = c pll_s 0.8 r pll bw pll ------------------------------------ f [] = 001aai776 100 m a ssm oscset pll 001aai777 100 m a pll oscset r pll c pll_p (1) c pll_s ssm
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 12 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics in non-i 2 c-bus mode pin mod is used to select: 1. ad or bd modulation type (see section 8.4.1 ). 2. 1 2 p phase shift when oscillator is used in slave mode (see section 8.4.2 ). 3. parallel mode operation (see section 8.4.3 ). in i 2 c-bus mode, pin mod can only select parallel mode. in addition, the modulation type and phase shift are programmed using i 2 c-bus commands. the information on pin mod is latched when one of the tdf8599 outputs starts switching to avoid incorrect information on pin mod caused by disturbances of switching ampli?er outputs. 8.4.1 modulation mode in non-i 2 c-bus mode, pin mod is used to select either ad or bd modulation mode. in i 2 c-bus mode, the modulation mode is selected using an i 2 c-bus command. ? ad modulation mode: the bridge halves switch in opposite phase. ? bd modulation mode: the bridge halves switch in phase but the input signal for the modulators is inverted. figure 10 , figure 11 and figure 12 show simpli?ed representations of ad and bd modulation. table 8. operation mode selection with the mod pin r mod (k w ) i 2 c-bus mode non-i 2 c-bus mode 0 (short to gnd) stereo mode ad modulation: no phase shift in slave mode 4.7 bd modulation: no phase shift in slave mode 13 ad modulation: 1 2 p phase shift in slave mode 33 bd modulation: 1 2 p phase shift in slave mode 100 parallel mode ad modulation: no phase shift in slave mode ( open) bd modulation: no phase shift in slave mode fig 10. ad/bd modulation switching circuit 001aai778 +v p outp ad bd inxp inxn outn +v p
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 13 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.4.2 phase staggering (slave mode) in slave mode with phase lock operation enabled, a phase shift with respect to the incoming clock signal can be selected to distribute the switching moments over time. in non-i 2 c-bus mode, 1 2 p phase shift can be programmed using pin mod. in i 2 c-bus mode, ?ve different phase shifts ( 1 4 p , 1 3 p , 1 2 p , 2 3 p , 3 4 p ) can be selected using the i 2 c-bus bits (ib3[d1:d3]). see figure 9 for selection of the phase shift in non-i 2 c-bus mode with pin mod. an additional capacitor must be connected to pin ssm when 1 4 p phase shift is used (see figure 9 ). an example of using 1 2 p phase shift for bd modulation is shown in figure 13 . a. bridge half 1. b. bridge half 2 switched in the opposite phase to bridge half 1. fig 11. ad modulation a. phase switching cycle. b. inverted signal to the modulator. fig 12. bd modulation 001aai779 inxp outxp 001aai780 inxn outxn 001aai781 inxp outxp outxp, outxn 001aai782 inxn outxn
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 14 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.4.3 parallel mode in parallel mode; the two output stages operate in parallel to enlarge the drive capability. the inputs and outputs for parallel mode must be connected on the printed-circuit board (pcb) as shown in figure 14 . the parallel connection can be made after the output ?lter, as shown in figure 14 or directly to the device output pins. in parallel mode, the channel 1 i 2 c-bus bits can be programmed using the i 2 c-bus. however, clip detection must be deactivated by disabling clip detection for both channel 1 and channel 2. fig 13. master and slave operation with 1 2 p phase shift. 001aai783 out1p phase 0 p 1/2 p 3/2 p out1n out2p out2n out1p out1n out2p master slave out2n fig 14. mono and parallel modes 001aai784 in1p mod r mod in2n in1n out1n out2n out1p out2p + - - + in2p tdf8599
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 15 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.5 protection the tdf8599 includes a range of built-in protection functions. how the tdf8599 handles the various possible fault conditions differs for each protection and is described in the following sections: 8.5.1 thermal foldback thermal foldback protection (tfp) is activated when the junction temperature exceeds the threshold level (145 c). tfp decreases ampli?er gain such that the combination of dissipation and r th(j-a) create a junction temperature around the threshold level. the device will not completely switch off but remains operational at the lower output power levels. if the junction temperature continues to increase, a second built-in temperature protection threshold level shuts down the ampli?er completely. 8.5.2 overtemperature protection if the junction temperature t j > 160 c, the overtemperature protection (otp) is activated and the power stage immediately shuts down. 8.5.3 overcurrent protection overcurrent protection (ocp) is activated when the output current exceeds the maximum output current of 8 a. ocp regulates the output voltage such that the maximum output current is limited to 8 a. the ampli?er outputs keep switching and the ampli?er is not shutdown completely. this is called current limiting. ocp also detects when the loudspeaker terminals are short circuited or one of the ampli?ers demodulated outputs is short circuited to one of the supply lines. in either case, the shorted channel(s) are switched off. the ampli?er can distinguish between loudspeaker impedance drops and a low-ohmic short across the load or one of the supply lines. this impedance threshold depends on the supply voltage used. when a short is made across the load causing the impedance to drop below the threshold level, the shorted channel(s) are switched off. they try to restart every 50 ms. if the short circuit condition is still present after 50 ms, the cycle repeats. the average dissipation will be low because of this forced reduced duty cycle. when a channel is switched off due to a short circuit on one of the supply lines, window protection (wp) is activated. wp ensures the ampli?er does not start-up after 50 ms until the supply line short circuit is removed. table 9. overview of protection types protection type reference thermal foldback section 8.5.1 overtemperature section 8.5.2 overcurrent section 8.5.3 window section 8.5.4 dc offset section 8.5.5 undervoltage section 8.5.6 overvoltage section 8.5.6
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 16 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.5.4 window protection window protection (wp) checks the pwm output voltage before switching from standby mode to mute mode (outputs switching) and is activated as follows: ? during the start-up sequence: C when the tdf8599 is switched from standby to mute (t d(stb-mute) ). when a short circuit on one of the output terminals (i.e. between v p and gnd) is detected, the start-up procedure is interrupted and the tdf8599 waits for open circuit outputs. no large currents ?ow in the event of a short circuit to the supply lines because the check is performed before the power stages are enabled. ? during operation: C a short to one of the supply lines activates ocp causing the ampli?er channel to shutdown. after 50 ms the ampli?er channel restarts and wp is activated. however, the corresponding ampli?er channel will not start-up until the supply line short circuit has been removed. 8.5.5 dc protection dc protection (dcp) is activated when the dc content in the demodulated output voltage exceeds a set threshold (typically 2 v). dcp is active in both mute mode and operating mode. false triggering of the dcp by low frequencies in the audio signal is prevented using the external capacitor (c f ) to generate a cut-off frequency as shown in figure 15 . fig 15. dc offset protection and diagnostic output 001aai785 out1p out1n v to i out2p out2n dcp diag switch off channels ib1[d6] ib2[d6] v to i v ref sq db1[d7] ib1[d7] ib2[d7] s4 50 k w s3 c f
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 17 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics in i 2 c-bus mode, dc offsets generate a voltage shift around the bias voltage. when the voltage shift exceeds threshold values, the offset alarm bit db1[d2] is set and if bit ib1[d7] is set, diagnostic information is also given. any detected offset shuts down both channels when bit ib2[d7] is not set. to restart the tdf8599 in i 2 c-bus mode, pin en must be toggled or dcp disabled by connecting pin dcp to pin gnd. in non-i 2 c-bus mode, when an offset is detected, dcp always gives diagnostic information on pin diag and shuts down both channels. connecting pin dcp to pin gnd disables dcp. 8.5.6 supply voltages undervoltage protection (uvp) is activated when the supply voltage drops below the uvp threshold (typically 7.5 v). uvp triggers the uvp circuit causing the system to ?rst mute and then stop switching. when the supply voltage rises above the threshold level, the system restarts. overvoltage protection (ovp) is activated when the supply voltage exceeds the ovp threshold (typically 27 v). the ovp (or load dump) circuit is activated and the power stages are shutdown. an overview of all protection circuits and the ampli?er states is given in t ab le 10 . 8.5.7 overview of protection circuits and ampli?er states [1] when fault is removed. [2] ampli?er gain depends on the junction temperature and size of the heat sink. [3] tfp in?uences restart timing depending on heat sink size. [4] shorted load causes a restart of the channel every 50 ms. [5] latched protection is reset by toggling the pin en or by disabling dcp in i 2 c-bus mode. [6] in i 2 c-bus mode deep supply voltage drops will cause a power-on reset (por). the restart requires an i 2 c-bus command. table 10. overview of tdf8599 protection circuits and ampli?er states protection circuit name ampli?er state complete shutdown channel shutdown restart [1] tfp n [2] n [2] y [3] otp y n y [3] ocp n y y [4] wp n y y dcp y n n [5] uvp y n y [6] ovp y n y
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 18 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.6 diagnostic output 8.6.1 diagnostic table the diagnostic information for i 2 c-bus mode and non-i 2 c-bus mode is shown in t ab le 11 . the instruction bitmap and data bytes are described in t ab le 14 and t ab le 15 . pins diag and clip have an open-drain output which must have an external pull-up resistor connected to an external voltage. pins clip and diag can show both ?xed and i 2 c-bus selectable information. pin diag goes low when a short circuit to one of the ampli?er outputs occurs. the microprocessor reads the failure information using the i 2 c-bus. the i 2 c-bus bits are set for a short circuit. these bits can be reset with the i 2 c-bus read command. even after the short has been removed, the microprocessor knows what was wrong after reading the i 2 c-bus. in principle, during a single i 2 c-bus read command, the old information is read. to read the current information, two read commands must be sent, one-after-another. when selected, pin diag gives the current diagnostic information. pin diag is released instantly when the failure is removed, independent of the i 2 c-bus latches. when ocp is triggered, the open-drain diag output is activated. the diagnostic output signal during different short circuit conditions is illustrated in figure 16 . table 11. available data at diag and clip pin diagnostic i 2 c-bus mode non-i 2 c-bus mode diag clip diag clip power-on reset yes no yes no uvp or ovp yes no yes no clip detection no selectable no yes temperature pre-warning no selectable no yes ocp yes no yes no dcp selectable no yes no otp yes no yes no fig 16. diagnostic output for short circuit conditions 001aai786 amplifier restart shorted load pull up v agnd = 0 v ? 50 ms ? 50 ms ? 50 ms no restart short to gnd or vp line
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 19 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.6.2 load identi?cation (i 2 c-bus mode only) 8.6.2.1 dc load detection dc load detection is only available in i 2 c-bus mode and is controlled using bit ib2[d2]. the default setting is logic 0 for bit ib2[d2] which disables dc load detection. dc load detection is enabled when bit ib2[d2] = 1. load detection takes place before the class-d ampli?er output stage starts switching in mute mode (see figure 17 ) and the start-up time from standby mode to mute mode is increased by t det(dcload) the capacitor connected to pin sel_mute (see figure 4 ) is used to create an inaudible current test pulse, drawn from the positive ampli?er output. the diagnostic speaker load (or open load), based on the voltage difference between pins outxp and outxn is shown in figure 19 . fig 17. dc load detection circuit fig 18. dc load detection procedure fig 19. dc load detection limits 001aai787 pwm control driver high v p pgnd1 outn outp r l b driver low pwm control driver high v p pgnd2 driver low 001aai788 out (v) t det(dcload) t d(mute-off) t (s) out - out+ 001aai789 0 w 25 w 350 w speaker load open load
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 20 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics remark: dc load detection identi?es a short circuited speaker as a valid speaker load. ocp detection, using byte db1[d3] for channel 1 and byte db2[d3] for channel 2, performs diagnostics on shorted loads. however, the diagnostics are performed after the dc load detection cycle has ?nished and once the ampli?er is in operating mode. the result of the dc load detection is stored in db1[d4] and db2[d4]. remark: after dc load detection has been performed, the dc load valid bit db1[d6] must be set. the dc load data bits are only valid when bit db1[d6] = 1. when dc load detection is interrupted by a sudden large change in supply voltage (triggered by uvp or ovp) or if the ampli?er hangs up, the dc load valid bit is reset to db1[d6] = 0. the dc load enable bit db2[d2] must be reset after the dc load protection cycle to release any ampli?er hang-up. once the dc load detection cycle has ?nished, dc load detection can be restarted by toggling the dc load detection enable bit ib2[d2]. however, this can only be used if both ampli?er channels have not been enabled with bit ib1[d1] or bit ib2[d1]. see section 8.6.2.2 recommended star t-up sequence with dc load detection enab led for detailed information. 8.6.2.2 recommended start-up sequence with dc load detection enabled the ?ow diagram ( figure 20 ) illustrates the tdf8599s ability to perform a dc load detection without starting the ampli?ers. after a dc load detection cycle ?nishes without setting the dc load valid bit db1[d6], dc load detection is repeated (when bit ib2[d2] is toggled). to limit the maximum number of dc load detection cycle loops, a counter and limit have been added. the loop exits after the prede?ned number of cycles (countmax), if the dc load detection cycle ?nishes with an invalid detection. depending on the application needs the invalid dc load detection cycle can be handled as follows: ? the ampli?er can be started without dc load detection ? the dc load detection loop can be executed again a valid dc load detection cycle does not affect the normal ampli?er start-up timing. table 12. interpretation of dc load detection bits dc load bits db1[d4] and db2[d4] ocp bits db1[d3] and db2[d3] meaning 0 0 speaker load 0 1 shorted load 1 0 open load
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 21 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 8.6.2.3 ac load detection ac load detection is only available in i 2 c-bus mode and is controlled using bit ib3[d4]. the default setting for bit ib3[d4] = 0 which disables ac load detection. when ac load detection is enabled (bit ib3[d4] = 1), the ampli?er load current is measured and compared with a reference level. pin clip is activated when this threshold is reached. using this information, ac load detection can be performed using a predetermined input signal frequency and level. the frequency and signal level should be chosen so that the load current exceeds the programmed current threshold when the ac coupled load (tweeter) is present. 8.6.2.4 clip detection clip detection gives instantaneous information for clip levels 3 1 %. pin clip is used as the output for the clip detection circuitry on both channel 1 and channel 2. setting either bit ib1[d5] or bit ib2[d5] de?nes which channel reports clip information on the clip pin. fig 20. recommended start-up sequence with dc load detection enabled 001aaj061 no no yes yes restart dc load start amplifier anyway i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 1 enable dc load ib1[d1] = 1 disable channel 1 ib2[d1] = 1 disable channel 2 i 2 c-bus rx db1[d4] = 1 ch1 openload db2[d4] = 1 ch2 openload db1[d6] = 1 dc load valid i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 0 disable dc load ib1[d1] = 0 enable channel 1 ib2[d1] = 0 enable channel 2 i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 0 disable dc load ib1[d1] = 1 disable channel 1 ib2[d1] = 1 disable channel 2 i 2 c-bus tx ib1[d0] = 1 startup ib2[d2] = 1 enable dc load ib1[d1] = 1 disable channel 1 ib2[d1] = 1 disable channel 2 error handling count = 0 wait dc load count = count + 1 db1[d6] = 1 dc load valid count countmax
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 22 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics in parallel mode, disabling clip detection on both channels requires both bits to be set to bit ib1[d5] = 1 and bit ib2[d5] = 1. 8.6.3 start-up and shutdown sequence to prevent the switch on or switch off pop noise, a capacitor (c svr ) connected to pin svr is used to smooth start-up and shutdown. during start-up and shutdown, the output voltage tracks the voltage on pin svr. increasing c svr results in a longer start-up and shutdown time. enhanced pop performance is achieved by muting the ampli?er until the svr voltage reaches its ?nal value and the outputs start switching. the capacitor on the pin sel_mute (c on ) determines the unmute and mute timing. the voltage on pin sel_mute determines the ampli?er gain. increasing c on increases the unmute and mute times. in addition, a larger c on value increases the dc load detection cycle. when the ampli?er is switched off with an i 2 c-bus command or by pulling pin en low, the ampli?er is ?rst muted and then capacitor (c svr ) is discharged. in slave mode, the device enters the off state immediately after capacitor (c svr ) is discharged. in master mode, the clock is kept active by an additional delay (t d (2) ) of approximately 50 ms to allow slave devices to enter off state. when an external clock is connected to pin oscio (in slave mode), the clock remains active during the shutdown sequence (t d (1) ) to ensure that the slaved tdf8599 devices are able to enter the off state. (1) shutdown hold delay (2) master mode shutdown delay (3) shutdown delay fig 21. start-up and shutdown timing in i 2 c-bus mode with dc load detection 001aai790 v dda diag en acgnd ib1[d0] and ib2[d0]=0 sel_mute svr out t d (2) t d (1) mute on delay t d(stb-mute) t wake t det(dcload) t d (3)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 23 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 9. i 2 c-bus speci?cation tdf8599 address with hardware address select. [1] required external resistor accuracy is 1 %. the information on pin ads is latched when the ampli?er starts switching. (1) shutdown hold delay (2) shutdown delay (3) master mode shutdown delay fig 22. start-up and shutdown timing in non-i 2 c-bus mode 001aai791 v dda diag en t d (2) t d (1) t d (3) mute on delay t d(stb-mute) acgnd sel_mute svr out table 13. tdf8599 address using an external resistor ads [1] a6 a5 a4 a3 a2 a1 a0 r/w open 01011000=wr ite to tdf8599 1 = read from tdf8599 100 k w to ground 0101011 33 k w to ground 0101010 13 k w to ground 0101001 4.7 k w to ground 0101000 ground non-i 2 c-bus mode select
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 24 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics (1) when sdl is high, sda changes to form the start or stop condition. (1) sda is allowed to change. (2) all data bits must be valid on the positive edges of the scl. fig 23. i 2 c-bus start and stop conditions fig 24. data bits sent from master microprocessor (m m p) stop start 001aai792 scl sda m m p slave (1) scl sda 001aai793 (2) (1) m m p slave (1) to stop the transfer after the last acknowledge a stop condition must be generated. fig 25. i 2 c-bus write 001aai794 lsb+1 lsb+1 lsb msb - 1 msb msb - 1 msb ack ack ack (1) ack stop write data write start address 12 789 789 12 scl sda m m p slave (1) to stop the transfer, the last byte must not be acknowledged (sda is high) and a stop condition must be generated. fig 26. i 2 c-bus read 001aai795 lsb+1 lsb+1 lsb msb - 1 msb msb - 1 msb ack ack (1) acknowledge stop read data read start address 12 789 789 12 scl sda m m p slave
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 25 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 9.1 instruction bytes if r/w bit = 0, the tdf8599 expects three instruction bytes: ib1, ib2 and ib3. after a power-on reset, all instruction bits are set to zero. [1] see section 8.3.3 on page 10 for information on ib1[d3]. [2] see t ab le 15 f requency bit settings for information. [3] see t ab le 4 , t ab le 5 and t ab le 16 for information on ib2[d0]. table 14. instruction byte descriptions bit value description instruction byte ib1 instruction byte ib2 instruction byte ib3 d7 0 offset detection on diag offset protection on 1 no offset detection on diag offset protection off d6 0 channel 1 offset monitoring on channel 2 offset monitoring on 1 channel 1 offset monitoring off channel 2 offset monitoring off d5 0 channel 1 clip detect on clip channel 2 clip detect on clip 1 channel 1 no clip detect on clip channel 2 no clip detect on clip d4 0 disable frequency hopping thermal pre-warning on clip disable ac load detection 1 enable frequency hopping [1] no thermal pre warning on clip enable ac load detection d3 0 oscillator frequency as set with r osc - 10 % temperature pre-warning on 140 c [2] 1 oscillator frequency as set with r osc +10% temperature pre-warning on 120 c d2 0 dc-load detection disabled [2] 1 dc-load detection enabled d1 0 channel 1 enabled channel 2 enabled [2] 1 channel 1 disabled channel 2 disabled d0 0 tdf8599 in standby all channels operating ad modulation 1 tdf8599 in mute or operating [3] all channels muted bd modulation table 15. frequency bit settings d3 d2 d1 phase 0000 001 1 4 p 010 1 3 p 011 1 2 p 100 2 3 p 101 3 4 p
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 26 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 9.2 data bytes if r/w = 1, the tdf8599 sends two data bytes to the microprocessor (db1 and db2). all short diagnostic and offset protection bits are latched. in addition, all bits are reset after a read operation except the dc load detection bits (dbx[d4], db1[d6]). the default setting for all bits is logic 0. in parallel mode, the diagnostic information is stored in byte db1. data byte db1[d7] indicates whether the instruction bits have been set to logic 0. in principle, db1[d7] is set after a por or when all the instruction bits are programmed to logic 0. pin diag is activated when bit ib1[d7] = 1. table 16. description of data bytes bit value db1 channel 1 db2 channel 2 d7 0 at least 1 instruction bit set to logic 1 below maximum temperature 1 all instruction bits are set to logic 0 maximum temperature protection activated d6 0 invalid dc load data no temperature warning 1 valid dc load data temperature pre-warning active d5 0 no overvoltage no undervoltage 1 overvoltage protection active undervoltage protection active d4 0 speaker load channel 1 speaker load channel 2 1 open load channel 1 open load channel d3 0 no shorted load no shorted load 1 shorted load channel 1 shorted load channel 2 d2 0 no offset reserved 1 offset detected reserved d1 0 no short to v p channel 1 no short to v p channel 2 1 short to v p channel 1 short to v p channel 2 d0 0 no short to ground channel 1 no short to ground channel 2 1 short to ground channel 1 short to ground channel 2
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 27 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 10. limiting values [1] floating condition assumed for outputs. [2] current limiting concept. [3] human body model (hbm). [4] charged-device model (cdm). [5] the output pins are de?ned as the output pins of the ?lter connected between the tdf8599 output pins and the load. 11. thermal characteristics table 17. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v p supply voltage operating mode - 18 v off state [1] - 150v load dump; duration 50 ms, t r >2.5 ms -50v i orm repetitive peak output current maximum output current limiting [2] 8- a i om peak output current maximum; non-repetitive [2] -12a v i input voltage pins scl, sda, ads, mod, ssm, oscio, en and sel_mute 0 5.5 v v o output voltage pins diag and clip 0 10 v t j junction temperature - 150 c t stg storage temperature - 55 +150 c t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage hbm [3] c = 100 pf; r s = 1500 w - 2000 v cdm [4] non-corner pins - 500 v corner pins - 750 v v (prot) protection voltage ac and dc short circuit voltage of output pins across load and to supply and ground [5] 0v p v p max maximum power dissipation t case =70 c - 15 w table 18. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 35 k/w r th(j-c) thermal resistance from junction to case 1 k/w
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 28 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 12. static characteristics table 19. static characteristics v p = 14.4 v; f osc = 320 khz; - 40 c < t amb < +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v p supply voltage 8 14.4 18 v i p supply current off state; t j 85 c; v p = 14.4 v - 2 10 m a i stb standby current voltage on pin en < 0.8 v - - 10 m a i q(tot) total quiescent current operating mode; no load, snubbers and ?lter connected - 90 120 ma series resistance output switches r dson drain-source on-state resistance power switch; t j =25 c - 130 - m w t j = 100 c - 170 - m w i 2 c-bus interface: pins scl and sda v il low-level input voltage 0 - 1.5 v v ih high-level input voltage 2.3 - 5.5 v v ol low-level output voltage pin sda; i load = 5 ma 0 - 0.4 v address, phase shift and modulation mode select: pins ads and mod v i input voltage pins not connected [1] 1.5 2 2.7 v i i input current pins shorted to gnd [1] 80 120 160 m a enable and sel_mute input: pins en and sel_mute v i input voltage pin en; off state 0 - 0.8 v pin en; standby mode; i 2 c-bus mode 2- 5 v pin en; mute mode or operating mode; non-i 2 c-bus mode 2- 5 v pin sel_mute; mute mode; voltage on pin e n>2v 0 - 0.8 v pin sel_mute; operating mode; voltage on pin e n>2v 3- 5 v i i input current pin en; 2.5 v - - 5 m a pin sel_mute; operating mode; 0.8 v --50 m a diagnostic output thd clip total harmonic distortion clip detection level - 0.2 - % v th(offset) threshold voltage for offset detection [2] 123 v v ol low-level output voltage diag or clip pins activated; i o =1ma - - 0.3 v i l leakage current diag and clip pins; diagnostic not activated --50 m a audio inputs; pins in1n, in1p, in2n and in2p v i input voltage - 2.45 - v
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 29 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics svrr voltage and acgnd input bias voltage in mute and operating modes v ref reference voltage input acgnd pin 2 2.45 3 v half supply reference svrr pin 6.9 7.2 7.5 v ampli?er outputs; pins out1n, out1p, out2n and outp2 v o(offset) output offset voltage btl; mute mode - - 25 mv btl; operating mode [3] [5] --70mv stabilizer output; pins vstab1 and vstab2 v o output voltage stabilizer output in mute mode and operating mode 81012v voltage protections v (prot) protection voltage undervoltage; ampli?er is muted 6.8 7.2 8 v overvoltage; load dump protection is activated 26.2 27 - v v p that a por occurs at 3 3.7 4.4 v current protection i o(ocp) overcurrent protection output current current limit 8 - - a temperature protection t prot protection temperature 155 - 160 c t act(th_fold) thermal foldback activation temperature gain = - 1 db 140 - 150 c t j(av)(warn1) average junction temperature for pre-warning 1 ib2[d3] = 0; non-i 2 c-bus mode - 140 150 c t j(av)(warn2) average junction temperature for pre-warning 2 ib2[d3] = 1 - 120 130 c dc load detection levels: i 2 c-bus mode only [6] z th(load) load detection threshold impedance for normal speaker; db1[d4] = 0; db2[d4] = 0 --25 w z th(open) open load detection threshold impedance db1[d4] = 1; db2[d4] = 1 350 - - w ac load detection levels: i 2 c-bus mode only i th(o)det(load)ac ac load detection output threshold current 700 900 1100 ma start-up/shut-down/mute timing t wake wake-up time on pin en before ?rst i 2 c-bus transmission is recognized [4] - - 500 m s t det(dcload) dc load detection time c on = 470 nf [4] - 250 - ms t d(stb-mute) delay time from standby to mute measured from ampli?er enabling to start of mute release (no dc load detection); c svr =47 m f c on = 470 nf - 140 - ms t d(mute-fgain) mute to full gain delay time c on = 470 nf [5] -15- ms table 19. static characteristics continued v p = 14.4 v; f osc = 320 khz; - 40 c < t amb < +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 30 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics [1] required resistor accuracy for pins ads and mod is 1 %; see section 9 on page 23 . [2] maximum leakage current from dcp pin to ground = 3 m a. [3] dc output offset voltage is applied to the output during the transition between mute mode and operating mode in a gradual wa y. [4] i 2 c-bus mode only. [5] the transition time between mute mode and operating mode is determined by the time constant on the sel_mute pin. [6] the dc load valid bit db1[d6] must be used; section 8.6.2.1 on page 19 . the dc load enable bit ib2[d2] must be reset after each load detection cycle to prevent ampli?er hang-up incidents. t d delay time shutdown delay time from en pin low to svrr low; svrr < 0.1 v; c svr =47 m f 145 260 425 ms shutdown delay time from pin en low to acgnd low; voltage on pin acgnd < 0.1 v; master mode - 400 - ms delay in master mode to allow slaved devices to shutdown f osc = 320 khz -50- ms speaker load impedance r l load resistance stereo mode 1.6 4 - w parallel mode 0.8 - - w table 19. static characteristics continued v p = 14.4 v; f osc = 320 khz; - 40 c < t amb < +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 31 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 12.1 switching characteristics table 20. switching characteristics v p = 14.4 v; - 40 c < t amb < +85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit internal oscillator f osc oscillator frequency external clock frequency; r osc =39k w - 320 - khz internal ?xed frequency and spread spectrum mode frequency 300 - 500 khz master/slave setting (oscio pin) r osc oscillator resistance resistor value on pin oscset; master setting 26 39 49 k w v ol low-level output voltage output - - 0.8 v v oh high-level output voltage output 4 - - v v il low-level input voltage input - - 0.8 v v ih high-level input voltage input 4 - - v f track tracking frequency pll enabled 300 - 500 khz n slave number of slaves driven by one master - - 12 spread spectrum mode setting d f osc oscillator frequency variation between maximum and minimum values; spread spectrum mode activated -10 -% f sw switching frequency spread spectrum mode activated; c ssm =1 m f -7 -hz frequency hopping f osc(int) internal oscillator frequency change positive; ib1[d4] = 1; ib1[d3] = 0 -f osc +10% - khz change negative; ib1[d4] = 1; ib1[d3] = 1 -f osc - 10 % - khz timing t r rise time pwm output; i o =0 - 10 - ns t f fall time pwm output; i o =0 - 80 - ns t w(min) minimum pulse width i o =0 - 80 - ns
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 32 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 13. dynamic characteristics [1] r s(l) is the sum of the inductor series resistance from the low-pass lc ?lter in the application together with all resistance from p cb traces or wiring between the output pin of the tdf8599 and the inductor to the measurement point. lc ?lter dimensioning is l = 10 m h, c=1 m f is used and for 2 w load l = 5 m h, c = 2.2 m f for 4 w load. [2] output power is measured indirectly based on r dson measurement. [3] total harmonic distortion is measured at the bandwidth of 22 hz to 20 khz, aes brick wall. the maximum limit is guaranteed but may not be 100 % tested. [4] v ripple =v ripple(max) = 1 v rms; r s =0 w . table 21. dynamic characteristics v p = 14.4 v; r l =4 w ; f i = 1 khz; f osc = 320 khz; r sl < 0.04 w [1] ; - 40 c < t amb < +85 c; stereo mode; unless otherwise speci?ed. symbol parameter conditions min typ max unit p o output power stereo mode; thd = 1 %; r l =4 w [2] 18 20 - w thd = 10 %; r l =4 w 24 26 - w square wave (eiaj); r l =4 w -40-w thd = 1 %; r l =2 w 29 32 - w thd = 10 %; r l =2 w 39 43 - w square wave (eiaj); r l =2 w -70-w parallel mode thd = 10 %; r l =1 w [2] -85-w thd total harmonic distortion f i = 1 khz; p o =1 w [3] - 0.02 0.1 % f i = 10 khz; p o =1 w [3] - 0.02 0.1 % g v(cl) closed-loop voltage gain 25 26 27 db a cs channel separation f i = 1 khz; p o = 1 w - 70 - db svrr supply voltage rejection ratio operating mode f ripple = 100 hz [4] -70-db f ripple = 1 khz [4] -70-db mute mode f ripple = 1 khz [4] -70-db off state and standby mode f ripple = 1 khz [4] -90-db | z i(dif) | differential input impedance 60 100 150 k w v n(o) output noise voltage operating mode bd mode [5] -6077 m v ad mode [5] - 100 140 m v mute mode bd mode [6] -2532 m v ad mode [6] - 85 110 m v a bal(ch) channel balance - 0 1 db a mute mute attenuation [7] 66 - - db cmrr common mode rejection ratio v i(cm) = 1 v rms 65 80 - db h po output power ef?ciency p o = 20 w - 90 - %
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 33 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics [5] b = 22 hz to 20 khz, aes brick wall, r s =0 w . [6] b = 22 hz to 20 khz, aes brick wall, independent of r s . [7] v i =v i(max) = 0.5 v rms. 14. application information 14.1 output power estimation (stereo mode) the output power, just before clipping, can be estimated using the following equations: (5) where, ? p o = 0.5 % ? v p = supply voltage (v) ? r l = load impedance ( w ) ? r dson = on-resistance power switch ( w ) ? r s = series resistance output inductor ( w ) ? t w(min) = minimum pulse width(s) depending on output current ? f osc = oscillator frequency in hz (typically 320 khz) the output power at 10 % thd can be estimated by: where p o(1) = 0.5 % and p o(2) =10%. figure 27 and figure 28 show the estimated output power at thd = 0.5 % and thd = 10 % as a function of supply voltage for different load impedances at stereo mode. p o r l r l 2r dson r s + () + ------------------------------------------------------ ? ?? 1t wmin () f osc 2 --------- - C ? ?? v p ? ? 2 ? 2r l ------------------------------------------------------------------------------------------------------------------------------- ---------- = p 02 () 1.25 p o1 () =
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 34 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics thd = 0.5 %. (1) r dson = 0.12 w (at t j =25 c), r s = 0.025 w , t w(min) = 130 ns and i o(ocp) = 8 a (minimum). (2) r l =1 w . (3) r l =2 w . (4) r l =4 w . thd = 10 %. (1) r dson = 0.12 w (at t j =25 c), r s = 0.025 w , t w(min) = 130 ns and i o(ocp) = 8 a (minimum). (2) r l =1 w . (3) r l =2 w . (4) r l =4 w . fig 27. p o as a function of v p in stereo mode with thd = 0.5 % fig 28. p o as a function of v p in stereo mode with thd = 10 % v p (v) 818 16 12 14 10 (1) (2) (3) 001aai796 40 20 60 80 p o (w) 0 v p (v) 818 16 12 14 10 (1) (2) 001aai797 40 20 60 80 p o (w) 0 (3)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 35 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 14.2 output power estimation (parallel mode) figure 29 and figure 30 show the estimated output power at thd = 0.5 % and thd = 10 % as a function of the supply voltage for different load impedances in parallel mode. 14.3 output current limiting the peak output current is internally limited to 8 a maximum. during normal operation, the output current should not exceed this threshold level otherwise the output signal will be distorted. the peak output current can be estimated using the following equation: (6) ? i o = output current (a) ? v p = supply voltage (v) ? r l = load impedance ( w ) ? r dson = on-resistance power switch ( w ) ? r s = series resistance output inductor ( w ) example: a 1 w speaker can be used with a supply voltage of 11 v before current limiting is triggered. current limiting (clipping) avoids audio holes but can cause distortion similar to voltage clipping. in parallel mode, the output current is internally limited above 16 a. thd = 0.5 %. (1) r dson = 0.06 w (at t j =25 c), r s = 0.0125 w , t w(min) = 130 ns and i o(ocp) = 16 a (minimum). (2) r l =1 w . (3) r l =2 w . (4) r l =4 w . thd = 10 %. (1) r dson = 0.06 w (at t j =25 c), r s = 0.0125 w , t w(min) = 130 ns and i o(ocp) = 16 a (minimum). (2) r l =1 w . (3) r l =2 w . (4) r l =4 w . fig 29. p o as a function of v p in parallel mode with thd = 0.5 % fig 30. p o as a function of v p parallel mode with thd = 10 % v p (v) 818 16 12 14 10 (1) 001aai798 80 40 120 160 p o (w) 0 (3) (2) v p (v) 818 16 12 14 10 (1) 001aai799 80 40 120 160 p o (w) 0 (3) (2) i o v p r l 2 + r rson r s + () ----------------------------------------------------- - 8 a
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 36 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 14.4 speaker con?guration and impedance a ?at-frequency response (due to a 2 nd order butterworth ?lter) is obtained by changing the low-pass ?lter components (l lc , c lc ) based on the speaker con?guration and impedance. t ab le 22 shows the required values. remark: when using a 1 w load impedance in parallel mode, the outputs are shorted after the low-pass ?lter switches two 2 w ?lters in parallel. 14.5 heat sink requirements in some applications, it may be necessary to connect an external heat sink to the tdf8599. thermal foldback activates at t j = 145 c. the expression below shows the relationship between the maximum power dissipation before activation of thermal foldback and the total thermal resistance from junction to ambient; (7) p max is determined by the ef?ciency ( h ) of the tdf8599. the ef?ciency measured as a function of output power is given in figure 39 . the power dissipation can be derived as a function of output power (see figure 32 ). example 1: ? v p = 14.4 v ? p o =2 25 w into 4 w (thd = 10 % continuous) ? t j(max) = 140 c ? t amb =25 c ? p max = 5.8 w (from figure 39 ) ? the required r th(j-a) = 115 c/5. 8w=19k/w the total thermal resistance r th(j-a) consists of: ? r th(j-c) + r th(c-h) + r th(h-a) where: ? thermal resistance from junction to case (r th(j-c) ) = 1.1 k/w ? thermal resistance from case to heat sink (r th(c-h) ) = 0.5 - 1 k/w (depending on mounting) ? thermal resistance from heat sink to ambient (r th(h-a) ) would then be 19 - (1.1+1)=17k/w. if an audio signal has a crest factor of 10 (the ratio between peak power and average power = 10 db) then t j will be much lower. table 22. filter components values load impedance ( w ) l lc ( m h) c lc ( m f) 1 2.5 4.4 2 5 2.2 4101 r th j a C () t j max () t amb C p max ------------------------------------ =
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 37 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics example 2: ? v p = 14.4 v ? p o =2 (25 w/10) = 2 2.5 w into 4 w (audio with crest factor of 10) ? t amb =25 c ? p max = 2.5 w (from figure 39 ) ? r th(j-a) =19k/w ? t j(max) =25 c + 2.5 w 19 k/w = 72 c 14.6 curves measured in reference design (1) v p = 14.4 v; r l =2 w at 6 khz. (2) v p = 14.4 v; r l =2 w at 1 khz. (3) v p = 14.4 v, r l =2 w at 100 hz. (1) v p = 14.4 v; r l =4 w at 6 khz. (2) v p = 14.4 v; r l =4 w at 1 khz. (3) v p = 14.4 v, r l =4 w at 100 hz. fig 31. thd + n as a function of output power fig 32. thd + n as a function of output power 001aai800 w 10 - 1 10 2 10 1 10 - 1 10 - 2 10 1 10 2 % 10 - 3 (3) (2) (1) 001aai801 w 10 - 1 10 2 10 1 10 - 1 10 - 2 10 1 10 2 % 10 - 3 (3) (2) (1)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 38 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics (1) v p = 14.4 v; r l =2 w at 10 w. (2) v p = 14.4 v; r l =2 w at 1 w. (1) v p = 14.4 v; r l =4 w at 10 w. (2) v p = 14.4 v; r l =4 w at 1 w. fig 33. thd + n as a function of frequency with a 2 w load fig 34. thd + n as a function of frequency with a 4 w load 001aai802 10 - 1 10 - 2 1 % 10 - 3 hz 10 10 5 10 4 10 2 10 3 (2) (1) 001aai803 10 - 1 10 - 2 1 % 10 - 3 hz 10 10 5 10 4 10 2 10 3 (2) (1) p o = 1 w; v p = 14.4 v; r l =2 w . (1) channel 1 to channel 2. (2) channel 2 to channel 1. p o = 1 w; v p = 14.4 v; r l =4 w . (1) channel 1 to channel 2. (2) channel 2 to channel 1. fig 35. channel separation as a function of frequency with a 2 w load fig 36. channel separation as a function of frequency with a 4 w load 001aai804 - 80 - 90 - 70 - 60 db - 100 hz 10 10 5 10 4 10 2 10 3 (2) (1) 001aai805 - 80 - 90 - 70 - 60 db - 100 hz 10 10 5 10 4 10 2 10 3 (2) (1)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 39 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics v i =1v; r i =0 w . (1) v p = 14.4 v; r l =2 w . (2) v p = 14.4 v; r l =4 w . v i =100 mv rms; r i =0 w . (1) v p = 14.4 v; r l =2 w . (2) v p = 14.4 v; r l =4 w . fig 37. cmrr as a function of frequency fig 38. gain as a function of frequency 001aai806 - 85 - 80 - 75 cmrr (db) - 90 khz 10 - 2 10 2 10 10 - 1 1 (2) (1) 001aai807 - 0.2 0.2 - 0.6 0.6 1.0 - 0.4 0 - 0.8 0.4 0.8 a (dbr) - 1.0 hz 10 10 5 10 4 10 2 10 3 (2) (1) (1) v p = 14.4 v; r l =2 w at 1 khz. (2) v p = 14.4 v; r l =4 w at 1 khz. (1) v p = 14.4 v; r l =2 w at 1 khz. (2) v p = 14.4 v; r l =4 w at 1 khz. fig 39. ef?ciency as a function of p o fig 40. power dissipation as a function of total output power 001aai808 p o (w) 060 40 20 50 30 10 40 60 20 80 100 n (%) 0 (2) (1) 001aai809 p o (w) 060 40 20 8 12 4 16 20 p d (w) 0 (2) (1)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 40 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 14.7 typical application schematics dual btl mode (stereo) in non-i 2 c-bus mode with dc offset protection disabled spread spectrum mode enabled bd modulation. (1) see figure 4 on page 7 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 9 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on disabling dc offset protection. fig 41. example application diagram for dual btl in non-i 2 c-bus mode 001aai810 22 w 39 k w 10 k w 10 k w 4.7 k w 10 w 10 w 22 w 100 m f 35 v 100 m f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in1p 470 nf c in1n 470 nf c in2p 470 nf 470 nf 100 nf 47 m f c in2n l lc l lc c lc 100 nf pgnd1 pgnd1 vp1 vp1 vp1 vp2 vpa tdf8599 bead bead bead bead out1n out1p out1n vp gnd out1p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p vp1 pgnd1 pgnd1 pgnd2 v ddd 1000 m f 35 v 100 nf 220 nf vstab2 dcp oscio 220 nf 22 w 10 w 10 w 22 w 100 nf 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc l lc l lc c lc 100 nf pgnd2 vp2 vp2 pgnd2 out2p out2n out2p out2n boot2p boot2n vp2 pgnd2 in2n agnd in2p in1p acgnd svrr en sel_mute in1n in2n 100 nf 100 nf 1 m f (2) c acgnd enable (1) mute/on (1) in2p in1p in1n scl ssm oscset v dda sda vpa vpa vpa bd modulation setting master mode non-i 2 c-bus mode ads diag mod clip (3)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 41 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics dual btl mode (stereo) in non-i 2 c-bus mode with dc offset protection enabled spread spectrum mode disabled. (1) see figure 4 on page 7 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 9 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on disabling dc offset protection. fig 42. example application diagram for dual btl in i 2 c-bus mode 001aai811 22 w 39 k w 10 k w 10 k w 33 k w 10 w 10 w 22 w 100 m f 35 v 100 m f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in1p 470 nf c in1n 470 nf c in2p 470 nf 470 nf 100 nf 47 m f c in2n l lc l lc c lc 100 nf pgnd1 pgnd1 vp1 vp1 vp1 vp2 vpa tdf8599 bead bead rads bead bead out1n out1p out1n vp gnd out1p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p vp1 pgnd1 pgnd1 pgnd2 v ddd 1000 m f 35 v 4.7 m f 100 nf 220 nf vstab2 dcp oscio 220 nf 22 w 10 w 10 w 22 w 100 nf 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc l lc l lc c lc 100 nf pgnd2 pgnd2 vp2 vp2 out2p out2n out2p out2n boot2p boot2n vp2 pgnd2 in2n agnd in2p in1p acgnd svrr en sel_mute (1) in1n in2n 100 nf 100 nf (2) c acgnd enable (1) in2p in1p in1n scl ssm oscset v dda sda vpa vpa vpa stereo mode setting connect with m p master mode i 2 c-bus address select ads diag mod clip (3)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 42 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics single btl mode (parallel) in i 2 c-bus mode with dc offset protection enabled spread spectrum mode disabled. (1) see figure 4 on page 7 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 9 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on disabling dc offset protection. fig 43. example application diagram for a single btl in i 2 c-bus mode 001aai812 22 w 39 k w 10 k w 10 k w 3 100 k w 10 w 10 w 22 w 100 m f 35 v 100 m f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c inp 470 nf c inn 470 nf 100 nf 47 m f l lc l lc c lc 100 nf pgnd1 pgnd1 vp1 vp1 vp1 vp2 vpa tdf8599 bead bead rads bead bead out1n out1p outn vp gnd outp vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p vp1 pgnd1 pgnd1 pgnd2 v ddd 1000 m f 35 v 4.7 m f 100 nf 220 nf vstab2 dcp oscio 220 nf 10 w 10 w 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf l lc l lc pgnd2 pgnd2 vp2 vp2 out2p out2n boot2p boot2n vp2 pgnd2 in2n agnd in2p in1p acgnd svrr en sel_mute (1) in1n 100 nf 100 nf c acgnd enable (1) inp inn scl ssm oscset v dda sda vpa vpa vpa parallel mode setting connect with m p fixed frequency (2) master mode i 2 c-bus address select ads diag mod clip (3)
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 43 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics i 2 c-bus mode: single btl in master mode with two btls in slave mode; dc offset protection enabled. (1) see figure 4 on page 7 for a diagram of the connection for pins en and sel_mute. (2) see section 8.3.2 on page 9 for detailed information. (3) see section 8.5.5 on page 16 for detailed information on disabling dc offset protection. fig 44. master-slave example application diagram; one btl master and two btl slaves in i 2 c-bus mode 22 w 39 k w 20 k w 10 k w 10 k w 33 k w 10 w 10 w 22 w 100 m f 35 v 100 m f 35 v 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in1p 470 nf c in1n 470 nf c in2p 470 nf 470 nf 100 nf 47 m f 1 m f c in2n l lc l lc c lc 100 nf pgnd1 pgnd1 vp1 vp1 vp1 vp2 vpa tdf8599 bead bead rads bead bead out1n out1p out1n vp gnd out1p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p vp1 pgnd1 pgnd1 pgnd2 v ddd 1000 m f 35 v 4.7 m f 100 nf 220 nf vstab2 dcp oscio 220 nf 22 w 10 w 10 w 22 w 100 nf 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc l lc l lc c lc 100 nf pgnd2 pgnd2 vp2 vp2 out2p out2n out2p out2n boot2p boot2n vp2 pgnd2 in2n agnd in2p in1p acgnd svrr en (1) sel_mute (1) in1n in2n 100 nf 100 nf c acgnd enable in2p in1p in1n scl ssm oscset v dda sda vpa vpa vpa stereo mode setting spread spectrum mode (2) dc offset protection enabled (3) dc offset protection enabled (3) master mode i 2 c-bus address select ads diag mod clip 001aai813 22 w 5.1 k w 10 k w 10 k w 3 100 k w 10 w 10 w 22 w 100 nf 15 nf 470 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf c lc c in 470 nf c in 470 nf 100 nf 47 m f l lc l lc c lc 100 nf pgnd1 pgnd1 vp1 vp1 tdf8599 bead rads out1n out1p out3n out3p vstab1 gndd/hw 33 32 31 30 29 28 34 35 36 25 24 23 22 21 20 19 26 27 4 5 6 7 8 9 3 2 1 12 13 14 15 16 17 18 11 10 boot1n boot1p vp1 pgnd1 v ddd 4.7 m f 100 nf 220 nf vstab2 dcp oscio 220 nf 10 w 10 w 15 nf 100 nf 15 nf 470 pf 470 pf 470 pf 470 pf l lc l lc pgnd2 pgnd2 vp2 vp2 out2p out2n boot2p boot2n vp2 pgnd2 in2n agnd in2p in1p acgnd svrr en (1) sel_mute (1) in1n 100 nf 10 nf 270 nf c acgnd in3p in3n scl ssm oscset v dda sda vpa vpa vpa parallel mode setting connect with m p phase lock operation (2) slave mode i 2 c-bus address select ads diag mod clip
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 44 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 15. package outline fig 45. package outline sot851-2 (hsop36) references outline version european projection issue date iec jedec jeita sot851-2 sot851-2 04-05-04 hsop36: plastic, heatsink small outline package; 36 leads; low stand-off height b p z 118 36 19 d 1 d 2 e 1 e a h e d e 2 y x e w m pin 1 index va m x q l p detail x (a 3 ) a 2 a 4 c a q 0 5 10 mm scale unit a 4 (1) mm + 0.08 - 0.04 3.5 0.35 dimensions (mm are the original dimensions) notes 1. limits per individual lead. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. a max. a 2 3.5 3.2 d 2 1.1 0.9 h e 14.5 13.9 l p 1.1 0.8 q 1.7 1.5 2.55 2.20 v 0.25 w 0.12 yz 8 0 q 0.07 x 0.03 d 1 13.0 12.6 e 1 6.2 5.8 e 2 2.9 2.5 b p c 0.32 0.23 e 0.65 d (2) 16.0 15.8 e (2) 11.1 10.9 0.38 0.25 a 3
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 45 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics fig 46. package outline sot938-1 (hsop36) references outline version european projection issue date iec jedec jeita sot938-1 sot938-1 06-01-20 06-04-07 notes 1. limits per individual lead. 2. plastic or metal protrusions of 0.25 mm maximum per side are not included. unit a max mm 3.6 0.3 0.1 3.3 3.0 0.1 0 0.38 0.25 0.32 0.23 16.0 15.8 1.1 0.9 11.1 10.9 2.9 2.5 a 1 dimensions (mm are the original dimensions) hsop36: plastic, heatsink small outline package; 36 leads; low stand-off height 0 5 10 mm scale a 2 a 3 0.35 a 4 (1) b p c d (2) d 2 13.0 12.6 d 1 e (2) e 2 6.2 5.8 e 1 14.5 13.9 1.5 1.4 h e q 1.1 0.8 l p v 0.25 e 0.65 w 0.12 2.55 2.20 y 0.1 z q 8 0 b p e w m pin index 36 19 118 z d 1 e 1 d 2 y d detail x q a 4 a 1 (a 3 ) l p a 2 q a a va m x h e e 2 e c
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 46 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 16. handling information in accordance with snw-fq-611-d. the number of the quality speci?cation can be found in the quality reference handbook. the handbook can be ordered using the code 9398 510 63011. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 47 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 17.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 47 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 23 and 24 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 47 . table 23. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 24. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 48 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 18. abbreviations msl: moisture sensitivity level fig 47. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 25. abbreviations abbreviation description bcdmos bipolar complementary and double diffused metal-oxide semiconductor btl bridge-tied load dcp dc offset protection emi electromagnetic interference i 2 c inter-integrated circuit lsb least signi?cant bit msb most signi?cant bit ndmost n-type double diffused metal-oxide semiconductor transistor ocp overcurrent protection otp overtemperature protection ovp overvoltage protection por power-on reset pwm pulse-width modulation soi silicon on insulator tfp thermal foldback protection uvp undervoltage protection wp window protection
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 49 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 19. revision history table 26. revision history document id release date data sheet status change notice supersedes tdf8599_1 20081113 product data sheet - -
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 50 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. quick reference data the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 20.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
tdf8599_1 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 01 13 november 2008 51 of 52 nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics 22. tables table 1. quick reference data . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 table 4. i 2 c-bus mode operation . . . . . . . . . . . . . . . . . . .8 table 5. non-i 2 c-bus mode operation . . . . . . . . . . . . . . .8 table 6. mode setting oscio . . . . . . . . . . . . . . . . . . . . .8 table 7. oscillator modes . . . . . . . . . . . . . . . . . . . . . . .11 table 8. operation mode selection with the mod pin . .12 table 9. overview of protection types . . . . . . . . . . . . . .15 table 10. overview of tdf8599 protection circuits and ampli?er states . . . . . . . . . . . . . . . . . . . . . . . . .17 table 11. available data at diag and clip pin . . . . . . . .18 table 12. interpretation of dc load detection bits . . . . . .20 table 13. tdf8599 address using an external resistor . .23 table 14. instruction byte descriptions . . . . . . . . . . . . . . 25 table 15. frequency bit settings . . . . . . . . . . . . . . . . . . . 25 table 16. description of data bytes . . . . . . . . . . . . . . . . . 26 table 17. limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. thermal characteristics . . . . . . . . . . . . . . . . . . 27 table 19. static characteristics . . . . . . . . . . . . . . . . . . . . 28 table 20. switching characteristics . . . . . . . . . . . . . . . . . 31 table 21. dynamic characteristics . . . . . . . . . . . . . . . . . 32 table 22. filter components values . . . . . . . . . . . . . . . . 36 table 23. snpb eutectic process (from j-std-020c) . . . 47 table 24. lead-free process (from j-std-020c) . . . . . . 47 table 25. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 26. revision history . . . . . . . . . . . . . . . . . . . . . . . . 49 23. figures fig 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 fig 2. heatsink up (top view) pin con?guration TDF8599TH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 fig 3. heatsink down (top view) pin con?guration tdf8599td . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 fig 4. mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . .7 fig 5. oscillator frequency as function of r osc . . . . . . . . .9 fig 6. master and slave con?guration . . . . . . . . . . . . . . .9 fig 7. spread spectrum mode . . . . . . . . . . . . . . . . . . . .10 fig 8. spread spectrum operation in master mode . . . .10 fig 9. phase lock operation . . . . . . . . . . . . . . . . . . . . . .11 fig 10. ad/bd modulation switching circuit . . . . . . . . . . .12 fig 11. ad modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 12. bd modulation . . . . . . . . . . . . . . . . . . . . . . . . . . .13 fig 13. master and slave operation with 1 2 p phase shift.14 fig 14. mono and parallel modes . . . . . . . . . . . . . . . . . .14 fig 15. dc offset protection and diagnostic output . . . . .16 fig 16. diagnostic output for short circuit conditions . . . .18 fig 17. dc load detection circuit . . . . . . . . . . . . . . . . . . .19 fig 18. dc load detection procedure . . . . . . . . . . . . . . . .19 fig 19. dc load detection limits . . . . . . . . . . . . . . . . . . . .19 fig 20. recommended start-up sequence with dc load detection enabled. . . . . . . . . . . . . . . . . . . . . . . . .21 fig 21. start-up and shutdown timing in i 2 c-bus mode with dc load detection . . . . . . . . . . . . . . . . . . . . .22 fig 22. start-up and shutdown timing in non-i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 fig 23. i 2 c-bus start and stop conditions. . . . . . . . . . . . .24 fig 24. data bits sent from master microprocessor (mmp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 25. i 2 c-bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 26. i 2 c-bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 27. p o as a function of v p in stereo mode with thd = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 28. p o as a function of v p in stereo mode with thd = 10 % . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 29. p o as a function of v p in parallel mode with thd = 0.5 % . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 fig 30. p o as a function of v p parallel mode with thd = 10 %. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 fig 31. thd + n as a function of output power . . . . . . . . 37 fig 32. thd + n as a function of output power . . . . . . . . 37 fig 33. thd + n as a function of frequency with a 2 w load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 fig 34. thd + n as a function of frequency with a 4 w load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 fig 35. channel separation as a function of frequency with a 2 w load . . . . . . . . . . . . . . . . . . 38 fig 36. channel separation as a function of frequency with a 4 w load . . . . . . . . . . . . . . . . . . 38 fig 37. cmrr as a function of frequency . . . . . . . . . . . . 39 fig 38. gain as a function of frequency. . . . . . . . . . . . . . 39 fig 39. ef?ciency as a function of p o . . . . . . . . . . . . . . . . 39 fig 40. power dissipation as a function of total output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 fig 41. example application diagram for dual btl in non-i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . 40 fig 42. example application diagram for dual btl in i 2 c-bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . 41 fig 43. example application diagram for a single btl in i 2 c-bus mode. . . . . . . . . . . . . . . . . . . . . . . . . . 42 fig 44. master-slave example application diagram; one btl master and two btl slaves in i 2 c-bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 fig 45. package outline sot851-2 (hsop36) . . . . . . . . 44 fig 46. package outline sot938-1 (hsop36) . . . . . . . . 45 fig 47. temperature pro?les for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
nxp semiconductors tdf8599 class-d power ampli?er with load diagnostics ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 13 november 2008 document identifier: tdf8599_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 functional description . . . . . . . . . . . . . . . . . . . 6 8.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2 mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 7 8.3 pulse-width modulation frequency . . . . . . . . . . 8 8.3.1 master and slave mode selection . . . . . . . . . . . 8 8.3.2 spread spectrum mode (master mode) . . . . . . 9 8.3.3 frequency hopping (master mode). . . . . . . . . 10 8.3.4 phase lock operation (slave mode) . . . . . . . . 10 8.4 operation mode selection. . . . . . . . . . . . . . . . 11 8.4.1 modulation mode . . . . . . . . . . . . . . . . . . . . . . 12 8.4.2 phase staggering (slave mode) . . . . . . . . . . . 13 8.4.3 parallel mode . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.5 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.5.1 thermal foldback . . . . . . . . . . . . . . . . . . . . . . 15 8.5.2 overtemperature protection . . . . . . . . . . . . . . 15 8.5.3 overcurrent protection . . . . . . . . . . . . . . . . . . 15 8.5.4 window protection . . . . . . . . . . . . . . . . . . . . . 16 8.5.5 dc protection . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.5.6 supply voltages . . . . . . . . . . . . . . . . . . . . . . . 17 8.5.7 overview of protection circuits and ampli?er states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.6 diagnostic output . . . . . . . . . . . . . . . . . . . . . . 18 8.6.1 diagnostic table . . . . . . . . . . . . . . . . . . . . . . . 18 8.6.2 load identi?cation (i 2 c-bus mode only) . . . . . 19 8.6.2.1 dc load detection . . . . . . . . . . . . . . . . . . . . . . 19 8.6.2.2 recommended start-up sequence with dc load detection enabled . . . . . . . . . . . . . . . . . . 20 8.6.2.3 ac load detection . . . . . . . . . . . . . . . . . . . . . . 21 8.6.2.4 clip detection . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6.3 start-up and shutdown sequence. . . . . . . . . . 22 9i 2 c-bus speci?cation . . . . . . . . . . . . . . . . . . . . 23 9.1 instruction bytes . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 data bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 11 thermal characteristics. . . . . . . . . . . . . . . . . . 27 12 static characteristics. . . . . . . . . . . . . . . . . . . . 28 12.1 switching characteristics . . . . . . . . . . . . . . . . 31 13 dynamic characteristics . . . . . . . . . . . . . . . . . 32 14 application information . . . . . . . . . . . . . . . . . 33 14.1 output power estimation (stereo mode) . . . . 33 14.2 output power estimation (parallel mode) . . . . 35 14.3 output current limiting . . . . . . . . . . . . . . . . . . 35 14.4 speaker con?guration and impedance. . . . . . 36 14.5 heat sink requirements . . . . . . . . . . . . . . . . . 36 14.6 curves measured in reference design . . . . . . 37 14.7 typical application schematics . . . . . . . . . . . . 40 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 44 16 handling information . . . . . . . . . . . . . . . . . . . 46 17 soldering of smd packages . . . . . . . . . . . . . . 46 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 46 17.2 wave and re?ow soldering . . . . . . . . . . . . . . . 46 17.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 46 17.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 47 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 48 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 49 20 legal information . . . . . . . . . . . . . . . . . . . . . . 50 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 50 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 50 21 contact information . . . . . . . . . . . . . . . . . . . . 50 22 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 23 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

▲Up To Search▲

Price & Availability of TDF8599TH

	To Download TDF8599TH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .