rev. 4154c?8051?04/03 1 active errata list uart/reception in modes 1, 2 and 3/uart false start bits detection during uart reception, clearing ren may generate unexpected it jbc/double it when external it occurs during jbc instruction timer2/downcounter mode/double it with slow external clock input trigger consumption/all c51 type i/o ports movx/port0/read mode errata history TS80C51RB2 ts87c51rb2 errata descriptions 1. uart/reception in modes 1, 2 and 3/uart false start bits detection when a false start bit occurs on the uart, some uart internal signals are not reset. then when a real start bit occurs, the sampling is shifted. workaround none. 2. during uart reception, clearing ren may generate unexpected it during uart reception, if the ren bit is clear between a start bit detection and the end of reception, the uart will not discard the data (ri is set). workaround test ren at the beginning of interrupt routine just after clr ri, and run the interrupt routine code only if ren is set. 3. jbc/double it when external it occurs during jbc instruction on polling algorithm in isr on ie1 or ie0, when the external it appears during jbc instruction, the flag is not cleared. on the next jbc instruction another it is pending. therefore, the same it is seen twice. workaround use jb instruction instead of jbc instruction to test bit and clr instruction to clear it.n twice. lot number errata list 38584 t01, t02 ,t03, t04, t05, t06 > 38584 t02 ,t03, t04, t05, t06 lot number errata list 36425 t01, t02 ,t03, t04, t05, t06 > 36425 t02 ,t03, t04, t05, t06 8051 microcontrollers ts87c51rb2 TS80C51RB2 errata sheet
2 tsc8xrb2 4154c ? 8051 ? 04/03 4. timer2/downcounter mode/double it with slow external clock double it with slow external clock in downcount mode. timer 2 in 16-bit autoreload in count-down mode with external clock input two interrupts are generated successively with low frequency on clock input (typ 10-40 khz). workaround reload fffe into th2-tl2 in isr and count down to rcap-1 (to recover cycle lost in isr) caution: do not work if initially rcap = 0x0000 5. input trigger consumption/all c51 type i/o ports some static consumption in input triggers of i/o ports may occur when entries are driven close to the trigger threshold (1 ma to 2 ma for each i/o at vin = 2.4v for vcc = 5v) workaround none. 6. movx/port0/read mode when reading external ram using movx instruction, port0 ? s sfr may contain ? 0 ? whereas any acces to external memories (data or program) should write ? 1 ? into them . ? 0 ? is written to each bit of the port0 buffers prior to a movx access. this problem has no consequence when the movx cycle is a write, as the correct value is immediately substitued and is present on port0 during the duration of the write pulse (wr = 0). when the movx is a read, the strong internal pull-down n transistor creates a short circuit with the external ram buffer or peripheral when the ram or peripheral reads ? 1 ? . workaround replace any movx a,@ri instruction by the sequence: replace any movx a,@dptr instruction by the sequence: mov p0, #ffh mov p0, #ffh movx a, @ri movx a, @dptr
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