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regarding the change of names mentioned in the document, such as hitachi electric and hitachi xx, to renesas technology corp. the semiconductor operations of mitsubishi electric and hitachi were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although hitachi, hitachi, ltd., hitachi semiconductors, and other hitachi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. renesas technology home page: http://www.renesas.com renesas technology corp. customer support dept. april 1, 2003 to all our customers
cautions keep safety first in your circuit designs! 1. renesas technology corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas technology corporation or a third party. 2. renesas technology corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by renesas technology corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact renesas technology corporation or an authorized renesas technology corporation product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corporation by various means, including the renesas technology corporation semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact renesas technology corporation or an authorized renesas technology corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corporation is necessary to reprint or reproduce in whole or in part these materials. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corporation for further details on these materials or the products contained therein. H7N1002LD, h7n1002ls, h7n1002lm silicon n channel mos fet high speed power switching ade-208-1573e (z) 6th. edition aug. 2002 features ? low on-resistance ? r ds(on) = 8 m ? typ. ? low drive current ? available for 4.5 v gate drive outline 1. gate 2. drain 3. source 4. drain ldpak H7N1002LD h7n1002ls h7n1002lm d g s 1 2 3 4 1 2 3 4 1 2 3 4 H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 2 of 12 absolute maximum ratings (ta = 25c) item symbol ratings unit drain to source voltage v dss 100 v gate to source voltage v gss 20 v drain current i d 75 a drain peak current i d(pulse) note1 300 a body-drain diode reverse drain current i dr 75 a avalanche current i ap note3 50 a avalanche energy e ar note3 166 mj channel dissipation pch note2 100 w channel temperature tch 150 c storage temperature tstg ?55 to +150 c notes: 1. pw 10 s, duty cycle 1 % 2. value at tc = 25c 3. value at tch = 25c, rg 50 ? H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 3 of 12 electrical characteristics (ta = 25 c) item symbol min typ max unit test conditions drain to source breakdown voltage v (br)dss 100 ? ? v i d = 10 ma, v gs = 0 gate to source breakdown voltage v (br)gss 20 ? ? v i g = 100 a, v ds = 0 gate to source leak current i gss ? ? 10 a v gs = 16 v, v ds = 0 zero gate voltege drain current i dss ? ? 10 a v ds = 100 v, v gs = 0 gate to source cutoff voltage v gs(off) 1.0 ? 2.5 v i d = 1 ma, v ds = 10 v* 1 static drain to source on state r ds(on) ? 8 10 m ? i d = 37.5 a, v gs = 10 v* 1 resistance ? 10 15 m ? i d = 37.5 a, v gs = 4.5 v* 1 forward transfer admittance |y fs | 57 95 ? s i d = 37.5 a, v ds = 10 v* 1 input capacitance ciss ? 9700 ? pf v ds = 10 v output capacitance coss ? 740 ? pf v gs = 0 reverse transfer capacitance crss ? 330 ? pf f = 1 mhz total gate charge qg ? 155 ? nc v dd = 50 v gate to source charge qgs ? 35 ? nc v gs = 10 v gate to drain charge qgd ? 33 ? nc i d = 75 a turn-on delay time t d(on) ? 43 ? ns v gs = 10 v, i d = 37.5 a rise time t r ? 245 ? ns r l = 0.8 ? turn-off delay time t d(off) ? 130 ? ns r g = 4.7 ? fall time t f ? 25 ? ns body ? drain diode forward voltage v df ? 0.93 ? v i f = 75 a, v gs = 0 body ? drain diode reverse recovery time t rr ? 70 ? ns i f = 75 a, v gs = 0 dif/ dt = 100 a/ s notes: 1. pulse test H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 4 of 12 main characteristics 30 10 3 1 0.3 0.1 0.1 0.3 1 3 10 30 100 50 40 30 20 10 0 2 46810 50 40 30 20 10 0 1 5 0.03 100 ta = 25 c 10 v v = 3 v gs 3.4 v tc = 75 c 25 c -25 c drain to source voltage v (v) ds drain current i (a) d maximum safe operation area drain to source voltage v (v) drain current i (a) d typical output characteristics ds pulse test gate to source voltage v (v) gs drain current i (a) typical transfer characteristics d v = 10 v ds pulse test 100 s 1 ms pw = 10 ms (1shot) dc o pera tion (tc = 25 c) 10 s 4 v 3.6 v operation in this area is limited by r ds(on) 2 34 200 150 100 50 0 50 100 150 200 channel dissipation pch (w) case temperature tc ( c) power vs. temperature derating 300 H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 5 of 12 200 5 20 100 21050 5 10 20 50 1 2 0.5 0.01 100 10 100 10 0.1 1 0.02 0.1 1 static drain to source on state resistance vs. drain current 25 c tc = ? 25 c 75 c ds v = 10 v pulse test drain current i (a) drain to source on state resistance r ds(on) pulse test d (m ? ) static drain to source on state resistance vs. temperature forward transfer admittance vs. drain current case temperature tc ( c) drain current i (a) d static drain to source on state resistance (m ? ) r ds(on) |yfs| (s) forward transfer admittance v = 4.5 v gs 10 v 0.8 0.6 0.4 0.2 0 5 101520 drain to source saturation voltage vs. gate to source voltage 1.0 i = 50 a d 20 a 10 a pulse test gate to source voltage v (v) v (v) ds(on) drain to source saturation voltage gs 40 32 24 16 8 -40 0 40 80 120 160 0 i d = 10 a, 20 a 10 a, 20 a v = 4.5 v gs 10 v pulse test 50 a 50 a 200 H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 6 of 12 01020304050 2000 5000 10000 1000 100 200 500 200 160 120 80 40 0 20 16 12 8 4 80 160 240 320 400 0 1000 100 1 10 0.1 0.3 1 3 10 30 100 20 50 20000 v = 0 f = 1 mhz gs ciss coss crss i = 75 a d v ds v gs v = 25 v 50 v 80 v dd v = 80 v 50 v 25 v dd r t d(on) t d(off) t t f v = 10 v, v = 30 v pw = 5 s, duty 1% r = 4.7 ? gs dd g typical capacitance vs. drain to source voltage capacitance c (pf) drain to source voltage v (v) ds dynamic input characteristics switching characteristics drain to source voltage v (v) ds gate to source voltage v (v) gs switching time t (ns) gate charge qg (nc) drain current i (a) d 0.1 0.3 1 3 10 30 100 100 20 50 10 di / dt = 100 a / s v = 0, ta = 25 c gs body-drain diode reverse recovery time reverse recovery time trr (ns) reverse drain current i (a) dr H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 7 of 12 d. u. t rg i monitor ap v monitor ds v dd 50 ? vin 15 v 0 i d v ds i ap v (br)dss l v dd e = l i 2 1 v v ? v ar ap dss dss dd 2 200 160 120 80 40 25 50 75 100 125 150 0 i = 50 a v = 25 v duty < 0.1 % rg > 50 ? ap dd channel temperature tch ( c) repetitive avalanche energy e ar (mj) maximum avalanche energy vs. channel temperature derating avalanche test circuit avalanche waveform 0 0.4 0.8 1.2 1.6 2.0 100 80 60 40 20 v = 10 v gs 5v pulse test 0, -5 v reverses drain current vs. source to drain voltage reverse drain current i (a) dr source drain voltage v (v) sd H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 8 of 12 vin monitor d.u.t. vin 10 v r l v = 30 v ds tr td(on) vin 90% 90% 10% 10% vout td(off) vout monitor 90% 10% t f switching time test circuit switching time waveform rg normalized transient thermal impedance vs. pulse width pulse width pw (s) normalized transient thermal impedance s (t) 3 1 0.3 0.1 0.03 0.01 10 100 1 m 10 m 100 m 1 10 tc = 25 c d = 1 0.5 0.2 0.1 0.05 0.02 0.01 1shot p ulse dm p pw t d = pw t ch - c(t) = s (t) ? ch - c ch - c = 1.25 c/ w, tc = 25 c H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 9 of 12 package dimensions ? H7N1002LD hitachi code jedec jeita mass (reference value) ldpak (l) ? ? 1.4 g 10.2 0.3 0.86 2.54 0.5 2.54 0.5 + 0.2 ? 0.1 1.3 0.2 4.44 0.2 1.3 0.15 2.49 0.2 0.4 0.1 11.0 0.5 8.6 0.3 10.0 11.3 0.5 + 0.3 ? 0.5 (1.4) unit: mm 1.37 0.2 H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 10 of 12 ? h7n1002ls hitachi code jedec jeita mass (reference value) ldpak (s)-(1) ? ? 1.3 g 10.2 0.3 3.0 + 0.3 ? 0.5 7.8 6.6 2.2 1.7 7.8 7.0 unit: mm (1.5) 4.44 0.2 1.3 0.2 0.1 + 0.2 ? 0.1 2.49 0.2 0.4 0.1 (1.4) 8.6 0.3 10.0 + 0.3 ? 0.5 (1.5) 0.86 + 0.2 ? 0.1 2.54 0.5 2.54 0.5 1.3 0.2 1.37 0.2 H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 11 of 12 ? h7n1002lm hitachi code jedec jeita mass (reference value) ldpak (s)-(2) ? ? 1.35 g (2.3) 4.44 0.2 1.3 0.2 0.1 + 0.2 ? 0.1 0.4 0.1 7.8 6.6 2.2 1.7 7.8 7.0 unit: mm 2.49 0.2 10.2 0.3 5.0 + 0.3 ? 0.5 (1.4) 8.6 0.3 10.0 + 0.3 ? 0.5 (1.5) 0.86 + 0.2 ? 0.1 2.54 0.5 2.54 0.5 1.3 0.2 1.37 0.2 H7N1002LD, h7n1002ls, h7n1002lm rev.5, aug. 2002, page 12 of 12 disclaimer |
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