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an10896 mounting and soldering of rf transistors rev. 01 ? 17 may 2010 application note document information info content keywords surface mount, reflow soldering, bolt down abstract this application note provides bolt down and soldering guidelines for nxp?s rf transistor packages
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 2 of 49 contact information for additional information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com revision history rev date description 01 20100517 initial release
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 3 of 49 1. introduction 1.1 general (mounting recommendations rf power) this document is intended to guide customers in ways how to mount and solder rf power transistors. the typical frequency bands involved range from 800 mhz up to 3.5 ghz. it includes packages ranging from t he base station, br oadcast and microwave applications. each customer has its own way of designing applications and mounting the devices, so therefore not possible to cover all specific requirements. the intention of this document is to have a general mounting re commendation/guideline suitable for each individual device, whether it is a ceramic or a plastic over-molded package. 1.2 definition the following words in this document: ?heat sink? refers to the heat sink located under the pcb, the application heat sink. ?exposed heat spreader? is used fo r plastic over molded devices. "flange" (also a heat spreader) is used for the ceramic devices. "eared" is a flange with 2 slotted holes allowing bolt down. "earless" is a flange used for devices that are being soldered. "foot print or solder land" is used to define the area on which to solder. 1.3 main product groups the introduction of ldmos transistors started with the use of an air cavity package. the construction consists of a metal flange with on top an insolated ring frame with leads. the x-tals and in- and output capacitors are eutectic soldered onto the flange. gold wire bonds (later aluminum) where used to make the connection between the lead and the x- tal. as a final step the package is closed wi th a lid, see illustration. typically these packages where bolted down to a heat sink, while the lead are hand soldered to the pcb board. fig 1. over-molded versus air cavity based package some customer do prefer the air cavity pac kages to be reflow-ed in their application, meaning no thermal compound/paste under the flan ge but solder as well, as was already used to make the connect the lead to the pc b. main reasons to follow this route are thermal conductivity and as a result of t hat better mean time between failures (mttf). plastic over molded packages came on the r oadmap somewhat later. price pressure and technical feasibility of packaging at such high frequency devices have been the major factors in starting to follow this additional r oute. with the arrival of plastic over molded packages came also the request for straight as well as gull wing (surface mount) leaded packages. this document is divided in 2 main product groups: ?air cavity packages? and ?over molded packages? (omp).
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 4 of 49 2. design rules for pcb design 2.1 air cavity devices 2.1.1 smdp if the solder mask extends onto the solder land s, the remaining solder-able area is solder mask defined or also called a smdp (solder mask defined pad). the ?effective? solder pad is equal to the copper area that is not covered by solder mask. this situation is illustrated in fig 2 . fig 2. solder mask defined pads (smdp) in case of a smdp, the copper will normally extend 75 m underneath the solder mask on all sides; in other words, the copper di mension is 0.15 mm larger than the solder mask dimension. these values may vary depending on the class of pcbs used. this allows for tolerances in copper etching and solder mask placement, during pcb production. in fig 2, the copper underneath the solder mask is shown in an orange/green hatch. it is possible to design a solder mask bridge in between the pads and the pcb aperture. this is illustrated in fig 3. fig 3. smdp with solder mask bridge
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 5 of 49 if a solder mask bridge is designed between the pads and the pcb aperture, the leads will lay over this bridge. for smdps, the lead will hover (see fig 4. ) a little above the copper. this should not present a problem , as the ridge will only be, at most, 10 m high, but it does mean that the gap has to be filled with solder during the soldering process. fig 4. lead resting on a smdp 2.1.1.1 foot print dimensions smdp when it comes to defining the dimensions of the footprint on the pcb, only a few of the package dimensions are relevant. these are summarized in fig 5 . fig 5. relevant package dimensions for footprint definition 2.1.1.2 pcb aperture dimensions the package body is placed through an aperture in the pcb, and onto the heat sink. the dimensions of the aperture in the pcb should be such that the package can be comfortably inserted through it. in general, apertures in a pcb are made with certain accuracy. therefore it is advisable to design the pc b aperture larger than the maximum package body dimensions in that way t here will always be at least 200 m left for package insertion.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 6 of 49 fig 6. pcb aperture dimensions aperture dimension (al and aw) = u max + 0.2 (allow insertion) + aperture ac curacy fabrication (typically 0.2) because of the production method, the radius at the corner of an aperture is at least 0.4 mm. for easy insertion of the package throu gh the pcb, it is advised that the minimum radius is used in pcb design. the copper and solder mask dimensions for the air cavity packages are summarized in fig 7. and fig 8. this is for the smdp situation. fig 7. cu footprint dimensions for smdp fig 8. solder land/resist/mask dimensions for smdp the main rules used to define the footprint dimensions are: ? the solder mask apertures are 250 m larger than the package leads, on the three outer sides (the total dimensions are 500 m larger). this value is relatively large, so that placement accuracy of the package on the pcb is not critical. ? the copper extends 75 m underneath the solder mask on all sides, i.e. the total dimensions are 150 m larger than the copper dimensions. ? the solder mask must lay 150 m away from the aperture on all sides. if a solder mask ridge is designed between the pcb aperture and the pads, it must be at least 100 m wide. the main rules are summarized in fig 9.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 7 of 49 purple = package/lead edge grey = edge of pcb aperture orange = edge of cu green = edge of solder mask aperture fig 9. main rules in defining the smdp foot print
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 8 of 49 2.1.2 nsmdp if the solder mask layer starts outside of t he solder lands, and does not cover the copper, this is referred to as non solder mask defined pad (nsmdp). the ?effective? solder pad is equal to the copper area. fig 10. non solder mask defined pads (nsmdp) in case of a nsmdp, the solder mask must be at least 75 m away from the solder land on all sides. in other words, the solder mask dimension is 150 m larger than the copper dimension. these values may vary depending on the class of pcbs used. the main requirement is that the solder mask is far enough away from the copper, so that ? with the given tolerances in solder mask applicati on ? it does not extend onto the copper. this is shown in fig 10. in the figure, color grey is bar e fr4, orange is copper, and green is solder mask. basically, there is a large tr ench in the solder mask, around the copper. the ceramic package is placed through an aperture in the pcb. this aperture is indicated by the white rectangle. note that the solder mask does not reach the edge of the pcb aperture: it must always be at least 150 m away from the edge of the aperture. if so desired, it is also possible to design a narrow bridge of solder mask between the pads and the aperture in the pcb. this is illustrated in fig 11 . this is not strictly necessary, as the pcb material is also non-so lder-able. note that a solder mask bridge must have a minimum width of 100 m.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 9 of 49 fig 11. nsmdp with solder mask bridge for nsmdps, this situation is shown in fig 12 . usually a solder mask layer is roughly 20 m thick, whereas the copper is 30 m ? 35 m thick. thus, the solder mask will be lower than the copper, and the lead will rest on the copper. fig 12. lead resting on a nsmdp 2.1.2.1 pcb footprint ? dimensions nsmdp when it comes to defining the dimensions of the footprint on the pcb, only a few of the package dimensions are relevant. these are summarized in fig 13. fig 13. relevant package dimensions for footprint definition
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 10 of 49 2.1.2.2 pcb aperture dimensions the package body is placed through an aperture in the pcb, and onto the heat sink. the dimensions of the aperture in the pcb should be such that the package can be comfortably inserted through it. in general, apertures in a pcb are made with certain accuracy. therefore it is advisable to design the pc b aperture larger than the maximum package body dimensions in that way t here will always be at least 200 m left for package insertion. aperture dimension (al and aw) = u max + 0.2 mm (allow insertion) + aperture accuracy fabrication (typically 0.2 mm) because of the production method, the radius at the corner of an aperture is at least 0.4 mm. for easy insertion of the package throu gh the pcb, it is advised that the minimum radius is used in pcb design. the copper and solder mask dimensions for the air cavity packages are summarized in fig 15 and fig 16. this is for the nsmd situation. note: the 45 degrees drain lead angle (used for some outlines) is considered as being negligible and therefore not taken into account in the solder mask / foot print designs. fig 15. cu foot print dimensions for nsmdp fig 16. solder mask/resist/land dimensions for nsmdp the main rules used to define the copper footprint dimensions are: fig 14. pcb aperture dimension
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 11 of 49 ? the copper pads are 250 m larger than the package leads, on the three outer sides (the total dimensions are 500 m larger). this value is relatively large, so that placement accuracy of the package on the pcb is not critical. ? the distance between the two copper pads is equal to the aperture dimension, plus 325 m per side, to accommodate 100 m of solder mask if desired. in other words, the copper lies 325 m away from the aperture. the main rules used to define the solder mask dimensions are: ? the solder mask must lay 150 m away from the aperture ? must be at least 100 m wide ? and it must also lay 75 m away from the copper. the solder mask lays 75 m outside the copper on all sides, i.e. the total dimensions are 150 m larger than the copper dimensions. the main rules are summarized in fig 17. purple = package/lead edge grey = edge of pcb aperture orange = edge of cu green = edge of solder mask aperture fig 17. main rules in defining the nsmdp
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 12 of 49 2.2 over molded devices a footprint design describes the recommended dimensions of the solder lands on the pcb, to make reliable solder joints between the semiconductor package and the pcb. for semiconductor packages with a small pitch it is not possible to apply a solder resist bridge between two terminals, and a cu defi ned or combination layout must be used. if a solder land is solder resist defined, the cu must extend far enough underneath the solder resist to allow for tolerances in cu etching and solder resist placement during board production. similarly, if a solder land is cu defined, the solder resist must lie sufficiently far away from the solder land to prevent bleeding of the solder resist onto the cu pad. typical values for these distances are 50 m to 75 m. the footprints referred to in this document indicate the areas that can be soldered. 2.2.1 smd fig 18. solder mask/resist defined footprint (smdp) figure 18 shows the solder resist defined pads; yellow is cu and dark green is solder resist. the cu underneath the solder resist is shown in a lighter shade of green. the alternative situation is that the solder resist layer starts outside of the cu. in that case, the solder lands are cu defined. this is so metimes referred to as a non solder mask defined pad (nsmdp). 2.2.2 nsmdp a cu defined layout is shown in fig 19. (white is the bare board). fig 19. cu defined footprint (nsmdp) note that a solder resist defined layout requi res the application of a solder resist bridge between two terminals. there is a minimum widt h of solder resist that can be applied by
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 13 of 49 board suppliers. this fact, in combination with a maximum solder resist placement accuracy, implies that solder resist def ined layouts are not always possible. a foot print design describes the recommende d dimensions of the solder lands on the pcb, to make reliable solder joints between the semiconductor package and the pcb. the package outline and pcb footprints of n xp semiconductor plastic packages can be found by clicking ?packages? in the ?loo king for products? panel on the product information page of the nxp semiconductors web site at the url given in ?contact information? at the bottom of page 2. the uni que identifier for the pcb footprint is the nxp package outline code (the package sot or sod number). for general guidelines on board design, see ipc-7351 (paragraph 12 ): generic requirements for surface mount devic es and land pattern standard. the next paragraph explains how to read the pcb footprint. fig 20 shows an example of a pcb footprint, as can be found on the nxp semiconductors web site. fig 20. example of a foot print the soldering process is carried out under a set of process parameters that includes accuracies in the process, and semiconducto r package, board, and stencil tolerances. the footprint design is directly related to these aspects of the soldering process; the calculation of these dimensions is based on process parameters that are compliant with modern machines and a state-of-the-art process. the substrates used for mounting the package s can be made of a variety of materials with different properties. due to the in creased transistor density in the latest semiconductor technologies, and higher current (power) handling requirements, generation of heat has become a major limitati on of the semiconductor performance. by applying an exposed pad or heat sink in the semiconductor package, in combination with thermal vias in the pcb, the heat can be tr ansferred from the active die to the outside
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 14 of 49 world. four examples of vias capped in different ways, are shown in fig 21. note that the only difference lies in the solder resist pattern. fig 21. capped vias; left to right: via tenting from top, via tenting from bottom, via capping from bottom, via encroached from bottom
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 15 of 49 3. design rules for pcb design the heat sink design depends primarily on dissipated heat and on the other components located on the pcb. these vary from one application to the next. therefore no general recommendations on the size and thickness of the heat sink. the size of the cavity in the heat sink is defined by the package. for easy placement of the package flange into the heat sink cavity, t he cavity width and length must be a little larger than the flange width and length. nxp recommends making both the width and the length of the heat sink cavity 100 m larger than the flange dimensions. the formula used is similar to the one used for determining the aperture in the pcb: cavity dimension = u max + 0.1 mm + tolerance for the pcb, the aperture should be a little lar ger (+ 0.2 mm) than the cavity in the heat sink (+ 0.1 mm). this is because of the risk of positional inaccuracy of the aperture in the pcb and the ensuing risk of placing the package leads on the ridge of solder mask. this risk does not exist with the heat sink cavity. as the tolerance in the heat sink cavity varies per application, the end values are not given in this document. for these packages, it is essential that, after mounting, the package leads make good contact with the pcb pads, and that at t he same time the bottom of the flange makes good contact with the heat sink. the main parameters here are: ? the pcb thickness (pt, see fig 22 .). ? the thickness of the interface (adhesive) between the pcb and the heat sink. ? solder thickness under the lead. ? the height of the heat sink cavity (or pedestal) (cd). ? the thickness of the thermal comp ound between the flange and the heat sink (sf) ? q: this is the dimension (also know n as stand off/seating plane) between the bottom of the flange and the bottom of the l eads. this is defined by the package. all of these parameters will vary due to thei r tolerances. determining, the to be made, cavity depth is a simple calculation of a wors t case tolerance stack up; however it might end up in a value simple too large for normal production (the leads will likely lay too high above the pcb). a more common way is to make use of the square root of sum of the square method (2 or 3 respectively 97.3 % and 95.4 % of the population). use the actual distribution of all valid parts. in case these are not available take the actual specification.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 16 of 49 fig 22. main rules in defining the smd footprint two main factors need to be taken into account with the design of the heat sink cavity depth: ? in a situation with a too deep cavity the leads will be lifted upwards when bolting down the flange. with a pcb edge close to the package this could lead not only to high stresses at zero hours, but during o perating life (temperature differences, cte mismatches of materials) these might even become higher. thus it is important to test these worse case conditions prior to release the process. another phenomena is the end of the lead tip laying high above t he pcb, this might be compensated when soldering the leads. fig 23. main rules in defining the smd footprint ? in a situation with a too shallow cavity t he distance between the solder of the leads and the flange becomes smaller, increasing the chance of solder bridging resulting in short circuits.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 17 of 49 fig 24. main rules in defining the smd footprint 3.1 surface condition of the (heat sink) cavity nxp recommends the following for bolt down applications: ? flatness of mounting areas to be 0.01 mm. ? roughness ra must be less then 0.5 m (for bolt down applications) ? free of burrs
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 18 of 49 4. solder paste printing solder paste printing requires a stencil apertu re to be completely filled with paste. when the board is released from the stencil, the solder paste is supposed to adhere to the board so that all of the paste is released from the stencil aperture and a good solder paste deposit remains on the board. ideally, the volume of solder paste on the board should equal the ?volume? of the stencil apertu re. in practice, however, not all of the solder paste is released from the stencil aperture. the percentage of paste released depends largely on the aperture dimensions, that is, the length and width and the depth (the stencil thickness). if a stencil aperture be comes very small, the paste will no longer release completely. furthermore, stencil aperture s must be larger if a thicker stencil is used. another important factor is the aperture shape, that is, whether the aperture is rectangular, trapezoidal, or otherwise. paste release also depends - amongst others ? on the loading and speed of the squeegee, t he board separation speed, the printing direction and the aperture orientation. in essence, all of these parameters must be adjusted so that all solder paste deposits on one board, from the smallest to the largest, are printed properly. fig 25. stencil printing consequences of insufficient solder paste printing are usually open contacts or bad joints. these may arise because: ? the solder paste deposit is not sufficien tly high: components or their leads may not make proper contact with the paste, resu lting in open circuits or bad joints, or ? there is insufficient solder volume for a proper solder joint, also resulting in open circuits, or ? the activator is used up rapidly in a small solder paste deposit, so that the paste no longer properly wets the component metallization, also resulting in open circuits
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 19 of 49 4.1 stencil thickness a second important aspect in solder paste printing is smearing. if some solder paste bleeds between the stencil and the board durin g one printing stroke, then the next board may not fit tightly to the stencil, allowing more paste to bleed onto the bottom of the stencil. once this effect starts, it strength ens itself. as a result, the solder paste may eventually form bridges that stretch from one paste deposit to the next. if a bridge is narrow enough, it will snap open during reflow, as the volume of molten solder seeks to attain minimum surface area. a wider bridge, however, may remain stable, resulting in a short circuit. to achieve a difference in solder paste volumes on one board, it is possible to use a stencil that has a different thickness at differ ent locations. an example of this is the step- stencil. this, however, is only recommended if there is no other solution. stencils are commonly made from nickel; they may be either electro-formed or laser-cut (preferred). typical stencil thickness is given in table 1. fig 26. stencil table 1. stencil thickness semiconductor package pitch stencil thickness 0.5 mm 150 p m 0.4 mm to 0.5 mm 100 p m to 125 p m in most cases, the package will be mounted on a pcb after the rest of the pcb has been populated. in other words, the following steps precede mounting of a package: x solder paste printing (sometimes in combination with a solder preform) x component placement x reflow x only after the above, will mounting of a package start. ii may be useful to print solder paste on the pcb pads for the air cavity package as well. this solder will have been reflow-ed by the time the package is placed. however, it will nonetheless ensure that there is some solder underneath the leads. the height of the solder on the pcb pads will depend on the stencil that was used for stencil printing.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 20 of 49 no-clean solder paste and no-clean solder wire should be used, so the pcb and the package do not have to be cleaned after reflow- or manual soldering. the footprint design describes the recomm ended solder land on the pcb to make a reliable solder joint between the semiconductor package and the pcb. a proven solder material is snpb, but due to legislation, the industry has changed, to a large extent, to pb-free solutions such as sn/ag/cu (sac). process requirements for solder paste printing and reflow soldering, for snpb and pb-f ree, are also discussed in this document. printed-circuit boards and footprints printed- circuit boards (pcbs) are not only used as mechanical carriers for electronic component s; they also provide the electronic interconnection between these components and also between these components and the outside world. these electronic components may be semiconductors, or other types such as capacitors and resistors. through co mponent selection and the use of cu interconnections between the components, an electronic system, such as a mobile phone, can be assembled on a pcb. fig 27. example of surface mounted device common board finishes include niau, organic solder-ability preservative (osp), and immersion sn. although finishes may look different after reflow, and some appear to have better wetting characteristics than others, all common finishes can be used, provided that they are in accordance with t he specifications. examples of other issues in board quality are tolerances on the pad and solder resist dimensions and component placement, maximum board dimensions, and flatness. the application board is usually a mix of large and small components together with thermal design features. in board designs where large components or thermal design features are in close proximity to small components, solder-ability issues may arise.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 21 of 49 4.2 stencil aperture a general rule is that the stencil apertures mu st be 25 um smaller than the solder lands, on all sides. in other words, the solder paste lays 25 um inward from the solder land edge. this usually results in stencil aperture dimensions that are 50 um smaller than the corresponding solder land dimensions; see fig 28. fig 28. solder paste printing on nsmdp and smdp another exception lies with the very large solder lands, such as when printing solder paste on a heat sink land. in that case, it is advised to print an array of smaller solder paste deposits. the solder paste should cover approximately 20 % of the total land area. it is also advised to keep the solder paste aw ay from the edges of this land: the solder paste pattern, including the spacing between the deposits, should have coverage of 35 % of the land area; see fig 29. and fig 30. fig 29. solder paste printing on nsmdp and smdp fig 30. solder paste printing on nsmdp and smdp a paste-printing pattern for exposed die pad s is illustrated by t he example shown in figure 31. a hvqfn48 with an exposed pad of 5.1 mm x 5.1 mm, for example, should have nine solder paste deposits that are arr anged in a three-by-three array. the solder paste deposits are 0.76 mm x 0.76 mm, and the distance between them is 0.37 mm. this way, the solder paste area is 9 x (0.76 mm x 0.76 mm), and dividing this by the land area 5.1 mm x 5.1 mm yields a solder paste co verage of approximately 20 %. similarly, the solder paste pattern (the paste, plus t he area between the deposits) has a length of
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 22 of 49 3.02 mm. the pattern area, 3.02 mm x 3.02 mm, divided by the land area, yields a solder past pattern coverage of approximately 35 %. depending on the solder paste used, the solder paste deposits printed on a large land may not always coalesce completely. in some cases, individual solder joints can still be recognized between the exposed die pad and sold er land on the board. it is possible that voids remain in the solder joints. whether or not voids or incomplete coalescing of the solder are a problem, depends on the application. for low-power devices in which little heat is generated, up to 80 % of voids may still be acceptable. fig 31. solder paste dimensions on the land area for an exposed die pad
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 23 of 49 5. solder past and preform there are several materials that ensure a good thermal and electrical conductive interface. in table 2 gives a summary of the possible combinations. the ?x? marked cells are typically used in the industry while the ?o? marked cells might be optional. table 2. overview of solder pastes and preforms used (x = commonly used, o = optional) air cavity over molded eared earless eared earless lead shape and solder type leads flange leads flange leads flange leads flange s = straight, g = gull wing s - s - - - s & g - solder paste x - x o - - x x solder preform o - o x - - - o thermal paste - x - - - - - - 5.1 solders in line with european legislation, it is recommended to use a pb-free solder paste or preform, although exemptions are granted for se lected applications, such as automotive. a wide variety of pb-free solder pastes are available, containing combinations of tin, copper, antimony, silver, bismuth, indium, and other elements. the different types of pb- free solder pastes/preforms have a wide range of melting temperatures. solders with a high melting point may be more suitable for the automotive industr y, whereas solders with a low melting point can be used for soldering consumer semiconductor packages. as a substitute for snpb solder, the most common pb-free paste/preforms is sac, which is a combination of tin (sn), silver (ag) , and copper (cu). these three elements are usually in the range of 3 % to 4 % of ag and 0 % to 1 % of cu, which is near eutectic. sac typically has a melting temperature of around 217 c, and it requires a reflow temperature of more than 235 c. table 3. minimum peak temperature for soldering solder melting temperature minimum peak reflow temperature (measured at the solder joint) sac 217 c 235 c pbsn 183 c 215 c care should be taken when selecting a solder, and note that solder types are categorized by solder sphere size. for small packages or fine pitch applications solder paste type 3 or better is recommended. a no-clean solder paste or preform does not require cleaning after reflow soldering and is therefore preferred, provided t hat this is possible within the process window. if a no-clean paste is used, flux residues may be visible on the board after reflow. preforms with pre-applied flux are available in market. in case separate flux (manually, like with a brush, pen or dipping) is applied in combination with a preform, extra care need s to be taken not too use excessive amounts of flux. these might increase the chance of voids in the solder joint.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 24 of 49 for more information on the solder paste and solder preforms, please contact your solder supplier. 5.2 thermal paste/preform the eared (bolt down) ceramic packages are typically using a thermal paste or preform to improve the thermal conductivity, meani ng better than a metal on metal contact. a ?metal to metal? contact area is very small (could be ~ 2 % depending on the roughness). applying pressure by bolt down will increase this contact area, but still those areas not being in contact are filled up by air, known as a bad heat conductor. filling these air pockets with a thermal past e (in lesser extend with a preform) will increase the contact area further resu lting in a better thermal conductivity. solder offers the best thermal contact but c an create other problems such as trapped flux (voids) and tce mismatch (bow). nxp does use thermal grease for the evaluation of eared (bolt down) and solder preforms for the earless devices. for production reasons (efficiency) customers use thermal preforms, such as metal foils (like copper) and graphite containing pads. point of attention when pads are used: ? check for galvanic corrosion in the application. ? keep the pad size close to the size of the backside of the device. too short pads give additional stress when bolting down the flange ands might even cause cracking of the package. 5.3 solder amount this document does not give recommendation about the amount of solder to be used for every type of product. for air cavity packages howe ver it is important to take notice of the gold plating. in 10.3 the information needed to prevent gold embrittlement can be found.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 25 of 49 6. reflow soldering procedure nxp advises to use a convection oven rat her than a conduction or radiation oven. a convection oven provides a uniform heat and a very controlled temperature ( 2 c). moreover, it allows soldering a wide range of products due to the temperature uniformity. during the reflow soldering process all parts of the board are subjected to an accurate temperature/time profile. a temperature profile essentially consists of three phases: ? pre-heat: the board is warmed up to a temperature that lies lower than the melting point of the solder alloy. ? reflow : the board is heated to a peak tem perature well above the melting point of the solder, but below the temperat ure at which the components and boards are damaged. ? cooling down: the board is cooled down, so that soldered joints freeze before the board exits the oven. the peak temperature during reflow has an upper and a lower limit. 6.1 lower limit of peak temperature the minimum peak temperature must at least be high enough for the solder to make reliable solder joints. this is determined by solder paste characteristics; contact your paste supplier for details. 6.2 upper limit of peak temperature the maximum peak temperature must be lower than the temperature at which the components are damaged. this is defined by msl testing of the package. the maximum body temperature during reflow soldering depends on the body size and on the demand to respect the package msl. 6.3 the temperature at which the boards are damaged this is a board characteristic; contact your board supplier for details. when a board is exposed to the temperat ure profile, certain ar eas on the board will become hotter than others: a board has hot spot s (the hottest areas) and cold spots (the coolest areas). cold spots are usually found in sections of the board that hold a high density of large components, as these soak up a lot of heat, or near heat sinks. hot spots, on the other hand, are found in areas with few components, or only the smallest components, and with little cu nearby. finally, the board dimensions, and the board orientation in the oven, may also affect the location of hot and cold spots. the hot spot on a board may not surpass t he upper limit to the peak temperature. similarly, the cold spot must reach the lower lim it at least. thus, it is imperative that all areas on the board, including the hot and cold spots, fall within the upper and lower limits of the peak temperature.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 26 of 49 fig 32. temperature profiles for large and small components in fig 32 the yellow band with the large component represents cold spots, and the red band, with the smallest component, represents hot spots. in the pre-heat phase, the hot spots will heat up rapidly to a temperature lowe r than the melting point of the solder alloy. they may remain at this temperature for a wh ile. note, however, that small solder paste deposits should not remain at an intermediate temperature for so long that their activator runs out: for small solder paste deposits, a fast temperature profile is preferred. the cold spots on the board will warm up far more slowly. the oven settings should be planned so that the cold as well as the hot spots will have reached roughly the same temperature by the end of the pre-heat phase. the second phase in the reflow profile is the reflow zone, in which the solder melts and forms soldered joints. the minimum peak temper ature, in which all solder joints in the cold as well as the hot spots must reach, depends on the solder alloy. however, no region on the board may surpass a maximum peak temperature, as this would result in component and/or board damage. even if the cold and hot spots start the reflow phase with roughly the same temperature, the hot spots will reach a higher peak temperature than the cold spots. yet, both the hot spots and the cold spots must lie within the allowed peak temperature range. this may require some tweaking of the oven temperature settings and conveyor belt speeds. in extrem e cases, even the board layout may have to be optimised to limit the temperature differ ence between the cold and the hot spots. when reflow soldering, the peak temperatur e should never exceed the temperature at which either the components or the board are damaged. the maximum peak temperature for components is partially deter mined by their moisture sensitivity. for reflow soldering with snpb solder, the peak temperature should be larger than 210 oc; when soldering with sac, the peak temperature should be larger than 235 oc. note that this usually implies a smaller process window fo r pb-free soldering, thus requiring tighter process control. temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 27 of 49 fig 33. fitting both the hot and cold spots into the required peak temperature range the black lines in fig 33 represent the actual temper ature profiles for a number of different spots on a board. the bottom line represents the cold spot, and the top line corresponds to the hot spot. the blue line represents the minimum allowed peak temperature, and the red line is the maximum allowed peak temperature. at the top left, some regions on the board are exposed to tem peratures that are too high, resulting in damage. at the bottom left, some regions on t he board are exposed to temperatures that are too low, resulting in unreliable joints. at the right, all of the regions on the board have peak temperatures that fall within the upper and lower limits. reflow may be done either in air or in nitrogen. in general, nitrogen should not be necessary; in that case, air is preferred because of the lower cost. reflow may be done in convection reflow ovens, some of whic h have additional infrared heating. furthermore, using vapour phase reflow soldering can reduce temperature differences on a board. proper joint formation should always be verified by visual inspection through a microscope. in general, pb-free solder is a little less successful at wetting than snpb solders; sac fillets will have a larger contact angle between the fillet and the wetted surface. when using pb-free solder this contact angle may typically be 20 to 30 . in paragraph 7 more information is given concerning wetting behaviour. 6.4 an example of a reflow prof ile used for internal study: calibration: the reflow soldering profile should be calibrated with a thermo couple glued down on the cap of the acp device to prevent a temperature offset. all reflow activities were performed in the heller oven (model 1700 exl) with 6 zones, and reflow was in an inert atmosphere (n 2 ). an inert atmosphere improves wetting and reduces the chances of solder balling. this is a belt oven, and changing zone temperatures and belt speed can alter temper ature profiles. the monitored temperature profiles are compared to the jedec recommendations ( table 4 ). thermal damage unreliable joints thermal damage unreliable joints maximum peak temperature: damage level for package minimum peak temperature: minimum solder joint temperature thermal damage unreliable joints thermal damage unreliable joints maximum peak temperature: damage level for package minimum peak temperature: minimum solder joint temperature
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 28 of 49 table 4. reflow profile cl assification (jedec jstd020d) parameter units specification comments time above liquidus s 60 ? 150 sac liquiqus is 217 o c ramp-up slope (max) o c / s 3 heating rate max. package temperature o c 245 the solder used was sac (pb-free) with a melting point of 217 o c, and peak-soldering temperature was between 235 o c to 245 o c (jedec jstd020d). the reflow profile shown in table 5 provided the measured out put parameters presented in table 6. table 5. reflow oven settings ? zone temperature and belt speed zone # 1 2 3 4 5 6 belt speed temperature ( c) 150 155 170 230 245 260` 36 cm/min table 6. measured temperature profile parameter units spec measured value time above liquidus s 60 ? 150 83 ramp-up slope (max) o c / s 3 1.71 max package temperature o c 245 239 fig 34. measured reflow profile
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 29 of 49 7. inspection 7.1 wetting appearance notice the difference between snpb and pb-free solder in fig 35 the photograph on the left (snpb) shows the solder lands have been wetted completely. the photograph on the right shows the solder has left part of the solder lands non-wetted. a. snpb solder joints b. pb free solder joints fig 35. wetting appearance c. snpb solder joints d. pb free solder joints fig 36. visual appearance (shiny versus dull) another visual aspect in pb-free soldering is that pb-free solder joints tend to be less shiny than snpb solder joints and they may have striation marks. this is due to the different microstructure that is formed duri ng solidification. although snpb solder joints should be rejected if they look this way, this is normal for pb-free and no reason to reject pb-free solder joints. non-wetting of lead frame parts as a result of punching or sawing is not a reason for rejection. other inspection methods besides optical inspection, such as, for design and process development purposes are: ? automatic optical inspection (aoi) ? examination by roentgen ray (x-ray) ? cross-sectional analysis ? dye penetration test ? csam (scanning acoustic microscope)
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 30 of 49 7.2 x-ray x-ray can only provide information between the leads and laminate interface. void levels under 10 % do provide confidence in the materials and soldering process. in the fig 37 an example can be seen of voiding under the lead tip. fig 37. x-ray lead-pcb interface 7.3 c-sam this method is used to examine in partic ular the interface between the exposed heat spreader/flange and the heat sink, as it is not det ectable by x-ray. variability in gray scale (dark ? bright) indicates presence of voids. in several demo boards, the solder interfaces are in the same plane. consequently focusing is required only on one plane. the interface between the heat spreader and heat sink shows very little variation, which implies low level of voids.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 31 of 49 8. mounting procedure 8.1 air cavity devices 8.1.1 manual mounting 8.1.1.1 package placement even though the ceramic package is not passed through a reflow oven, it may be heated by a soldering iron or bar. therefore, for the sake of moisture sensitivity, it is best to store the packages in dry environment or in nitrogen. using an in-house method, apply an even layer of thermal compound to the bottom of the package flange. this thermal compound w ill improve the therma l conductivity between the metal surfaces of the flange and the heat sink. the layer must be thin, and it must be evenly spread out before placing the package, so that no air bubbles are trapped. use of excessive thermal compound is not desirable, as it adds a ?layer? of thermal resistance. in addition, excess thermal compound may leak out of the heat sink cavity when the package is bolted to the heat sink ? this could contaminate the pcb near the package. place the package in its position, with the flange sticking through the pcb and into the cavity in the heat sink. package alignment is done visually, by adjusting the position so that the package leads are exactly aligned with the pcb pads. in order to ensure a good interconnection between the flange and the bottom of the heat sink cavity, the package is bolted down onto the heat sink. the holes in the heat sink may have thread, in which case the bolt is fix ed to the heat sink itself. they may also be plain, in which case nuts are used to tighten the bolts. both situati ons are illustrated in fig 38. fig 38. main rules in defining the smd footprint do not use hexagonal bolts, as these may interfere with some of the smaller flange- mount packages during the bolting step. the force applied when tightening the bolts is important to ensure a good contact between the flange and the heat sink. it is reco mmended to tighten the bolts in two steps to ensure the packages free from damages during mounting: ? first, both bolts should be tightened (finger tight). ? second, the bolts should be fully tightened to the recommended torque with a controlled torque wrench, such as a to rque screwdriver. excessive torque may damage the device. the range of torques (calculated for m3) recommended for flange packages.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 32 of 49 table 7. torque torque minimum value maximum value nm 0.60 0.75 washers are recommended in order to spread the force equally. in addition, use of spring-lock washers will make sure that the bolts do not come loose with vibrations when the product is used. 8.1.1.2 soldering the leads soldering the leads to the pcb pads is largel y a question of good workmanship, as it is done manually. use a soldering iron, or bar, with a tip that is at least as wide as the leads. the width should be smaller than t he package width, to eliminate the risk of accidentally touching othe r components on the pcb. use a soldering iron or bar that is esd-safe. use solder wire. use an alloy that has a me lting temperature that is not higher (and preferably lower) than the solder that was used on the rest of the pcb. set the soldering iron or bar to the temperature specified by the solder supplier. flux containing solder wire is preferred. using the iron or bar, apply solder to the pcb pad, around the package lead. make sure that the solder has melted completely and apply enough solder to ensure a good joint. if there is a small gap between the lead and the pad apply extra solder to fill this. throughout this process care must be taken t hat the soldering iron or bar makes contact with neither the package body nor the nei ghboring components. the solder may not touch the package body. proper joint formation should be verified by visual inspection through a microscope. if there is a gap between the leads and the pcb pad, check the filling by the solder. also, an angle of 20 ? 30 degrees indicates good wetting, for lead-free solders. 8.1.1.3 reflow mounting for these packages, it is critical the lead s make good contact with the pads on the pcb, and that ? at the same time ? the flange ma kes good contact with the heat sink. for these reasons, the package is usually bolted to the board with a fixture, during reflow. firstly, the package must be placed on the pc b and into the heat sink cavity, in such a way that the flange makes contact with the bo ttom of the heat sink cavity. at the same time, contact between the leads and the pcb pads may not be optimal. next, the fixture is bolted down over the package, so that good contact between the leads and the pcb pads are also ensured. this is described in more detail in the following sections.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 33 of 49 8.1.1.4 fixture design fig 39. fixture dimensions these ceramic packages should be fixed to the pcb using a fixture. the fixture is bolted to the heat sink, with bolts that pass through the pcb. in fig 39 .an example of a fixture can be seen. fig 40. fixture top view fig 41. fixture bottom view the fixture has a small ridge that presses down on the package leads. a close-up of this ridge is shown in fig 42. fig 42. close-up of ridge in fixture the package is placed in the heat sink cavity through an aperture in the pcb.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 34 of 49 fig 43. example apertures in the pcb fig 44. placed device fig 45. placed fixture the fixture is also bolted through holes in the pcb. place the package in its position, with the flange sticking through the pcb and into the cavity in the heat sink. package alignment is done visually, by adjusting the position so that the package leads are exactly over the pc b pads. if the depth of the heat sink cavity was designed correctly, contact should be made between the package leads and the printed solder paste. the package leads should ideally be pressed at least 20 m into the solder paste. in some cases, however, depen ding on the various values in the stack in the z direction, and on tolerances, the leads may also hover above the solder paste. verify manually that the package flange rests on the solder preform that has been placed in the heat sink cavity. if the cavity is t oo deep, so that the package flange does not make good thermal contact with the bottom of the heat sink cavity, a thicker preform may be used ? but keep the r th increase in mind. it must be stressed that it is acceptable at th is point in the process if the leads do not make contact with the solder paste, but it is not acceptable if the flange does not make contact with the solder preform. in order to ensure a good interconnection between the leads and the pads on the pcb, a reflow fixt ure is now bolted down over the package, onto the heat sink. the bolts pass through holes in the pcb. the holes in the heat sink may have thread, in which case the bolt is fix ed to the heat sink itself. the bolts may also be plain, in which case nuts are used to tighten the bolts. fig 46. bolting down the reflow fixture it is recommended that the bolts be tightened in two steps: x first, the bolts should be tightened by hand so they are finger tight. x second, the bolts should be fully tightened to the recommended torque with a controlled torque wrench, such as a torque screwdriver.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 35 of 49 a difference in torque between bolts may lead to a tilted reflow fixture and joints that have not been soldered properly. table 8. suggested torque ranges for bolting down the fixture torque minimum value maximum value nm 0.60 0.75 the maximum recommended torques were calculated for m3 bolts. after bolting down the fixture, check to ma ke sure that the package leads make good contact with the solder paste the tips of the leads should be pressed at least 20 m into the solder paste. if there is no proper contact between the leads and the so lder paste, extra solder paste can be dispensed onto the leads. the leads may not be bent downward more than 300 m. after bolting down the fixture, make sure that this is not the case. the re ason for this limit is that too much lead deflection may cause great mechanical stre ss at the lead/body interface, causing damage to the package. 8.1.1.5 reflow soldering the most important step in reflow soldering is when the solder paste deposits melt and soldered joints are formed. this is achieved by passing the boards through an oven and exposing them to a temperature profile with varied times. a rough indication of the recommended minimum peak temperatures for snpb and sac alloys is given in table 3 , however, these values should be verified with your solder paste supplier. after reflow, check that the solder in the heat sink cavity does not make contact with the package body. fig 47. inspection of solder finally, remove the reusable reflow fixture. ok not ok ? solder touches package body
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 36 of 49 8.2 over molded devices 8.2.1 manual mounting 8.2.1.1 package placement the required placement accuracy of a package depends on a variety of factors, such as package size and the terminal pitch, but also the package type itself. during reflow, when the solder is molten, a package that has not been placed perfectly may center itself on the pads: this is referred to as self-alignment. therefore, the required placement accuracy of a package may be less tight if th is package is a trusted self-aligner. it is known, for example, that a bga is good at self-alignment, as the package body essentially rests on a number of droplets of molten solder, resulting in minimal friction. remark: self-alignment properties can be improved by performing the reflow process in an n2 environment. typical placement tolerances, as a function of the semiconductor package terminal pitch, are given in table 9. table 9. typical placement accuracy package terminal pitch placement tolerance (3 sigma) > 0.65 mm 100 m < 0.65 mm > 0.5 mm 50 m < 0.5 mm 30 m semiconductor packages are usually placed with two types of machines. if the highest placement accuracy is required, the slower but more accurate mach ines must be used. these machines are also often more flexible when it comes to unusual package shapes, that may require dedicated nozzles and non-st andard trays. if the highest placement accuracy is not necessary, and there are no special requirements, fast component mounters or chip shooters, can be used. these machines can process up to 100,000 components per hour. the placement force may also be an important parameter for some packages. in theory, a semiconductor package is always pressed do wn into the solder paste until it rests on a single layer of solder paste powder particles - the rest of the solder paste is pressed aside. a consequence immediately apparent is t hat the solder paste that is pushed aside, or that bulges outside the package, may cause bridges with neighboring solder paste deposits. in extreme cases, solder paste may not onl y bulge outside the pads, but may actually be blasted further away from the pads, so that a small amount of solder paste is no longer connected to the paste deposit it originally came from. this must always be avoided as the splattered solder paste may cause a short circuit on the board, and the original solder paste deposit may then have insufficient solder. in cidentally, this effect is often caused in part by use of an improper nozzle shape, so t hat the paste is actually blown away by air from the nozzle. if the placement force is too low, there is a chance that a semiconductor package terminal does not make sufficient contact with the solder paste. in that case, there is a risk that the solder paste tackiness will not be able to hold it in place up to the reflow zone in the oven, and the package may be displaced. in addition, even if the semiconductor package remains in place, there may be bad contact between the package terminals and the solder paste resulting in open contacts or bad joints.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 37 of 49 therefore, the placement force must always be adjusted so that there is no excessive paste bulging or even splattering and there is a proper contact between the semiconductor package and the solder paste. the necessary placement force to achieve this will depend on a number of factors, including the package dimensions. typical forces are 1.5 n to 4 n. note however, that some of the more modern machines have a sensor that detects the package?s proximity to the so lder paste so that the placement speed is reduced as soon as the package comes near to, or touches, the solder paste. in this way, splattering can be minimized.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 38 of 49 9. reworking a package lead, not being soldered properly, can be repaired by heating it with the tip of a soldering iron. in that case, it is suffi cient to heat the lead until the solder melts completely, and a new device should not be necessary. in other situations, however, there may be a need to replace the package. in that case, the rework process should consist of the following steps: ? removal of old package ? site preparation ? new package placement ? soldering new package 9.1 removal of the package prior to removal of the old package it is adv ised to dry-bake the pcb for 4 hours at 125 o c, then: ? unscrew the bolts holdi ng down the eared package. ? remove the old package using a specially designed soldering iron tip. the tip may have two parts pressing down on the two leads at the same time, and leave room in the middle for a nozzle to lift the component. examples of special tips for soldering irons are shown in fig 48. fig 48. two part soldering iron tips if the package is going to be submitted to a fa ilure analysis, use a soldering iron that is esd-safe.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 39 of 49 it is essential that both leads are heated si multaneously, while a vacuum wand nozzle is attached to the top of the package body, for lifting it off. the process steps are as follows: ? set the soldering iron or bar to a temp erature that is high enough to melt the solder. this value depends on the solder that was used to attach the package. ? attach a vacuum wand nozzle to the top of the package body. ? when the soldering iron has reached th e desired temperature, place it over the package so that both package le ads are heated simultaneously. ? watch carefully as the soldering iron or bar heats the solder joint. ? as soon as the solder melts, lift the package off the pcb using the vacuum wand. do not lift the package before the solder in the joints has melted completely, as this may damage the package and the pcb. throughout this process, care must be taken t hat the soldering iron or bar makes contact with neither the package body nor the neighboring components. although a hot air gun with a dedicated nozzle c ould theoretically be used, this is not recommended. with hot air guns, the package b ody is also heated, and the temperatures are often poorly defined. if a soldering iron with a suitable tip is not available, it is possible to remove the old package by de-soldering the leads one lead at a time. in that case, apply the iron to one of the leads, and wait until the solder in t he joint has melted completely. then, lift the package. as the other lead is still soldered to the pcb, this will result in damage. next, de-solder the other lead. due to the damage this method causes, it is not preferred if the package is going to be submitted for failure analysis. after the old package has been removed, check whether excess thermal compound has remained in the cavity in the heat sink. if this is the case, remove the heat sink from the pcb and discard it. 9.2 site preparation after the package has been removed, the pcb pads must be prepared for the new package. prepare the pads by removing any ex cess solder and/or flux remains. ideally this is done on an appropriate de-soldering stat ion. alternately, use a soldering iron set to the temperature specified for the solder that was originally used to attach the package. clean the pads using the soldering iron and so lder wick, or another in-house technique. note: use a temperature that is needed to just liquefy the solder but that does not damage the pcb. after most of the solder has been removed from a solder land, a very thin layer of solder will be left, on top of a few intermetallic layers. in the case of cu p ads, for example, there will be layers of cu 3 sn, cu 6 sn 5 , and finally solder, on top of the cu. the top layer of solder is easily solder-able.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 40 of 49 fig 49. overheating and cu 3 sn formation if, however, the pad is heated too much durin g removal of the rejected ic package, and during site preparation, the top two layers will also be converted into cu 3 sn; in that case, there will only be the cu 3 sn inter-metallic layer on top of the cu. unfortunately, cu 3 sn is hardly wettable. as a result, it will become very difficult to solder the replacement package at this location. therefore, care must be taken during reject package removal and site redress, that the solder lands ar e heated only as much as is absolutely necessary. 9.3 placement of the new package if the heat sink was discarded, mount a new heat sink. next, mount a new package in much the same way as the original package was mounted. re-use of removed packages is not recommended. finally, the new package is soldered to the pcb in the same manner as the original package. cu cu 3 sn cu 6 sn 5 solder cu cu 3 sn normal too hot for too long
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 41 of 49 10. appendices 10.1 appendix i: msl if there is moisture trapped inside a plasti c over molded surface mount package, and the package is exposed to a reflow temperature profile, the moisture may turn into steam, which expands rapidly. this may cause damage to the inside of the package (delamination), and it may result in a cracked semiconductor package body (the popcorn effect). a package?s sensitivity to moisture, or moisture sensitivity level (msl), depends on the package characteristics and on the te mperature it is exposed to during reflow soldering. the msl of semiconductor pac kages can be determined through standardized tests in which the packages are moisturized to a predetermined level and then exposed to a temperature profile. studies have shown that small and thin packages reach higher temperatures during reflow than larger pa ckages. therefore, small and thin packages must be classified at higher reflow temperat ures. the temperatures that packages are exposed to are always measured at the top of the package body. depending on the damage after this test, an msl of 1 (not sens itive to moisture) to 6 (very sensitive to moisture) is attached to the semiconductor package. for every plastic over molded product, this msl is given on a packing label on the shipping box. each package is rated at two temperatures, for snpb and pb-free sol dering conditions. an example of a packing label is given in fig 50. fig 50. example of msl information on packing label; note the two msls corresponding to the two reflow processes an msl corresponds to a certain out-of-bag time (or floor life). if semiconductor packages are removed from their sealed dry- bags and not soldered within their out-of- bag time, they must be baked prior to reflow, in order to remove any moisture that might have soaked into the package. msls and temp eratures on the packing labels are to be respected at all times. naturally, this also means that semiconductor packages with a critical msl may not remain on the plac ement machine between assembly runs. nor should partial assembled boards, between two reflow steps, be stored longer than indicated by the msl level. the semiconducto r package floor life, as a function of the msl, can be found in table 10.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 42 of 49 table 10. msl levels floor life msl time conditions 1 unlimited 30 q c / 85 % rh 2 1 year 30 q c / 85 % rh 3a 4 weeks 30 q c / 85 % rh 3 168 hours 30 q c / 85 % rh 4 72 hours 30 q c / 85 % rh 5 48 hours 30 q c / 85 % rh 5a 24 hours 30 q c / 85 % rh 6 6 hours 30 q c / 85 % rh note: the definition of surface mount imp lies to have the exposed heat spreader and the lead surface to be at the same level. with other words an over molded package with straight leads is not purely surface mount. the msl levels are normally determined for only surface mount devices (typically gull wing), but nxp also specifies the msl level for plastic over molded packages containing straight leads.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 43 of 49 10.2 esd damage to semiconductors from electro static discharge (esd) is a major cause of rejects and poses an increased risk to mini aturized packages. electrostatic charge can be stored in many things, for example, m an-made fiber clothing, moving machinery, objects with air blowing across them, plastic storage bins, sheets of paper stored in plastic envelopes, paper from electrostati c copying machines, and people. electrostatic discharge is the transfer of an electrostatic charge between bodies at different potentials and occurs with direct contact or when i nduced by an electrostatic field. it is recommended that the following esd precautions be complied with. 10.2.1 workstations for handling esd sensitive components fig 50 shows a working area suitable for safely handling electrostatic-sensitive devices. the following precautions should be observed: ? workbench and floor surface should be lined with anti-static material ? persons at a workbench should be earthed via a wrist strap and a resistor ? all mains-powered equipment should be connected to the mains via an earth leakage switch ? equipment cases should be grounded ? relative humidity should be maintained between 40 % and 50 % ? an ionizer should be used to neutralize objects with immobile static charges in case other solutions fail ? keep static materials, such as plastic envelopes and plastic trays away from the workbench. if there are any such static materials on the workbench remove them before handling the semiconductor devices. ? refer to the current version of the handbook en 100015 (cecc 00015) ?protection of electrostatic sensitive devices? (see 12 ), which explains in more detail how to arrange an esd protective area for handling esd sensitive devices. fig 51. work place
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 44 of 49 10.2.2 receipt and storage of components packing for electrostatic devices should be made of anti-static/conductive materials. warning labels on both primary and secondary packing show that the contents are sensitive to electrostatic discharge. the electronic components should be kept in their original packing whilst in storage. if a bulk co ntainer is partially unpacked, the unpacking should be done at a protected workstation. any electronic components that are stored temporarily should be re-packed in conducti ve or anti-static packing or carriers. 10.2.3 pcb assembly all tools used during assembly, including so ldering tools and solder baths, must be grounded. all hand tools should be of condu ctive or anti-static material and where possible should not be insulated. standa rd precautions for manual handling of electrostatic-sensitive devices need to be taken into account.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 45 of 49 10.3 gold embrittlement air cavity packages are gold plated. in or der to avoid brittle ausn inter-metallics (reliability) in the solder joints enough solder should be applied. the level of gold within the solder joint may not exceed 4% by weight. 10.3.1 solder paste nxp used pb-free solder 95.5sn3.8ag0.7%cu sac for its evaluation. this solder paste contained 88% w/w 1 of powdered solder alloy (96sc) and 12% w/w flux. the density of the sn3.8ag0.7cu pb-free solder alloy is approximately 7.5 g/cc. 10.3.2 flange to heat sink attachment required amount of solder (after the reflow soldering step): w eight au 4% w eight total w eight total = w eight au + w eight solder therefore, the amount of solder required after reflow is calculated using, w eight au = ( v olume au ) x au = ( t hickness au x w idth flange x l ength flange ) x au w eight au = ( t hickness au x 1 x 1 ) x au (for 1 unit of surface area) weight au = ( t hickness au ) x au w eight total = ( t hickness au ) x au + ( t hickness solder ) x solder (for 1 unit of surface area) with: ? ! is the density of the material . the density of gold is 19.3 g/cc ? t hickness au = 2.54 m ? the density of solder is 7.5 g/cc ? t hickness solder = x m to avoid brittle solder joint due to too much gold in the joint, x 150 m solder thickness (only based on nxp part) is requir ed for flange /heat sink attachment. 1. w/w : in relation to the weight and not to the volume
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 46 of 49 the difference in thickness before soldering and after reflow is about 50 %. therefore, the thickness of solder paste to spread on to the soldering surface is min 300 m to ensure the min 150 m of solder required afte r reflow. therefore, the thickness of stencil that should be used to spread the solder paste must be between 12 - 15 mils so that after re-flowing the solder layer thickness is more than 150 m. it is tricky to ensure a proper and reliable soldering step with this amount of solder paste. it is also the reason why nxp advises to use preform for flange to heat sink attachment. 10.3.3 usage of a preform nxp advises using preform with pre-applied flux for flange to heat sink attachment. it reduces voids and ensures the required amount of solder. nxp recommend to use a min 150 m solder perform in order to ensure the required amount of solder (to avoid ausn embrittlement of solder joints). the solder preform may not be less than 150 m thick: note that a greater thickness will increase the r th value. 10.3.4 lead to pcb attachment the leads are plated with a thinner au layer compared to the flange: [0.8 m ? 1.27 m]. therefore, the thickness of solder required after soldering is about 75 m. as seen previously, the difference in thicknes s before soldering and after the reflow step is about 50 %. therefore, the thickness of solder to spread onto the soldering surface (pcb pad) is about 150 m. it allows ensuring about 75 m of solder after the reflow step. a 6 mils stencil should then be used to evenly spread the solder paste.
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 47 of 49 11. abbreviations table 11. abbreviations acronym description snpb (solder) sn (tin) pb (lead) sac (solder) sn (tin) ag (silver) cu (copper) msl moisture sensitivity level omp (packages) over-molded plastic rh relative humidity nsmdp non solder mask defined pads smdp solder mask defined pads pcb printed circuit board 12. references [1] ipc/jedec j-std-020d august 2007 joint industry standard moisture/reflow, sens itivity classification for non hermetic solid state surface mount devices [2] ipc-7351 generic requirements for surface mount design and land pattern standard, ipc [3] en 100015/cecc 00015 protection of electrostatic sens itive devices, european standard [4] 3997.750.04888 quality reference handbook, nxp [5] ipc-a-610d acceptability of electr onic assemblies, ipc
nxp semiconductors an10896 mounting and soldering of rf transistors an10896_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. application note rev. 01 ? 17 may 2010 48 of 49 13. legal information 13.1 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 13.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such informatio n and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business inte rruption, costs related to the removal or replacement of any products or re work charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that cu stomer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and condi tions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product de scriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors produ cts are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconduct ors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is custom er?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as for the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is bas ed on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. evaluation products ? this product is provided on an ?as is? and ?with all faults? basis for evaluation purposes on ly. nxp semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non- infringement, merchantability and fitness for a particular purpose. the entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. in no event shall nxp semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inab ility to use the product, whether or not based on tort (including negligence), stri ct liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. notwithstanding any damages that cu stomer might incur for any reason whatsoever (including wit hout limitation, all damag es referenced above and all direct or general damages), the entire liability of nxp semiconductors, its affiliates and their suppliers and custom er?s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (us$5.00). the foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 13.3 trademarks notice: all referenced brands, product names, service names and trademarks are property of their respective owners.
nxp semiconductors an10896 mounting and soldering of rf transistors please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'legal information'. ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an please send an email to: salesaddresses@nxp.com date of release: 17 may 2010 document identifier: an10896_1 14. contents 1. introduction ......................................................... 3 1.1 general (mounting recommendations rf power).. 3 1.2 defini tion ............................................................... 3 1.3 main produc t groups.............................................. 3 2. design rules fo r pcb d esign .............................. 4 2.1 air cavity devices................................................... 4 2.1.1 smdp.................................................................... 4 2.1.1.1 foot print dime nsions smdp.............................. 5 2.1.1.2 pcb aperture dimens ions .................................. 5 2.1.2 nsmdp ................................................................. 8 2.1.2.1 pcb footprint ? dim ensions nsmdp ................. 9 2.1.2.2 pcb aperture dimensio ns................................ 10 2.2 over molded devices........................................... 12 2.2.1 smd .................................................................... 12 2.2.2 nsmdp ............................................................... 12 3. design rules fo r pcb d esign........................... 15 3.1 surface condition of t he (heat sink ) cavity........... 17 4. solder past e printing ........................................ 18 4.1 stencil thic kness.................................................. 19 4.2 stencil a perture ................................................... 21 5. solder past and preform ................................... 23 5.1 solders ................................................................ 23 5.2 thermal paste /preform ........................................ 24 5.3 solder amount ..................................................... 24 6. reflow solderi ng procedure ............................. 25 6.1 lower limit of p eak temperature .......................... 25 6.2 upper limit of p eak temperature .......................... 25 6.3 the temperature at whic h the boards are damaged ......................................................................... 25 6.4 an example of a reflow profile used for internal study: ............................................................... 27 7. inspection .......................................................... 29 7.1 wetting app earance ............................................ 29 7.2 x-ray.................................................................... 30 7.3 c-sam................................................................. 30 8. mounting procedure.......................................... 31 8.1 air cavity devices................................................. 31 8.1.1 manual mo unting................................................. 31 8.1.1.1 package pl acem ent.......................................... 31 8.1.1.2 soldering the l eads .......................................... 32 8.1.1.3 reflow m ounting .............................................. 32 8.1.1.4 fixture design .................................................. 33 8.1.1.5 reflow soldering............................................... 35 8.2 over molded devices........................................... 36 8.2.1 manual mo unting................................................. 36 8.2.1.1 package pl acem ent .......................................... 36 9. reworking .......................................................... 38 9.1 removal of the package ...................................... 38 9.2 site prep aration ................................................... 39 9.3 placement of t he new pac kage............................ 40 10. appendices ........................................................ 41 10.1 appendix i: msl .................................................. 41 10.2 esd ..................................................................... 43 10.2.1 workstations for handling esd sensitive compo nents...................................................... 43 10.2.2 receipt and storag e of comp onents................. 44 10.2.3 pcb assembly.................................................. 44 10.3 gold embr ittlement .............................................. 45 10.3.1 solder paste ..................................................... 45 10.3.2 flange to heat si nk atta chment........................ 45 10.3.3 usage of a preform........................................... 46 10.3.4 lead to pcb attach ment .................................. 46 11. abbreviations..................................................... 47 12. references ......................................................... 47 13. legal information .............................................. 48 13.1 defini tions............................................................ 48 13.2 disclai mers .......................................................... 48 13.3 trademar ks ......................................................... 48 14. contents ............................................................. 49

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