1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f82048c may 2001 rev. 5 eco #14128 features n 2 meg x 8 bit cmos static n random access memory ? access times 70 thru 100ns ? data retention function (edi8f82048lp ) ? ttl compatible inputs and outputs ? fully static, no clocks n high density packaging ? 36 pin sip n single +5v (10%) supply operation description the edi8f82048c is a 16 megabit cmos static ram based on four 512k x 8 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. a low power version with data retention (edi8f82048lp) is also available. the edi8f82048c is offered in a 36 pin single-in-line package (sip), which provides a cost effective solution to very high packing density. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the edi8f82048c requires no clocks or refreshing for operation. fig. 1 pin configuration pin names 2 megabits x 8 static ram cmos, module block diagram a?-a20 address inputs e chip enable w write enable g output enable dq?-dq7 common data input/output vcc power (+5v10%) vss ground nc no connection dq 0-7 512k x 8 512k x 8 512k x 8 512k x 8 a 0-18 w g a 19-20 e dec 8f82048c blk dia 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 a19 vcc w dq2 dq3 dq0 a1 a2 a3 a4 vss dq5 a10 a11 a5 a13 a14 a20 e a15 a16 a12 a18 a6 dq1 vss a0 a7 a8 a9 dq7 dq4 dq6 a17 vcc g 8f82048c pin config
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f82048c may 2001 rev. 5 eco #14128 absolute maximum ratings* recommended dc operating conditions dc electrical characteristics capacitance (f=1.0mhz, vin=vcc or vss) ac test conditions * stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. truth table parameter sym min typ max units supply voltage vcc 4.5 5.0 5.5 v supply voltage vss 0 0 0 v input high voltage vih 2.2 -- 6.0 v input low voltage vil -0.3 -- 0.8 v note: for tehqz,tghqz and twlqz, cl = 5pf input pulse levels vss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load ttl, cl =100pf parameter sym conditions min typ* max units operating power icc1 w, e = vil, ii/o = 0ma, -- 105 ma supply current min cycle standby (ttl) power icc2 e 3 vih, vin vil -- 10 ma supply current vin 3 vih full standby power icc3 e 3 vcc-0.2v c -- 15 ma supply current (cmos) vin 3 vcc-0.2v or lp -- 400 a vin 0.2v input leakage current ili vin = 0v to vcc -- -- 20 a output leakage current ilo v i/o = 0v to vcc -- -- 20 a output high voltage voh ioh =-1.0ma 2.4 -- -- v output low voltage vol iol = 2.1ma -- -- 0.4 v *typical: ta = 25c, vcc = 5.0v g e w mode output power x h x standby high z icc2, icc3 h l h output deselect high z icc1 l l h read dout icc1 x l l write din icc1 parameter sym max unit address lines ci 32 pf data lines cd/q 40 pf chip enable and a17-a20 lines cc 32 pf these parameters are sampled, not 100% tested. voltage on any pin relative to vss -0.5v to 7.0v operating temperature ta (ambient) commercial 0c to +70c industrial -40c to +85c storage temperature -55c to +125c power dissipation 1 watt output current. 20 ma
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f82048c may 2001 rev. 5 eco #14128 ac characteristics read cycle fig. 2 read cycle 1 - w high, g, e low fig. 3 read cycle 2 - w high symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units read cycle time tavav trc 70 85 100 ns address access time tavqv taa 70 85 100 ns chip enable access time telqv tacs 70 85 100 ns chip enable to output in low z (1) telqx tclz 5 5 5 ns chip disable to output in high z (1) tehqz tchz 30 35 40 ns output hold from address change tavqx toh 3 3 3 ns output enable to output valid tglqv toe 40 45 50 ns output enable to output in low z (1) tglqx tolz 0 0 0 ns output disable to output in high z (1) tghqz tohz 30 35 40 ns note: parameter guaranteed, but not tested. address 1 address 2 tavav data 1 data 2 tavqv tavqx 8f82048c rd cyc1 a q e g q a tavqv telqv telqx tavav tglqx tglqv tghqz tehqz 8f82048c rd cyc2
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f82048c may 2001 rev. 5 eco #14128 fig. 4 write cycle 1 - w controlled ac characteristics write cycle note: parameter guaranteed, but not tested. write cycle symbol 70ns 85ns 100ns parameter jedec alt. min max min max min max units write cycle time tavav twc 70 85 100 ns chip enable to end of write telwh tcw 65 70 80 ns teleh tcw 65 70 80 ns address setup time tavwl tas 0 0 0 ns tavel tas 0 0 0 ns address valid to end of write tavwh taw 65 70 80 ns taveh taw 65 70 80 ns write pulse width twlwh twp 65 70 80 ns twleh twp 65 70 80 ns write recovery time twhax twr 0 0 0 ns tehax twr 0 0 0 ns data hold time twhdx tdh 0 0 0 ns tehdx tdh 0 0 0 ns write to output in high z (1) twlqz twhz 0 30 0 35 0 40 ns data to write time tdvwh tdw 30 35 40 ns tdveh tdw 30 35 40 ns output active from end of write (1) twhqx twlz 5 5 5 ns e a tavav telwh tavwh twlwh tavwl twhax w high z data valid twlqz twhqx tdvwh twhdx q d 8f82048c write cyc1
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f82048c may 2001 rev. 5 eco #14128 fig. 5 write cycle 2 - e controlled data retention characteristics fig. 6 data retention - e controlled characteristic sym test conditions vdd min typ max unit 70c 85c data retention voltage vdd 2 -- -- -- v data retention quiescent current iccdr e 3 vdd - 0.2v 2v -- 150 200 a vin 3 vdd - 0.2v 3v 250 400 a chip disable to data retention time(1) tcdr or vin 0.2v 0 -- -- -- ns operation recovery time (1) tr tavav* -- -- -- ns note: parameter guaranteed, but not tested. * read cycle time lp version only a tavel high z tavav 8f82048c write cyc2 teleh e taveh tehax w twleh tehdx tdveh q data valid d 8f82048c data reten vcc e tcdr tr data retention mode e vdd -0.2v 4.5v vdd 4.5v
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com edi8f82048c may 2001 rev. 5 eco #14128 package description 36 pin single-in-line package ordering information standard power low power speed package with data retention (ns) edi8f82048c70bsc edi8f82048lp70bsc 70 36 pin sip edi8f82048c85bsc edi8f82048lp85bsc 85 36 pin sip edi8f82048c100bsc edi8f82048lp100bsc 100 36 pin sip note: to order an industrial grade product substitute the letter c in the suffix with the letter i, (e.g., edi8f82048c70bsc becomes edi8f82048c70bsi). 4.005 max 3.500 0.003 0.100 (35 plcs) dimensions are in inches 0.855 max 0.144 max 8f82048c pkg
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