1mx32 bits pc133 sdram aimm based on 1mx32 sdram with lvttl, 2 banks & 4k refresh this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.1/apr.01 hym4v33100btwg series description the hynix hym4v33100btwg series are 1mx32bits synchronous dram modules. the modules are composed of one 1mx32bits cmos synchronous drams in 400mil 86pin tsop-ii package, on a 132pin glass-epoxy printed circuit board. two 0.22uf and one 0.1uf decoupling capacitors per each sdram are mounted on the pcb. the hyundai hym4v33100btwg series are agp in-line memory modules suitable for easy interchange and addition of 4mbytes memory. the hyundai hym4v33100btwg series are fully synchronous operation referenced to the positive edge of the clock . all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. features ? pc133/pc100mhz support ? 132pin sdram aimm ? 1.4? (35.56mm) height pcb with double sided com- ponents ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? data mask function by dqm ? sdram internal banks : two banks ? module bank : one physical bank ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4 or 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency internal bank ref. power sdram package plating HYM4V33100BTWG-75 133mhz 2 banks 4k normal tsop-ii gold
pc133 sdram aimm rev. 0.1/apr.01 2 hym4v33100btwg series pin description pin pin name description ck0, ck1 clock inputs the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh /cs chip select enables or disables all inputs except ck, cke and dqm ba sdram bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0 ~ a10 address row address : ra0 ~ ra10, column address : ca0 ~ ca7 auto-precharge flag : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details dqm0~dqm3 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq31 data input/output multiplexed data input / output pin vcc power supply (3.3v) power supply for internal circuits and input buffers v ss ground ground nc no connection no connection
pc133 sdram aimm rev. 0.1/apr.01 3 hym4v33100btwg series pin assignments front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 nc 2 typedet 67 nc 68 nc 3 nc 4 nc 69 nc 70 nc 5 gnd 6 nc 71 gnd 72 nc 7 nc 8 nc 73 nc 74 dq27 9 vcc 10 dqm3 75 vcc 76 dq28 11 nc 12 dq24 77 dq29 78 dq30 13 gnd 14 nc 79 gnd 80 nc 15 dq25 16 vcc 81 dq31 82 vcc 17 dq26 18 nc 83 dqm2 84 nc 19 gnd 20 we 85 gnd 86 dq23 21 fsel 22 keyway 87 dq22 88 keyway 23 keyway 24 keyway 89 keyway 90 keyway 25 keyway 26 tclk0 91 keyway 92 dq21 27 tclk1 28 vcc 93 dq20 94 vcc 29 cas 30 nc 95 dq19 96 dq18 31 gnd 32 nc 97 gnd 98 nc 33 ras 34 vddq 99 dq17 100 vddq a0 36 a9 101 dq16 102 dq15 35 37 gnd 38 a11 103 gnd 104 dq14 39 a8 40 vddq 105 dq13 106 vddq 41 a10 42 nc 107 dq12 108 nc 43 gnd 44 nc 109 gnd 110 nc 45 vcc 46 a7 111 vcc 112 dq11 47 cs 48 nc 113 vddq 114 nc 49 gnd 50 a6 115 gnd 116 nc 51 a1 52 vddq 117 dq10 118 vddq 53 a5 54 a2 119 dq9 120 dq8 55 gnd 56 a4 121 gnd 122 dqm1 57 a3 58 vddq 123 dq0 124 vddq 59 nc 60 dq5 125 nc 126 dq1 61 gnd 62 dq6 127 gnd 128 dq2 63 dq7 64 vddq 129 dq3 130 vddq 65 dqm0 66 nc 131 dq4 132 nc
pc133 sdram aimm rev. 0.1/apr.01 4 hym4v33100btwg series absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc outpu t load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 c sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
pc133 sdram aimm rev. 0.1/apr.01 5 hym4v33100btwg series capacitance (ta=25 c , f=1mhz) output load circuit parameter pin symbol -75 unit min max input capacitance ck0, ck1 c i1 5 10 pf cke0, cke1 c i2 5 10 pf /s0, /s1 c i3 10 15 pf a0~10, ba0 c i4 10 20 pf /ras, /cas, /we c i5 10 20 pf dqm0~dqm3 ci 6 5 10 pf data input / output capacitance dq0 ~ dq31 c i/o 5 15 pf vtt =1.4v rt=250 w 50 pf output 50 pf output dc output load circuit ac output load circuit
pc133 sdram aimm rev. 0.1/apr.01 6 hym4v33100btwg series dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 dc characteristics ii note : 1. i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3.HYM4V33100BTWG-75 parameter symbol min. max unit note input leakage current i li -8 8 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol - 0.4 v i ol = +4ma parameter symbol test condition speed unit note -75 operating current i dd1 burst length=1, one bank active t rc 3 t rc (min), i ol =0ma 220 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = min 2 ma i dd2ps cke v il (max), t ck = 2 precharge standby current in non power down mode i dd2n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks. all other pins 3 v dd -0.2v or 0.2v 40 ma i dd2ns cke 3 v ih (min), t ck = input signals are stable. 30 active standby current in power down mode i dd3p cke v il (max), t ck = min 60 ma i dd3ps cke v il (max), t ck = 60 active standby current in non power down mode i dd3n cke 3 v ih (min), cs 3 v ih (min), t ck = min input signals are changed one time during 2clks. all other pins 3 v dd -0.2v or 0.2v 100 ma i dd3ns cke 3 v ih (min), t ck = input signals are stable. 60 burst mode operating current i dd4 t ck 3 t ck (min), i ol =0ma all banks active cl=3 220 ma 1 auto refresh current i dd5 t rrc 3 t rrc (min), all banks active 220 ma 2 self refresh current i dd6 cke 0.2v 4 ma 3
pc133 sdram aimm rev. 0.1/apr.01 7 hym4v33100btwg series ac characteristics i (ac operating conditions unless otherwise noted) note : 1.assume tr / tf (input rise and fall time ) is 1ns if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 2.access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -75 unit note min max system clock cycle time cas latency = 3 tck3 7.5 1000 ns cas latency = 2 tck2 10 ns clock high pulse width tchw 2.5 - ns 1 clock low pulse width tclw 2.5 - ns 1 access time from clock cas latency = 3 tac3 - 5.4 ns 2 cas latency = 2 tac2 - 6 ns data-out hold time toh 2.7 - ns data-input setup time tds 1.5 - ns 1 data-input hold time tdh 0.8 - ns 1 address setup time tas 1.5 - ns 1 address hold time tah 0.8 - ns 1 cke setup time tcks 1.5 - ns 1 cke hold time tckh 0.8 - ns 1 command setup time tcs 1.5 - ns 1 command hold time tch 0.8 - ns 1 clk to data output in low-z time tolz 1 - ns clk to data output in high-z time cas latency = 3 tohz3 2.7 5.4 ns cas latency = 2 tohz2 3 6 ns
pc133 sdram aimm rev. 0.1/apr.01 8 hym4v33100btwg series ac characteristics ii note : 1. a new command can be given trrc after self refresh exit parameter symbol -75 unit note min max ras cycle time operation trc 65 - ns auto refresh trrc 65 - ns ras to cas delay trcd 20 - ns ras active time tras 45 100k ns ras precharge time trp 20 - ns ras to ras bank active delay trrd 15 - ns cas to cas delay tccd 1 - clk write command to data-in delay twtl 0 - clk data-in to precharge command tdpl 2 - clk data-in to active command tdal 5 - clk dqm to data-out hi-z tdqz 2 - clk dqm to data-in mask tdqm 0 - clk mrs to new command tmrd 2 - clk precharge to data output hi-z cas latency = 3 tproz3 3 - clk cas latency = 2 tproz2 2 - clk power down exit time tpde 1 - clk self refresh exit time tsre 1 - clk 1 refresh time tref - 64 ms
pc133 sdram aimm rev. 0.1/apr.01 9 hym4v33100btwg series device operating option table HYM4V33100BTWG-75 command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x h x x x x x l h h h bank active h x l l h h x ra v read h x l h l h x ca l v read with autoprecharge h write h x l h l l x ca l v write with autoprecharge h precharge all banks h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x self refresh 1 entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
pc133 sdram aimm rev. 0.1/apr.01 10 hym4v33100btwg series package demension ??3.175 x4 x
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