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? 1996 data sheet 8-bit single-chip microcontroller document no. u11598ej2v0ds00 (2nd edition) date published may 1997 n printed in japan m pd78p064b mos integrated circuit the mark shows major revised points. the information in this document is subject to change without notice. description the m pd78p064b is a product of m pd78064b subseries in 78k/0 series, in which the on-chip mask rom of the m pd78064b is replaced by one-time prom. as program write by user is possible, the m pd78p064b is best suited for evaluation, short-run and multiple-device production, and early rise upon system development. functions are described in detail in the following users manuals, which should be read when carrying out design work. m pd78064b subseries users manual: u10785e 78k/0 series users manual instruction: u12326e features ? pin compatible with mask rom products (except the v pp pin) ? internal prom: 32k bytes one-time programming possible (most suitable for small-scale production) ? internal high-speed ram: 1024 bytes ? lcd display ram: 40 4 bits ? operable in the same supply voltage as mask rom products (v dd = 2.0 to 6.0 v) ? corresponding to qtop tm microcomputers remarks 1. for the differences between prom products and mask rom products, refer to 1. differences between m pd78p064b and mask rom products . 2. qtop microcomputer is the general name for a total support as far as writing service, marking, screening, and verification after programming one-time prom internal signal-chip microcontroller offered by nec. ordering information part number package on-chip rom m pd78p064bgc-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) one-time prom m pd78p064bgc-8eu 100-pin plastic lqfp (fine pitch) (14 14 mm) one-time prom m pd78p064bgf-3ba 100-pin plastic qfp (14 20 mm) one-time prom caution the m pd78p064bgc has two types of package. (refer to 7. package drawings). for the package suppliable to your device, consult nec sales personnels.
2 m pd78p064b 78k/0 series development the following shows the products organized according to usage. the names in the parallelograms afe subseries names. 64-pin 64-pin 64-pin 64-pin 80-pin 80-pin emi-noise reduced version of the pd78054 uart and d/a converter were enhanced to the pd78014 and i/o was enhanced pd78054 pd78054y pd78058f pd78058fy pd780034 pd780024 pd780964 pd780924 pd780034y pd780024y m m m m m m m m m m 64-pin a/d converter of the pd780024 was enhanced serial i/o of the pd78018f was added and emi-noise was reduced. on-chip inverter control circuit and uart. emi-noise was reduced. m m m m a/d converter of the pd780924 was enhanced m pd78044f pd78044h 80-pin 80-pin pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y pd78098 80-pin pd78p0914 64-pin 78k/0 series an n-ch open drain i/o was added to the pd78044f, display output total: 34 basic subseries for driving fip, display output total: 34 lcd drive the sio of the pd78064 was enhanced, and rom, ram capacity increased emi-noise reduced version of the pd78064 basic subseries for driving lcds, on-chip uart iebus tm supported an iebus controller was added to the pd78054 lv on-chip pwm output, lv digital code decoder, and hsync counter m m m m m m m m m m m m m m m m pd78083 pd78002 pd78002y pd780001 pd78014 pd78014y pd78018f pd78018fy low-voltage (1.8 v) operation version of the pd78014, with larger selection of rom and ram capacities an a/d converter and 16-bit timer were added to the pd78002 an a/d converter was added to the pd78002 basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) m m m m m m m m 42/44-pin 64-pin 64-pin 64-pin 64-pin pd78014h m emi-noise reduced version of pd78018f m m pd780058 pd780058y note m m 80-pin serial i/o of the pd78054 was enhanced and emi-noise was reduced. 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. a timer was added to the pd78054 and external interface was enhanced rom-less version of the pd78078 pd78070a pd78070ay m pd78078 pd78078y pd780018 note pd780018y m m m m m m 100-pin serial i/o of the pd78078 was enhanced and the function is limited. m m 100-pin control pd78075b pd78075by m m emi-noise reduced version of pd78078 m inverter control pd780228 100-pin the i/o and fip c/d of the pd78044h were enhanced, display output total: 48 m m m pd780208 100-pin fip tm drive the i/o and fip c/d of the pd78044f were enhanced, display output total: 53 m m pd780208 m pd78098b emi-noise reduced version of the pd78098 m 80-pin m pd780805 100-pin meter control on-chip automobile meter driving controller/driver m pd780973 general purpose version of automobile meter driving controller of the pd780805 m 80-pin m note under planning
3 m pd78p064b the following lists the main functional differences between subseries products. function rom timer 8-bit 10-bit 8-bit serial interface i/o v dd min. external subseries name capacity 8-bit 16-bit watch wdt a/d a/d d/a value expansion control m pd78075b 32k-40k 4ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 88 1.8 v m pd78078 48k-60k m pd78070a C 61 2.7 v m pd780018 48k-60k C 2ch (time division 3-wire: 1ch) 88 m pd780058 24k-60k 2ch 2ch 3ch (time division uart: 1ch) 68 1.8 v m pd78058f 48k-60k 3ch (uart: 1ch) 69 2.7 v m pd78054 16k-60k 2.0 v m pd780034 8k-32k C 8ch C 3ch (uart: 1ch, 51 1.8 v m pd780024 8ch C time division 3-wire: 1ch) m pd78014h 2ch 53 1.8 v m pd78018f 8k-60k m pd78014 8k-32k 2.7 v m pd780001 8k C C 1ch 39 C m pd78002 8k-16k 1ch C 53 m pd78083 C 8ch 1ch (uart: 1ch) 33 1.8 v C inverter m pd780964 8k-32k 3ch note C 1ch C 8ch C 2ch (uart: 2ch) 47 2.7 v control m pd780924 8ch C fip m pd780208 32k-60k 2ch 1ch 1ch 1ch 8ch C C 2ch 74 2.7 v C drive m pd780228 48k-60k 3ch C C 1ch 72 4.5 v m pd78044h 32k-48k 2ch 1ch 1ch 68 2.7 v m pd78044f 16k-40k 2ch lcd m pd780308b 48k-60k 2ch 1ch 1ch 1ch 8ch C C 3ch (time division uart: 1ch) 57 2.0 v C drive m pd78064 32k 2ch (uart: 1ch) m pd78064 16k-32k iebus m pd78098b 40k-60k 2ch 1ch 1ch 1ch 8ch C 2ch 3ch (uart: 1ch) 69 2.7 v supported m pd78098 32k-60k meter m pd780973 24k-32k 3ch 1ch 1ch 1ch 5ch C C 2ch (uart: 1ch) 56 4.5 v C control m pd780805 40k-60k 2ch 8ch 39 2.7 v lv m pd78p0914 32k 6ch C C 1ch 8ch C C 2ch 54 4.5 v note 10-bit timer: 1 channel
4 m pd78p064b function description item function internal memory ? prom : 32 k bytes ? ram high-speed ram : 1024 bytes note lcd display ram : 40 4 bits general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) instruction when main system 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (when operating at 5.0 mhz) cycles clock is selected when subsystem 122 m s (when operating at 32.768 khz) clock is selected instruction set ? 16-bit operation ? multiplication/division (8 bits 8 bits, 16 bits ? 8 bits) ? bit manipulation (set, reset, test, boolean operation) ? bcd correction, etc. i/o ports total : 57 include segment signal ? cmos input : 2 output dual-function pin ? cmos input/output : 55 a/d converter ? 8-bit resolution 8 ch lcd controller/driver ? segment signal output : 40 max. ? common signal output : 4 max. ? bias : 1/2, 1/3, bias switchable serial interface ? 3-wire serial i/o/sbi/2-wire serial i/o mode selectable : 1 ch ? 3-wire serial i/o/uart mode selectable : 1 ch timer ? 16-bit timer/event counter : 1 ch ? 8-bit timer/event counter : 2 ch ? watch timer : 1 ch ? watchdog timer : 1 ch timer output 3 pins (14-bit pwm output enable 1 pin) clock output 19.5 khz, 39.1 khz, 78.1 khz, 156 khz, 313 khz, 625 khz, 1.25 mhz, 2.5 mhz, 5.0 mhz (when operating at main system clock 5.0 mhz), 32.768 khz (when operating at subsystem clock 32.768 khz) buzzer output 1.2 khz, 2.4 khz, 4.9 khz, 9.8 khz (when operating at main system clock 5.0 mhz) vectored maskable internal : 12, external : 6 interrupt sources non-maskable internal : 1 software 1 test input internal : 1, external : 1 supply voltage v dd = 2.0 to 6.0 v package ? 100-pin plastic (fine pitch) qfp (14 14 mm) ? 100-pin plastic lqfp (fine pitch) (14 14 mm) ? 100-pin plastic qfp (14 20 mm)
5 m pd78p064b pin configuration (top view) (1) normal operating mode ? 100-pin plastic qfp (fine pitch) (14 14 mm) m pd78p064bgc-7ea ? 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd78p064bgc-8eu cautions 1. connect v pp pin directly to v ss . 2. av dd pin shares the port power supply with that of the a/d converter. when using in applications where noise from inside the microcomputer has to be reduced, connect the av dd pin to a separate power supply, whose electrical potential is the same as that of v dd . 3. av ss pin shares the port gnd with that of the a/d converter. when using in applications where noise from inside the microcomputer has to be reduced, connect the av ss pin to a separate ground line. 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av dd av ref p100 p101 v ss p102 p103 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 v ss s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 p70/si2/r x d p27/sck0 p26/so0/sb1 p25/si0/sb0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/s34 p86/s33 p87/s32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 s23 s22 s21 s20 s19 p10/ani0 av ss p117 p116 p115 p114 p113 p112 p111 p110 p05/intp5 p04/intp4 p03/intp3 p02/intp2 p01/intp1/ti01 p00/intp0/ti00 reset xt2 xt1/p07 v dd x1 x2 v pp p72/sck2/asck p71/so2/t x d
6 m pd78p064b ? 100-pin plastic qfp (14 20 mm) m pd78p068bgf-3ba 100 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 v ss v lc2 v lc1 v lc0 bias com3 com2 com1 com0 p26/so0/sb1 p27/sck0 p70/si2/r x d p71/so2/t x d p72/sck2/asck v pp x2 x1 v dd xt1/p07 xt2 reset p00/intp0/ti00 p01/intp1/ti01 p02/intp2 p03/intp3 p04/intp4 p05/intp5 p110 p111 p112 p113 p114 p115 p116 p117 av ss p10/ani0 p11/ani1 p12/ani2 p13/ani3 p14/ani4 p15/ani5 p16/ani6 p17/ani7 av dd av ref p100 p101 v ss p102 p103 p30/to0 p31/to1 p32/to2 p33/ti1 p34/ti2 p35/pcl p36/buz p37 p25/si0/sb0 p80/s39 p81/s38 p82/s37 p83/s36 p84/s35 p85/p34 p86/p33 p87/p32 p90/s31 p91/s30 p92/s29 p93/s28 p94/s27 p95/s26 p96/s25 p97/s24 s23 s22 s21 cautions 1. connect v pp pin directly to v ss . 2. av dd pin shares the port power supply with that of the a/d converter. when using in applications where noise from inside the microcomputer has to be reduced, connect the av dd pin to a separate power supply, whose electrical potential is the same as that of v dd . 3. av ss pin shares the port gnd with that of the a/d converter. when using in applications where noise from inside the microcomputer has to be reduced, connect the av ss pin to a separate ground line.
7 m pd78p064b ani0-ani7 : analog input pcl : programmable clock asck : asynchronous serial clock reset : reset av dd : analog power supply rxd : receive data av ref : analog reference voltage s0-s39 : segment output av ss : analog ground sb0, sb1 : serial bus bias : lcd power supply bias control si0, si2 : serial input buz : buzzer clock so0, so2 : serial output com0-com3 : common output sck0, sck2 : serial clock intp0-intp5 : interrupt from peripherals ti00, ti01 : timer input p00-p05, p07 : port 0 ti1,ti2 : timer input p10-p17 : port 1 to0-to2 : timer output p25-p27 : port 2 txd : transmit data p30-p37 : port 3 v dd : power supply p70-p72 : port 7 v lc0 -v lc2 : lcd power supply p80-p87 : port 8 v ss : ground p90-p97 : port 9 v pp : programming power supply p100-p103 : port 10 x1, x2 : crystal (main system clock) p110-p117 : port 11 xt1, xt2 : crystal (subsystem clock)
8 m pd78p064b (2) prom programming mode ? 100-pin plastic qfp (fine pitch) (14 14 mm) m pd78p064bgc-7ea ? 100-pin plastic lqfp (fine pitch) (14 14 mm) m pd78p064bgc-8eu 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 v dd v ss v ss d0 d1 d2 d3 d4 d5 d6 d7 (l) a0 a1 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 a14 a15 ce oe pgm (l) a9 reset open (l) v dd (l) open v pp (l) (l) (l) (l) (l) (l) (l) (l) (l) cautions 1. (l) : individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset : set to low level. 4. open : no connection
9 m pd78p064b cautions 1. (l) : individually connect to v ss via a pull-down resistor. 2. v ss : connect to gnd. 3. reset : set to low level. 4. open : no connection a0 to a16 : address bus reset : reset ce : chip enable v dd : power supply d0 to d7 : data bus v pp : programming power supply oe : output enable v ss : ground pgm : program 100 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 v pp open (l) v dd (l) open reset a9 (l) pgm oe ce v dd v ss v ss d0 d1 d2 d3 d4 d5 d6 d7 (l) a0 a1 a2 a3 a4 a5 a6 a7 a8 a16 a10 a11 a12 a13 a14 a15 (l) (l) (l) (l) (l) (l) (l) (l) ? 100-pin plastic qfp (14 20 mm) m pd78p064bgf-3ba
10 m pd78p064b to0/p30 16-bit timer/ event counter ti00/intp0/p00 ti01/intp1/p01 to1/p31 8-bit timer/event counter 1 ti1/p33 to2/p32 8-bit timer/event counter 2 ti2/p34 watchdog timer watch timer si0/sb0/p25 serial interface 0 so0/sb1/p26 sck0/p27 si2/rxd/p70 serial interface 2 so2/txd/p71 sck2/asck/p72 a/d converter av ref ani0/p10- ani7/p17 interrupt control intp0/p00- intp5/p05 buzzer output buz/p36 clock output control pcl/p35 p00 port0 p01-p05 p07 port1 p10-p17 port11 p110-p117 port2 p25-p27 port3 p30-p37 port7 p70-p72 port8 p80-p87 port9 p90-p97 port10 p100-p103 lcd controller/ driver s0-s23 bias f lcd reset x1 x2 xt1/p07 xt2 78k/0 cpu core prom ram system control v dd v ss v pp s24/p97- s31/p90 s32/p97- s39/p80 com0-com3 v lc0 -v lc2 av dd av ss block diagram
11 m pd78p064b contents 1. differences between m pd78p064b and mask rom products ........................................... 12 2. pin function table ............................................................................................................................. 13 2.1 pins in normal operating mode ........................................................................................................... 13 2.2 pins in prom programming mode ......................................................................................................... 16 2.3 pin input/output circuits and recommended connection of unused pins ...................... 17 3. memory size switching register (ims) ....................................................................................... 20 4. prom programming ............................................................................................................................ 21 4.1 operating modes ......................................................................................................................................... 21 4.2 prom write procedure ............................................................................................................................ 23 4.3 prom read procedure .............................................................................................................................. 27 5. one-time prom products screening .......................................................................................... 28 6. electrical specifications ............................................................................................................ 29 7. package drawings ............................................................................................................................. 52 8. recommended soldering conditions ...................................................................................... 55 appendix a. development tools ........................................................................................................ 56 appendix b. related documents ....................................................................................................... 61
12 m pd78p064b 1. differences between m pd78p064b and mask rom products the m pd78p064b is a single-chip microcontroller with an on-chip one-time writable prom. it is possible to make all the functions exception prom specification, and mask option of lcd drive power supply dividing resistor, to the same as those of mask rom products by setting the memory size switching register (ims). difference between the prom product ( m pd78p064b) and mask rom product ( m pd78064b) are shown is table 1-1. table 1-1. differences between m pd78p064b and mask rom products item m pd78p064b mask rom products internal rom structure one-time prom mask rom ic pin no yes v pp pin yes no mask option of lcd drive power no yes supply dividing resistor electrical characteristics refer to data sheet for each product caution noise resistance and noise radiation are different in prom version and mask rom versions. if using a mask rom version instead of the prom version for processes between prototype development and full production, be sure to fully evaluate the cs of the mask rom version (not es). remark the internal prom becomes to 32k bytes and the internal high-speed ram becomes 1024 bytes by the reset input.
13 m pd78p064b 2. pin function table 2.1 pins in normal operating mode (1) port pins (1/2) pin name input/output function dual-function pin p00 input port 0 input only intp0/ti00 7-bit input/output p01 input/output port input/output is specifiable intp1/ti01 bit-wise. p02 when used as the input port, intp2 an on-chip pull-up resistor can p03 be used by software. intp3 p04 intp4 p05 intp5 p07 note 1 input input only xt1 p10 to p17 input/output port 1 ani0 to ani7 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, an on-chip pull-up resistor can be used by software. note 2 p25 input/output port 2 si0/sb0 3-bit input/output port p26 input/output is specifiable bit-wise. so0/sb1 when used as the input port, an on-chip pull-up resistor p27 can be used by software. sck0 p30 input/output port 3 to0 8-bit input/output port p31 input/output is specifiable bit-wise. to1 when used as the input port, an on-chip pull-up resistor p32 can be used by software. to2 p33 ti1 p34 ti2 p35 pcl p36 buz p37 p70 input/output port 7 si2/r x d 3-bit input/output port p71 input/output is specifiable bit-wise. so2/t x d when used as the input port, an on-chip pull-up resistor p72 can be used by software. sck2/asck notes 1. when p07/xt1 pins are used as the input ports, set processor clock control register (pcc) bit 6 (frc) to 1. (do not use the on-chip feedback resistor of the subsystem clock oscillation circuit.) 2. when p10/ani0 to p17/ani7 pins are used as the analog inputs for a/d converter, set port 1 to input mode. the on-chip pull-up resistor is automatically disabled. input input input input input input input after reset
14 m pd78p064b (1) port pins (2/2) pin name input/output function dual-function pin p80 to p87 input/output port 8 s39 to s32 8-bit input/output port input/output is specifiable bit-wise. when used as the input port, an on-chip pull-up resistor can be used by software. input/output port/segment signal output function specifiable in 2-bit units by lcd display control register (lcdc). p90 to p97 input/output port 9 s31 to s24 8-bit input/output port. input/output is specifiable bit-wise. when used as the input port, an on-chip pull-up resistor can be used by software. input/output port/segment signal output function specifiable in 2-bit units by lcd display control register. (lcdc). p100 to p103 input/output port 10 4-bit input/output port input/output is specifiable in bit-wise. when used as the input port, an on-chip pull-up resistor can be used by software. it is possible to directly drive led. p110 to p117 input/output port 11 8-bit input/output port input/output is specifiable in bit-wise. when used as the input port, an on-chip pull-up resistor can be used by software. falling edge detection possible. caution do not perform the following operation on the pins shared with port pins during a/d conversion operation; otherwise, the specifications of the total error during a/d conversion cannot be satisfied (except the pins shared with lcd segment output pins). (1) rewriting the output latch of an output pin used as a port pin (2) changing the output level of an output pin even when it is not used as a port pin after reset input input input input
15 m pd78p064b (2) pins other than port pins (1/2) pin name input/output function input input output input/output input/output input outpu input input output output output output output intp0 intp1 intp2 intp3 intp4 intp5 si0 si2 so0 so2 sb0 sb1 sck0 sck2 r x d t x d asck ti00 ti01 ti1 ti2 to0 to1 to2 pcl buz s0 to s23 s24 to s31 s32 to s39 com0 to com3 v lc0 to v lc2 bias external interrupt request input with specifiable valid edges (rising edge, falling edge, and both rising and falling edges). serial data input of the serial interface serial data output of the serial interface serial data input/output of the serial interface serial clock input/output of the serial interface serial data input for asynchronouse serial interface serial data output for asynchronous serial interface serial clock input for asynchronous serial interface external count clock input to the 16-bit timer (tm0). capture trigger signal input to the capture register (cr00). external count clock input to the 8-bit timer (tm1). external count clock input to the 8-bit timer (tm2). 16-bit timer (tm0) output (dual-function as 14-bit pwm output) 8-bit timer (tm1) output 8-bit timer (tm2) output clock output (for trimming main system clock and subsystem clock) buzzer output lcd controller/driver segment signal output lcd controller/driver common signal output lcd drive voltage lcd drive power supply after reset dual-function pin input input input input input input input input input input input output input output p00/ti00 p01/ti01 p02 p03 p04 p05 p25/sb0 p70/r x d p26/sbi p71/t x d p25/si0 p26/so0 p27 p72/asck p70/si2 p71/so2 p72/sck2 p00/intp0 p01/intp1 p33 p34 p30 p31 p32 p35 p36 p97-p90 p87-p80 input
16 m pd78p064b after reset input input (2) pins other than port pins (2/2) pin name input/output function dual-function pin ani0 to ani7 input analog input of a/d converter p10 to p17 av ref input reference voltage input of a/d converter av dd analog power supply of a/d converter (shared by power supply of port) av ss ground potential of a/d converter (shared by ground potential of port) reset input system reset input x1 input main system clock oscillation crystal connection x2 xt1 input subsystem clock oscillation crystal connection p07 xt2 v dd positive power supply (except port) v pp high-voltage applied during program write/verification connected directly to v ss in normal operating mode v ss ground potential (except port) cautions 1. av dd pin shares the port power supply with that of the a/d converter. when using in applications where noise from inside the microcomputer has to be reduced, connect the av dd pin to a separate power supply, whose electrical potential is the same as that of v dd . 2. av ss pin shares the port gnd with that of the a/d converter. when using in applications where noise from inside the microcomputer has to be reduced, connect the av ss pin to a separate ground line. 2.2 pins in prom programming mode pin name input/output function reset input prom programming mode setting when +5 v or +12.5 v is applied to the v pp pin and a low level signal is applied to the reset pin, this chip is set in the prom programming mode. v pp input prom programming mode setting and high-voltage applied during program write/ verification a0 to a16 input address bus d0 to d7 input/output data bus ce input prom enable input/program pulse input oe input read strobe input to prom pgm input program/program inhibit input in prom programing mode. v dd positive power supply v ss ground potential
17 m pd78p064b 2.3 pin input/output circuits and recommended connection of unused pins types of input/output circuits of the pins and recommended connection of unused pins are shown in table 2-1. for the configuration of each type of input/output circuit, refer to figure 2-1. table 2-1. type of input/output circuit of each pin input/output recommended connection pin name i/o circuit type when not used p00/intp0/ti00 2 input connect to v ss . p01/intp1/ti01 8-d i/o individually connect to v ss via a resistor p02/intp2 p03/intp3 p04/intp4 p05/intp5 p07/xt1 16 input connect to v dd . p10/ani0 to p17/ani7 11-c i/o individually connect to v dd or v ss via a resistor p25/si0/sb0 10-c p26/so0/sb1 p27/sck0 p30/to0 5-j p31/to1 p32/to2 p33/ti1 8-d p34/ti2 p35/pcl 5-j p36/buz p37 p70/si2/rxd 8-d p71/so2/txd 5-j p72/sck2/asck 8-d p80/s39 to p87/s32 17-e p90/s31 to p97/s24 p100 to p103 5-j p110 to p117 8-d individually connect to v dd via resistor s0 to s23 17-d output leave open com0 to com3 18-b v lc0 to v lc2 bias reset 2 input xt2 16 leave open av ref connect to v ss av dd connect to separate power supply whose electrical potential is the same as that of v dd . av ss connect to separate ground line whose electrical potential is the same as that of v ss . v pp connect directly to v ss
18 m pd78p064b pull-up enable data output disable p-ch in/out av dd av dd p-ch n-ch av ss pull-up enable data output disable input enable p-ch in/out av dd av dd p-ch n-ch av ss pull-up enable data output disable input enable p-ch in/out av dd av dd p-ch n-ch n-ch v ref + p-ch (threshold voltage) comparator av ss av ss pull-up enable data output disable p-ch in/out av dd av dd p-ch n-ch open drain av ss in figure 2-1. list of pin input/output circuits (1/2) type 2 type 5-j type 8-d type 11-c type 16 type 10-c schmitt-triggered input with hysteresis characteristic feedback cut-off p-ch xt1 xt2
19 m pd78p064b pull-up enable data output disable input enable p-ch in/out av dd av dd p-ch n-ch p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data av ss v ss out p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 seg data v ss figure 2-1. list of pin input/output circuits (2/2) type 17-d type 17-e type 18-b p-ch n-ch p-ch n-ch p-ch n-ch v lc0 v lc1 v lc2 com data n-ch p-ch out v ss
20 m pd78p064b 3. memory size switching register (ims) this is a register to disable use of part of internal memories by software. by setting this memory size switching register (ims), it is possible to get the same memory mapping as that of mask rom product having different internal memories (rom, ram). the ims is set up by the 8-bit memory manipulating instruction. c8h will result by the reset input. figure 3-1. memory size switching register format 7654321 0 symbol address r/w after reset ram2 ram1 ram0 0 rom3 rom2 rom1 rom0 ims fff0h c8h selection of internal rom capacity r/w rom3 rom2 rom1 rom0 1 0 0 0 32k bytes other than above setting prohibited selection of internal high-speed ram capacity 1 1 0 1024 bytes other than above setting prohibited ram2 ram1 ram0 table 3-1 shows the set values of ims which makes the memory map the same as that of the various mask rom products. table 3-1. memory size switching register setting values target mask rom product ims setting value m pd78064b c8h
21 m pd78p064b 4. prom programming the m pd78p064b has an on-chip 32k-byte prom as a program memory. for programming, set the prom programming mode by the v pp and reset pins. for processing unused pins, refer to pin configuration (2) prom programming mode . caution when writing in a program, use locations 0000h-7fffh. (specify the last address as 7fffh). you cannot write in using a prom programmer that cannot specify the addresses to write. 4.1 operating modes when +5 v or +12.5 v is applied to the v pp pin and a low level signal is applied to the reset pin, the prom programming mode is set. this mode will become the operating mode as shown in table 4-1 when the ce, oe and pgm pins are set as shown. further, when the read mode is set, it is possible to read the contents of the prom. table 4-1. operating modes of prom programming pin reset v pp v dd ce oe pgm d0 to d7 operating mode page data latch l +12.5 v +6.5 v h l h data input page write h h l high-impedance byte write l h l data input program verify l l h data output program inhibit h h high-impedance ll read +5 v +5 v l l h data output output disable l h high-impedance standby h high-impedance : l or h
22 m pd78p064b (1) read mode read mode is set if ce = l, oe = l is set. (2) output disable mode data output becomes high-impedance, and is in the output disable mode, of oe = h is set. therefore, it allows data to be read from any device by controlling the oe pin, if multiple m pd78p064bs are connected to the data bus. (3) standby mode standby mode is set if ce = h is set. in this mode, data outputs become high-impedance irrespective of the oe status. (4) page data latch mode page data latch mode is set if ce = h, pgm = h, oe = l are set at the beginning of page write mode. in this mode, 1 page 4-byte data is latched in an internal address/data latch circuit. (5) page write mode after 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1 ms program pulse (active low) to the pgm pin with ce = h, oe = h. then, program verification can be performed, if ce = l, oe = l are set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (6) byte write mode byte write is executed when a 0.1 ms program pulse (active low) is applied to the pgm pin with ce = l, oe = h. then, program verification can be performed if oe = l is set. if programming is not performed by a one-time program pulse, x (x 10) write and verification operations should be executed repeatedly. (7) program verify mode program verify mode is set if ce = l, pgm = h, oe = l are set. in this mode, check if a write operation is performed correctly, after the write. (8) program inhibit mode program inhibit mode is used when the oe pin, v pp pin and d0 to d7 pins of multiple m pd78p064bs are connected in parallel and a write is performed to one of those devices. when a write operation is performed, the page write mode or byte write mode described above is used. at this time, a write is not performed to a device which has the pgm pin driven high.
23 m pd78p064b address = g v dd = 6.5 v, v pp = 12.5 v x = 0 latch address = address + 1 latch address = address + 1 latch address = address + 1 latch x = x + 1 x = 10 ? address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 0.1 ms program pulse verify 4 bytes verify all bytes start write end faulty product 4.2 prom write procedure figure 4-1. page program mode flow chart g = start address n = program last address
24 m pd78p064b a2 to a16 a0, a1 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input figure 4-2. page program mode timing
25 m pd78p064b address = g v dd = 6.5 v, v pp = 12.5 v x = 0 x = x + 1 address = n ? v dd = 4.5 to 5.5 v, v pp = v dd yes no fail fail all pass pass no yes pass address = address + 1 x = 10 ? 0.1 ms program pulse verify verify all bytes start write end faulty product figure 4-3. byte program mode flow chart g = start address n = program last address
26 m pd78p064b a0 to a16 d0 to d7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il data output data input program program verify figure 4-4. byte program mode timing cautions 1. v dd should be applied before v pp and cut after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. reliability may be adversely affected of removal/reinsertion is performed while +12.5 v is being applied to v pp .
27 m pd78p064b a0 to a16 d0 to d7 ce (input) oe (input) hi-z hi-z data output address input 4.3 prom read procedure the contents of prom are readable to the external data bus (d0 to d7) according to the read procedure shown below. (1) fix the reset pin at low level, supply +5 v to the v pp pin, and process all other unused pins as shown in pin configuration (2) prom programming mode . (2) supply +5 v to the v dd and v pp pins. (3) input address of read data into the a0 to a16 pins. (4) read mode (5) output data to d0 to d7 pins. the timings of the above steps (2) to (5) are shown in figure 4-5. figure 4-5. prom read timings
28 m pd78p064b 5. one-time prom products screening the one-time prom product ( m pd78p064bgc-7ea, m pd78p064bgc-8eu, m pd78p064bgf- 3ba) can not be tested completely by nec before it is shipped, because of its structure. it is recommended to perform screening to verify prom after writing necessary data and performing high-temperature storage under the condition below. storage temperature storage time 125 c 24 hours at present, a fee is charged by nec for one-time prom after-programming writing, marking, screening, and verify service for the qtop microcomputer. for details, contact your sales representative.
29 m pd78p064b 6. electrical specifications absolute maximum ratings (t a = 25 c) v dd v pp av dd av ref av ss v i v i2 v o v an i oh i ol note parameter symbol test conditions rating unit v v v v v v v v v ma ma ma ma ma ma c c supply voltage input voltage output voltage analog input voltage output current, high p00-p05, p07, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, p110-p117 a9 (prom programming mode) p10-p17 analog input pin 1 pin total for p01-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, p110-p117 C0.3 to +7.0 C0.3 to +13.5 C0.3 to v dd +0.3 C0.3 to v dd +0.3 C0.3 to +0.3 C0.3 to v dd +0.3 C0.3 to +13.5 C0.3 to v dd +0.3 av ss C0.3 to av ref +0.3 C10 C15 30 15 100 70 C40 to +85 C65 to +150 peak value r.m.s. value peak value r.m.s. value 1 pin total for p01-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, p110-p117 operating ambient temperature storage temperature t a t stg note the r.m.s. value should be calculated as follows: [r.m.s. value] = [peak value] duty caution the product quality may be damaged even if a value of only one of the above parameters exceeds the absolute maximum rating or any value exceeds the absolute maximum rating for an instant. that is, the absolute maximum rating is a rating value which may cause a product to be damaged physically. the absolute maximum rating values must therefore be observed in using the product. remark unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. capacitance (t a = 25 c, v dd = v ss = 0 v) ? output current, low input capacitance output capacitance i/o capacitance pf pf pf parameter symbol test conditions min. typ. max. unit 15 15 15 c in c out c io f = 1 mhz unmeasured pins returned to 0 v.
30 m pd78p064b x1 x2 v pp c1 c2 x1 x2 v pp c1 c2 main system clock oscillation circuit characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) unit mhz ms mhz ms mhz ns max. 5 4 5 10 30 5.0 500 recommended circuit parameter oscillator frequency (f x ) note 1 oscillation stabilization time note 2 oscillator frequency (f x ) note 1 oscillation stabilization time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) min. 1 1 1.0 85 resonator ceramic resonator crystal resonator external clock notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop mode release. cautions 1. when using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. if the main system clock oscillation circuit is operated by the subsystem clock when the main system clock is stopped, reswitching to the main system clock should be performed after the stable oscillation time has been obtained by the program. typ. m pd74hcu04 test conditions v dd = oscillator voltage range after v dd reaches oscil- lator voltage range min. v dd = 4.5 to 6.0 v x1 x2
31 m pd78p064b xt1 xt2 r1 xt2 xt1 v pp c4 c3 subsystem clock oscillator characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. indicates only oscillation circuit characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after v dd has reached the minimum oscillation voltage range. cautions 1. when using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. ? wiring should be as short as possible. ? wiring should not cross other signal lines. ? wiring should not be placed close to a varying high current. ? the potential of the oscillator capacitor ground should be the same as v ss . ? do not ground it to the ground pattern in which a high current flows. ? do not fetch a signal from the oscillator. 2. the subsystem clock oscillation circuit is designed as a low amplification circuit to provide low consumption current, causing misoperation to noise more frequently than the main system clock oscillation circuit. special care should therefore be taken to wiring method when the subsystem clock is used. v dd = 4.5 to 6.0 v crystal resonator external clock oscillator frequency (f xt ) note 1 oscillation stabilization time note 2 xt1 input frequency (f xt ) note 1 xt1 input high-/low-level width (t xth /t xtl ) 35 2 10 100 15 32.768 1.2 32 32 5 khz s khz m s resonator recommended circuit parameter test conditions min. typ. max. unit
32 m pd78p064b main system clock: ceramic resonator (t a = C40 to +85 c) murata mfg. co., ltd. recommended oscillation circuit constant product name frequency (mhz) matsushita electronics components co., ltd. kyocera corporation oscillator voltage range recommended circuit constant manufaturer remarks c1 (pf) c2 (pf) min. (v) max. (v) csa5.00mg 5.00 30 30 2.7 6.0 cst5.00mgw 5.00 built-in built-in 2.7 6.0 ef0gc5004a4 5.00 built-in built-in 2.7 6.0 lead type ef0ec5004a4 5.00 built-in built-in 2.7 6.0 round lead type ef0en5004a4 5.00 33 33 2.7 6.0 lead type ef0s5004b4 5.00 built-in built-in 2.7 6.0 chip type kbr-5.0msa 5.00 33 33 2.7 6.0 lead type pbrc5.00a 5.00 33 33 2.7 6.0 chip type kbr-5.0mks 5.00 built-in built-in 2.7 6.0 lead type kbr-5.0mws 5.00 built-in built-in 2.7 6.0 chip type caution the oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation but do not guarantee accuracy of the oscillation frequency. if the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. for this, it is necessary to directly contact the manufacturer of the resonator being used.
33 m pd78p064b dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) 0.7 v dd v dd v 0.8 v dd v dd v 0.8 v dd v dd v 0.85 v dd v dd v v dd C0.5 v dd v v dd C0.2 v dd v 0.8 v dd v dd v 0.9 v dd v dd v 0.9 v dd v dd v 0 0.3 v dd v 0 0.2 v dd v 0 0.2 v dd v 0 0.15 v dd v 0 0.4 v 0 0.2 v 0 0.2 v dd v 0 0.1 v dd v 0 0.1 v dd v v dd C1.0 v dd v v dd C0.5 v dd v 0.4 2.0 v 0.4 v 0.2 v dd v 0.5 v parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v 4.5 v dd 6.0 v 2.7 v dd < 4.5 v 2.0 v dd < 2.7 v note v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v v dd = 2.7 to 6.0 v 4.5 v dd 6.0 v 2.7 v dd < 4.5 v 2.0 v dd < 2.7 v note input voltage, low v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v il4 v oh v ol1 v ol2 v ol3 output voltage, high output voltage, low note when used as p07, the inverse phase of p07 should be input to xt2 using an inverter. remark unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. p10-p17, p30-p32, p35-p37, p80-p87, p90-p97, p100-p103 p00-p05, p25-p27, p33, p34, p70-p72, p110-p117, reset x1, x2 xt1/p07, xt2 p10-p17, p30-p32, p35-p37, p80-p87, p90-p97, p100-p103 p00-p05, p25-p27, p33, p34, p70-p72, p110-p117, reset x1, x2 xt1/p07, xt2 v dd = 4.5 to 6.0 v i oh = C1 ma i oh = C100 m a p100-p103 p01-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p110-p117 sb0, sb1, sck0 i ol = 400 m a input voltage, high v dd = 4.5 to 6.0 v, i ol = 15 ma v dd = 4.5 to 6.0 v, i ol = 1.6 ma v dd = 4.5 to 6.0 v, open-drain, pulled up (r = 1 k w )
34 m pd78p064b symbol test conditions min. typ. max. unit p00-p05, p10-p17, p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, 3 m a p110-p117 i lih2 x1, x2, xt1/p07, xt2 20 m a p00-p05, p10-p17, p25-p27, i lil1 p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, C3 m a p110-p117 i lih2 x1, x2, xt1/p07, xt2 C20 m a i loh v out = v dd 3 m a i lol v out = 0 v C3 m a v in = 0 v, p01-p05, p10-p17, r p25-p27, p30-p37, p70-p72, p80-p87, p90-p97, p100-p103, p110-p117 v dd = 5.0 v 10 % note 5 5.0 15.0 ma v dd = 3.0 v 10 % note 6 0.7 2.1 ma v dd = 2.2 v 10 % note 6 0.4 1.2 ma v dd = 5.0 v 10 % note 5 9.0 27.0 ma v dd = 3.0 v 10 % note 6 1.0 3.0 ma v dd = 5.0 v 10 % 1.4 4.2 ma v dd = 3.0 v 10 % 500 1500 m a v dd = 2.2 v 10 % 280 840 m a v dd = 5.0 v 10 % 1.6 4.8 ma v dd = 3.0 v 10 % 650 1950 m a v dd = 5.0 v 10 % 135 270 m a v dd = 3.0 v 10 % 95 190 m a v dd = 2.2 v 10 % 70 140 m a v dd = 5.0 v 10 % 25 55 m a v dd = 3.0 v 10 % 5 15 m a v dd = 2.2 v 10 % 2.5 12.5 m a v dd = 5.0 v 10 % 1 30 m a v dd = 3.0 v 10 % 0.5 10 m a v dd = 2.2 v 10 % 0.3 10 m a v dd = 5.0 v 10 % 0.1 30 m a v dd = 3.0 v 10 % 0.05 10 m a v dd = 2.2 v 10 % 0.05 10 m a dc characteristics (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter v in = v dd v in = 0 v i lih1 2.7 v v dd < 4.5 v 20 500 k w 4.5 v v dd 6.0 v 15 40 90 k w 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note 2 halt mode 5.00 mhz, crystal oscillation (f xx = 2.5 mhz) note 2 operating mode 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note 3 operating mode i dd1 5.00 mhz, crystal oscillation (f xx = 5.0 mhz) note 3 halt mode 32.768 khz, crystal oscillation operating mode note 4 32.768 khz, crystal oscillation halt mode note 4 i dd3 i dd2 i dd4 i dd6 i dd5 xt1 = v dd stop mode when feedback resistor is connected xt1 = v dd stop mode when feedback resistor is disconnected notes 1. current flowing v dd and av dd pin. not including a/d converter, on-chip pull-up resistors or lcd dividing resistors. 2. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 3. main system clock f xx = f x operation (when osms is set to 01h) 4. when the main system clock is stopped. 5. high-speed mode operation (when processor clock control register (pcc) is set to 00h) 6. low-speed mode operation (when pcc is set to 04h) remark unless specified otherwise, the characteristics of dual-function pins are the same as the those of port pins. input leakage current, high input leakage current, low output leakage current, high output leakage current, low software pull-up resistor supply current note 1
35 m pd78p064b symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.5 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage deviation note (common) lcd output voltage deviation note (segment) dc characteristics (t a = C10 to +85 c) symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.0 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage deviation note (common) lcd output voltage deviation note (segment) (1) static display mode (v dd = 2.0 to 6.0 v) v odc i o = 5 m a0 0.2 v v ods i o = 1 m a0 0.2 v 2.0 v v lcd v dd v lcd0 = v lcd note the voltage deviation is the difference from the out voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). (2) 1/3 bias method (v dd = 2.5 to 6.0 v) note the voltage deviation is the difference from the out voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). symbol test conditions min. typ. max. unit lcd drive voltage v lcd 2.7 v dd v lcd dividing resistor r lcd 60 100 150 k w lcd output voltage deviation note (common) lcd output voltage deviation note (segment) (3) 1/2 bias method (v dd = 2.7 to 6.0 v) note the voltage deviation is the difference from the out voltage corresponding to the ideal value of the segment and common outputs (v lcdn ; n = 0, 1, 2). v odc i o = 5 m a0 0.2 v v ods i o = 1 m a0 0.2 v 2.5 v v lcd v dd v lcd0 = v lcd v lcd1 = v lcd v lcd2 = v lcd 2 3 1 3 1 2 v ods i o = 1 m a0 0.2 v v odc i o = 5 m a0 0.2 v parameter parameter parameter 2.7 v v lcd v dd v lcd0 = v lcd v lcd1 = v lcd v lcd2 = v lcd1
36 m pd78p064b ac characteristics (1) basic operation (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) parameter notes 1. main system clock f xx = f x /2 operation (when oscillation mode selection register (osms) is set to 00h) 2. main system clock f xx = f x operation (when osms is set to 01h) 3. this is the value when the external clock is used. the value is 114 m s (min.) when the crystal resonator is used. 4. in combination with bits 0 (scs0) and 1 (scs1) of sampling clock select register (scs), selection of f sam is possible between f xx /2 n+1 , f xx /32, f xx /64 and f xx /128 (when n = 0 to 4). symbol test conditions min. typ. max. unit t cy operating on main system clock v dd = 2.7 to 6.0 v 0.8 64 m s (f xx = 2.5 mhz) note 1 2.2 64 m s operating on main system clock 4.5 v dd 6.0 v 0.4 32 m s (f xx = 5.0 mhz) note 2 2.7 v dd < 4.5 v 0.8 32 m s operating on subsystem clock 40 note 3 122 125 m s t tih00 , 4.5 v v dd 6.0 v 2/f sam +0.1 note 4 m s t til00 2.7 v v dd < 4.5 v 2/f sam +0.2 note 4 m s 2.0 v v dd < 2.7 v 2/f sam +0.5 note 4 m s t tih01 ,v dd = 2.7 to 6.0 v 10 m s t til01 20 m s f ti v dd = 4.5 to 6.0 v 0 4 mhz 0 275 khz t tih, v dd = 4.5 to 6.0 v 100 ns t til 1.8 m s t inth , intp0 8/f sam note 4 m s t intl intp1-intp5, p110-p117 v dd = 2.7 to 6.0 v 10 m s 20 m s t rst v dd = 2.7 to 6.0 v 10 m s 20 m s cycle time (min. instruction execution time) ti input frequency reset low level width ti00 input high/ low-level width ti01 input high/ low-level width ti1, ti2 input high/low-level width interrupt input high/low-level width
37 m pd78p064b (2) serial interface (t a = C40 to +85 c, v dd = 2.0 to 6.0 v) (a) serial interface channel 0 (i) 3-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy1 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh1 ,v dd = 4.5 to 6.0 v t kcy1 /2C50 ns t kl1 t kcy1 /2C100 ns 4.5 v v dd 6.0 v 100 ns t sik1 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi1 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck0, so0 output line. sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 60 10 2.0 1.0 1 023456 0.8 0.4 60 10 2.0 1.0 1 023456 0.8 0.4 supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range supply voltage v dd [v] cycle time t cy [ s] m guaranteed operation range 32 t cy vs v dd (at main system clock f xx = f x /2 operation) t cy vs v dd (at main system clock f xx = f x operation)
38 m pd78p064b (iii) sbi mode (sck0...internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v t kcy3 /2C50 ns t kcy3 /2C150 ns v dd = 4.5 to 6.0 v 100 ns 300 ns r = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns c = 100 pf note 0 1000 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 ns t kcy3 t kh3 , t kl3 t sik3 t ksi3 t kso3 t ksb t sbk t sbh t sbl t kcy3 /2 ns note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. sck0 cycle time sck0 high/low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 - sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width t kh2 , t kl2 note c is the load capacitance of so0 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy2 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik2 100 ns t ksi2 400 ns t kso2 c = 100 pf note 300 ns 1000 ns t r2 , t f2 sck0 cycle time sck0 high/low-level width si0 setup time (to sck0 - ) si0 hold time (from sck0 - ) so0 output delay time from sck0 sck0 rise, fall time (ii) 3-wire serial i/o mode (sck0...external clock input)
39 m pd78p064b (v) 2-wire serial i/o mode (sck0... internal clock output) parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v 1600 ns 3200 ns v dd = 2.7 to 6.0 v t kcy5 /2C160 ns t kcy5 /2C190 ns v dd = 4.5 to 6.0 v t kcy5 /2C50 ns t kcy5 /2C100 ns 4.5 v v dd 6.0 v 300 ns 2.7 v v dd < 4.5 v 350 ns 400 ns 600 ns 300 ns r = 1 k w , c = 100 pf note note r and c are the load resistance and load capacitance of the sck0, sb0 and sb1 output line. t kcy5 t ksi5 t kso5 t sik5 t kh5 t kl5 sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 (iv) sbi mode (sck0...external clock input) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns v dd = 4.5 to 6.0 v 100 ns 300 ns r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns c = 100 pf note 0 1000 ns t kcy4 ns t kcy4 ns t kcy4 ns t kcy4 ns 1000 ns t kcy4 /2 ns note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. t kcy4 t kh4 , t kl4 t sik4 t ksi4 t kso4 t ksb t sbk t sbh t sbl t r4 , t f4 sck0 cycle time sck0 high/low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sb0, sb1 from sck0 - sck0 from sb0, sb1 sb0, sb1 high-level width sb0, sb1 low-level width sck0 rise, fall time
40 m pd78p064b (b) serial interface channel 2 (i) 3-wire serial i/o mode (sck2... internal clock output) parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy7 2.7 v v dd < 4.5 v 1600 ns 3200 ns t kh7 ,v dd = 4.5 to 6.0 v t kcy7 /2C50 ns t kl7 t kcy7 /2C100 ns 4.5 v v dd 6.0 v 100 ns t sik7 2.7 v v dd < 4.5 v 150 ns 300 ns t ksi7 400 ns t kso1 c = 100 pf note 300 ns note c is the load capacitance of sck2, so2 output line. sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 - ) si2 hold time (from sck2 - ) so2 output delay time from sck2 (vi) 2-wire serial i/o mode (sck0... external clock input) note r and c are the load resistance and load capacitance of the sb0 and sb1 output line. parameter symbol test conditions min. typ. max. unit v dd = 2.7 to 6.0 v 1600 ns 3200 ns v dd = 2.7 to 6.0 v 650 ns 1300 ns v dd = 2.7 to 6.0 v 800 ns 1600 ns 100 ns t kcy6 /2 ns r = 1 k w ,v dd = 4.5 to 6.0 v 0 300 ns c = 100 pf note 0 500 ns 1000 ns t kcy6 t kh6 t kl6 t sik6 t ksi6 t kso6 sck0 cycle time sck0 high-level width sck0 low-level width sb0, sb1 setup time (to sck0 - ) sb0, sb1 hold time (from sck0 - ) sb0, sb1 output delay time from sck0 sck0 rise, fall time t r6 , t f6
41 m pd78p064b asck cycle time asck high/low-level width transfer rate asck rise, fall time parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy9 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns 4.5 v v dd 6.0 v 39063 bps 2.7 v v dd < 4.5 v 19531 bps 9766 bps 1000 ns parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 78125 bps 2.7 v v dd < 4.5 v 39063 bps 19531 bps transfer rate (iii) uart mode (dedicated baud rate generator output) (iv) uart mode (external clock input) t kh9 , t kl9 t r9 , t f9 note c is the load capacitance of so2 output line. parameter symbol test conditions min. typ. max. unit 4.5 v v dd 6.0 v 800 ns t kcy8 2.7 v v dd < 4.5 v 1600 ns 3200 ns 4.5 v v dd 6.0 v 400 ns 2.7 v v dd < 4.5 v 800 ns 1600 ns t sik8 100 ns t ksi8 400 ns t kso8 c = 100 pf note 300 ns 1000 ns t r8 , t f8 sck2 cycle time sck2 high/low-level width si2 setup time (to sck2 - ) si2 hold time (from sck2 - ) so2 output delay time from sck2 sck2 rise, fall time t kh8 , t kl8 (ii) 3-wire serial i/o mode (sck2...external clock input)
42 m pd78p064b t xl t xh 1/f x v ih3 (min.) v il3 (max.) t xtl t xth 1/f xt v ih4 (min.) v il4 (max.) x1 input xt1 input 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points ac timing test point (excluding x1, xt1 input) clock timing ti timing ti00, ti01 t til00 , t til01 t tih00 , t tih01 t til t tih 1/f ti ti1, ti2
43 m pd78p064b t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t ksb t sbk t ksi3.4 t kso3, 4 sb0, sb1 t r4 t f4 t sik3, 4 t kcy3, 4 t kl3, 4 t kh3, 4 sck0 t sbl t sbh t ksb t sbk t ksi3, 4 t kso3, 4 sb0, sb1 t r4 t f4 t kcym t klm t khm sck0, sck2 si0, si2 so0, so2 t sikm t ksim t ksom input data output data t rn t fn m = 1, 2, 7, 8 n = 2, 8 serial transfer timing 3-wire serial i/o mode: sbi mode (bus release signal transfer): sbi mode (command signal transfer):
44 m pd78p064b asck t kcy9 t kl9 t kh9 t r9 t f9 2-wire serial i/o mode: uart mode: a/d converter (t a = C40 to +85 c, av dd = v dd = 4.5 to 6.0 v, av ss = v ss = 0 v) parameter symbol test conditions min. typ. max. unit 8 8 8 bit 4.5 v av ref av dd 2.0 % t conv 19.1 200 m s t samp 12/f xx m s v ian av ss av ref v av ref 2.0 av dd v r airef 414 k w resolution overall error note conversion time sampling time analog input voltage reference voltage av ref -av ss resistance note quantization error ( 1/2 lsb) is not included. this is expressed in proportion to the full-scale value. t kso5, 6 t sik5, 6 t kcy5.6 t kl5, 6 t kh5, 6 sck0 t ksi5, 6 sb0, sb1 t r6 t f6
45 m pd78p064b t srel t wait v dd stop instruction execution stop mode data retention mode halt mode operating mode standby release signal (interrupt request) v dddr t srel t wait v dd reset stop mode data retention mode internal reset operation halt mode operating mode v dddr stop instruction execution data retention supply voltage data retention v dddr = 1.8 v power supply i dddr subsystem clock stop and 0.1 10 m a current feed-back resistor disconnected release signal set time t srel 0 m s oscillation release by reset 2 17 /f x ms stabilization t wait wait time release by interrupt note ms data memory stop mode low supply voltage data retention characteristics (t a = C40 to +85 c) parameter symbol test conditions min. typ. max. unit v dddr 1.8 6.0 v note in combination with bits 0 to 2 (osts0 to osts2) of oscillation stabilization time select register (osts), selection of 2 12 /f xx and 2 14 /f xx to 2 17 /f xx is possible. data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt signal)
46 m pd78p064b t rsl reset t intl t inth intp0?ntp5 interrupt input timing reset input timing
47 m pd78p064b parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v v oh1 v oh1 i oh = C1 ma v dd C1.0 v v oh2 v oh2 i oh = C100 m av dd C0.5 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a output leakage current i lo i lo 0 v out v dd , oe = v ih C10 +10 m a v pp supply voltage v pp v pp v dd C0.6 v dd v dd +0.6 v v dd supply voltage v dd v cc 4.5 5.0 5.5 v v pp supply current i pp i pp v pp = v dd 100 m a v dd supply current i dd i cca1 ce = v il , v in = v ih 50 ma prom programming characteristics dc characteristics (1) prom write mode (t a = 25 5 ?c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note test conditions min. typ. max. unit input voltage, high v ih v ih 0.7 v dd v dd v input voltage, low v il v il 0 0.3 v dd v output voltage, high v oh v oh i oh = C1 ma v dd C1.0 v output voltage, low v ol v ol i ol = 1.6 ma 0.4 v input leakage current i li i li 0 v in v dd C10 +10 m a v pp supply voltage v pp v pp 12.2 12.5 12.8 v v dd supply voltage v dd v cc 6.25 6.5 6.75 v v pp supply current i pp i pp pgm = v il 50 ma v dd supply current i dd i cc 50 ma note symbol corresponding to the m pd27c1001a. (2) prom read mode (t a = 25 5 ?c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) note symbol corresponding to the m pd27c1001a. output voltage, high
48 m pd78p064b parameter symbol symbol note test conditions min. typ. max. unit address setup time (to pgm ) t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to pgm ) t ces t ces 2 m s input data setup time (to pgm ) t ds t ds 2 m s address hold time (from oe -) t ah t ah 2 m s nput data hold time (from pgm -) t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to pgm ) t vps t vps 1.0 ms v dd setup time (to pgm ) t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe hold time t oeh 2 m s ac characteristics (1) prom write mode (a) page program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) parameter symbol symbol note test conditions min. typ. max. unit address setup time (to oe ) t as t as 2 m s oe setup time t oes t oes 2 m s ce setup time (to oe ) t ces t ces 2 m s input data setup time (to oe ) t ds t ds 2 m s t ah t ah 2 m s address hold time (from oe -) t ahl t ahl 2 m s t ahv t ahv 0 m s input data hold time (from oe -) t dh t dh 2 m s data output float delay time from oe - t df t df 0 250 ns v pp setup time (to oe ) t vps t vps 1.0 ms v dd setup time (to oe ) t vds t vcs 1.0 ms program pulse width t pw t pw 0.095 0.1 0.105 ms valid data delay time from oe t oe t oe 1 m s oe pulse width during data latching t lw t lw 1 m s pgm setup time t pgms t pgms 2 m s ce hold time t ceh t ceh 2 m s oe hold time t oeh t oeh 2 m s note corresponding m pd27c1001a symbol (b) byte program mode (t a = 25 5 c, v dd = 6.5 0.25 v, v pp = 12.5 0.3 v) note corresponding m pd27c1001a symbol
49 m pd78p064b t df a2?16 a0, a1 d0?7 v pp v pp v dd v dd v dd + 1.5 v dd ce v ih v il pgm v ih v il oe v ih v il page data latch page program program verify data output data input hi? hi? hi? t ah t deh t des t ceh t pw t ahv t df t ces t alh t as t dh t lw t vds t vps t ds t pgms (2) prom read mode (t a = 25 5 c, v dd = 5.0 0.5 v, v pp = v dd 0.6 v) note corresponding m pd27c1001a symbol (3) prom programming mode setting (t a = 25 c, v ss = 0 v) parameter symbol test conditions min. typ. max. unit m s 10 t sma prom programming mode setup time prom write mode timing (page program mode) parameter symbol symbol note test conditions min. typ. max. unit data output time from address t acc t acc ce = oe = v il 800 ns data output delay time from ce t ce t ce oe = v il 800 ns data output delay time from oe t oe t oe ce = v il 200 ns data output float delay time from oe - t df t df ce = v il 060ns data hold time from address t dh t dh ce = oe = v il 0ns
50 m pd78p064b pgm program program/verify t as t ds t vps t vds t dem t ces t pw t dh hi-z hi-z hi-z t df t ah t oes t oe oe ce v dd v pp d0?7 v pp v dd v dd + 1.5 v dd v ih v il v ih v il v ih v il a0?16 data input data output notes 1. when reading within the t acc range, the oe input delay time from the ce fall time must be maximum of t acc C t oe . 2. t df is the time from the point at which either oe or ce (whichever is first) reaches v ih . prom write mode timing (byte program mode) cautions 1. v dd must be applied before v pp and cut off after v pp . 2. v pp must not exceed +13.5 v including overshoot. 3. removing and reinserting may adversely affect in reliability while +12.5 v is applied to v pp . prom read mode timing oe ce d0?7 a0?16 t ce t acc t oe hi-z hi-z t oh t df effective address data output note 1 v ih v il v ih v il note 1 note 2
51 m pd78p064b a0?16 effective address t sma reset v dd v pp v pp 0 v dd 0 prom programming mode setting timing
52 m pd78p064b 100 pin plastic qfp (fine pitch) ( 14) item millimeters inches i j 0.5 (t.p.) 0.10 0.004 0.020 (t.p.) a note each lead centerline is located within 0.10 mm (0.004 inch) of its true position (t.p.) at maximum material condition. s a 16.0?.2 0.630?.008 b 14.0?.2 0.551 +0.009 ?.008 c 14.0?.2 0.551 +0.009 ?.008 d 16.0?.2 0.630?.008 f g 1.0 1.0 0.039 0.039 h 0.22 0.009?.002 p100gc-50-7ea-2 k 1.0?.2 0.039 +0.009 ?.008 l 0.5?.2 0.020 +0.008 ?.009 m 0.17 0.007 n 0.10 0.004 p 1.45 0.057 +0.05 ?.04 +0.03 ?.07 b c d j h i g f p n l k m q r detail of lead end q 0.125?.075 0.005?.003 r s 1.7 max. 55? 55? 0.067 max. +0.001 ?.003 m 1 25 26 50 100 76 75 51 7. package drawings remark dimensions and materials of es products are the same as those of the mass production product.
53 m pd78p064b remark dimensions and materials of es products are the same as those of the mass production product. 100 pin plastic lqfp (fine pitch) (14 14) item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. s100gc-50-8eu f 1.00 0.039 b 14.00?.20 0.551 +0.009 ?.008 s 1.60 max. 0.063 max. l 0.50?.20 0.020 +0.008 ?.009 +0.009 ?.008 c 14.00?.20 0.551 +0.009 ?.008 a 16.00?.20 0.630?.008 g 1.00 0.039 h 0.22 0.009?.002 i 0.08 0.003 j 0.50 (t.p.) 0.020 (t.p.) k 1.00?.20 0.039 +0.009 ?.008 n 0.08 0.003 p 1.40?.05 0.055?.002 r3 3 +7 ? +7 ? d 16.00?.20 0.630?.008 m q r k m l j h i f g p n detail of lead end m 0.17 0.007 +0.001 ?.003 +0.03 ?.07 q 0.10?.05 0.004?.002 +0.05 ?.04 1 25 26 50 100 76 75 51 cd s a b
54 m pd78p064b remark dimensions and materials of es products are the same as those of the mass production product. j n m p 80 81 50 100 pin plastic qfp (14 20) 100 1 31 30 51 g detail of lead end s 5 5 c d a b h q k l f m i p100gf-65-3ba1-2 item millimeters inches a b c d f g h i j k l 23.6 0.4 14.0 0.2 0.6 0.30 0.10 0.15 20.0 0.2 0.929 0.016 0.031 0.024 0.006 0.026 (t.p.) 0.795 note m n 0.10 0.15 1.8 0.2 0.65 (t.p.) 0.006 0.031 +0.009 ?.008 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.012 0.551 0.8 0.2 0.071 p 2.7 0.106 0.693 0.016 17.6 0.4 0.8 +0.008 ?.009 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008 +0.004 ?.003 0.004
55 m pd78p064b 8. recommended soldering conditions the m pd78p064b should be soldered and mounted under the conditions recommended in the table below. for detail of recommended soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact our sales personnel. table 8-1. surface mounting type soldering conditions (1) m pd78p064bgc-7ea: 100-pin plastic qfp (fine pitch) (14 14 mm) m pd78p064bgc-8eu: 100-pin plastic lqfp (fine pitch) (14 14 mm) soldering method soldering conditions recommended soldering symbols infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-107-2 number of times: twice max., time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) products cannot be baked while packed in anything other than in a heat resistant tray (i.e. they cannot be baked in a magazine, taping, or heat-labile tray). vps package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), vp15-107-2 number of times: twice max., time limit: 7 days note (thereafter 10 hours prebaking required at 125 c) products cannot be baked while packed in anything other than in a heat resistant tray (i.e. they cannot be baked in a magazine, taping, or heat-labile tray). partial heating pin temperature: 300 c max., duration: 3 sec. max. (per device side) note for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65 % rh. (2) m pd78p064bgf-3ba: 100-pin plastic qfp (14 20 mm) soldering method soldering conditions recommended soldering symbols infrared reflow package peak temperature: 235 c, duration: 30 sec. max. (at 210 c or above), ir35-00-3 number of times: three times max. vps package peak temperature: 215 c, duration: 40 sec. (at 200 c or above), vp15-00-3 number of times: three times max. wave soldering solder bath temperature: 260 c max., duration: 10 sec. max., number of times: ws60-00-1 once, preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., duration: 3 sec. max. (per device side) caution use of more than one soldering method should be avoided (except in the case of partial heating).
56 m pd78p064b appendix a. development tools the following development tools are available for system development using m pd78p064b. language processing software ra78k/0 note 1, 2, 3, 4 cc78k/0 note 1, 2, 3, 4 df78064 note 1, 2, 3, 4 cc78k/0-l note 1, 2, 3, 4 78k/0 series common assembler package 78k/0 series common c compiler package m pd78064 subseries common device file 78k/0 series common c compiler library source file prom writing tools pg-1500 pa-78p064gc pa-78p064gf pa-pg-1500 controller note 1, 2 prom programmer programmer adapters connected to pg-1500 pg-1500 control program debugging tools 78k/0 series common in-circuit emulators 78k/0 series common in-circuit emulators (for integrated debugger) 78k/0 series common break board m pd780308 subseries common evaluation emulation boards m pd78064 subseries common emulation probes adapter to be mounted on a target system board made for 100-pin plastic qfp (gc-7ea, gc-8eu type) a product of tokyo eletech corp. (tokyo 03-5295-1661). when purchasing this product, consult your nec distributor. socket to be mounted on a target system board made for 100-pin plastic qfp (gf-3ba type) 78k/0 series common system simulators ie-78000-r-a integrated debuggers ie-78000-r screen debuggers m pd78064 subseries common device file ie-78000-r ie-78000-r-a ie-78000-r-bk ie-780308-r-em ep-78064gc-r ep-78064gf-r tgc-100sdw ev-9200gf-100 sm78k0 note 5, 6, 7 id78k0 note 4, 5, 6, 7 sd78k/0 note 1, 2 df78064 note 1, 2, 4, 5, 6, 7 real-time os 78k/0 series real-time os 78k/0 series os rx78k/0 note 1, 2, 3, 4 mx78k/0 note 1, 2, 3, 4
57 m pd78p064b fuzzy inference development support system notes 1. pc-9800 series (ms-dos tm ) based 2. ibm pc/at tm and compatible machines (pc dos tm /ibm dos tm /ms-dos) based 3. hp9000 series 300 tm (hp-ux tm ) based 4. hp9000 series 700 tm (hp-ux) based, sparcstation tm (sunos tm ) based, ews4800 series (ews-ux/v) based 5. pc-9800 series (ms-dos + windows tm ) based 6. ibm pc/at and compatible machines (pc dos/ibm dos/ms-dos + windows) based 7. news tm (news-os tm ) based remarks 1. for third party development tools, refer to 78k/0 series selection guide (u11126e) . 2. ra78k/0, cc78k/0, sm78k0, id78k0, sd78k/0, and rx78k/0 are used in combination with df78064. fe9000 note 1 , fe9200 note 6 ft9080 note 1 , ft9085 note 2 fi78k/ii note 1, 2 fd78k/ii note 1, 2 fuzzy knowledge data creation tool translator fuzzy inference module fussy inference debugger
58 m pd78p064b ev-9200gf-100 a d e b f 1 no.1 pin index m n o l k s r q i h g p c j ev-9200gf-100-g0 item millimeters inches a b c d e f g h i j k l m n o p q r s 24.6 21 15 18.6 4-c 2 0.8 12.0 22.6 25.3 6.0 16.6 19.3 8.2 8.0 2.5 2.0 0.35 2.3 1.5 0.969 0.827 0.591 0.732 4-c 0.079 0.031 0.472 0.89 0.996 0.236 0.654 076 0.323 0.315 0.098 0.079 0.014 0.091 0.059 f f f f conversion socket (ev-9200gf-100) package drawings and recommended board mounting pattern figure a-1. ev-9200gf-100 package drawing
59 m pd78p064b figure a-2. ev-9200gf-100 board mounting pattern f h e d a b c i j k l 0.026 1.142=0.742 0.026 0.748=0.486 ev-9200gf-100-p0 item millimeters inches a b c d e f g h i j k l 26.3 21.6 15.6 20.3 12 0.05 6 0.05 0.35 0.02 2.36 0.03 2.3 1.57 0.03 1.035 0.85 0.614 0.799 0.472 0.236 0.014 0.093 0.091 0.062 0.65 0.02 29=18.85 0.05 0.65 0.02 19=12.35 0.05 f +0.001 ?.002 +0.002 ?.002 +0.001 ?.002 +0.003 ?.002 +0.003 ?.002 +0.003 ?.002 +0.001 ?.001 +0.001 ?.002 f +0.001 ?.002 f f g f f dimensions of mount pad for ev-9200 and that for target device (qfp) may be different in some parts. for the recommended mount pad dimensions for qfp, refer to "semiconductor device mounting technology manual" (c10535e). caution
60 m pd78p064b conversion adapter (tgc-100sdw) package drawings figure a-3. tgc-100sdw package drawing item millimeters inches b 1.85?.25 0.073?.010 c 3.5 0.138 a 14.45 0.569 d 2.0 0.079 h 16.0 0.630 i 1.125?.3 0.044?.012 j 0~5 0.000~0.197 e 3.9 0.154 f 0.25 g 4.5 0.177 tgc-100sdw-g0e 0.010 k 5.9 0.232 l 0.8 0.031 m 2.4 0.094 n 2.7 0.106 item millimeters inches b 0.5x24=12 0.020x0.945=0.472 c 0.5 0.020 a 21.55 0.848 d 0.5x24=12 0.020x0.945=0.472 h 10.9 0.429 i 13.3 0.524 j 15.7 0.618 e 15.0 0.591 f 21.55 g 3.55 0.140 0.848 k 18.1 0.713 l 13.75 0.541 m 0.5x24=12.0 0.020x0.945=0.472 q 10.0 0.394 r 11.3 0.445 s 18.1 0.713 n 1.125?.3 0.044?.012 o 1.125?.2 p 7.5 0.295 0.044?.008 w 1.8 0.071 x c 2.0 c 0.079 y 0.9 0.035 t 5.0 0.197 u 5.0 v 4- 1.3 4- 0.051 0.197 z 0.3 0.012 f ff f f f f f f f ff reference diagram: tgc-100sdw package dimension (unit: mm) h a b c i j k g f e d n o l m x p q r s u protrusion height w v k i m n z j g i h a e d c b y f x t remark manufactured by tokyo eletech corp.
61 m pd78p064b appendix b. related documents device related documents document name document no. japanese english m pd78064b subseries users manual u10785j u10785e m pd78064b data sheet u11590j u11590e m pd78p064b data sheet u11598j this document 78k/0 series users manual (instruction) u12326j u12326e 78k/0 series instruction list u10903j 78k/0 series instruction set u10904j m pd78064b subseries special function register table planned document name document no. japanese english ra78k series assembler package operation eeu-809 eeu-1399 language eeu-815 eeu-1404 ra78k series structured assembler preprocessor eeu-817 eeu-1402 ra78k0 assembler package operation u11802j u11802e assembly language u11801j u11801e structured assembly language u11789j u11789e cc78k series c compiler operation eeu-656 eeu-1280 language eeu-655 eeu-1284 cc78k0 c compiler operation u11517j u11517e language u11518j u11518e cc78k/0 c compiler application note programming know-how eea-618 eea-1208 cc78k series library source file u12322j pg-1500 prom programmer u11940j u11940e pg-1500 controller pc-9800 series (ms-dos) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos) based eeu-5008 u10540e ie-78000-r u11376j u11376e ie-78000-r-a u10057j u10057e ie-78000-r-bk eeu-867 eeu-1427 ie-780308-r-em u11362j u11362e ep-78064 eeu-934 eeu-1469 development tool related documents (users manual) (1/2)
62 m pd78p064b document name document no. japanese english sm78k0 system sumilator windows based reference eeu-5002 u10181e sm78k series system simulator external components user u10092j u10092e open interface specification id78k0 integrated debugger ews based reference u11151j id78k0 integrated debugger pc based reference u11539j u11539e id78k0 integrated debugger windows based guide u11649j u11649e sd78k/0 screen debugger introduction eeu-852 u10539e pc-9800 series (ms-dos) based reference u10952j sd78k/0 screen debugger introduction eeu-5024 eeu-1414 ibm pc/at (pc dos) based reference u11279j u11279e caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. embedded software related documents (users manual) document name document no. japanese english 78k/0 series real-time os basic u11537j installation u11536j 78k/0 series os mx78k0 basic u12257j fuzzy knowledge data creation tool eeu-829 eeu-1438 78k/0, 78k/ii, 87ad series fuzzy inference development support system eeu-862 eeu-1444 translator 78k/0 series fuzzy inference development support system fuzzy inference eeu-858 eeu-1441 module 78k/0 series fuzzy inference development support system fuzzy inference eeu-921 eeu-1458 debugger document name document no. japanese english ic package manual c10943x semiconductor device mounting technology manual c10535j c10535e quality grades on semiconductor devices c11531j c11531e nec semiconductor device reliability and quality control c10983j c10983e electrostatic discharge (esd) test mem-539 semiconductor devices quality guarantee guide c11893j mei-1202 microcomputer-related product guide (products by other manufacturers) u11416j caution the above related documents are subject to change without notice. for design purpose, etc., be sure to use the latest documents. other related documents development tool related documents (users manual) (2/2)
63 m pd78p064b [memo]
64 m pd78p064b notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
65 m pd78p064b nec electronics inc. (u.s.) santa clara, california tel: 800-366-9782 fax: 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. sao paulo-sp, brasil tel: 011-889-1680 fax: 011-889-1689 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 regional information some information contained in this document may vary from country to country. before using any nec product in your application, please contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. j96. 8
m pd78p064b 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. fip, qtop and iebus are trademarks of nec corporation. ms-dos and windows are trademarks of microsoft corporation. ibm dos, pc/at and pc dos are trademarks of ibm corporation. hp9000 series 300, hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sun os is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation. the documents referred to in this publication may include preliminary versions. however preliminary versions are not marked as such.

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