cd74fct244, cd74fct244at bicmos octal buffers/line drivers with 3-state outputs scbs722a july 2000 revised july 2000 1 post office box 655303 ? dallas, texas 75265 bicmos technology with low quiescent power buffered inputs noninverted outputs input/output isolation from v cc controlled output edge rates 64-ma output sink current output voltage swing limited to 3.7 v scr latch-up-resistant bicmos process and circuit design package options include plastic small-outline (m) and shrink small-outline (sm) packages and standard plastic (e) dip description the cd74fct244 and cd74fct244at are octal buffer/line drivers with 3-state outputs using a small-geometry bicmos technology. the output stages are a combination of bipolar and cmos transistors that limit the output high level to two diode drops below v cc . this resultant lowering of output swing (0 v to 3.7 v) reduces the power-bus ringing [a source of electromagnetic interference (emi)] and minimizes v cc bounce and ground bounce and their effects during simultaneous output switching. the output configuration also enhances switching speed and is capable of sinking 64 ma. these devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (oe ) inputs. when oe is low, the device passes data from the a inputs to the y outputs. when oe is high, the outputs are in the high-impedance state. to ensure the high-impedance state during power up or power down, oe should be tied to v cc through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. the cd74fct244 and cd74fct244at devices are characterized for operation from 0 c to 70 c. function table (each buffer/driver) inputs output oe a y l h h l ll h x z copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. cd74fct244, cd74fct244a t...e, m, or sm p ackage (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 1oe 1a1 2y4 1a2 2y3 1a3 2y2 1a4 2y1 gnd v cc 2oe 1y1 2a4 1y2 2a3 1y3 2a2 1y4 2a1
cd74fct244, cd74fct244at bicmos octal buffers/line drivers with 3-state outputs scbs722a july 2000 revised july 2000 2 post office box 655303 ? dallas, texas 75265 logic symbol 2 2 1a1 4 1a2 6 1a3 8 1a4 en 1 1y1 18 1y2 16 1y3 14 1y4 12 11 2a1 13 2a2 15 2a3 17 2a4 en 19 2y1 9 2y2 7 2y3 5 2y4 3 1oe 2oe 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. logic diagram (positive logic) 1 218 1y1 1oe 1a1 416 1y2 1a2 614 1y3 1a3 812 1y4 1a4 19 11 9 2y1 2oe 2a1 13 7 2y2 2a2 15 5 2y3 2a3 17 3 2y4 2a4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 3 dc supply voltage range, v cc 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc input clamp current, i ik (v i < 0.5 v) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc output clamp current, i ok (v o < 0.5 v) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc output sink current per output pin, i ol 70 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . dc output source current per output pin, i oh 30 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc , i cc 140 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through gnd 528 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 1): e package 69 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m package 58 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sm package 70 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the package thermal impedance is calculated in accordance with jesd 51.
cd74fct244, cd74fct244at bicmos octal buffers/line drivers with 3-state outputs scbs722a july 2000 revised july 2000 3 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 2) min max unit v cc supply voltage 4.75 5.25 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 v cc v v o output voltage 0 v cc v i oh high-level output current 15 ma i ol low-level output current 64 ma d t/ d v input transition rise or fall rate (slew rate) 0 10 ns/v t a operating free-air temperature 0 70 c note 2: all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs , literature number scba004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c min max unit parameter test conditions v cc min max min max unit v ik i i = 18 ma 4.75 v 1.2 1.2 v v oh i oh = 15 ma 4.75 v 2.4 2.4 v v ol i ol = 64 ma 4.75 v 0.55 0.55 v i i v i = v cc or gnd 5.25 v 0.1 1 a i oz v o = v cc or gnd 5.25 v 0.5 10 a i os 2 v i = v cc or gnd, v o = 0 5.25 v 60 60 ma i cc v i = v cc or gnd, i o = 0 5.25 v 8 80 a d i cc 3 one input at 3.4 v, other inputs at v cc or gnd 5.25 v 1.6 1.6 ma c i v i = v cc or gnd 10 10 pf c o v o = v cc or gnd 15 15 pf 2 not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. 3 this is the increase in supply current for each input at one of the specified ttl voltage levels rather than 0 v or v cc . switching characteristics over recommended operating free-air temperature range, v cc = 5 v 0.25 v (unless otherwise noted) (see figure 1) from to cd74fct244 cd74fct244at parameter from (input) to (output) t a = 25 c min max t a = 25 c min max unit (input) (output) typ min max typ min max t pd a y 4.5 1.5 6.5 3.8 1.5 5.3 ns t en oe y 6 1.5 8 4.8 1.5 6.5 ns t dis oe y 5 1.5 7 4.5 1.5 5.8 ns noise characteristics, v cc = 5 v, c l = 50 pf, t a = 25 c parameter min typ max unit v ol(p) quiet output, maximum dynamic v ol 1 v v oh(v) quiet output, minimum dynamic v oh 0.5 v v ih(d) high-level dynamic input voltage 2 v v il(d) low-level dynamic input voltage 0.8 v
cd74fct244, cd74fct244at bicmos octal buffers/line drivers with 3-state outputs scbs722a july 2000 revised july 2000 4 post office box 655303 ? dallas, texas 75265 operating characteristics, v cc = 5 v, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance no load, f = 1 mhz 35 pf
cd74fct244, cd74fct244at bicmos octal buffers/line drivers with 3-state outputs scbs722a july 2000 revised july 2000 5 post office box 655303 ? dallas, texas 75265 parameter measurement information 3 v 3 v 0 v 0 v t h t su voltage waveforms setup and hold times data input t plh t phl t phl t plh v oh v oh v ol v ol 3 v 0 v 1.5 v 1.5 v input out-of-phase output in-phase output timing input voltage waveforms propagation delay times inverting and noninverting outputs output control output waveform 1 (see note b) output waveform 2 (see note b) v ol v oh t pzl t pzh t plz t phz 3.5 v 0 v 1.5 v v ol + 0.3 v 1.5 v 0 v 3 v voltage waveforms enable and disable times low- and high-level enabling t plh /t phl t plz /t pzl t phz /t pzh open drain open 7 v open 7 v test s1 3 v 0 v 1.5 v t w voltage waveforms pulse duration input notes: a. c l includes probe and jig capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. all input pulses are supplied by generators having the following characteristics: prr 1 mhz, z o = 50 w , t r and t f = 2.5 ns. d. the outputs are measured one at a time with one input transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t phl and t plh are the same as t pd . from output under test c l = 50 pf (see note a) load circuit for 3-state and open-drain outputs s1 7 v 500 w gnd from output under test c l = 50 pf (see note a) test point load circuit for totem-pole outputs open v oh 0.3 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 500 w 500 w 1.5 v 1.5 v voltage waveform input rise and fall times 1.5 v 1.5 v 10% 10% 90% 90% 3 v 0 v t r t f figure 1. load circuit and voltage waveforms
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated
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