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PCI1450 gfn/gjg pc card controller scps044 september 1998 1 post office box 655303 ? dallas, texas 75265 1997 pc standard compliant pci bus power management interface specification 1.0 acpi 1.0 compliant pci local bus specification revision 2.1/2.2 compliant pc 98/99 compliant compliant with the pci bus interface specification for pci-to-cardbus bridges fully compliant with the pci bus power management specification for pci to cardbus bridges specification ultra zoomed video zoomed video auto-detect advanced filtering on card detect lines provide 90 microseconds of noise immunity. programmable d3 status pin internal ring oscillator 3.3-v core logic with universal pci interfaces compatible with 3.3-v and 5-v pci signaling environments mix-and-match 5-v/3.3-v pc card16 cards and 3.3-v cardbus cards supports two pc card or cardbus slots with hot insertion and removal uses serial interface to ti ? tps2206 dual power switch supports 132 mbyte/sec. burst transfers to maximize data throughput on both the pci bus and the cardbus bus supports serialized irq with pci interrupts 8-way legacy irq multiplexing interrupt modes supported: serial isa/serial pci, serial isa/parallel pci, parallel isa/parallel pci, parallel pci only. eeprom interface for loading subsystem id and subsystem vendor id supports zoomed video with internal buffering dedicated pin for pci clkrun four general purpose i/o's multifunction pci device with separate configuration space for each socket five pci memory windows and two i/o windows available to each pc card16 socket two i/o windows and two memory windows available to each cardbus socket exca ? -compatible registers are mapped in memory or i/o space supports distributed dma and pc/pci dma intel ? 82365sl-df register compatible supports 16-bit dma on both pc card sockets supports ring indicate, suspend , and pci clkrun advanced submicron, low-power cmos technology provides vga / palette memory and i/o, and subtractive decoding options led activity pins supports pci bus lock (lock) packaged in a 256-pin bga or 257-pin micro-star bga copyright ? 1998, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. intel is a trademark of intel corporation. pc card is a trademark of personal computer memory card international association (pcmcia). ti is a trademark of texas instruments incorporated.
PCI1450 gfn/gjg pc card controller scps044 september 1998 2 post office box 655303 ? dallas, texas 75265 description 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . terminal assignments 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal names and terminal assignments 5 . . . . . . . . . . . . . . . . . . PCI1450 system block diagram 9 . . . . . . . . . . . . . . . . . . . . . . . . . . terminal functions 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i/o characteristics 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clamping rail voltages 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci interface 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pc card applications overview 26 . . . . . . . . . . . . . . . . . . . . . . . . . programmable interrupt subsystem 34 . . . . . . . . . . . . . . . . . . . . . . power management overview 38 . . . . . . . . . . . . . . . . . . . . . . . . . . pc card controller programming model 44 . . . . . . . . . . . . . . . . . . pci configuration registers (functions 0 and 1) 44 . . . . . . . . . . . exca compatibility registers (functions 0 and 1) 82 . . . . . . . . . cardbus socket registers (functions 0 and 1) 106 . . . . . . . . . . . . . . distributed dma (ddma) registers 114 . . . . . . . . . . . . . . . . . . . . . . . . absolute maximum ratings 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . recommended operating conditions 121 . . . . . . . . . . . . . . . . . . . . . . electrical characteristics 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . pci clock/reset timing requirements 123 . . . . . . . . . . . . . . . . . . . . . pci timing requirements 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . parameter measurement information 124 . . . . . . . . . . . . . . . . . . . . . . . pci bus parameter measurement information 125 . . . . . . . . . . . . . . . pc card cycle timing 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . timing requirements, (memory cycles) 127 . . . . . . . . . . . . . . . . . . . . timing requirements, (i/o cycles) 127 . . . . . . . . . . . . . . . . . . . . . . . . . switching characteristics (miscellaneous) 128 . . . . . . . . . . . . . . . . . . pc card parameter mesasurement information 128 . . . . . . . . . . . . . . mechanical data 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . table of contents
PCI1450 gfn/gjg pc card controller scps044 september 1998 3 post office box 655303 ? dallas, texas 75265 description the texas instruments PCI1450 is a high-performance pc card controller with a 32-bit pci interface. the device supports two independent pc card sockets compliant with the 1997 pc card standard and the pci bus interface specification for pci-to-cardbus bridges . the PCI1450 provides a rich feature set which makes it the best choice for bridging between pci and pc cards in both notebook and desktop computers. the 1995 and 1997 pc card standards retain the 16-bit pc card specification defined in pcmcia release 2.1, and defines the new 32-bit pc card, cardbus, capable of full 32-bit data transfers at 33 mhz. the PCI1450 supports any combination of 16-bit and cardbus pc cards in the two sockets, powered at 5 vdc or 3.3 vdc as required. the PCI1450 is compliant with the latest pci bus power management specification . it is also compliant with the pci local bus specification revision 2.1 , and its pci interface can act as either a pci master device or a pci slave device. the pci bus mastering is initiated during 16-bit pc card dma transfers, or cardbus pc card bridging transactions. all card signals are internally buffered to allow hot insertion and removal. the PCI1450 is register compatible with the intel 82365sl-df exca controller. the PCI1450 internal data-path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit pci cycles for maximum performance. independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. the PCI1450 can also be programmed to accept fast posted writes to improve system bus utilization. the PCI1450 provides an internally buffered zoom video (zv) path. this reduces the design effort of pc board manufacturers to add a zv compatible solution and guarantees compliance with the cardbus loading specifications. multiple system interrupt signaling options are provided: serial isa/serial pci, serial isa/parallel pci, parallel isa/parallel pci, and pci only interrupts. furthermore, general-purpose inputs and outputs (gpios) are provided for the board designer to implement sideband functions. many other features are designed into the PCI1450 such as socket activity led outputs, and are discussed in detail throughout the design specification. an advanced complementary metal-oxide semiconductor (cmos) process achieves low system power consumption while operating at pci clock rates up to 33 mhz. several low-power modes allow the host power management system to further reduce power consumption. unused PCI1450 inputs must be pulled up using a 43 k resistor. use of symbols in this document throughout this data sheet the overbar symbol denotes an active-low signal. for example: frame denotes that this is an active-low signal. 1.
PCI1450 gfn/gjg pc card controller scps044 september 1998 4 post office box 655303 ? dallas, texas 75265 terminal assignments ppppppp ppppppp ppppppp zzzzz p pppp pppp pppp pppp ppp ppp ppp pppp ppp p c cc cccc ccc c ccc cccccccc cccccccc ccc c cccc ccc cc cc cccc cccc ccc ccc cccc ccc ccc cccc cccc cccccccccccc cccccccccccc cccccccccccc ccc ccc cc cc c cc z z zz zz zz zzzzz zzz zzz z z zz z z z 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y bottom view p c z gnd power switch interrupt and miscellaneous pci signals cardbus signals zoom video signals v cc figure 1. PCI1450 pin diagram
PCI1450 gfn/gjg pc card controller scps044 september 1998 5 post office box 655303 ? dallas, texas 75265 signal names and terminal assignments signal names and their terminal assignments are shown in tables 1 and 2 and are sorted alphanumerically by the assigned terminal. table 1. gfn terminals sorted alphanumerically for cardbus and 16-bit signals gfn signal name gfn signal name gfn signal name a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 a20 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 c1 c2 c3 c4 c5 c6 c7 c8 gnd zv_uv3 zv_y7 v ccz zv_y1 zv_href b_rsvd//b_d2 b_cad28//b_d8 b_cstschg//b_bvd1(stschg /ri ) b_cint //b_ready(ireq ) b_cvs1//b_vs1 b_cad24//b_a2 b_cad22//b_a4 b_cad20//b_a6 b_cad18//b_a7 b_cirdy //b_a15 b_cclk//b_a16 b_cdevsel //b_a21 b_cpar//b_a13 b_rsvd//b_a18 zv_uv5 zv_uv4 zv_uv1 zv_y6 zv_y4 zv_y0 b_cad31//b_d10 b_cad29//b_d1 b_cclkrun //b_wp(iois16 ) b_cserr //b_wait b_cad25//b_a1 b_cc/be3 //b_reg b_cad21//b_a5 b_cvs2//b_vs2 b_cad17//b_a24 v ccb b_cperr //b_a14 b_cblock //b_a19 b_cc/be1 //b_a8 b_cad14//b_a9 zv_rsvd1 zv_sclk zv_uv6 zv_uv2 zv_y5 zv_y3 zv_vsync b_cad30//b_d9 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 e1 e2 e3 e4 e17 e18 e19 e20 f1 f4 f17 f18 f19 f20 g1 g2 b_ccd2 //b_cd2 v ccb b_cad26//b_a0 b_cad23//b_a3 b_crst //b_reset b_cad19//b_a25 b_cframe //b_a23 b_ctrdy //b_a22 b_cstop //b_a20 b_cad16//b_a17 b_cad15//b_iowr b_cad11//b_oe v ccz zv_uv7 zv_mclk gnd zv_uv0 v cc zv_y2 gnd b_cad27//b_d0 b_caudio//b_bvd2(spkr ) v cc b_creq //b_inpack gnd b_cc/be2 //b_a12 v cc b_cgnt //b_we gnd b_cad12//b_a11 b_cad10//b_ce2 b_cc/be0 //b_ce1 zv_pclk zv_sdata zv_lrclk zv_rsvd0 b_cad13//b_iord b_cad9//b_a10 b_cad8//b_d15 b_rsvd//b_d14 g_rst v cc v cc v ccb b_cad5//b_d6 b_cad3//b_d5 a_cad2//a_d11 a_cad0//a_d3 g3 g17 g18 g19 g20 h1 h2 h3 h4 h17 h18 h19 h20 j1 j2 j3 j4 j17 j18 j19 j20 k1 k2 k3 k4 k17 k18 k19 k20 l1 l2 l3 l4 l17 l18 l19 l20 m1 m2 m3 m4 m17 m18 m19 m20 n1 n2 n3 a_ccd1 //a_cd1 b_cad7//b_d7 b_cad6//b_d13 b_cad4//b_d12 b_cad1//b_d4 a_cad3//a_d5 a_cad4//a_d12 a_cad1//a_d4 gnd gnd b_cad2//b_d11 b_cad0//b_d3 b_ccd1 //b_cd1 a_cad7//a_d7 a_rsvd//a_d14 a_cad5//a_d6 a_cad6//a_d13 pclk clkrun prst gnt a_cc/be0 //a_ce1 v cca a_cad8//a_d15 v cc req ad31 ad30 v ccp a_cad9//a_a10 a_cad10//a_ce2 a_cad11//a_oe a_cad13//a_iord v cc ad28 ad27 ad29 a_cad12//a_a11 a_cad15//a_iowr a_cad14//a_a9 a_cad16//a_a17 c/be3 ad24 ad25 ad26 a_cc/be1 //a_a8 a_rsvd//a_a18 a_cpar//a_a13
PCI1450 gfn/gjg pc card controller scps044 september 1998 6 post office box 655303 ? dallas, texas 75265 signal names and terminal assignments (continued) table 1. gfn terminals sorted alphanumerically for cardbus and 16-bit signals (continued) gfn signal name gfn signal name gfn signal name n4 n17 n18 n19 n20 p1 p2 p3 p4 p17 p18 p19 p20 r1 r2 r3 r4 r17 r18 r19 r20 t1 t2 t3 t4 t17 t18 t19 t20 u1 u2 u3 u4 u5 u6 u7 u8 gnd gnd ad22 ad23 idsel a_cblock //a_a19 a_cperr //a_a14 a_cgnt //a_we a_ctrdy //a_a22 ad17 v ccp ad20 ad21 a_cstop //a_a20 a_cdevsel //a_a21 v cca v cc v cc ad16 ad18 ad19 a_cclk//a_a16 a_cirdy //a_a15 a_cc/be2 //a_a12 a_cad19//a_a25 stop irdy frame c/be2 a_cframe //a_23 a_cad17//a_a24 a_cvs2//a_vs2 gnd a_cad26//a_a0 v cc a_cclkrun //a_wp(iois16 ) gnd u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 v20 w1 w2 w3 w4 w5 irqmux1 v cc pcgnt /irqmux6 clock gnd ad6 v cc ad11 gnd perr serr trdy a_cad18//a_a7 a_cad20//a_a6 a_cad21//a_a5 a_cad25//a_a1 a_cserr //a_wait a_cstschg//a_bvd1(stschg /ri ) a_cad28//a_d8 a_rsvd//a_d2 irqmux2 v cci gpio0/leda1 data gpio3/inta ad3 v ccp ad8 ad12 ad15 gpio2/lock devsel a_crst //a_reset a_cad22//a_a4 a_cad23//a_a3 a_cad24//a_a2 v cca w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 w19 w20 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 a_ccd2 //a_cd2 a_cad29//a_d1 a_cad31//a_d10 irqmux3 irqmux5 gpio1/leda2 latch irqser/intb ad1 ad4 ad7 ad9 ad13 c/be1 v ccp a_creq //a_inpack a_cc/be3 //a_reg a_cvs1//a_vs1 a_cint //a_ready(ireq ) a_caudio//a_bvd2(spkr ) a_cad27//a_d0 a_cad30//a_d9 irqmux0 irqmux4 spkrout suspend pcreq /irqmux7 ri_out /pme ad0 ad2 ad5 c/be0 ad10 ad14 par
PCI1450 gfn/gjg pc card controller scps044 september 1998 7 post office box 655303 ? dallas, texas 75265 signal names and terminal assignments (continued) table 2. gjg terminals sorted alphanumerically for cardbus and 16-bit signals no. signal name no. signal name no. signal name a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 c1 c2 c18 c19 d1 d2 d4 d5 d6 d7 d8 d9 d10 d11 zv_uv6 zv_uv4 zv_uv2 zv_y6 zv_y3 zv_vsync v cc b_cclkrun //b_wp(iois16 ) b_cserr //b_wait b_cad24//b_a2 b_cad21//b_a5 b_cad20//b_a6 b_cad17//b_a24 v ccb b_cgnt //b_we b_cperr //b_a14 b_cblock //b_a19 zv_sclk zv_uv5 zv_uv3 zv_uv1 zv_y7 zv_y4 zv_y0 b_cad30//b_d9 b_ccd2 //b_cd2 v ccb b_cad25//b_a1 b_cad22//b_a4 b_cvs2//b_vs2 gnd b_cirdy //b_a15 b_cdevsel //b_a21 b_cstop //b_a20 b_cpar//b_a13 b_rsvd//b_a18 zv_uv7 zv_mclk b_cc/be1 //b_a8 b_cad14//b_a9 zv_rsvd0 zv_rsvd1 gnd zv_uv0 v ccz gnd b_rsvd//b_d2 b_cad27//b_d0 b_caudio//b_bvd2(spkr ) b_cc/be3 //b_reg d12 d13 d14 d15 d16 d18 d19 e1 e2 e4 e5 e6 e7 e8 e9 e10 e11 e12 e13 e14 e15 e16 e18 e19 f1 f2 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f18 f19 g1 g2 g4 g5 g6 g7 g13 g14 g15 b_creq //b_inpack b_crst //b_reset b_cc/be2 //b_a12 b_cclk//b_a16 b_cad16//b_a17 b_cad15//b_iowr b_cad12//b_a11 zv_sdata zv_pclk v ccz zv_lrclk zv_y5 zv_y1 b_cad31//b_d10 b_cad28//b_d8 b_cstschg//b_bvd1(stschg/ri b_cad26//b_a0 b_cad23//b_a3 b_cad19//b_a25 b_cframe //b_a23 b_ctrdy //b_a22 b_cad13//b_iord b_cad11//b_oe b_cad10//b_ce2 a_ccd1 //a_cd1 a_cad0//a_d3 g_rst gnd v cc zv_y2 b_cad29//b_d1 gnd b_cint //b_ready(ireq ) b_cvs1//b_vs1 v cc b_cad18//b_a7 vcc b_cad9//b_a10 b_cc/be0 //b_ce1 b_cad8//b_d15 v ccb a_cad4//a_d12 v cc a_cad3//a_d5 a_cad1//a_d4 a_cad2//a_d11 zv_href b_cad3//b_d5 b_cad7//b_d7 b_rsvd//b_d14 g16 g18 g19 h1 h2 h4 h5 h6 h14 h15 h16 h18 h19 j1 j2 j4 j5 j6 j14 j15 j16 j18 j19 k1 k2 k4 k5 k6 k14 k15 k16 k18 k19 l1 l2 l4 l5 l6 l14 l15 l16 l18 l19 m1 m2 m4 m5 m6 m14 m15 gnd b_cad5//b_d6 b_cad6//b_d13 a_cad5//a_d6 a_rsvd//a_d14 a_cad7//a_d7 gnd a_cad6//a_d13 b_ccd1 //b_cd1 b_cad4//b_d12 b_cad1//b_d4 b_cad2//b_d11 b_cad0//b_d3 a_cad8//a_d15 a_cc/be0 //a_ce1 v cca a_cad9//a_a10 v cc gnt pclk clkrun prst gnd a_cad11//a_oe a_cad13//a_iord a_cad12//a_a11 gnd a_cad10//a_ce2 v ccp req ad31 ad30 v cc a_cad14//a_a9 a_cad16//a_a17 a_cc/be1 //a_a8 a_rsvd//a_a18 a_cad15//a_iowr ad29 ad28 ad25 ad27 ad26 a_cpar//a_a13 a_cblock //a_a19 a_cperr //a_a14 a_cstop //a_a20 v cc ad22 ad24
PCI1450 gfn/gjg pc card controller scps044 september 1998 8 post office box 655303 ? dallas, texas 75265 signal names and terminal assignments (continued) table 2. gjg terminals sorted alphanumerically for cardbus and 16-bit signals. (continued) no. signal name no. signal name no. signal name m16 m18 m19 n1 n2 n4 n5 n6 n7 n13 n14 n15 n16 n18 n19 p1 p2 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p18 p19 r1 r2 r4 r5 cbe3 idsel ad23 a_cdevsel //a_a21 gnd a_cclk//a_a16 a_ctrdy //a_a22 v cca a_cgnt //a_we ad1 gnd ad19 ad21 v ccp ad20 a_cirdy //a_a15 a_cframe //a_23 a_cc/be2 //a_a12 v cc a_cad17//a_a24 a_cad27//a_d0 v cc v cci spkrout pcreq /irqmux7 ri_out /pme ad5 ad8 c/be2 ad16 ad18 ad17 a_cad18//a_a7 a_cad19//a_a25 a_cvs2//a_vs2 a_cserr //a_wait r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r18 r19 t1 t2 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t18 t19 u1 u2 u18 u19 v1 v2 a_cstschg//a_bvd1(stschg /ri ) a_cad28//a_d8 irqmux2 irqmux5 pcgnt /irqmux6 clock ad0 gnd c/be0 v cc trdy frame irdy a_cad20//a_a6 a_crst //a_reset a_cad21//a_a5 a_cint //a_ready(ireq ) a_cclkrun //a_wp(iois16 ) a_rsvd//a_d2 irqmux1 irqmux3 gpio0/leda1 data gpi03/inta ad4 ad7 ad11 ad15 devsel stop gnd a_cad22//a_a4 perr serr a_creq //a_inpack a_cad23//a_a3 v3 v4 v5 v6 v7 v8 v9 v10 v11 v12 v13 v14 v15 v16 v17 v18 v19 w2 w3 w4 w5 w6 w7 w8 w9 w10 w11 w12 w13 w14 w15 w16 w17 w18 a_cad25//a_a1 a_cvs1//a_vs1 a_caudio//a_bvd2(spkr ) gnd a_cad29//a_d1 irqmux0 gnd gpi01/leda2 latch v cc ad3 v ccp ad10 ad13 c/be1 v ccp gpi02/lock a_cc/be3 //a_reg a_cad24//a_a2 a_cad26//a_a0 v cca a_ccd2 //a_cd2 a_cad30//a_d9 a_cad31//a_d10 irqmux4 suspend gnd irqser/intb ad2 ad6 ad9 ad12 ad14 par
PCI1450 gfn/gjg pc card controller scps044 september 1998 9 post office box 655303 ? dallas, texas 75265 PCI1450 system block diagram figure 2 shows a simplified system implementation example using the PCI1450. the pci interface includes all address/data and control signals for pci protocol. highlighted in this diagram is the functionality supported by the PCI1450. the PCI1450 supports pc/pci dma, pci way dma (distributed dma), pme wake-up from d3 cold through d0, 4 interrupt modes, an integrated zoomed video port, and 12 multifunction pins (8 irqmux, and 4 gpio pins) that can be programmed for a wide variety of functions. PCI1450 activity led's south bridge irqser embedded controller dma pme 68 23 for zv (see note) pc card socket a tps2206 power switch 2 pc card socket b vga controller zoomed video 19 video 4 audio clkrun interrupt routing options: 1) serial isa/serial pci 2) serial isa/parallel pci 3) parallel pci/parallel isa 4) parallel pci only zv enable 23 for zv 68 note: the pc card interface is 68 pins for cardbus and 16-bit pc cards. in zoomed-video mode 23 pins are used for routing the zoomed video signals to the vga controller. pci bus real time clock clock audio codec 4 audio figure 2. PCI1450 system block diagram
PCI1450 gfn/gjg pc card controller scps044 september 1998 10 post office box 655303 ? dallas, texas 75265 terminal functions this section describes the PCI1450 terminal functions. the terminals are grouped in tables by functionality such as pci system function, power supply function, etc., for quick reference. the terminal numbers are also listed for convenient reference. table 3. power supply terminal function name gfn no. gjg no. function gnd a1, d4, d8, d13, d17, h4, h17, n4, n17, u4, u8, u13, u17 b14, d4, d7, f5, f9, g16, h5, j19, k5, n2, n14, r13, u1, v6, v9, w11 device ground terminals v cc d6, d11, d15, f4, f17, k4, l17, r4, r17, u6, u10, u15 a8, f6, f12, f14, g2, j6, k19, m6, p5, p8, r15, v12 power supply terminal for core logic (3.3 vdc) v cca k2, r3, w5 j4, n6, w5 clamp voltage for pc card a interface. indicates card a signaling environment. v ccb b16, c10, f18, a15, b10, f19 clamp voltage for pc card b interface. indicates card b signaling environment. v cci v10 p9 clamp voltage for interrupt subsystem interface and miscellaneous i/o. indicates signaling level of the following inputs and shared outputs: irqser, pcgnt , pcreq , suspend , spkrout, gpio1:0, irqmux7irqmux0, inta , intb , clock, data, latch, and ri_out . v ccp k20, p18, v15, w20 k14, n18, v14, v18 clamp voltage for pci signaling (3.3 vdc or 5 vdc) v ccz a4, d1 d6, e4 clamp voltage for zoom video interface (3.3 vdc or 5 vdc) and g_rst table 4. pc card power switch terminal i/o function name gfn no. gjg no. type function clock u12 r11 i/o 3-line power switch clock. information on the data line is sampled at the rising edge of clock. this terminal defaults as an input which means an external clock source must be used. if the internal ring oscillator is used, then an external clock source is not required. the internal oscillator may be enabled by setting bit 27 of the system control register (pci offset 80h) to a 1b. a 43 k pulldown resistor should be tied to this terminal. data v12 t11 o 3-line power switch data. data is used to serially communicate socket power-control information to the power switch. latch w12 v11 o 3-line power switch latch. latch is asserted by the PCI1450 to indicate to the pc card power switch that the data on the data line is valid.
PCI1450 gfn/gjg pc card controller scps044 september 1998 11 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 5. pci system terminal i/o function name gfn no. gjg no. type function clkrun j18 j16 i/o pci clock run. clkrun is used by the central resource to request permission to stop the pci clock or to slow it down, and the PCI1450 responds accordingly. if clkrun is not implemented, then this pin should be tied low. clkrun is enabled by default by bit 1 (keepclk) in the system control register . pclk j17 j15 i pci bus clock. pclk provides timing for all transactions on the pci bus. all pci signals are sampled at the rising edge of pclk. prst j19 j18 i pci reset. when the pci bus reset is asserted, prst causes the PCI1450 to place all output buffers in a high-impedance state and reset all internal registers. when prst is asserted, the device is completely nonfunctional. after prst is deasserted, the PCI1450 is in its default state. when the suspend mode is enabled, the device is protected from the prst , and the internal registers are preserved. all outputs are placed in a high-impedance state, but the contents of the registers are preserved. g_rst f1 f4 i global reset. when the global reset is asserted, the g_rst signal causes the PCI1450 to 3-state all output buffers and reset all internal registers. when g_rst is asserted, the device is completely in its default state. for systems that require wake-up from d3, g_rst will normally be asserted only during initial boot. prst should be asserted following initial boot so that pme context is retained when transitioning from d3 to d0. for systems that do not require wake-up from d3, g_rst should be tied to prst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 12 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 6. pci address and data terminal i/o function name gfn no. gjg no. type function ad31 ad30 ad29 ad28 ad27 ad26 ad25 ad24 ad23 ad22 ad21 ad20 ad19 ad18 ad17 ad16 ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 k18 k19 l20 l18 l19 m20 m19 m18 n19 n18 p20 p19 r20 r19 p17 r18 v18 y19 w18 v17 u16 y18 w17 v16 w16 u14 y16 w15 v14 y15 w14 y14 k16 k18 l14 l15 l18 l19 l16 m15 m19 m14 n16 n19 n15 p18 p19 p16 t16 w17 v16 w16 t15 v15 w15 p14 t14 w14 p13 t13 v13 w13 n13 r12 i/o pci address/data bus. these signals make up the multiplexed pci address and data bus on the primary interface. during the address phase of a primary bus pci cycle, ad31ad0 contain a 32-bit address or other destination information. during the data phase, ad31ad0 contain data. c/be3 c/be2 c/be1 c/be0 m17 t20 w19 y17 m16 p15 v17 r14 i/o pci bus commands and byte enables. these signals are multiplexed on the same pci terminals. during the address phase of a primary bus pci cycle, c/be3 c/be0 define the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. c/be0 applies to byte 0 (ad7ad0), c/be1 applies to byte 1 (ad15ad8), c/be2 applies to byte 2 (ad23ad16), and c/be3 applies to byte 3 (ad31ad24). par y20 w18 i/o pci bus parity. in all pci bus read and write cycles, the PCI1450 calculates even parity across the ad31ad0 and c/be3 c/be0 buses. as an initiator during pci cycles, the PCI1450 outputs this parity indicator with a one-pclk delay. as a target during pci cycles, the calculated parity is compared to the initiator's parity indicator. a compare error results in the assertion of a parity error (perr ).
PCI1450 gfn/gjg pc card controller scps044 september 1998 13 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 7. pci interface control terminal i/o function name gfn no. gjg no. type function devsel v20 t18 i/o pci device select. the PCI1450 asserts devsel to claim a pci cycle as the target device. as a pci initiator on the bus, the PCI1450 monitors devsel until a target responds. if no target responds before timeout occurs, then the PCI1450 terminates the cycle with an initiator abort. frame t19 r18 i/o pci cycle frame. frame is driven by the initiator of a bus cycle. frame is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when frame is deasserted, the pci bus transaction is in the final data phase. gnt j20 j14 i pci bus grant. gnt is driven by the pci bus arbiter to grant the PCI1450 access to the pci bus after the current data transaction has completed. gnt may or may not follow a pci bus request, depending on the pci bus parking algorithm. gpio2/lock v19 v19 i/o pci bus general-purpose i/o pins or pci bus lock. gpio2/lock can be configured as pci lock and used to gain exclusive access downstream. since this functionality is not typically used, a general-purpose i/o may be accessed through this terminal. gpio2/lock defaults to a general-purpose input and can be configured through the gpio2 control register . idsel n20 m18 i initialization device select. idsel selects the PCI1450 during configuration space accesses. idsel can be connected to one of the upper 24 pci address lines on the pci bus. irdy t18 r19 i/o pci initiator ready. irdy indicates the pci bus initiator's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk where both irdy and trdy are asserted. until irdy and trdy are both sampled asserted, wait states are inserted. perr u18 u18 i/o pci parity error indicator. perr is driven by a pci device to indicate that calculated parity does not match par when perr is enabled through bit 6 of the command register . req k17 k15 o pci bus request. req is asserted by the PCI1450 to request access to the pci bus as an initiator. serr u19 u19 o pci system error. serr is an output that is pulsed from the PCI1450 when enabled through the command register , indicating a system error has occurred. the PCI1450 need not be the target of the pci cycle to assert this signal. when serr is enabled in the bridge control register , this signal also pulses, indicating that an address parity error has occurred on a cardbus interface. stop t17 t19 i/o pci cycle stop signal. stop is driven by a pci target to request the initiator to stop the current pci bus transaction. stop is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. trdy u20 r16 i/o pci target ready. trdy indicates the primary bus target's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of pclk when both irdy and trdy are asserted. until both irdy and trdy are asserted, wait states are inserted.
PCI1450 gfn/gjg pc card controller scps044 september 1998 14 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 8. system interrupt terminal i/o function name gfn no. gjg no. type function gpio3/inta v13 t12 i/o parallel pci interrupt. inta can be optionally mapped to gpi03 when parallel pci interrupts are used. see programmable interrupt subsystem for details on interrupt signaling. gpio3/inta defaults to a general-purpose input. irqser/intb w13 w12 i/o serial interrupt signal. irqser provides the irqser-style serial interrupting scheme. serialized pci interrupts can also be sent in the irqser stream. see programmable interrupt subsystem for details on interrupt signaling. this terminal can be used to signal pci intb when one of the parallel interrupt modes is selected in the device control register . irqmux7 irqmux6 irqmux5 irqmux4 irqmux3 irqmux2 irqmux1 irqmux0 y12 u11 w10 y9 w9 v9 u9 y8 p11 r10 r9 w9 t9 r8 t8 v8 o interrupt request/secondary functions multiplexed. the primary function of these terminals is to provide the isa-type irq signaling supported by the PCI1450. these interrupt multiplexer outputs can be mapped to any of 15 irqs. the device control register must be programmed for the isa irq interrupt mode and the irqmux routing register must have the irq routing programmed before these terminals are enabled. all of these terminals have secondary functions, such as pci intb , pc/pci dma request/grant, ring indicate output, and zoom video status, that can be selected with the appropriate programming of this register. when the secondary functions are enabled, the respective terminals are not available for irq routing. see the irqmux routing register for programming options. ri_out /pme y13 p12 o ring indicate out and power management event output. terminal provides an output for ring-indicate or pme signals. table 9. pc/pci dma terminal i/o function name gfn no. gjg no. type function pcgnt / irqmux6 u11 r10 i/o pc/pci dma grant. pcgnt is used to grant the dma channel to a requester in a system supporting the pc/pci dma scheme. interrupt request mux 6. when configured for irqmux6, this terminal provides the irqmux6 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 isa-type irqs. irqmux6 takes precedence over pcgnt , and should not be enabled in a system using pc/pci dma. this terminal is also used for the serial eeprom interface. pcreq / irqmux7 y12 p11 o pc/pci dma request. pcreq is used to request dma transfers as dreq in a system supporting the pc/pci dma scheme. interrupt request mux 7. when configured for irqmux7, this terminal provides the irqmux7 interrupt output of the interrupt multiplexer, and can be mapped to any of 15 isa-type irqs. irqmux7 takes precedence over pcreq , and should not be enabled in a system using pc/pci dma. this terminal is also used for the serial eeprom interface.
PCI1450 gfn/gjg pc card controller scps044 september 1998 15 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 10. zoom video terminal i/o and memory i/o name gfn no. gjg no. interface signal i/o type function zv_href a6 g7 a10 o horizontal sync to the zoom video port zv_vsync c7 a7 a11 o vertical sync to the zoom video port zv_y7 zv_y6 zv_y5 zv_y4 zv_y3 zv_y2 zv_y1 zv_y0 a3 b4 c5 b5 c6 d7 a5 b6 b5 a5 e6 b6 a6 f7 e7 b7 a20 a14 a19 a13 a18 a8 a17 a9 o video data to the zoom video port in yv:4:2:2 format zv_uv7 zv_uv6 zv_uv5 zv_uv4 zv_uv3 zv_uv2 zv_uv1 zv_uv0 d2 c3 b1 b2 a2 c4 b3 d5 c1 a2 b2 a3 b3 a4 b4 d5 a25 a12 a24 a15 a23 a16 a22 a21 o video data to the zoom video port in yv:4:2:2 format zv_sclk c2 b1 a7 o audio sclk pcm zv_mclk d3 c2 a6 o audio mclk pcm zv_pclk e1 e2 iois16 o pixel clock to the zoom video port zv_lrclk e3 e5 inpack o audio lrclk pcm zv_sdata e2 e1 spkr o audio sdata pcm zv_rsvd1 zv_rsvd0 c1 e4 d2 d1 a5 a4 o reserved. no connection in the pc card. zv_rsvd1 and zv_rsvd0 are put into the high-impedance state by host adapter.
PCI1450 gfn/gjg pc card controller scps044 september 1998 16 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 11. miscellaneous terminal i/o name gfn no. gjg no. i/o type function gpio0/leda1 v11 t10 i/o gpio0/socket activity led indicator 1. when gpio0/leda1 is configured as leda1, it provides an output indicating pc card socket 0 activity. otherwise, gpio0/leda1 can be configured as a general-purpose input and output, gpio0. the zoom video enable signal (zv_stat) can also be routed to this signal through the gpio0 control register . gpio0/leda1 defaults to a general-purpose input. gpio1/leda2 w11 v10 i/o gpio1/socket activity led indicator 2. when gpio1/leda2 is configured as leda2, it provides an output indicating pc card socket 1 activity. otherwise, gpio1/leda2 can be configured as a general-purpose input and output, gpio1. a csc interrupt can be generated on a gpdata change, and this input can be used for power switch overcurrent (oc) sensing. see gpio1 control register for programming details. gpio1/leda2 defaults to a general-purpose input. spkrout y10 p10 o speaker output. spkrout is the output to the host system that can carry spkr or caudio through the PCI1450 from the pc card interface. spkrout is driven as the xor combination of card spkr //caudio inputs. suspend y11 w10 i suspend. suspend is used to protect the internal registers from clearing when prst is asserted. see suspend mode for details.
PCI1450 gfn/gjg pc card controller scps044 september 1998 17 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 12. 16-bit pc card address and data (slots a and b) terminal gfn no. gjg no. i/o function name slot a 2 slot b 3 slot a 2 slot b 3 type function a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 t4 u2 u1 p4 r2 r1 p1 n2 m4 t1 t2 p2 n3 t3 m1 l1 m3 n1 v1 v2 v3 w2 w3 w4 v4 u5 c14 b15 c15 c16 a18 c17 b18 a20 c18 a17 a16 b17 a19 d14 d18 e18 b20 b19 a15 a14 b13 a13 c12 a12 b11 c11 r2 p6 p2 n5 n1 m5 m2 l5 l2 n4 p1 m4 m1 p4 k4 j5 l1 l4 r1 t1 t4 u2 v2 w3 v3 w4 e13 a14 e14 e15 b16 b17 a18 b19 d16 d15 b15 a17 b18 d14 d19 f15 c19 c18 f13 a13 a12 b12 e12 a11 b11 e11 o pc card address. 16-bit pc card address lines. a25 is the most-significant bit. d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 k3 j2 j4 h2 g1 w8 y7 v7 j1 j3 h1 h3 g2 v8 w7 y6 e19 e20 g18 g19 h18 b7 c8 a8 g17 f19 f20 g20 h19 a7 b8 d9 j1 h2 h6 g1 g6 w8 w7 r7 h4 h1 g4 g5 f2 t7 v7 p7 f18 g15 g19 h15 h18 e8 b8 e9 g14 g18 g13 h16 h19 d8 f8 d9 i/o pc card data. 16-bit pc card data lines. d15 is the most-significant bit. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal t4 is a_a25. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal c14 is b_a25.
PCI1450 gfn/gjg pc card controller scps044 september 1998 18 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 13. 16-bit pc card interface control (slots a and b) terminal gfn no. gjg no. i/o function name slot a 2 slot b 3 slot a 2 slot b 3 type function bvd1 (stschg /ri ) v6 a9 r6 e10 i battery voltage detect 1. bvd1 is generated by 16-bit memory pc cards that include batteries. bvd1 and bvd2 indicate the condition of the batteries on a memory pc card. both bvd1 and bvd2 are kept high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see exca card status-change interrupt configuration register for the enable bits. see exca card status-change register and the exca interface status register for the status bits for this signal. status change. stschg is used to alert the system to a change in the ready, write protect, or battery voltage dead condition of a 16-bit i/o pc card. ring indicate. ri is used by 16-bit modem cards to indicate a ring detection. bvd2 (spkr ) y5 d10 v5 d10 i battery voltage detect 2. bvd2 is generated by 16-bit memory pc cards that include batteries. bvd2 and bvd1 indicate the condition of the batteries on a memory pc card. both bvd1 and bvd2 are high when the battery is good. when bvd2 is low and bvd1 is high, the battery is weak and should be replaced. when bvd1 is low, the battery is no longer serviceable and the data in the memory pc card is lost. see exca card status-change interrupt configuration register for enable bits. see exca card status-change register and the exca interface status register for the status bits for this signal. speaker. spkr is an optional binary audio signal available only when the card and socket have been configured for the 16-bit i/o interface. the audio signals from cards a and b are combined by the PCI1450 and are output on spkrout. dma request. bvd2 can be used as the dma request signal during dma operations to a 16-bit pc card that supports dma. the pc card asserts bvd2 to indicate a request for a dma operation. cd1 cd2 g3 w6 h20 c9 f1 w6 h14 b9 i pc card detect 1 and pc card detect 2. cd1 and cd2 are internally connected to ground on the pc card. when a pc card is inserted into a socket, cd1 and cd2 are pulled low. for signal status, see exca interface status register . ce1 ce2 k1 l2 d20 d19 j2 k6 f16 e19 o card enable 1 and card enable 2. ce1 and ce2 enable even- and odd-numbered address bytes. ce1 enables even-numbered address bytes, and ce2 enables odd-numbered address bytes. inpack y1 d12 v1 d12 i input acknowledge. inpack is asserted by the pc card when it can respond to an i/o read cycle at the current address. dma request. inpack can be used as the dma request signal during dma operations from a 16-bit pc card that supports dma. if used as a strobe, the pc card asserts this signal to indicate a request for a dma operation. iord l4 e17 k2 e16 o i/o read. iord is asserted by the PCI1450 to enable 16-bit i/o pc card data output during host i/o read cycles. dma write. iord is used as the dma write strobe during dma operations from a 16-bit pc card that supports dma. the PCI1450 asserts iord during dma transfers from the pc card to host memory. iowr m2 c19 l6 d18 o i/o write. iowr is driven low by the PCI1450 to strobe write data into 16-bit i/o pc cards during host i/o write cycles. dma read. iowr is used as the dma write strobe during dma operations from a 16-bit pc card that supports dma. the PCI1450 asserts iowr during transfers from host memory to the pc card.
PCI1450 gfn/gjg pc card controller scps044 september 1998 19 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 13. 16-bit pc card interface control (slots a and b) (continued) terminal gfn no. gjg no. i/o function name slot a 2 slot b 3 slot a 2 slot b 3 type function oe l3 c20 k1 e18 o output enable. oe is driven low by the PCI1450 to enable 16-bit memory pc card data output during host memory read cycles. dma terminal count. oe is used as terminal count (tc) during dma operations to a 16-bit pc card that supports dma. the PCI1450 asserts oe to indicate tc for a dma write operation. ready (ireq ) y4 a10 t5 f10 i ready. the ready function is provided by ready when the 16-bit pc card and the host socket are configured for the memory-only interface. ready is driven low by the 16-bit memory pc cards to indicate that the memory card circuits are busy processing a previous write command. ready is driven high when the 16-bit memory pc card is ready to accept a new data transfer command. interrupt request. ireq is asserted by a 16-bit i/o pc card to indicate to the host that a device on the 16-bit i /o pc card requires service by the host software. ireq is high (deasserted) when no interrupt is requested. reg y2 b12 w2 d11 o attribute memory select. reg remains high for all common memory accesses. when reg is asserted, access is limited to attribute memory (oe or we active) and to the i/o space (iord or iowr active). attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. dma acknowledge. reg is used as a dma acknowledge (dack ) during dma operations to a 16-bit pc card that supports dma. the PCI1450 asserts reg to indicate a dma operation. reg is used in conjunction with the dma read (iowr ) or dma write (iord ) strobes to transfer data. reset w1 c13 t2 d13 o pc card reset. reset forces a hard reset to a 16-bit pc card. wait v5 b10 r5 a10 i bus cycle wait. wait is driven by a 16-bit pc card to delay the completion of (i.e., extend) the memory or i/o cycle in progress. we p3 d16 n7 a16 o write enable. we is used to strobe memory write data into 16-bit memory pc cards. we is also used for memory pc cards that employ programmable memory technologies. dma terminal count. we is used as tc during dma operations to a 16-bit pc card that supports dma. the PCI1450 asserts we to indicate tc for a dma read operation. wp (iois16 ) u7 b9 t6 a9 i write protect. wp applies to 16-bit memory pc cards. wp reflects the status of the write-protect switch on 16-bit memory pc cards. for 16-bit i/o cards, wp is used for the 16-bit port (iois16 ) function. i/o is 16 bits. iois16 applies to 16-bit i/o pc cards. iois16 is asserted by the 16-bit pc card when the address on the bus corresponds to an address to which the 16-bit pc card responds, and the i/o port that is addressed is capable of 16-bit accesses. dma request. wp can be used as the dma request signal during dma operations to a 16-bit pc card that supports dma. if used, the pc card asserts wp to indicate a request for a dma operation. vs1 vs2 y3 u3 a11 b14 v4 r4 f11 b13 i/o voltage sense 1 and voltage sense 2. vs1 and vs2 , when used in conjunction with each other, determine the operating voltage of the 16-bit pc card. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal p3 is a_we . 3 terminal name for slot b is preceded with b_. for example, the full name for terminal d16 is b_we .
PCI1450 gfn/gjg pc card controller scps044 september 1998 20 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 14. cardbus pc card interface system (slots a and b) terminal gfn no. gjg no. i/o function name slot a 2 slot b 3 slot a 2 slot b 3 type function cclk t1 a17 n4 d15 o cardbus pc card clock. cclk provides synchronous timing for all transactions on the cardbus interface. all signals except crst , cclkrun , cint , cstschg, caudio, ccd2:1 , and cvs2cvs1 are sampled on the rising edge of cclk, and all timing parameters are defined with the rising edge of this signal. cclk operates at the pci bus clock frequency, but it can be stopped in the low state or slowed down for power savings. cclkrun u7 b9 t6 a9 o cardbus pc card clock run. cclkrun is used by a cardbus pc card to request an increase in the cclk frequency, and by the PCI1450 to indicate that the cclk frequency is decreased. cardbus clock run (cclkrun ) follows the pci clock run (clkrun ). crst w1 c13 t2 d13 i/o cardbus pc card reset. crst is used to bring cardbus pc card-specific registers, sequencers, and signals to a known state. when crst is asserted, all cardbus pc card signals must be 3-stated, and the PCI1450 drives these signals to a valid logic level. assertion can be asynchronous to cclk, but deassertion must be synchronous to cclk. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal t1 is a_cclk. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal a17 is b_cclk.
PCI1450 gfn/gjg pc card controller scps044 september 1998 21 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 15. cardbus pc card address and data (slots a and b) terminal gfn no. gjg no. i/o function name slot a 2 slot b 3 slot a 2 slot b 3 type function cad31 cad30 cad29 cad28 cad27 cad26 cad25 cad24 cad23 cad22 cad21 cad20 cad19 cad18 cad17 cad16 cad15 cad14 cad13 cad12 cad11 cad10 cad9 cad8 cad7 cad6 cad5 cad4 cad3 cad2 cad1 cad0 w8 y7 w7 v7 y6 u5 v4 w4 w3 w2 v3 v2 t4 v1 u2 m4 m2 m3 l4 m1 l3 l2 l1 k3 j1 j4 j3 h2 h1 g1 h3 g2 b7 c8 b8 a8 d9 c11 b11 a12 c12 a13 b13 a14 c14 a15 b15 c18 c19 b20 e17 d18 c20 d19 e18 e19 g17 g18 f19 g19 f20 h18 g20 h19 w8 w7 v7 r7 p7 w4 v3 w3 v2 u2 t4 t1 r2 r1 p6 l2 l6 l1 k2 k4 k1 k6 j5 j1 h4 h6 h1 g1 g4 g6 g5 f2 e8 b8 f8 e9 d9 e11 b11 a11 e12 b12 a12 a13 e13 f13 a14 d16 d18 c19 e16 d19 e18 e19 f15 f18 g14 g19 g18 h15 g13 h18 h16 h19 i/o pc card address and data. these signals make up the multiplexed cardbus address and data bus on the cardbus interface. during the address phase of a cardbus cycle, cad31cad0 contain a 32-bit address. during the data phase of a cardbus cycle, cad31cad0 contain data. cad31 is the most-significant bit. cc/be3 cc/be2 cc/be1 cc/be0 y2 t3 n1 k1 b12 d14 b19 d20 w2 p4 l4 j2 d11 d14 c18 f16 i/o cardbus bus commands and byte enables. cc/be3 cc/be0 are multiplexed on the same cardbus terminals. during the address phase of a cardbus cycle, cc/be3 cc/be0 defines the bus command. during the data phase, this 4-bit bus is used as byte enables. the byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. cc/be0 applies to byte 0 (cad7cad0), cc/be1 applies to byte 1 (cad15cad8), cc/be2 applies to byte 2 (cad23cad8), and cc/be3 applies to byte 3 (cad31cad24). cpar n3 a19 m1 b18 i/o cardbus parity. in all cardbus read and write cycles, the PCI1450 calculates even parity across the cad and cc/be buses. as an initiator during cardbus cycles, the PCI1450 outputs cpar with a one-cclk delay. as a target during cardbus cycles, the calculated parity is compared to the initiator's parity indicator; a compare error results in a parity error assertion. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal n3 is a_cpar. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal a19 is b_cpar.
PCI1450 gfn/gjg pc card controller scps044 september 1998 22 post office box 655303 ? dallas, texas 75265 terminal functions (continued) table 16. cardbus pc card interface control (slots a and b) terminal gfn no. gjg no. i/o function name slot a 2 slot b 3 slot a 2 slot b 3 type function caudio y5 d10 v5 d10 i cardbus audio. caudio is a digital input signal from a pc card to the system speaker. the PCI1450 supports the binary audio mode and outputs a binary signal from the card to spkrout. cblock p1 b18 m2 a18 i/o cardbus lock. cblock is used to gain exclusive access to a target. ccd1 g3 h20 f1 h14 i cardbus detect 1 and cardbus detect 2. ccd1 and ccd2 are used in conjunction with cvs1 and cvs2 to identify card insertion and interrogate cards to determine the ccd2 w6 c9 w6 b9 i w ith cvs1 an d cvs2 t o id en tif y car d i nser ti on an d i n t erroga t e car d s t o d e t erm i ne th e operating voltage and card type. cdevsel r2 a18 n1 b16 i/o cardbus device select. the PCI1450 asserts cdevsel to claim a cardbus cycle as the target device. as a cardbus initiator on the bus, the PCI1450 monitors cdevsel until a target responds. if no target responds before timeout occurs, then the PCI1450 terminates the cycle with an initiator abort. cframe u1 c15 p2 e14 i/o cardbus cycle frame. cframe is driven by the initiator of a cardbus bus cycle. cframe is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. when cframe is deasserted, the cardbus bus transaction is in the final data phase. cgnt p3 d16 n7 a16 i cardbus bus grant. cgnt is driven by the PCI1450 to grant a cardbus pc card access to the cardbus bus after the current data transaction has been completed. cint y4 a10 t5 f10 i cardbus interrupt. cint is asserted low by a cardbus pc card to request interrupt servicing from the host. cirdy t2 a16 p1 b15 i/o cardbus initiator ready. cirdy indicates the cardbus initiator's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk when both cirdy and ctrdy are asserted. until cirdy and ctrdy are both sampled asserted, wait states are inserted. cperr p2 b17 m4 a17 i/o cardbus parity error. cperr is used to report parity errors during cardbus transactions, except during special cycles. it is driven low by a target two clocks following that data when a parity error is detected. creq y1 d12 v1 d12 i cardbus request. creq indicates to the arbiter that the cardbus pc card desires use of the cardbus bus as an initiator. cserr v5 b10 r5 a10 i cardbus system error. cserr reports address parity errors and other system errors that could lead to catastrophic results. cserr is driven by the card synchronous to cclk, but deasserted by a weak pullup, and may take several cclk periods. the PCI1450 can report cserr to the system by assertion of serr on the pci interface. cstop r1 c17 m5 b17 i/o cardbus stop. cstop is driven by a cardbus target to request the initiator to stop the current cardbus transaction. cstop is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. cstschg v6 a9 r6 e10 i cardbus status change. cstschg is used to alert the system to a change in the card's status and is used as a wake-up mechanism. ctrdy p4 c16 n5 e15 i/o cardbus target ready. ctrdy indicates the cardbus target's ability to complete the current data phase of the transaction. a data phase is completed on a rising edge of cclk, when both cirdy and ctrdy are asserted; until this time, wait states are inserted. cvs1 cvs2 y3 u3 a11 b14 v4 r4 f11 b13 i/o cardbus voltage sense 1 and cardbus voltage sense 2. cvs1 and cvs2 are used in conjunction with ccd1 and ccd2 to identify card insertion and interrogate cards to determine the operating voltage and card type. 2 terminal name for slot a is preceded with a_. for example, the full name for terminal y5 is a_caudio. 3 terminal name for slot b is preceded with b_. for example, the full name for terminal d10 is b_caudio.
PCI1450 gfn/gjg pc card controller scps044 september 1998 23 post office box 655303 ? dallas, texas 75265 i/o characteristics figure 3 shows a 3-state bidirectional buffer illustration for reference. the table, recommended operating conditions provides the electrical characteristics of the inputs and outputs. the PCI1450 meets the ac specifications of the pc card 95 standard and the pci bus 2.1 specifications. tied for open drain oe pad v ccp figure 3. 3-state bidirectional buffer clamping rail splits the i/o sites can be pulled through a clamping diode to a power rail for protection. the core power supply is independent of the clamping rails. the clamping (protection) diodes are required if the signaling environment on an i/o is system dependent. for example, pci signaling can be either 3.3 vdc or 5.0 vdc, and the PCI1450 must reliably accommodate both voltage levels. this is accomplished by using a 3.3-v buffer with tolerance (protection) at v ccp . if a system design requires a 5.0-v pci bus, then the v ccp would be connected to the 5.0-v power supply. a standard die has only one clamping rail for the sites as shown in figure 3. after the terminal assignments are fixed, the fabrication facility will support a design by splitting the clamping rail for customization. the PCI1450 requires five separate clamping rails since it supports a wide range of features. the five rails are listed and defined in the table, recommended operating conditions . pci interface this section describes the pci interface of the PCI1450, and how the device responds and participates in pci bus cycles. the PCI1450 provides all required signals for pci master/slave devices, and may operate in either 5-v or 3.3-v pci signaling environments by connecting the v ccp terminals to the desired signaling level. pci bus lock (lock ) the bus locking protocol defined in the pci specification is not highly recommended, but is provided on the PCI1450 as an additional compatibility feature. the pci lock terminal is multiplexed with gpio2, and the terminal function defaults to a general-purpose input (gpi). the use of lock is only supported by pci-to-cardbus bridges in the downstream direction (away from the processor). pci lock indicates an atomic operation that may require multiple transactions to complete. when lock is asserted, nonexclusive transactions may proceed to an address that is not currently locked. a grant to start a transaction on the pci bus does not guarantee control of lock ; control of lock is obtained under its own protocol. it is possible for different initiators to use the pci bus while a single master retains ownership of lock . to avoid confusion with the pci bus clock, the cardbus signal for this protocol is cblock . an agent may need to do an exclusive operation because a critical memory access to memory might be broken into several transactions, but the master wants exclusive rights to a region of memory. the granularity of the lock is defined by pci to be 16 bytes aligned. the lock protocol defined by pci allows a resource lock without interfering with nonexclusive, real-time data transfer, such as video.
PCI1450 gfn/gjg pc card controller scps044 september 1998 24 post office box 655303 ? dallas, texas 75265 the pci bus arbiter may be designed to support only complete bus locks using the lock protocol. in this scenario the arbiter will not grant the bus to any other agent (other than the lock master) while lock is asserted. a complete bus lock may have a significant impact on the performance of the video. the arbiter that supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified line when a locked operation is in progress. the PCI1450 supports all lock protocol associated with pci-to-pci bridges, as also defined for pci-to-cardbus bridges. this includes disabling write posting while a locked operation is in progress, which can solve a potential deadlock when using devices such as pci-to-pci bridges. the potential deadlock can occur if a cardbus target supports delayed transactions, and blocks access as the target until it completes a delayed read. this target characteristic is prohibited by the 2.1 pci specification, and the issue is resolved by the pci master using lock . loading the subsystem identification (eeprom interface) the subsystem vendor id register and subsystem id register make up a double-word of pci configuration space located at offset 40h for functions 0 and 1. this doubleword register, used for system and option card (mobile dock) identification purposes, is required by some operating systems. implementation of this unique identifier register is a pc `97 requirement. the PCI1450 offers two mechanisms to load a read-only value into the subsystem registers. the first mechanism relies upon the system bios providing the subsystem id value. the default access mode to the subsystem registers is read-only, but the access mode may be made read/write by clearing the subsysrw bit in the system control register (bit 5 of the system control register , offset 80h). once this bit is cleared (0), the bios may write a subsystem identification value into the registers at offset 40h. the bios must set the subsysrw bit such that the subsystem vendor id register and subsystem id register are limited to read-only access. this approach saves the added cost of implementing the serial eeprom. in some conditions, such as in a docking environment, the subsystem vendor id register and subsystem id register must be loaded with a unique identifier through a serial eeprom interface. the PCI1450 loads the double-word of data from the serial eeprom after a reset of the primary bus. the suspend input gates the prst and g_rst from the entire PCI1450 core, including the serial eeprom state machine. refer to suspend mode for details on using suspend . the PCI1450 provides a two-line serial bus interface to the serial eeprom. the system designer must implement a pulldown resistor on the PCI1450 latch terminal to indicate the serial eeprom mode. only when this pulldown resistor is present will the PCI1450 attempt to load data through the serial eerpom interface. the serial eeprom interface is a two-pin interface with one data signal (sda) and one clock signal (scl). the sda signal is mapped to the PCI1450 irqmux6 terminal and the scl signal is mapped to the PCI1450 irqmux7 terminal. figure 4 illustrates a typical PCI1450 application using the serial eeprom interface.
PCI1450 gfn/gjg pc card controller scps044 september 1998 25 post office box 655303 ? dallas, texas 75265 irqmux7 irqmux6 latch v cc a0 a1 a2 scl sda PCI1450 serial eeprom figure 4. serial eeprom application as stated above, when the PCI1450 is reset by g_rst , the subsystem data is read automatically from the eeprom. the PCI1450 masters the serial eeprom bus and reads four bytes as described in figure 5. s slave address b6 b5 b4 b3 b2 b1 b0 0 a b7 b6 b5 b4 b3 b2 b1 b0 a s b6 b5 b4 b3 b2 b1 b0 1 a word address slave address r/w# restart r/w# data byte 0 m p data byte 1 m data byte 2 m data byte 3 m s/p start/stop condition a slave acknowledgment m master acknowledgment figure 5. eeprom interface subsystem data collection the eeprom is addressed at word address 00h, as indicated in figure 5, and the address auto-increments after each byte transfers according to the protocol. thus, to provide the subsystem register with data aabbccddh the eeprom should be programmed with address 0 = aah, 1 = bbh, 2 = cch, and 3 = ddh. the serial eeprom is addressed at slave address 1010000b by the PCI1450. all hardware address bits for the eeprom should be tied to the appropriate level to achieve this address. the serial eeprom chip in the sample application circuit, figure 4, assumes the 1010b high address nibble. the lower three address bits are terminal inputs to the chip, and the sample application shows these terminal inputs tied to gnd. the serial eeprom interface signals require pullup resistors. the serial eeprom protocol allows bidirectional transfers. both the scl and sda signals are 3-stated and pulled high when the bus is not active. when the sda line transitions to a logic low, this signals a start condition (s). a low-to-high transition of sda while scl is high is defined as the stop condition (p). one bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse, as changes in the data line at this time will be interpreted as a control signal. data is valid and stable during the clock high period. figure 6 illustrates this protocol.
PCI1450 gfn/gjg pc card controller scps044 september 1998 26 post office box 655303 ? dallas, texas 75265 sda scl start condition stop condition change of data allowed data line stable, data valid figure 6. serial eeprom start/stop conditions and bit transfers each address byte and data transfer is followed by an acknowledge bit, as indicated in figure 5. when the PCI1450 transmits the addresses, it returns the sda signal to the high state and 3-states the line. the PCI1450 then generates an scl clock cycle and expects the eeprom to pull down the sda line during the acknowledge pulse. this procedure is referred to as a slave acknowledge with the PCI1450 transmitter and the eeprom receiver. figure 7 illustrates general acknowledges. during the data byte transfers from the serial eeprom to the PCI1450, the eeprom clocks the scl signal. after the eeprom transmits the data to the PCI1450, it returns the sda signal to the high state and 3-states the line. the eeprom then generates an scl clock cycle and expects the PCI1450 to pull down the sda line during the acknowledge pulse. this procedure is referred to as a master acknowledge with the eeprom transmitter and the PCI1450 receiver. figure 7 illustrates general acknowledges. scl from master 123 78 9 sda output by transmitter sda output by receiver figure 7. serial eeprom protocol acknowledge eeprom interface status information is communicated through the general status register located at pci offset 85h. the eedetect bit in this register indicates whether or not the PCI1450 serial eeprom circuitry detects the pulldown resistor on latch. an error condition, such as a missing acknowledge, results in the dataerr bit being set. the eebusy bit is set while the subsystem id register is loading (serial eeprom interface is busy). pc card applications overview this section describes the pc card interfaces of the PCI1450. a discussion is provided on pc card recognition, which details the card interrogation procedure. the card powering procedure is discussed in this section including the protocol of the p2c power switch interface. the internal zv buffering provided by the PCI1450 and programming model is detailed in this section. also, standard pc card register models are described, as well as a brief discussion of the pc card software protocol layers.
PCI1450 gfn/gjg pc card controller scps044 september 1998 27 post office box 655303 ? dallas, texas 75265 pc card insertion/removal and recognition the 1995 pc card standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold, unpowered socket. through this interrogation, card voltage requirements and interface (16-bit vs. cardbus) are determined. the scheme uses the cd1 , cd2 , vs1 , and vs2 signals (ccd1 , ccd2 , cvs1, cvs2 for cardbus). a pc card designer connects these four pins in a certain configuration depending on the type of card and the supply voltage. the encoding scheme for this, defined in the 1997 pc card standard, is shown in table 17. table 17. pc card card detect and voltage sense connections cd2 //ccd2 cd1 //ccd1 vs2 //cvs2 vs1 //cvs1 key interface voltage ground ground open open 5 v 16-bit pc card 5 v ground ground open ground 5 v 16-bit pc card 5 v and 3.3 v ground ground ground ground 5 v 16-bit pc card 5 v, 3.3 v, and x.x v ground ground open ground lv 16-bit pc card 3.3 v ground connect to cvs1 open connect to ccd1 lv cardbus pc card 3.3 v ground ground ground ground lv 16-bit pc card 3.3 v and x.x v connect to cvs2 ground connect to ccd2 ground lv cardbus pc card 3.3 v and x.x v connect to cvs1 ground ground connect to ccd2 lv cardbus pc card 3.3 v, x.x v, and y.y v ground ground ground open lv 16-bit pc card y.y v connect to cvs2 ground connect to ccd2 open lv cardbus pc card y.y v ground connect to cvs2 connect to ccd1 open lv cardbus pc card x.x v and y.y v connect to cvs1 ground open connect to ccd2 lv cardbus pc card y.y v ground connect to cvs1 ground connect to ccd1 reserved ground connect to cvs2 connect to ccd1 ground reserved p2c power switch interface (tps2202a/2206) a power switch with a pcmcia-to-peripheral control (p2c) interface is required for the pc card powering interface. the ti tps2206 (or tps2202a) dual-slot pc card power-interface switch provides the p2c interface to the clock, data, and latch terminals of the PCI1450. figure 8 shows the terminal assignments of the tps2206. figure 9 illustrates a typical application where the PCI1450 represents the pcmcia controller. there are two ways to provide a clock source to the power switch interface. the first method is to provide an external clock source such as a 32 khz real time clock to the clock terminal. the second method is to use the internal ring oscillator. if the internal ring oscillator is used, then the PCI1450 provides its own clock source for the pc card interrogation logic and the power switch interface. the mode of operation is determined by the setting of bit 27 of the system control register (pci offset 80h). this bit is encoded as follows: 0 = clock terminal (terminal u12) is an input (default). 1 = clock terminal is an output that utilizes the internal oscillator. a 43 k pulldown resistor should be tied to the clock pin.
PCI1450 gfn/gjg pc card controller scps044 september 1998 28 post office box 655303 ? dallas, texas 75265 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5v 5v data clock latch reset 12v avpp avcc avcc avcc gnd nc reset 3.3v 5v nc nc nc nc nc 12v bvpp bvcc bvcc bvcc nc oc 3.3v 3.3v nc no internal connection figure 8. tps2206 terminal assignments 3 v pp1 v pp2 v cc pc card a tps2206 v cc v pp1 v pp2 v cc pc card b v cc avpp avcc avcc avcc bvpp bvcc bvcc bvcc 12v 5v 3.3v reset reset serial i/f power supply 12v 5v 3.3v supervisor PCI1450 pc card interface (68 pins/socket) figure 9. tps2206 typical application zoomed video support the zoomed video (zv) port on the PCI1450 provides an internally buffered 16-bit zv pc card data path. this internal routing is programmed through the multimedia control register . figure 9 summarizes the zoomed video subsystem implemented in the PCI1450, and details the bit functions found in the multimedia control register . an output port (portsel) is always selected. the PCI1450 defaults to socket 0 (see the multimedia control register ). when zvouten is enabled, the zoom video output terminals are enabled and allow the PCI1450 to route the zoom video data. however, no data is transmitted unless either zven0 or zven1 is enabled in the multimedia control register . if the portsel maps to a card port that is disabled (zven =0 or zven1 = 0), then the zoom video port is driven low (i.e., no data is transmitted).
PCI1450 gfn/gjg pc card controller scps044 september 1998 29 post office box 655303 ? dallas, texas 75265 pc card i/f card output enable logic pc card socket 0 zven0 pc card i/f pc card socket 1 zven1 portsel zvouten zvstat note: zvstat must be enabled through the gpio control register 19 video signals 4 audio signals vga audio codec zoomed video subsystem notes: a. zvstat must be enabled through the gpio control register. figure 10. zoomed video subsystem zoomed video auto detect zoomed video auto detect, when enabled, allows the PCI1450 to automatically detect zoomed video data by sensing the pixel clock from each socket and/or from a third zoomed video source that may exist on the motherboard. the PCI1450 automatically switches the internal zoomed video mux to route the zoomed video stream to the PCI1450's zoomed video output port. this eliminates the need for software to switch the internal mux using the multimedia control register (pci offset 84h, bits 6 and 7). the PCI1450 can be programmed to switch a third zoomed video source by programming irqmux2 as a zoomed video pixel clock sense pin and connecting this pin to the pixel clock of the third zoomed video source. zvstat may then be programmed onto irqmux4 and this signal may switch the zoomed video buffers from the third zoomed video source. to account for the possibility of several zoomed video sources being enabled at the same time, a programmable priority scheme may be enabled.
PCI1450 gfn/gjg pc card controller scps044 september 1998 30 post office box 655303 ? dallas, texas 75265 the PCI1450 defaults with zoomed video auto-detect disabled so that it will function exactly like the pci1250a. to enable zoomed video auto-detect and the programmable priority scheme, the following bits must be set: multimedia control register (pci offset 84h) bit 5: writing a 1b enables zoomed video auto-detect multimedia control register (pci offset 84h) bits 42: set the programmable priority scheme 000 = slot a, slot b, external source 001 = slot a, external source, slot b 010 = slot b, slot a, external source 011 = slot b, external source, slot a 100 = external source, slot a, slot b 101 = external source, slot b, slot a 110 = external source, slot b, slot a 111 = reserved if it is desired to switch a third zoomed video source, then the following bits must also be set: irqmux routing register (pci offset 8ch), bits 118: write 0010b to program irqmux2 as a pixel clock input pin. irqmux routing register (pci ofset 8ch), bits 1916: write 0001b to program irqmux4 as a zvstat pin. pc card i/f card output enable logic pc card socket 0 zven0 pc card i/f pc card socket 1 zven1 irqmux2 zvstat enable 23 19 video signals 4 audio signals vga audio codec zoomed video subsystem pixel clock sense pixel clock sense auto z/v arbiter buffers zv data pixel clock sense programmed on irqmux2 3rd zoomed video source figure 11. zoomed video with auto detect enabled
PCI1450 gfn/gjg pc card controller scps044 september 1998 31 post office box 655303 ? dallas, texas 75265 ultra zoomed video ultra zoomed video is an enhancement to the PCI1450's dma engine and is intended to improve the 16-bit bandwidth for mpeg i and mpeg ii decoder pc cards. this enhancement allows the 1450 to fetch 32 bits of data from memory versus the 11xx/12xx 16-bit fetch capability. this enhancement allows a higher sustained throughput to the 16-bit pc card because the 1450 prefetches an extra 16 bits (32 bits total) during each pci read transaction. if the pci bus becomes busy, then the 1450 has an extra 16 bits of data to perform back-to-back 16-bit transactions to the pc card before having to fetch more data. this feature is built into the dma engine and software is not required to enable this enhancement. note: the 11xx and 12xx series cardbus controllers have enough 16-bit bandwidth to support mpeg ii pc card decoders. but it was decided to improve the bandwidth even more in the 14xx series cardbus controllers. d3_stat pin additional functionality added for the 1450 versus the 1250a/1251 series is the d3_stat (d3 status) pin. this pin is asserted under the following two conditions (both conditions must be true before d3_stat is asserted): function 0 and function 1 are placed in d3 pme is enabled the intent of including this feature in the PCI1450 is to use this pin to switch an external v cc /v aux switch. this feature can be programmed on gpio1 pin (terminal w11) by writing 01b to bits 76 of the gpio1 control register (pci offset 89h). internal ring oscillator the internal ring oscillator provides an internal clock source for the PCI1450 so that neither the pci clock nor an external clock is required in order for the PCI1450 to power down a socket or interrogate a pc card. this internal oscillator operates nominally at 16 khz and can be enabled by setting bit 27 of the system control register (pci offset 80h) to a 1b. this function is disabled by default. spkrout usage the spkrout signal carries the digital audio signal from the pc card to the system. when a 16-bit pc card is configured for i/o mode, the bvd2 pin becomes spkr . this terminal, also used in cardbus applications, is referred to as caudio. spkr passes a ttl level digital audio signal to the PCI1450. the cardbus caudio signal also can pass a single amplitude, binary waveform. the binary audio signals from the two pc card sockets are xor'ed in the PCI1450 to produce spkrout. figure 12 illustrates the spkrout connection. bit 1, card control register (offset 91h) speaker driver card a spkrout enable card b spkrout enable card b spkr card a spkr bit 1, card control register (offset 91h) card a spkrout enable card b spkrout enable spkrout figure 12. spkrout connection to speaker driver the spkrout signal is typically driven only by pc modem cards. to verify the spkrout on the PCI1450, a sample circuit was constructed, and this simplified schematic is provided below. the pci1130/1131 required a pullup resistor on the suspend /spkrout terminal. since the PCI1450 does not multiplex any other function on spkrout, this terminal does not require a pullup resistor.
PCI1450 gfn/gjg pc card controller scps044 september 1998 32 post office box 655303 ? dallas, texas 75265 spkrout v cc v cc speaker lm386 3 7 2 6 4 1 8 + figure 13. simplified test schematic led socket activity indicators the socket activity leds indicate when an access is occurring to a pc card. the led signals are multiplexed with general-purpose inputs and outputs (gpios); the default for these terminals is gpi. when configured for led outputs, these terminals output an active high signal to indicate socket activity. leda1 indicates socket 0 (card a) activity, and leda2 indicates socket 1 (card b) activity. the active-high led signal is driven for 64 ms durations. when the led is not being driven high, then it is driven to a low state. either of the two circuits illustrated in figure 14 can be implemented to provide the led signaling, and it is left for the board designer to implement the circuit to best fit the application. PCI1450 application- specific delay current limiting r 500 w led PCI1450 current limiting r 500 w led figure 14. two sample led circuits as indicated, the led signals are driven for 64 ms, and this is accomplished by a counter circuit. to avoid the possibility of the leds appearing to be stuck when the pci clock is stopped, the led signaling is cut off when either the suspend signal is asserted or when the pci clock is to be stopped per the clkrun protocol. furthermore, if any additional socket activity occurs during this counter cycle, then the counter is reset and the led signal remains driven. if socket activity is frequent (at least once every 64 ms), then the led signals will remain driven. pc card 16 dma support the PCI1450 supports both pc/pci (centralized) dma and a distributed dma slave engine for 16-bit pc card dma support. the distributed dma (ddma) slave register set provides the programmability necessary for the slave ddma engine. table 18 provides the ddma register configuration.
PCI1450 gfn/gjg pc card controller scps044 september 1998 33 post office box 655303 ? dallas, texas 75265 table 18. distributed dma registers type register name dma base address offset r reserved page current address 00h w reser v ed page base address r reserved reserved current count 04h w reser v ed reser v ed base count r n/a reserved n/a status 08h w mode reser v ed request command r multichannel reserved n/a reserved 0ch w mask reser v ed master clear reser v ed cardbus socket register the PCI1450 contains all registers for compatibility with the latest pci to pcmcia cardbus bridge specification. these registers exist as the cardbus socket registers, and are listed in table 19. table 19. cardbus socket registers register name offset socket event 00h socket mask 04h socket present state 08h socket force event 0ch socket control 10h reserved 14h reserved 18h reserved 1ch socket power management 20h
PCI1450 gfn/gjg pc card controller scps044 september 1998 34 post office box 655303 ? dallas, texas 75265 programmable interrupt subsystem interrupts provide a way for i/o devices to let the microprocessor know that they require servicing. the dynamic nature of pc cards, and the abundance of pc card i/o applications require substantial interrupt support from the PCI1450. the PCI1450 provides several interrupt signaling schemes to accommodate the needs of a variety of platforms. the different mechanisms for dealing with interrupts in this device are based upon various specifications and industry standards. the exca register set provides interrupt control for some 16-bit pc card functions, and the cardbus socket register set provides interrupt control for the cardbus pc card functions. the PCI1450 is therefore backward compatible with existing interrupt control register definitions, and new registers have been defined where required. the PCI1450 detects pc card interrupts and events at the pc card interface and notifies the host controller via one of several interrupt signaling protocols. to simplify the discussion of interrupts in the PCI1450, pc card interrupts are classified as either card status change (csc) or as functional interrupts. the method by which any type of PCI1450 interrupt is communicated to the host interrupt controller varies from system to system. the PCI1450 offers system designers the choice of using parallel pci interrupt signaling, parallel isa type irq interrupt signaling, or the irqser serialized isa and/or pci interrupt protocol. traditional isa irq signaling is provided through eight irqmux terminals. it is possible to use the parallel pci interrupts in combination with either parallel irqs or serialized irqs, as detailed in the sections that follow. pc card functional and card status change interrupts pc card functional interrupts are defined as requests from a pc card application for interrupt service. they are indicated by asserting specially defined signals on the pc card interface. functional interrupts are generated by 16-bit i/o pc cards and by cardbus pc cards. card status change (csc) type interrupts are defined as events at the pc card interface which are detected by the PCI1450 and may warrant notification of host card and socket services software for service. csc events include both card insertion and removal from pc card sockets, as well as transitions of certain pc card signals. table 20 summarizes the sources of pc card interrupts and the type of card associated with them. csc and functional interrupt sources are dependent upon the type of card inserted in the pc card socket. the three types of cards that may be inserted into any pc card socket are: 16-bit memory card, 16-bit i/o card, and cardbus cards. functional interrupt events are valid only for 16-bit i/o and cardbus cards, that is, the functional interrupts are not valid for 16-bit memory cards. furthermore, card insertion and removal type csc interrupts are independent of the card type.
PCI1450 gfn/gjg pc card controller scps044 september 1998 35 post office box 655303 ? dallas, texas 75265 table 20. pc card interrupt events and description card type event type signal description csc bvd1 (stschg) // a transition on the bvd1 si g nal indicates a chan g e battery conditions csc () cstschg gg in the pc card battery conditions. 16-bit memory y (bvd1, bvd2) csc bvd2 (spkr ) // caudio a transition on the bvd2 signal indicates a change in the pc card battery conditions. wait states (ready) csc ready (ireq ) // cint a transition on the ready signal indicates a change in the ability of the memory pc card to accept or provide data. 16 bit i/o change in card status (stschg) csc bvd1 (stschg ) // cstschg the assertion of the stschg signal indicates a status change on the pc card. 16 - bit i/o interrupt request (ireq) functional ready (ireq ) // cint the assertion of the ireq signal indicates an interrupt request from the pc card. change in card status (cstschg) csc bvd1 (stschg ) // cstschg the assertion of the cstschg signal indicates a status change on the pc card. cardbus interrupt request (cint ) functional ready (ireq ) // cint the assertion of the cint signal indicates an interrupt request from the pc card. power cycle complete csc n/a an interrupt is generated when a pc card power-up cycle has completed. all pc cards card insertion or removal csc cd1 // ccd1, cd2 // ccd2 a transition on either the cd1 //ccd1 signal or the cd2 //ccd2 signal indicates an insertion or removal of a 16-bit // cardbus pc card. power cycle complete csc n/a an interrupt is generated when a pc card power-up cycle has completed. the signal naming convention for pc card signals describes the function for 16-bit memory and i/o cards, as well as cardbus. for example, the ready(ireq )//cint signal includes the ready signal for 16-bit memory cards, the ireq signal for 16-bit i/o cards, and the cint signal for cardbus cards. the 16-bit memory card signal name is first, with the i/o card signal name second enclosed in parentheses. the cardbus signal name follows after a forward double slash (//). the pc card standard describes the power-up sequence that must be followed by the PCI1450 when an insertion event occurs and the host requests that the socket v cc and v pp be powered. upon completion of this power-up sequence, the PCI1450 interrupt scheme may be used to notify the host system, as in indicated in table 20, denoted by the power cycle complete event. this interrupt source is considered a PCI1450 internal event because it does not depend on a signal change at the pc card interface, but rather the completion of applying power to the socket. interrupt masks and flags host software may individually mask, or disable, most of the potential interrupt sources listed in table 21 by setting the appropriate bits in the PCI1450. by individually masking the interrupt sources listed in these tables, software can control which events will cause a PCI1450 interrupt. host software has some control over which system interrupt the PCI1450 will assert by programming the appropriate routing registers. the PCI1450 allows host software to route pc card csc and pc card functional interrupts to separate system interrupts. a discussion of interrupt routing is somewhat specific to the interrupt signaling method used, and will be discussed in more detail in the next few sections. when an interrupt is signaled by the PCI1450, the interrupt service routine must be able to discern which of the events in table 21 caused the interrupt. internal registers in the PCI1450 provide flags which report which of the interrupt sources was the cause of an interrupt. by reading these status bits, the interrupt service routine can determine which action is to be taken.
PCI1450 gfn/gjg pc card controller scps044 september 1998 36 post office box 655303 ? dallas, texas 75265 table 21 details the registers and bits associated with masking and reporting potential interrupts. all interrupts may be masked except the functional pc card interrupts, and an interrupt status flag is available for all types of interrupts. table 21. PCI1450 interrupt masks and flags registers card type event mask flag battery conditions exca offset 05h/45h/805h exca offset 04h/44h/804h battery conditions (bvd1 bvd2) exca offset 05h/45h/805h bits1&0 exca offset 04h/44h/804h bits1&0 16-bit memory (bvd1 , bvd2) bit s 1 & 0 bit s 1 & 0 16 - bit memory wait states (ready) exca offset 05h/45h/805h bit 2 exca offset 04h/44h/804h bit 2 16 bit i/o change in card status (stschg ) exca offset 05h/45h/805h bit 0 exca offset 04h/44h/804h bit 0 16 - bit i/o interrupt request (ireq ) always enabled pci configuration offset 91h bit 0 all 16-bit pc cards power cycle complete exca offset 05h/45h/805h bit 3 exca offset 04h/44h/804h bit 3 change in card status (cstschg) socket mask register bit 0 socket event register bit 0 cardbus interrupt request (cint ) always enabled pci configuration offset 91h bit 0 cardb u s power cycle complete socket mask register bit 3 socket event register bit 3 card insertion or removal socket mask register bits 2 & 1 socket event register bits 2 & 1 notice that there is not a mask bit to stop the PCI1450 from passing pc card functional interrupts through to the appropriate interrupt scheme. functional interrupts should not be fired until the pc card is initialized and powered. there are various methods of clearing the interrupt flag bits listed in table 21. the flag bits in the exca registers (16-bit pc card related interrupt flags) may be cleared by two different methods. one method is an explicit write of 1 to the flag bit to clear, and the other is a reading of the flag bit register. the selection of flag bit clearing is made by bit 2 in the global control register (exca offset 1eh/5eh/81eh), and defaults to the flag cleared on read method. the cardbus related interrupt flags can only be cleared by an explicit write of 1 to the interrupt flag in the socket event register . although some of the functionality is shared between the cardbus registers and the exca registers, software should not program the chip through both register sets when a cardbus card is functioning. legacy interrupt multiplexer the irq multiplexer implemented in the PCI1450 provides a mechanism to route the irqmux signals to any of the 15 legacy irq signals. the irqmux76 signals share the pc/pci dma terminals, and take precedence when routed. the other 6 irqmux signals (irqmux5irqmux0) are available in all platforms. to use the irqmux interrupt signaling, software must program the device control register , located at pci offset 92h, to select the legacy irq signaling scheme. figure 15 illustrates the irqmux functionality. this illustration describes only the pcreq/irqmux7/scl signal.
PCI1450 gfn/gjg pc card controller scps044 september 1998 37 post office box 655303 ? dallas, texas 75265 pcreq irqmux routing register eeprom scl system control register (bit 3): pcreq/irqmux7/scl 0000 0001 0010 1111 1 0 when bit 3 = 0 eeprom scl is routed on irqmux7 when bit 3 = 1 pcreq is routed on irqmux7 figure 15. interrupt mux functionality example of irqmux7 routing if parallel isa irqs are selected in the device control register , then the irqmux routing register , located at pci offset 8ch, must be programmed with the associated isa irq connections. the PCI1450 supports up to eight parallel isa irq signal connections, irqmux7irqmux0. figure 16 is an example PCI1450 irq implementation that provides eight isa interrupts. the system in this example cannot support pc/pci dma since all eight isa irqs are used. in this example, the irqmux7 and irqmux6 terminals are used to signal isa irqs, and are not available for pc/pci dma. for systems not using all eight irqs, pc/pci dma can be implemented and coexist with isa irqs by using irqmux6 and irqmux7 for pc/pci dma, i.e., legacy irqs and pc/pci dma implementation are not mutually exclusive. however, if the irqmux registers are programmed to use irqmux7irqmux6, then they will override pc/pci dma. PCI1450 pci irqmux0 irqmux1 irqmux2 irqmux3 irqmux4 irqmux5 irqmux6 irqmux7 irq3 irq4 irq5 irq9 irq10 irq11 irq12 irq15 figure 16. example PCI1450 irq implementation software is responsible for programming the irqmux routing register to reflect the irq configuration shown in figure 16. in this example, this programming is accomplished by writing a double-word of data fcba9543h to the PCI1450 irqmux routing register , pci offset 8ch. in this example (fcba9543h), f corresponds to irq15, c to irq12, b to irq11, a to irq10, 9 to irq9, 5 to irq5, 4 to irq4, and 3 to irq3. the irqmux routing register is shared between the two PCI1450 functions, and only one write to function 0 or function 1 is necessary to configure the irqmux signals. using parallel pci interrupts parallel pci interrupts are available when in pure parallel pci interrupt mode, irqmux signaling mode, and when only irqs are serialized with the irqser protocol. the pci interrupt signaling is dependent upon the interrupt mode and is summarized in table 22. the interrupt mode is selected in the device control register (92h). the irqser/intb signals intb when one of the parallel interrupt modes is selected via bits 21 in the
PCI1450 gfn/gjg pc card controller scps044 september 1998 38 post office box 655303 ? dallas, texas 75265 device control register (92h). pci intb is also available on the irqmux0 terminal by programming bits 30 to 0001b in the irqmux routing register (8ch). pci inta is available on the gpio3 terminal by programming bits 76 in the gpio3 control register . table 22. interrupt pin register cross reference interrupt signaling mode intpin function 0 intpin function 1 parallel pci interrupts only 0x01 (inta ) 0x02 (intb ) parallel irq & parallel pci interrupts 0x01 (inta ) 0x02 (intb ) irq serialized (irqser) & parallel pci interrupts 0x01 (inta ) 0x01 (inta ) irq & pci serialized (irqser) interrupts (default) 0x01 (inta ) 0x02 (intb ) power management overview in addition to the low-power cmos technology process used for the PCI1450, various features are designed into the device to allow implementation of popular power saving techniques. these features and techniques are discussed in this section. clkrun protocol clkrun is the primary method of power management on the pci bus side of the PCI1450. since some chipsets do not implement clkrun , this is not always available to the system designer, and alternate power savings features are provided. if clkrun is not implemented, then the clkrun pin should be tied low. clkrun is enabled by default via bit 1 (keepclk) in the system control register (80h). cardbus pc card power management the PCI1450 implements its own card power management engine that can turn off the cclk to a socket when there is no activity to the cardbus pc card. the cclk can also be configured as divide by 16 instead of stopped. the clkrun protocol is followed on the cardbus interface to control this clock management. pci bus power management the pci bus power management interface specification (pcipm) establishes the infrastructure required to let the operating system control the power of pci functions. this is done by defining a standard pci interface and operations to manage the power of pci functions on the bus. the pci bus and the pci functions can be assigned one of four software visible power management states, which result in varying levels of power savings. the four power management states of pci functions are: d0 - fully on state, d1 and d2 - intermediate states, and d3 - off state. similarly, bus power states of the pci bus are b0b3. the bus power states b0b3 are derived from the device power state of the upstream bridge device. for the operating system to manage the device power states on the pci bus, the pci function should support four power management operations. the four operations are: capabilities reporting; power status reporting; setting the power state; and system wake-up. the operating system identifies the capabilities of the pci function by traversing the new capabilities list. the presence of new capabilities is indicated by a 1b in bit 4 of the pci status register (pci offset 06h). when software determines that the device has a capabilities list by seeing that bit 4 of the pci status register is set, it will read the capability pointer register at pci offset 14h. this value in the register points the location in pci configuration space of the capabilities linked list.
PCI1450 gfn/gjg pc card controller scps044 september 1998 39 post office box 655303 ? dallas, texas 75265 the first byte of each capability register block is required to be a unique id of that capability. pci power management has been assigned an id of 01h. the next byte is a pointer to the next pointer item in the list of capabilities. if there are no more items in the list, then the next item pointer should be set to 0. the registers following the next item pointer are specific to the function's capability. the pcipm capability implements the following register block: power management register block power management capabilities (pmc) next item pointer capability id offset = 0 data pmcsr bridge support extensions power management control status (csr) offset = 4 the power management capabilities (pmc) register is a static read-only register that provides information on the capabilities of the function, related to power management. the pmcsr register enables control of power management states and enables/monitors power management events. the data register is an optional register that provides a mechanism for state-dependent power measurements such as power consumed or heat dissipation. cardbus device class power management the pci bus interface specification for pci-to-cardbus bridges was approved by pcmcia in december of 1997. this specification follows the device and bus state definitions provided in the pci bus power management interface specification published by the pci special interest group (sig). the main issue addressed in the pci bus interface specification for pci-to-cardbus bridges is wake-up from d3 hot or d3 cold without losing wake-up context (also called pme context). the specific issues addressed by the pci bus interface specification for pci-to-cardbus bridges for d3 wake up are as follows: preservation of device context: the pci power management specification version 1.0 states that prst must be asserted when transitioning from d3 cold to d0. some method to preserve wake-up context must be implemented so that prst does not clear the pme context registers. power source in d3 cold if wake-up support is required from this state. the texas instruments PCI1450 addresses these d3 wake-up issues in the following manner: preservation of device context: when prst is asserted, bits required to preserve pme context are not cleared. to clear all bits in the PCI1450, another reset pin is defined: g_rst (global reset). g_rst is normally only asserted during the initial power-on sequence. after the initial boot, prst should be asserted so that pme context is retained for d3-to-d0 transitions. bits cleared by g_rst , but not cleared by prst (if the pme enable bit is set), are referred to as pme context bits. please refer to the master list of pme context bits in the next section. power source in d3 cold if wake-up support is required from this state. since v cc is removed in d3 cold , an auxiliary power source must be switched to the PCI1450 v cc pins. this switch should be a make before break type of switch, so that v cc to the PCI1450 is not interrupted. master list of pme context bits and global reset only bits pme context bit means that the bit is cleared only by the assertion of g_rst when the pme enable bit is set (pci offset a4h, bit 8). if pme is not enabled, then these bits are cleared when either prst or g_rst is asserted. global reset only bits, as the name implies, are only cleared by g_rst . these bits are never cleared by prst regardless of the setting of the pme enable bit. (pci offset a4h, bit 8). the g_rst signal is gated only by the suspend signal. this means that assertion of suspend blocks the g_rst signal internally, thus preserving all register contents.
PCI1450 gfn/gjg pc card controller scps044 september 1998 40 post office box 655303 ? dallas, texas 75265 global reset only bits: subsystem id/subsystem vendor id (pci offset 40h): bits 310 pc card 16-bit legacy mode base address register (pci offset 44h): bits 311 system control register (pci offset 80h): bits 3129, 2724, 2214, 6, 5, 4, 3, 1, 0 multimedia control register (pci offset 84h): bits 70 general status register (pci offset 85h): bits 20 gpio0 control register (pci offset 88h): bits 7, 6, 4, 3, 1, 0 gpio1 control register (pci offset 89h): bits 7, 6, 3, 1, 0 gpio2 control register (pci offset 8ah): bits 7, 6, 4, 3, 1, 0 gpio3 control register (pci offset 8bh): bits 7, 6, 3, 1, 0 irqmux routing register (pci offset 8ch): bits 310 retry status register (pci offset 90h): bits 71 card control register (pci offset 91h): bits 7, 6, 2, 1, 0 device control register (pci offset 92h): bits 70 diagnostic register (pci offset 93h): bits 70 socket dma register 0 (pci offset 94h): bits 10 socket dma register 1 (pci offset 98h): bits 150 gpe control/status register (pci offset a8h): bits 10, 9, 8, 2, 1, 0 pme context bits bridge control register (pci offset 3eh): bit 6 power management capabilities register (pci offset a2h): bit 15 power management control/status register (pci offset a4h): bits 15, 8 exca power control register (exca 802h/842h): bits 4, 3, 1, 0 exca interrupt and general control (exca 803h/843h): bit 6 exca card status change register (exca 804h/844h): bits 3, 2, 1, 0 exca card status change interrupt register (exca 805h/845h): bits 3, 2, 1, 0 cardbus socket event register (cardbus offset 00h): bits 3, 2, 1, 0 cardbus socket mask register (cardbus offset 04h): bits 3, 2, 1, 0 cardbus socket control register (cardbus offset 10h): bits 6, 5, 4, 2, 1, 0
PCI1450 gfn/gjg pc card controller scps044 september 1998 41 post office box 655303 ? dallas, texas 75265 system diagram implementing cardbus device class power management PCI1450 south bridge embedded controller pme 68 pc card socket a tps2206 power switch 2 pc card socket b clkrun 68 note: the system connection to g_rst is implementation specific. g_rst should be applied whenever v cc is applied to the PCI1450. prst should be applied for subsequent warm resets. pci bus real time clock clock prst prst g_rst 1 gpio vcc system vcc v aux make before break switch d3 status not required if internal oscillator is used suspend mode the suspend signal, provided for backward compatibility, gates the prst (pci reset) signal and the g_rst (global reset) signal from the PCI1450. besides gating prst and g_rst , suspend also gates pclk inside the PCI1450 in order to minimize power consumption. gating pclk does not create any issues with respect to the power switch interface in the PCI1450. this is because the PCI1450 does not depend on the pci clock to clock the power switch interface. there are two methods to clock the power switch interface in the PCI1450: use an external clock to the PCI1450 clock pin use the internal oscillator it should also be noted that asynchronous signals, such as card status change interrupts and ri_out, can be passed to the host system without a pci clock. however, if card status change interrupts are routed over the serial interrupt stream, then the pci clock will have to be restarted in order to pass the interrupt, because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine. PCI1450 core prst g_rst suspend gnt pclk figure 17. suspend functional illustration
PCI1450 gfn/gjg pc card controller scps044 september 1998 42 post office box 655303 ? dallas, texas 75265 requirements for suspend a requirement for implementing suspend mode is that the pci bus must not be parked on the PCI1450 when suspend is asserted. the PCI1450 responds to suspend being asserted by 3-stating the req pin. the PCI1450 will also gate the internal clock and reset. the gpios, irqmux signals, and ri_out signals are all active during suspend , unless they are disabled in the appropriate PCI1450 registers. ring indicate the ri_out output is an important feature used in legacy power management. it is used so that a system can go into a suspended mode and wake up on modem rings and other card events. the ri_out signal on the PCI1450 may be asserted under any of the following conditions: a 16-bit pc card modem in a powered socket asserts ri to indicate an incoming call to the system. a powered down cardbus card asserts cstschg (cbwake) requesting system and interface wake up. a card status change (csc) event, such as insertion/removal of cards, battery voltage levels, occurs. a cstschg signal from a powered cardbus card is indicated as a csc event, not as a cbwake event. these two ri_out events are enabled separately. the following figure details various enable bits for the PCI1450 ri_out function; however, it does not illustrate the masking of csc events. see interrupt masks and flags for a detailed description of csc interrupt masks and flags. ri_out is multiplexed on the same pin with pme . the default is for ri_out to be signaled on this pin. in pci power managed systems, the pme signal should be enabled by setting bit 0 (ri_ou t/pme ) in the system control register (80h) and clearing bit 7 (rienb) in the card control register (91h). rienb ricsc(a) ri_out pc card socket 0 pc card socket 1 card i/f 16bit card bus card i/f 16bit card bus ricsc(b) ri_out function cbwake ri csc cbwake ri csc figure 18. ri_out functional illustration routing of csc events to the ri_out signal, enabled on a per socket basis, is programmed by the ricsc bit in the card control register . this bit is socket dependent (not shared), as illustrated in figure 18.
PCI1450 gfn/gjg pc card controller scps044 september 1998 43 post office box 655303 ? dallas, texas 75265 the ri signal from the 16-bit pc card interface is masked by the exca control bit ringen in the exca interrupt and general control register . this is programmed on a per socket basis, and is only applicable when a 16-bit card is powered in the socket. the cbwake signaling to ri_out is enabled through the same mask as the csc event for cstschg. the mask bit, cstsmask, is programmed through the socket mask register in the cardbus socket registers.
PCI1450 gfn/gjg pc card controller scps044 september 1998 44 post office box 655303 ? dallas, texas 75265 pc card controller programming model this section describes the PCI1450 pci configuration registers that make up the 256-byte pci configuration header for each PCI1450 function. as noted below, some bits are global in nature and should be accessed only through function 0. registers containing one or more global bits are denoted by a a.o any bit followed by a a2o is not cleared by the assertion of prst (refer to cardbus device class power management for more details) if pme is enabled (pci offset a4h, bit 8). in this case, these bits are only cleared by g_rst . if pme is not enabled, then these bits are cleared by g_rst or prst . these bits are sometimes referred to as pme context bits and are implemented to allow pme context to be preserved when transitioning from d3 hot or d3 cold to d0. if the pme context prst functionality is not desired, then the prst and g_rst signals should be tied together. if a bit is followed by a a3o, then this bit is only cleared by g_rst in all cases (not conditional on pme being enabled). these bits are intended to maintain device context such as interrupt routing and irqmux programming during awarmo resets. pci configuration registers (functions 0 and 1) the PCI1450 is a multifunction pci device, and the pc card controller is integrated as pci functions 0 and 1. the configuration header, compliant with the pci specification as a cardbus bridge header, is pc97/pc98 compliant as well. table 23 illustrates the pci configuration header, which includes both the predefined portion of the configuration space and the user definable registers. table 23. functions 0 and 1 pci configuration register map register name offset device id vendor id 00h status command 04h class code revision id 08h bist header type latency timer cache line size 0ch cardbus socket registers/exca base address 10h secondary status reserved capability pointer 14h cardbus latency timer subordinate bus number cardbus bus number pci bus number 18h cardbus memory base register 0 1ch cardbus memory limit register 0 20h cardbus memory base register 1 24h cardbus memory limit register 1 28h cardbus i/o base register 0 2ch cardbus i/o limit register 0 30h cardbus i/o base register 1 34h cardbus i/o limit register 1 38h bridge control 2 interrupt pin interrupt line 3ch subsystem id 3 subsystem vendor id 3 40h pc card 16-bit i/f legacy mode base address 3 44h reserved 48h7fh 2 one or more bits in the register are pme context bits and can only be cleared by the assertion of g_rst when pme is enabled. if pme is not enabled, then these bits are cleared by the assertion of prst or g_rst . 3 one or more bits in this register are only cleared by the assertion g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 45 post office box 655303 ? dallas, texas 75265 table 23 . functions 0 and 1 pci configuration register map (continued) system control 3 80h reserved reserved general status 2 multimedia control 3 84h gpio3 control 3 gpio2 control 3 gpio1 control 3 gpio0 control 3 88h irqmux routing 2 8ch diagnostic 3 device control 3 card control 3 retry status 3 90h socket dma register 0 3 94h socket dma register 1 3 98h reserved 9ch power management capabilities 2 next pointer item capability id a0h data (reserved) pmcsr bridge support extensions power management control/status 2 a4h reserved gpe control/status 3 a8h 2 one or more bits in the register are pme context bits and can only be cleared by the assertion of g_rst when pme is enabled. if pme is not enabled, then these bits are cleared by the assertion of prst or g_rst . 3 one or more bits in this register are only cleared by the assertion g_rst . vendor id register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name vendor id type r r r r r r r r r r r r r r r r default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 register: vendor id type: read-only offset: 00h (functions 0, 1) default: 104ch description: this 16-bit register contains a value allocated by the pci sig that identifies the manufacturer of the pci device. the vendor id assigned to texas instruments is 104ch. device id register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name device id type r r r r r r r r r r r r r r r r default 1 0 1 0 1 1 0 0 0 0 0 1 1 0 1 1 register: device id type: read-only offset: 02h (functions 0, 1) default: ac1bh description: this 16-bit register contains a value assigned to the PCI1450 by texas instruments. the device identification for the PCI1450 is ac1b.
PCI1450 gfn/gjg pc card controller scps044 september 1998 46 post office box 655303 ? dallas, texas 75265 command register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name command type r r r r r r r r/w r r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: command type: read-only, read/write offset: 04h default: 0000h description: the command register provides control over the PCI1450 interface to the pci bus. all bit functions adhere to the definitions in the pci local bus specification, see table 24. none of the bit functions in this register are shared between the two PCI1450 pci functions. two command registers exist in the PCI1450, one for each function. software manipulates the two PCI1450 functions as separate entities when enabling functionality through the command register . the serr_en and perr_en enable bits in this register are internally wired or between the two functions, and these control bits appear separate per function to software. table 24. pci command register description bit type function 1510 r reserved. these bits return 0s when read. writes have no effect. 9 r fast back-to-back enable. the PCI1450 will not generate fast back-to-back transactions; therefore, this bit is read-only. this bit returns a 0 when read. 8 r/w system error (serr ) enable. this bit controls the enable for the serr driver on the pci interface. serr can be asserted after detecting an address parity error on the pci bus. both this bit and bit 6 must be set for the PCI1450 to report address parity errors. 0 = disables the serr output driver (default). 1 = enables the serr output driver. 7 r address/data stepping control. the PCI1450 does not support address/data stepping, and this bit is hardwired to 0. writes to this bit have no effect. 6 r/w parity error response enable. this bit controls the PCI1450's response to parity errors through the perr signal. data parity errors are indicated by asserting perr , while address parity errors are indicated by asserting serr . 0 = PCI1450 ignores detected parity error (default). 1 = PCI1450 responds to detected parity errors. 5 r/w vga palette snoop. when set to 1, palette snooping is enabled (i.e., the PCI1450does not respond to palette register writes and snoops the data). when the bit is 0, the PCI1450 will treat all palette accesses like all other accesses. 4 r memory write and invalidate enable. this bit controls whether a pci initiator device can generate memory write and invalidate commands. the PCI1450 controller does not support memory write and invalidate commands, it uses memory write commands instead; therefore, this bit is hardwired to 0. this bit returns 0 when read. writes to this bit have no effect. 3 r special cycles. this bit controls whether or not a pci device ignores pci special cycles. the PCI1450 does not respond to special cycle operations; therefore, this bit is hardwired to 0. this bit returns 0 when read. writes to this bit have no ef fect. 2 r/w bus master control. this bit controls whether or not the PCI1450 can act as a pci bus initiator (master). the PCI1450 can take control of the pci bus only when this bit is set. 0 = disables the PCI1450's ability to generate pci bus accesses (default). 1 = enables the PCI1450's ability to generate pci bus accesses. 1 r/w memory space enable. this bit controls whether or not the PCI1450 may claim cycles in pci memory space. 0 = disables the PCI1450's response to memory space accesses (default). 1 = enables the PCI1450's response to memory space accesses. 0 r/w i/o space control. this bit controls whether or not the PCI1450 may claim cycles in pci i/o space. 0 = disables the PCI1450 from responding to i/o space accesses (default). 1 = enables the PCI1450 to respond to i/o space accesses.
PCI1450 gfn/gjg pc card controller scps044 september 1998 47 post office box 655303 ? dallas, texas 75265 status register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name status type r/w r/w r/w r/w r/w r r r/w r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 register: status type: read-only, read/write offset: 06h (functions 0, 1) default: 0210h description: the status register provides device information to the host system. bits in this register may be read normally. a bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. all bit functions adhere to the definitions in the pci bus specification, as seen in the bit descriptions. pci bus status is shown through each function. table 25. status register description bit type function 15 r/w par_err. detected parity error. this bit is set when a parity error is detected, either address or data parity errors. write a 1 to clear this bit. 14 r/w sys_err. signaled system error. this bit is set when serr is enabled and the PCI1450 signaled a system error to the host. write a 1 to clear this bit. 13 r/w mabort. received master abort. this bit is set when a cycle initiated by the PCI1450 on the pci bus has been terminated by a master abort. write a 1 to clear this bit. 12 r/w tabt_rec. received target abort. this bit is set when a cycle initiated by the PCI1450 on the pci bus was terminated by a target abort. write a 1 to clear this bit. 11 r/w tabt_sig. signaled target abort. this bit is set by the PCI1450 when it terminates a transaction on the pci bus with a target abort. write a 1 to clear this bit. 109 r pci_speed. devsel timing. these bits encode the timing of devsel and are hardwired 01b indicating that the PCI1450 asserts this signal at a medium speed on nonconfiguration cycle accesses. 8 r/w datapar. data parity error detected. write a 1 to clear this bit. 0 = the conditions for setting this bit have not been met. 1 = a data parity error occurred and the following conditions were met: a. perr was asserted by any pci device including the PCI1450. b. the PCI1450 was the bus master during the data parity error. c. the parity error response bit is set in the command register . 7 r fbb_cap. fast back-to-back capable. the PCI1450 cannot accept fast back-to-back transactions; thus, this bit is hardwired to 0. 6 r udf. udf supported. the PCI1450 does not support the user definable features; therefore, this bit is hardwired to 0. 5 r 66 mhz capable. the PCI1450 operates at a maximum pclk frequency of 33 mhz; therefore, this bit is hardwired to 0. 4 r capabilities list. this bit returns 1 when read. this bit indicates that capabilities in addition to standard pci capabilities are implemented. the linked list of pci power management capabilities is implemented in this function. 30 r reserved. these bits return 0s when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 48 post office box 655303 ? dallas, texas 75265 revision id register bit 7 6 5 4 3 2 1 0 name revision id type r r r r r r r r default 0 0 0 0 0 0 1 0 register: revision id type: read-only offset: 08h (functions 0, 1) default: 02h description: this register indicates the silicon revision of the PCI1450. this data sheet reflects the PCI1450 revision 02h silicon. pci class code register bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte base class sub class programming interface name pci class code type r r r r r r r r r r r r r r r r r r r r r r r r default 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 register: pci class code type: read-only offset: 09h (functions 0, 1) default: 060700h description: this register recognizes the PCI1450 functions 0 and 1 as a bridge device (06h), and cardbus bridge device (07h), with a 00h programming interface. cache line size register bit 7 6 5 4 3 2 1 0 name cache line size type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cache line size type: read/write offset: 0ch (functions 0, 1) default: 00h description: this register is programmed by host software to indicate the system cache line size.
PCI1450 gfn/gjg pc card controller scps044 september 1998 49 post office box 655303 ? dallas, texas 75265 latency timer register bit 7 6 5 4 3 2 1 0 name latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: latency timer type: read/write offset: 0dh default: 00h description: this register specifies the latency timer for the PCI1450, in units of pci clock cycles. when the PCI1450 is a pci bus initiator and asserts frame , the latency timer begins counting from zero. if the latency timer expires before the PCI1450 transaction has terminated, then the PCI1450 terminates the transaction when its gnt is deasserted. header type register bit 7 6 5 4 3 2 1 0 name header type type r r r r r r r r default 1 0 0 0 0 0 1 0 register: header type type: read-only offset: 0eh (functions 0, 1) default: 82h description: this register returns 82h when read, indicating that the PCI1450 functions 0 and 1 configuration spaces adhere to the cardbus bridge pci header. the cardbus bridge pci header ranges from pci register 0 to 7fh, and 80hffh is user definable extension registers. bist register bit 7 6 5 4 3 2 1 0 name bist type r r r r r r r r default 0 0 0 0 0 0 0 0 register: bist type: read-only offset: 0fh (functions 0, 1) default: 00h description: since the PCI1450 does not support a built-in self-test (bist), this register returns the value of 00h when read. this register returns 0s for the two PCI1450 functions.
PCI1450 gfn/gjg pc card controller scps044 september 1998 50 post office box 655303 ? dallas, texas 75265 cardbus socket registers / exca registers base address register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name cardbus socket registers/exca base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name cardbus socket registers/exca base address type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: cardbus socket registers/exca base address type: read-only, read/write offset: 10h default: 0000 0000h description: this register is programmed with a base address referencing the cardbus socket registers and the memory mapped exca register set. bits 3112 are read/write, and allow the base address to be located anywhere in the 32-bit pci memory address space on a 4k-byte boundary. bits 110 are read-only, returning 0s when read. when software writes all ones to this register, the value read back will be ffff f000h, indicating that at least 4k bytes of memory address space are required. the cardbus registers start at offset 000h, and the memory mapped exca registers begin at offset 800h. this register is not shared by functions 0 and 1, mapping each socket control register separately. capability pointer bit 7 6 5 4 3 2 1 0 name capability pointer type r r r r r r r r default 1 0 1 0 0 0 0 0 register: capability pointer type: read-only offset: 14h default: a0h description: this register provides a pointer into the pci configuration header where the pci power management register block resides. pci header doublewords at a0h and a4h provide the power management (pm) registers. each socket has its own capability pointer register . this register is read-only and returns a0h when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 51 post office box 655303 ? dallas, texas 75265 secondary status register bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name secondary status type r/wc r/wc r/wc r/wc r/wc r r r/wc r r r r r r r r default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 register: secondary status type: read-only, read/write to clear offset: 16h default: 0200h description: this register is compatible with the pci-pci bridge secondary status register. it indicates cardbus related device information to the host system. this register is very similar to the pci status register (offset 06h), and status bits are cleared by a writing a 1. this register is not shared by the two socket functions, but is accessed on a per socket basis. table 26. secondary status register description bit type function 15 r/wc cbparity. detected parity error. this bit is set when a cardbus parity error is detected; either address or data parity errors. write a 1 to clear this bit. 14 r/wc cbserr. signaled system error. this bit is set when cserr is signaled by a cardbus card. the PCI1450 does not assert the cserr signal. write a 1 to clear this bit. 13 r/wc cbmabort. received master abort. this bit is set when a cycle initiated by the PCI1450 on the cardbus bus has been terminated by a master abort. write a 1 to clear this bit. 12 r/wc rec_cbta. received target abort. this bit is set when a cycle initiated by the PCI1450 on the cardbus bus was terminated by a target abort. write a 1 to clear this bit. 11 r/wc sig_cbta. signaled target abort. this bit is set by the PCI1450 when it terminates a transaction on the cardbus bus with a target abort. write a 1 to clear this bit. 109 r cb_speed. cdevsel timing. these bits encode the timing of cdevsel and are hardwired 01b indicating that the PCI1450 asserts this signal at a medium speed. 8 r/wc cb_dpar. cardbus data parity error detected. write a 1 to clear this bit. 0 = the conditions for setting this bit have not been met. 1 = a data parity error occurred and the following conditions were met: a. cperr was asserted on the cardbus interface. b. the PCI1450 was the bus master during the data parity error. c. the parity error response bit is set in the bridge control register . 7 r cbfbb_cap. fast back-to-back capable. the PCI1450 cannot accept fast back-to-back transactions; therefore, this bit is hardwired to 0. 6 r cb_udf. user definable feature support. the PCI1450 does not support the user definable features; therefore, this bit is hardwired to 0. 5 r cb66mhz. 66 mhz capable. the PCI1450 cardbus interface operates at a maximum cclk frequency of 33 mhz; therefore, this bit is hardwired to 0. 40 r reserved. these bits return 0s when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 52 post office box 655303 ? dallas, texas 75265 pci bus number register bit 7 6 5 4 3 2 1 0 name pci bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: pci bus number type: read/write offset: 18h (functions 0, 1) default: 00h description: this register is programmed by the host system to indicate the bus number of the pci bus to which the PCI1450 is connected. the PCI1450 uses this register, in conjunction with the cardbus bus number and subordinate bus number registers , to determine when to forward pci configuration cycles to its secondary buses. cardbus bus number register bit 7 6 5 4 3 2 1 0 name cardbus bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cardbus bus number type: read/write offset: 19h default: 00h description: this register is programmed by the host system to indicate the bus number of the cardbus bus to which the PCI1450 is connected. the PCI1450 uses this register, in conjunction with the pci bus number and subordinate bus number registers , to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each PCI1450 controller function. subordinate bus number register bit 7 6 5 4 3 2 1 0 name subordinate bus number type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: subordinate bus number type: read/write offset: 1ah default: 00h description: this register is programmed by the host system to indicate the highest numbered bus below the cardbus bus. the PCI1450 uses this register, in conjunction with the pci bus number and cardbus bus number registers , to determine when to forward pci configuration cycles to its secondary buses. this register is separate for each cardbus controller function.
PCI1450 gfn/gjg pc card controller scps044 september 1998 53 post office box 655303 ? dallas, texas 75265 cardbus latency timer register bit 7 6 5 4 3 2 1 0 name cardbus latency timer type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: cardbus latency timer type: read/write offset: 1bh (functions 0, 1) default: 00h description: this register is programmed by the host system to specify the latency timer for the PCI1450 cardbus interface, in units of cclk cycles. when the PCI1450 is a cardbus initiator and asserts cframe , the cardbus latency timer begins counting. if the latency timer expires before the PCI1450 transaction has terminated, then the PCI1450 terminates the transaction at the end of the next data phase. a recommended minimum value for this register of 20h allows most transactions to be completed. memory base registers 0, 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory base registers 0, 1 type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory base registers 0, 1 type: read-only, read/write offset: 1ch, 24h default: 0000 0000h description: these registers indicate the lower address of a pci memory address range. they are used by the PCI1450 to determine when to forward a memory transaction to the cardbus bus, and likewise, when to forward a cardbus cycle to pci. bits 3112 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4k-byte boundaries. bits 110 are read-only and always return 0s. writes to these bits have no effect. bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero in order for the PCI1450 to claim any memory transactions through cardbus memory windows (i.e., these windows are not enabled by default to pass the first 4k bytes of memory to cardbus).
PCI1450 gfn/gjg pc card controller scps044 september 1998 54 post office box 655303 ? dallas, texas 75265 memory limit registers 0, 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name memory limit registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name memory limit registers 0, 1 type r/w r/w r/w r/w r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: memory limit registers 0, 1 type: read-only, read/write offset: 20h, 28h default: 0000 0000h description: these registers indicate the upper address of a pci memory address range. they are used by the PCI1450 to determine when to forward a memory transaction to the cardbus bus, and likewise, when to forward a cardbus cycle to pci. bits 3112 of these registers are read/write and allow the memory base to be located anywhere in the 32-bit pci memory space on 4k-byte boundaries. bits 110 are read-only and always return 0s. writes to these bits have no effect. bits 8 and 9 of the bridge control register specify whether memory windows 0 and 1 are prefetchable or nonprefetchable. the memory base register or the memory limit register must be nonzero in order for the PCI1450 to claim any memory transactions through cardbus memory windows (i.e., these windows are not enabled by default to pass the first 4k bytes of memory to cardbus). i/o base registers 0, 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o base registers 0, 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o base registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o base registers 0, 1 type: read-only, read/write offset: 2ch, 34h default: 0000 0000h description: these registers indicate the lower address of a pci i/o address range. they are used by the PCI1450 to determine when to forward an i/o transaction to the cardbus bus, and likewise, when to forward a cardbus cycle to the pci bus. the lower 16 bits of this register locate the bottom of the i/o window within a 64k-byte page, and the upper 16 bits (3116) are all 0s which locate this 64k-byte page in the first page of the 32-bit pci i/o address space. bits 3116 and bits 10 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary in the first 64k-byte page of pci i/o address space. these i/o windows are enabled when either the i/o base register or the i/o limit register are nonzero. the i/o windows are not enabled by default to pass the first doubleword of i/o to cardbus. either the i/o base or the i/o limit register must be nonzero to enable any i/o transactions.
PCI1450 gfn/gjg pc card controller scps044 september 1998 55 post office box 655303 ? dallas, texas 75265 i/o limit registers 0, 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name i/o limit registers 0, 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name i/o limit registers 0, 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: i/o limit registers 0, 1 type: read-only, read/write offset: 30h, 38h default: 0000 0000h description: these registers indicate the upper address of a pci i/o address range. they are used by the PCI1450 to determine when to forward an i/o transaction to the cardbus bus, and likewise, when to forward a cardbus cycle to pci. the lower 16 bits of this register locate the top of the i/o window within a 64k-byte page, and the upper 16 bits are a page register which locates this 64k-byte page in 32-bit pci i/o address space. bits 152 are read/write and allow the i/o limit address to be located anywhere in the 64k-byte page (indicated by bits 3116 of the appropriate i/o base register ) on doubleword boundaries. bits 3116 are read-only and always return 0s when read. the page is set in the i/o base register . bits 10 are read-only and always return 0s, forcing i/o windows to be aligned on a natural doubleword boundary. writes to read-only bits have no effect. the PCI1450 assumes that the lower two bits of the limit address are ones. these i/o windows are enabled when either the i/o base register or the i/o limit register are nonzero. the i/o windows are not enabled by default to pass the first doubleword of i/o to cardbus. either the i/o base or the i/o limit register must be nonzero to enable any i/o transactions. interrupt line register bit 7 6 5 4 3 2 1 0 name interrupt line type r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 1 1 1 1 1 1 register: interrupt line type: read/write offset: 3ch default: ffh description: this register communicates interrupt line routing information to the host system. this register is not used by the PCI1450, since there are many programmable interrupt signaling options. this register is considered reserved; however, host software may read and write to this register. each PCI1450 function has an interrupt line register .
PCI1450 gfn/gjg pc card controller scps044 september 1998 56 post office box 655303 ? dallas, texas 75265 interrupt pin register pci function 0 bit 7 6 5 4 3 2 1 0 name interrupt pin pci function 0 type r r r r r r r r default 0 0 0 0 0 0 0 1 pci function 1 bit 7 6 5 4 3 2 1 0 name interrupt pin pci function 1 type r r r r r r r r default 0 0 0 0 0 0 1 0 register: interrupt pin type: read-only offset: 3dh default: the default depends on the interrupt signaling mode. description: the value read from this register is function dependent. the value depends on the interrupt intrtie bit in the system control register and the signaling mode, selected through the device control register . when the intrtie bit is set, this register will read 0x01 (inta ) for both functions. the PCI1450 defaults to signaling pci & irq interrupts through the irqser serial interrupt terminal. refer to table 27 for a complete description of the register contents. table 27. interrupt pin register cross reference interrupt signaling mode intrtie bit intpin function 0 intpin function 1 parallel pci interrupts only 0 0x01 (inta ) 0x02 (intb ) parallel irq & parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq serialized (irqser) & parallel pci interrupts 0 0x01 (inta ) 0x02 (intb ) irq & pci serialized (irqser) interrupts (default) 0 0x01 (inta ) 0x02 (intb ) parallel pci interrupts only 1 0x01 (inta ) 0x01 (inta ) parallel irq & parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq serialized (irqser) & parallel pci interrupts 1 0x01 (inta ) 0x01 (inta ) irq & pci serialized (irqser) interrupts (default) 1 0x01 (inta ) 0x01 (inta ) bridge control register bit 15 14 13 12 11 10 9 8 7 6 2 5 4 3 2 1 0 name bridge control type r r r r r r/w r/w r/w r/w r/w r/w r r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 register: bridge control type: read-only, read/write offset: 3eh (function 0, 1) default: 0340h description: this register provides control over various PCI1450 bridging functions. some bits in this register are global in nature and should be accessed only through function 0.
PCI1450 gfn/gjg pc card controller scps044 september 1998 57 post office box 655303 ? dallas, texas 75265 table 28. bridge control register description bit type function 1511 r reserved. these bits return 0s when read. 10 r/w posten. write posting enable. enables write posting to and from the cardbus sockets. write posting enables posting of write data on burst cycles. operating with write posting disabled will inhibit performance on burst cycles. note that bursted write data can be posted, but various write transactions may not. this bit is socket dependent and is not shared between functions 0 and 1. 9 r/w prefetch1. memory window 1 type. this bit specifies whether or not memory window 1 is prefetchable. this bit is socket dependent. this bit is encoded as: 0 = memory window 1 is nonprefetchable. 1 = memory window 1 is prefetchable (default). 8 r/w prefetch0. memory window 0 type. this bit specifies whether or not memory window 0 is prefetchable. this bit is encoded as: 0 = memory window 0 is nonprefetchable. 1 = memory window 0 is prefetchable (default). 7 r/w pci interrupt ireq routing enable. this bit is used to select whether pc card functional interrupts are routed to pci interrupts or to the irq specified in the exca registers. 0 = functional interrupts are routed to pci interrupts (default). 1 = functional interrupts are routed by exca registers. 62 r/w crst. cardbus reset. when this bit is set, the crst signal is asserted on the cardbus interface. the crst signal may also be asserted by passing a prst assertion to cardbus. 0 = crst is deasserted. 1 = crst is asserted (default). this bit will not be cleared by the assertion of prst . it will only be cleared by the assertion of g_rst . 5 r/w mabtmode. master abort mode. this bit controls how the PCI1450 responds to a master abort when the PCI1450 is an initiator on the cardbus interface. this bit is common between each socket. 0 = master aborts not reported (default). 1 = signal target abort on pci and signal serr , if enabled. 4 r reserved. this bit returns 0 when read. 3 r/w vgaen. vga enable. this bit affects how the PCI1450 responds to vga addresses. when this bit is set, accesses to vga addresses will be forwarded. 2 r/w isaen. isa mode enable. this bit affects how the PCI1450 passes i/o cycles within the 64k-byte isa range. this bit is not common between sockets. when this bit is set, the PCI1450 will not forward the last 768 bytes of each 1k i/o range to cardbus. 1 r/w cserren. cserr enable. this bit controls the response of the PCI1450 to cserr signals on the cardbus bus. this bit is separate for each socket. 0 = cserr is not forwarded to pci serr . 1 = cserr is forwarded to pci serr . 0 r/w cperren. cardbus parity error response enable. this bit controls the response of the PCI1450 to cardbus parity errors. this bit is separate for each socket. 0 = cardbus parity errors are ignored. 1 = cardbus parity errors are reported using cperr . 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst . these bits are global in nature and should be accessed only through function 0.
PCI1450 gfn/gjg pc card controller scps044 september 1998 58 post office box 655303 ? dallas, texas 75265 subsystem vendor id register bit 153 143 133 123 113 103 93 83 73 63 53 43 33 23 13 03 name subsystem vendor id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 this bit is cleared only by the assertion of g_rst . register: subsystem vendor id type: read-only, read/write (when bit 5 in the system control register is 0.) offset: 40h (functions 0, 1) default: 0000h description: this register, used for system and option card identification purposes, may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register . when bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. the default mode is read-only. subsystem id register bit 153 143 133 123 113 103 93 83 73 63 53 43 33 23 13 03 name subsystem id type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 this bit is cleared only by the assertion of g_rst . register: subsystem id type: read-only, read/write (when bit 5 in the system control register is 0.) offset: 42h (functions 0, 1) default: 0000h description: this register, used for system and option card identification purposes, may be required for certain operating systems. this register is read-only or read/write, depending on the setting of bit 5 (subsysrw) in the system control register . when bit 5 is 0, this register is read/write; when bit 5 is 1, this register is read-only. the default mode is read-only. if an eeprom is present, then the subsystem id and subsystem vendor id will be loaded from eeprom after an reset.
PCI1450 gfn/gjg pc card controller scps044 september 1998 59 post office box 655303 ? dallas, texas 75265 pc card 16-bit i/f legacy mode base address register bit 313 303 293 283 273 263 253 243 233 223 213 203 193 183 173 163 name pc card 16-bit i/f legacy mode base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 153 143 133 123 113 103 93 83 73 63 53 43 33 23 13 0 name pc card 16-bit i/f legacy mode base address type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 this bit is cleared only by the assertion of g_rst . register: pc card 16-bit i/f legacy mode base address type: read-only, read/write offset: 44h (functions 0, 1) default: 0000 0001h description: the PCI1450 supports the index/data scheme of accessing the exca registers, which is mapped by this register. an address written to this register is the address for the index register and the address+1 is the data address. using this access method, applications requiring index/data exca access can be supported. the base address can be mapped anywhere in 32-bit i/o space on a word boundary; hence, bit 0 is read-only returning 1 when read. as specified in the yenta specification, this register is shared by functions 0 and 1. refer to the exca register set description for register offsets. system control register bit 313 303 293 28 273 263 253 243 23 223 213 203 193 183 173 163 name system control type r/w r/w r/w r r/w r/w r/w r/w r r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 bit 153 143 13 12 11 10 9 8 7 63 53 43 33 2 13 03 name system control type r/w r/w r r r r r r r r/w r/w r/w r/w r r/w r/w default 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 3 this bit is cleared only by the assertion of g_rst . register: system control type: read-only, read/write offset: 80h (functions 0, 1) default: 0044 9060h description: system level initializations are performed through programming this doubleword register. some of the bits are global in nature and should be accessed only through function 0.
PCI1450 gfn/gjg pc card controller scps044 september 1998 60 post office box 655303 ? dallas, texas 75265 table 29. system control register description bit type function 3130 3 r/w ser_step. serialized pci interrupt routing step. these bits are used to configure the serialized pci interrupt stream signaling and accomplish an even distribution of interrupts signaled on the four pci interrupt slots. these bits are global to both PCI1450 functions. 00 = inta /intb signal in inta /intb irqser slots (default) 01 = inta /intb signal in intb /intc irqser slots 10 = inta /intb signal in intc /intd irqser slots 11 = inta /intb signal in intd /inta irqser slots 29 3 r/w intrtie. tie internal pci interrupts. when this bit is set, the inta and intb signals are tied together internally and are signaled as inta . inta may then be shifted by using the ser_step bits. this bit is global to both PCI1450 functions. 0 = inta and intb are not tied together internally (default). 1 = inta and intb are tied together internally. 28 r reserved. this bit returns 0 when read. 27 3 r/w p2cclk. p2c power switch clock. this bit determines whether the clock terminal (terminal u12) is an input that requires an external clock source or if this terminal is an output that uses the internal oscillator. 0 = clock terminal (terminal u12) is an input (default) (disabled). 1 = clock terminal is an output, the internal oscillator is enabled. a 43 k pulldown resistor should be tied to this terminal. 26 3 r/w smiroute. smi interrupt routing. this bit is shared between functions 0 and 1, and selects whether irq2 or csc is signaled when a write occurs to power a pc card socket. 0 = pc card power change interrupts routed to irq2 (default). 1 = a csc interrupt is generated on pc card power changes. 25 3 r/w smistatus. smi interrupt status. this socket dependent bit is set when a write occurs to set the socket power, and the smienb bit is set. writing a 1 to this bit clears the status. 0 = smi interrupt is signaled. 1 = smi interrupt is not signaled. 24 3 r/w smienb. smi interrupt mode enable. when this bit is set, the smi interrupt signaling generates an interrupt when a write to the socket power control occurs. this bit is shared and defaults to 0 (disabled). 0 = smi interrupt mode is disabled (default). 1 = smi interrupt mode is enabled. 23 r reserved 22 3 r/w cbrsvd. cardbus reserved terminals signaling. when this bit is set, the rsvd cardbus terminals will be driven low when a cardbus card is inserted. when this bit is low, as default, these signals are 3-stated. 0 = 3-state the cardbus rsvd terminals 1 = drive the cardbus rsvd terminals low (default). 21 3 r/w vccprot. v cc protection enable. this bit is socket dependent. 0 = v cc protection is enabled for 16-bit cards (default). 1 = v cc protection is disabled for 16-bit cards. 20 3 r/w reduced zoom video enable. when this bit is enabled, a2522 of the card interface for pc card 16 cards is placed in the high impedance state. this bit is encoded as: 0 = reduced zoom video is disabled (default). 1 = reduced zoom video is enabled. 19 3 r/w cdreqen. pc/pci dma card enable. when this bit is set, the PCI1450 allows 16-bit pc cards to request pc/pci dma using the dreq signaling. dreq is selected through the socket dma register 0 . 0 = ignore dreq signaling from pc cards (default). 1 = signal dma request on dreq . 1816 3 r/w cdmachan. pc/pci dma channel assignment. these bits are encoded as: 03 = 8-bit dma channels 4 = pci master; not used (default) 57 = 16-bit dma channels these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 61 post office box 655303 ? dallas, texas 75265 table 29 . system control register description (continued) bit type function 15 3 r/w mrburstdn. memory read burst enable downstream. when this bit is set, memory read transactions are allowed to burst downstream. 0 = mrburstdn downstream is disabled. 1 = mrburstdn downstream is enabled (default). 14 3 r/w mrburstup. memory read burst enable upstream. when this bit is set, the PCI1450 allows memory read transactions to burst upstream. 0 = mrburstup upstream is disabled (default). 1 = mrburstup upstream is enabled. 13 r socactive. socket activity status. when set, this bit indicates access has been performed to or from a pc card, and is cleared upon read of this status bit. this bit is socket dependent. 0 = no socket activity (default) 1 = socket activity 12 r reserved. this bit returns 1 when read. this is the power rail bit in functions 0 and 1. 11 r pwrstream. power stream in progress status bit. when set, this bit indicates that a power stream to the power switch is in progress and a powering change has been requested. when this bit is clear, it indicates that the power stream is complete. 0 = power stream is complete, delay has expired. 1 = power stream is in progress. 10 r delayup. power-up delay in progress status bit. when set, this bit indicates that a power-up stream has been sent to the power switch, and proper power may not yet be stable. this bit is cleared when the power-up delay has expired. 0 = power-up delay has expired. 1 = power-up stream sent to switch. power might not be stable. 9 r delaydown. power-down delay in progress status bit. when set, this bit indicates that a power-down stream has been sent to the power switch, and proper power may not yet be stable. this bit is cleared when the power-down delay has expired. 0 = power-down delay has expired. 1 = power-down stream sent to switch. power might not be stable. 8 r interrogate. interrogation in progress. when set, this bit indicates an interrogation is in progress, and clears when the interrogation completes. this bit is socket dependent. 0 = interrogation not in progress (default) 1 = interrogation in progress 7 r reserved. this bit returns 0 when read. 6 3 r/w pwrsavings. power savings mode enable. when this bit is set, the PCI1450 will consume less power with no performance loss. this bit is shared between the two PCI1450 functions. 0 = power savings mode disabled 1 = power savings mode enabled (default) 5 3 r/w subsysrw. subsystem id (ss id), subsystem vendor id (ss vid), and the exca identification and revision registers read/write enable. this bit is shared by functions 0 and 1. 0 = subsystem id , subsystem vendor id , and the exca identification and revision registers are read/write. 1 = subsystem id , subsystem vendor id , and the exca identification and revision registers are read-only (default). 4 3 r/w cb_dpar. cardbus data parity serr signaling enable. 0 = cardbus data parity not signaled on pci serr signal (default) 1 = cardbus data parity signaled on pci serr signal 3 3 r/w cdma_en. pc/pci dma enable. enables pc/pci dma when set, and disables the irqmux7 and irqmux6 signaling. 0 = centralized dma disabled (default) 1 = centralized dma enabled 2 r reserved. this bit returns 0 when read. these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 62 post office box 655303 ? dallas, texas 75265 table 29 . system control register description (continued) bit type function 1 3 r/w keepclk. keep clock. when this bit is set, the PCI1450 will always follow clkrun protocol to maintain the system pclk and the cclk (cardbus clock). this bit is global to the PCI1450 functions. 0 = allow system pclk and cclk to stop (default) 1 = never allow system pclk or cclk clock to stop note that the functionality of this bit has changed versus the pci12xx series of ti cardbus controllers. in these cardbus controllers, setting this bit would only maintain the pci clock, not the cclk. in the PCI1450, setting this bit will maintain both the pci clock and the cclk. 0 3 r/w pme /ri_out select bit. when this bit is 1, the pme signal is routed on to pin y13 (pme /ri_out pin). when this bit is 0 and bit 7 (rienb) of the card control register is 1, the ri_out signal is routed on to pin y13. if this bit is 0 and bit 7 (rienb) of the card control register is 0, then the output (y13) will be 3-stated. this pin is encoded as: 0 = ri_out signal is routed to pin y13 if bit 7 of the card control register is 1*. (default) 1 = pme signal is routed on pin y13 of the PCI1450 controller. note: if this bit (bit 0) is 0 and bit 7 of the card control register is 0 , then the output on pin y13 is 3-stated. these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 63 post office box 655303 ? dallas, texas 75265 multimedia control register bit 73 63 53 43 33 23 13 03 name multimedia control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: multimedia control type: read/write offset: 84h (functions 0, 1) default: 00h description: this register provides port mapping for the PCI1450 zoom video/data ports. see zoomed video support for details on the PCI1450 zoom video support. access this register only through function 0. table 30. multimedia control register description bit type function 7 3 r/w zvouten. zv output enable. this bit enables the output for the PCI1450 outsourcing zv terminals. when this bit is reset, `0', these terminals are in a high impedance state. 0 = PCI1450 zv output terminals disabled (default) 1 = PCI1450 zv output terminals enabled 6 3 r/w portsel. zv port select. this bit controls the multiplexing control over which pc card zv port data will be driven to the outsourcing PCI1450 zv port. 0 = output card 0 zv if enabled (default) 1 = output card 1 zv if enabled 5 3 r/w zoomed video auto-detect. this bit enables the zoomed video auto-detect feature. this bit is encoded as: 0 = zoomed video auto detect disabled (default) 1 = zoomed video auto detect enabled 42 3 r/w auto-detect priority encoding. these bits have meaning only if zoomed video auto-detect is enabled in bit 5 of this register. if auto-detect is enabled, then bits 42 are encoded as follows: 000 = slot a, slot b, external source 001 = slot a, external source, slot b 010 = slot b, slot a, external source 011 = slot b, external source, slot a 100 = external source, slot a, slot b 101 = external source, slot b, slot a 110 = reserved 111 = reserved 1 3 r/w zven1. pc card 1 zv mode enable. enables the zoom video mode for socket 1. when set, the PCI1450 inputs zv data from the pc card interface, and disables output drivers on zv terminals. 0 = pc card 1 zv disabled (default) 1 = pc card 1 zv enabled 0 3 r/w zven0. pc card 0 zv mode enable. enables the zoom video mode for socket 0. when set, the PCI1450 inputs zv data from the pc card interface, and disables output drivers on zv terminals. 0 = pc card 0 zv disabled (default) 1 = pc card 0 zv enabled 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 64 post office box 655303 ? dallas, texas 75265 general status register bit 7 6 5 4 3 23 13 03 name general status type r r r r r r r r default 0 0 0 0 0 x 0 0 register: general status type: read-only offset: 85h (functions 0) default: 00h description: this register provides the general device status information. the status of the serial eeprom interface is provided through this register. table 31. general status register description bit type function 73 r reserved. these bits return 0s when read. 2 3 r eedetect. serial eeprom detect. when this bit is cleared, it indicates that the PCI1450 serial eeprom circuitry has detected an eeprom. a pull-up resistor must be implemented on the latch terminal for this bit to be set. this status bit is encoded as: 0 = eeprom not detected (default) 1 = eeprom detected 1 3 r dataerr. serial eeprom data error status. this bit indicates when a data error occurs on the serial eeprom interface. this bit may be set due to a missing acknowledge. this bit is cleared by a writing a 1. 0 = no error detected. (default) 1 = data error detected. 0 3 r eebusy. serial eeprom busy status. this bit indicates the status of the PCI1450 serial eeprom circuitry. this bit is set during the loading of the subsystem id value. 0 = serial eeprom circuitry is not busy (default). 1 = serial eeprom circuitry is busy. this bit is global in nature and should only be accessed through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 65 post office box 655303 ? dallas, texas 75265 gpio0 control register bit 73 63 5 43 33 2 13 03 name gpio0 control type r/w r/w r r/w r/wc r r/w r/w default 1 0 0 0 0 0 0 0 register: gpio0 control type: read-only, read/write, read/write to clear offset: 88h (functions 0, 1) default: 80h description: this register is used for control of the general-purpose i/o, gpio0. this terminal defaults to a general-purpose input, but can be reconfigured as the socket 0 activity led output, a zoom video enabled status output, or general-purpose output. access this register only through function 0. table 32. gpio0 control register description bit type function 76 3 r/w gp0. general-purpose 0 mode. these bits select the functionality of the leda1/gpio0 signal. these bits are encoded as: 00 = signal leda1 to indicate pc card socket 0 activity 01 = signal zvstat to indicate zoom video output enabled 10 = general-purpose input (gpi) 11 = general-purpose output (gpo) 5 r reserved. this bit returns 0 when read. a write has no effect. 4 3 r/w gpinten0. gp interrupt enable. when this bit is set, a socket a card status change (csc) interrupt is generated when the delta0 bit is set. 3 3 r/wc delta0. datain0 change status. this bit is set when the datain0 bit changes state when in gpi mode. glitches on the gpi terminal may not be detected by software without this bit. this bit is cleared by a write back of 1. 2 r reserved. this bit returns 0 when read. a write has no effect. 1 3 r/w dataout0. general-purpose data output. when in general-purpose output mode, this bit represents the data. data written to this bit in gpo mode is signaled to the output. 0 3 r/w datain0. general-purpose data input. when in either general-purpose input or output mode, this bit represents the data on the gpio terminal. data signaled on the gpi terminal is identified through this bit. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 66 post office box 655303 ? dallas, texas 75265 gpio1 control register bit 73 63 5 4 33 2 13 03 name gpio1 control type r/w r/w r r r/wc r r/w r/w default 1 0 0 0 0 0 0 0 register: gpio1 control type: read-only, read/write, read/write to clear offset: 89h (functions 0, 1) default: 80h description: this register is used for control of the general-purpose i/o, gpio1. this terminal defaults to a general-purpose input, but can be reconfigured as the socket 1 activity led output, or general-purpose output. access this register only through function 0. table 33. gpio1 control register description bit type function 76 3 r/w gp1. general-purpose 1 mode. these bits select the functionality of the leda2/gpio1 signal. these bits are encoded as: 00 = signal leda2 to indicate pc card socket 1 activity 01 = d3_stat . this programs gpio1 as a d3 status pin. d3 status will be asserted if both function 0 and function 1 are placed in the d3 state and pme is enabled via bit 8 of pci offset a4h. 10 = general-purpose input (gpi) 11 = general-purpose output (gpo) 5 r reserved. this bit returns 0 when read. a write has no effect. 4 r reserved. this bit returns 0 when read. a write has no effect. 3 3 r/wc delta1. datain1 change status. this bit is set when the datain1 bit changes state when in gpi mode. glitches on the gpi terminal may not be detected by software without this bit. this bit is cleared by a write back of 1. 2 r reserved. this bit returns 0 when read. a write has no effect. 1 3 r/w dataout1. general-purpose data output. when in general-purpose output mode, this bit represents the data. data written to this bit in gpo mode is signaled to the output. 0 3 r/w datain1. general-purpose data input. when in either general-purpose input or output mode, this bit represents the data on the gpio terminal. data signaled on the gpi terminal is identified through this bit. 3 this bit is cleared only by the assertion of g_rst.
PCI1450 gfn/gjg pc card controller scps044 september 1998 67 post office box 655303 ? dallas, texas 75265 gpio2 control register bit 73 63 5 43 33 2 13 03 name gpio2 control type r/w r/w r r/w r/wc r r/w r/w default 1 0 0 0 0 0 0 0 register: gpio2 control type: read-only, read/write, read/write to clear offset: 8ah (functions 0, 1) default: 80h description: this register is used for control of the general-purpose i/o, gpio2. this terminal defaults to a general-purpose input, but can be reconfigured as the pci lock signal, a zoom video enabled status output, or general-purpose output. access this register only through function 0. table 34. gpio2 control register description bit type function 76 3 r/w gp2. general-purpose 2 mode. these bits select the functionality of the lock /gpio2 signal. these bits are encoded as: 00 = terminal is configured as the pci lock signal. 01 = signal zvstat to indicate zoom video output is enabled. 10 = general-purpose input (gpi) 11 = general-purpose output (gpo) 5 r reserved. this bit returns 0 when read. a write has no effect. 4 3 r/w gpinten2. gp interrupt enable. when this bit and the delta2 bit are set, a socket b csc is generated. 3 3 r/wc delta2. datain2 change status. this bit is set when the datain2 bit changes state when in gpi mode. glitches on the gpi terminal may not be detected by software without this bit. this bit is cleared by a write back of 1. 2 r reserved. this bit returns 0 when read. a write has no effect. 1 3 r/w dataout2. general-purpose data output. when in general-purpose output mode, this bit represents the data. data written to this bit in gpo mode is signaled to the output. 0 3 r/w datain2. general-purpose data input. when in either general-purpose input or output mode, this bit represents the data on the gpio terminal. data signaled on the gpi terminal is identified through this bit. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 68 post office box 655303 ? dallas, texas 75265 gpio3 control register bit 73 63 5 4 33 2 13 03 name gpio3 control type r/w r/w r r r/wc r r/w r/w default 1 0 0 0 0 0 0 0 register: gpio3 control type: read-only, read/write, read/write to clear offset: 8bh (functions 0, 1) default: 80h description: this register is used for control of the general-purpose i/o, gpio3. this terminal defaults to a general-purpose input, but can be reconfigured as the pci inta signal, or general-purpose output. access this register only through function 0. table 35. gpio3 control register description bit type function 76 3 r/w gp3. general-purpose 3 mode. these bits select the functionality of the inta /gpio3 signal. these bits are encoded as: 00 = terminal is configured as the pci inta signal. 01 = reserved. 10 = general-purpose input (gpi) 11 = general-purpose output (gpo) 5 r reserved. this bit returns 0 when read. a write has no effect. 4 r reserved. this bit returns 0 when read. a write has no effect. 3 3 r/wc delta3. datain3 change status. this bit is set when the datain3 bit changes state when in gpi mode. glitches on the gpi terminal may not be detected by software without this bit. this bit is cleared by a write back of 1. 2 r reserved. this bit returns 0 when read. a write has no effect. 1 3 r/w dataout3. general-purpose data output. when in general-purpose output mode, this bit represents the data. data written to this bit in gpo mode is signaled to the output. 0 3 r/w datain3. general-purpose data input. when in either general-purpose input or output mode, this bit represents the data on the gpio terminal. data signaled on the gpi terminal is identified through this bit. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 69 post office box 655303 ? dallas, texas 75265 irqmux routing register bit 313 303 293 283 273 263 253 243 233 223 213 203 193 183 173 163 name irqmux routing type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 153 143 133 123 113 103 93 83 73 63 53 43 33 23 13 03 name irqmux routing type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: irqmux routing type: read/write offset: 8ch (functions 0, 1) default: 0000 0000h description: this register is used for the legacy interrupt mux routing feature of the PCI1450, which is described in the programmable interrupt support section. if the parallel irq interrupt scheme is selected, then all PCI1450 interrupts sent to isa irqs will be signaled on the corresponding irqmux7irqmux0 signals. these signals are routed directly to various irq inputs on the system pic. the routing information is programmed through this register. each terminal has at least one secondary function that can be selected by programming the bits appropriately. access this register only through function 0. table 36. irqmux routing register description bit type function 3128 3 r/w irqmux7 routing. these bits select 1 of 15 interrupts that can be routed on the irqmux7 pin. when these bits are 0000 and bit 3 in the system control register is set, this pin is used for pcreq dma signaling. note: these bits should not be configured for irq signaling if irqmux7 is being used for pcreq signaling. 0000 = eeprom scl routed on irqmux7 pin (default) 0000 = pcreq routed on irqmux 7 pin when bit 3 of the system control register is 1 0001 = pc/pci dma request (pcreq ) routed on irqmux7 pin 0010 = irq2 routed on irqmux7 pin 0011 = irq3 routed on irqmux7 pin : 1111 = irq15 routed on irqmux7 pin 2724 3 r/w irqmux6 routing. these bits select 1 of 15 interrupts that can be routed on the irqmux6 pin. when these bits are 0000 and bit 3 is the system control register is set, this pin is used for pcgnt dma signaling. note: these bits should not be configured for irq signaling if irqmux6 is being used for pcgnt signaling. an eeprom cannot be used if irqmux7 and irqmux 6 are being used for dma pcreq and pcgnt . 0000 = eeprom sda routed on irqmux6 pin (default) 0000 = pcgnt routed on irqmux6 pin when bit 3 of the system control register is 1 0001 = irq1 routed on irqmux6 pin 0010 = irq2 routed on irqmux6 pin : 1111 = irq15 routed on irqmux6 pin these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 70 post office box 655303 ? dallas, texas 75265 table 36 . irqmux routing register description (continued) bit type function 2320 3 r/w irqmux5 routing. these bits select 1 of 15 interrupts that the irqmux5 signal may be routed. when these bits are in the default state of all 0s, then no routing is selected. 0000 = no irq routing selected (default) 0001 = cardbus audio (cbaudio) routed on irqmux5 pin 0010 =gpe on irqmux5 pin 0011 = irq3 routed on irqmux5 pin : 1111 = irq15 routed on irqmux5 pin 1916 3 r/w irqmux4 routing. these bits select 1 of 15 interrupts that the irqmux4 signal may be routed. when these bits are in the default state of all 0s, then no routing is selected. 0000 = no irq routing selected (default) 0001 = zvstat is routed on irqmux4 pin 0010 = ri_out is routed on irqmux4 pin 0011 = irq3 routed on irqmux4 pin 0100 = irq4 routed on irqmux4 pin : 1111 = irq15 routed on irqmux4 pin 1512 3 r/w irqmux3 routing. these bits select 1 of 15 interrupts that the irqmux3 signal may be routed. when these bits are in the default state of all 0s, then no routing is selected. 0000 = no irq routing selected (default) 0001 = leda or ledb routed on irqmux3 pin 0010 = ri_out routed on irqmux3 pin 0011 = irq3 routed on irqmux3 pin 0100 = irq4 routed on irqmux3 pin : 1111 = irq15 routed on irqmux3 118 3 r/w irqmux2 routing. these bits select 1 of 15 interrupts that the irqmux2 signal may be routed. when these bits are in the default state of all 0s, then no routing is selected. 0000 = no irq routing selected (default) 0001 = ledb routed on irqmux2 pin 0010 = zoomed video pixel clock (pclk) input 0011 = irq3 routed on irqmux2 pin : 1111 = irq15 routed on irqmux2 pin 74 3 r/w irqmux1 routing. these bits select 1 of 15 interrupts that the irqmux1 signal may be routed. when these bits are in the default state of all 0s, then no routing is selected. 0000 = no irq routing selected (default) 0001 = leda routed on irqmux1 pin 0010 = irq2 routed on irqmux1 pin 0011 = irq3 routed on irqmux1 pin : 1111 = irq15 routed on irqmux1 pin 30 3 r/w irqmux0 routing. these bits select 1 of 15 interrupts that the irqmux0 signal may be routed. when these bits are in the default state of all 0s, then no routing is selected. 0000 = no irq routing selected (default) 0001 = intb routed on irqmux0 pin 0010 = irq2 routed on irqmux0 pin 0011 = irq3 routed on irqmux0 pin : 1111 = irq15 routed on irqmux0 pin 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 71 post office box 655303 ? dallas, texas 75265 retry status register bit 73 63 53 4 33 2 13 0 name retry status type r/w r/w r/wc r r/wc r r/wc r default 1 1 0 0 0 0 0 0 register: retry status type: read-only, read/write offset: 90h (functions 0, 1) default: c0h description: the contents of this register enable the retry time-out counters and display the retry expiration status. the flags are set when the PCI1450 retries a pci or cardbus master request, and the master does not return within 2 15 pci clock cycles. the flags are cleared by writing a 1 to the bit. these bits are expected to be incorporated into the pci command register , pci status register , and bridge control register by the pci sig. access this register only through function 0. table 37. retry status register description bit type function 7 3 r/w pciretry. pci retry time-out counter enable. this bit is encoded as: 0 = pci retry counter disabled 1 = pci retry counter enabled (default) 6 3 r/w cbretry. cardbus retry time-out counter enable. this bit is encoded as: 0 = cardbus retry counter disabled 1 = cardbus retry counter enabled (default) 5 3 r/wc texp_cbb. cardbus target b retry expired. write a 1 to clear this bit. 0 = inactive (default) 1 = retry has expired. 4 r reserved. this bit returns 0 when read. 3 3 r/wc texp_cba. cardbus target a retry expired. write a 1 to clear this bit. 0 = inactive (default) 1 = retry has expired. 2 r reserved. this bit returns 0 when read. 1 3 r/wc texp_pci. pci target retry expired. write a 1 to clear this bit. 0 = inactive (default) 1 = retry has expired. 0 r reserved. this bit returns 0 when read. these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 72 post office box 655303 ? dallas, texas 75265 card control register bit 73 63 5 4 3 23 13 03 name card control type r/w r/w r/w r r r/w r/w r/w default 0 0 0 0 0 0 0 0 register: card control type: read-only, read/write offset: 91h default: 00h description: this register is provided for pci1130 compatibility. the contents provide the pc card function interrupt flag (ifg) and an alias for the zven0 and zven1 bits found in the PCI1450 multimedia control register . when this register is accessed by function 0, the zven0 bit will alias with zvenable. when this register is accessed by function 1, the zven1 bit will alias with zvenable. setting zvenable only places the pc card socket interface zv terminals in a high impedance state, but does not enable the PCI1450 to drive zv data onto the zv terminals. the ri_out signal is enabled through this register, and the enable bit is shared between functions 0 and 1. table 38. card control register description bit type function 7 3 r/w rienb. ring indicate enable. when this bit is 1, the ri_out output is enabled. this bit is global in nature and should be accessed only through function 0. this bit defaults to 0. 6 3 r/w zvenable. compatibility zv mode enable. when this bit is 1, the corresponding pc card socket interface zv terminals will enter a high impedance state. this bit defaults to 0. 5 r/w reserved. 43 r reserved. these bits default to 0. 2 3 r/w aud2mux. cardbus audio-to-irqmux. when this bit is set, the caudio cardbus signal is routed to the corresponding irqmux terminal. function 0, a_caudio, is routed to irqmux0 and function 1, b_caudio, is routed to irqmux1. if this bit is set for both functions, then function 0 gets routed. 0 = caudio set to caudpwm on irqmux pin (default) 1 = caudio is not routed. 1 3 r/w spkrouten. speaker output enable. when this bit is 1, it enables spkr on the pc card and routes it to spkrout on the pci bus. the spkr signal from socket 0 is xor'ed with the spkr signal from socket 1 and sent to spkrout. the spkrout terminal only drives data then either functions spkrouten bit is set. this bit is encoded as: 0 = spkr to spkrout not enabled (default) 1 = spkr to spkrout enabled 0 3 r/w ifg. interrupt flag. this bit is the interrupt flag for 16-bit i/o pc cards and for cardbus cards. this bit is set when a funct ional interrupt is signaled from a pc card interface, and is socket dependent (i.e., not global). write back a `1' to clear this bit. 0 = no pc card functional interrupt detected (default) 1 = pc card functional interrupt detected these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 73 post office box 655303 ? dallas, texas 75265 device control register bit 73 63 53 4 33 23 13 03 name device control type r/w r/w r/w r r/w r/w r/w r/w default 0 1 1 0 0 1 1 0 register: device control type: read-only, read/write offset: 92h (functions 0, 1) default: 66h description: this register is provided for pci1130 compatibility. it contains bits which are shared between functions 0 and 1. the interrupt mode select is programmed through this register. the socket capable force bits are also programmed through this register. table 39. device control register description bit type function 7 3 r/w socket power lock bit. when this bit is set to 1, software will not be able to power down the pc card socket while in d3. this may be necessary to support wake on lan or ring if the operating system is programmed to power down a socket when the cardbus controller is placed in the d3 state. 6 3 r/w 3vcapable. 3-v socket capable force bit. 0 = not 3-v capable 1 = 3-v capable (default) 5 3 r/w io16r2. diagnostic bit. this bit defaults to 1. 4 r reserved. this bit returns 0 when read. a write has no effect. 3 3 r/w test. ti test bit. write only 0 to this bit. this bit can be set to shorten the interrogation counter. 21 3 r/w intmode. interrupt mode. these bits select the interrupt signaling mode. the interrupt mode bits are encoded: 00 = parallel pci interrupts only 01 = parallel irq & parallel pci interrupts 10 = irq serialized interrupts & parallel pci interrupts inta and intb 11 = irq & pci serialized interrupts (default) 0 3 r/w reserved. nand tree enable bit. there is a nand tree diagnostic structure in the PCI1450, and it tests only the pins that are inputs or i/os. any output only terminal on the PCI1450 is excluded from the nand tree test. these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 74 post office box 655303 ? dallas, texas 75265 diagnostic register bit 73 63 53 43 33 23 13 03 name diagnostic type r/w r/w r/w r/w r/w r/w r/w r/w default 0 1 1 0 0 0 0 1 register: diagnostic type: read/write offset: 93h (functions 0, 1) default: 61h description: this register is provided for internal texas instruments test purposes. table 40. diagnostic register description bit type function 7 3 r/w this bit defaults to 0. this bit is encoded as: 0 = reads true values in pci vendor id and pci device id registers (default). 1 = reads all ones in reads to the pci vendor id and pci device id registers . 6 3 r/w reserved. 5 3 r/w csc interrupt routing control 0 = csc interrupts routed to pci if exca 803 bit 4 = 1. 1 = csc interrupts routed to pci if exca 805 bits 74 = 0000b. (default) in this case, the setting of exca 803 bit 4 is a adon't care.o 4 3 r/w diag. diagnostic retry_dis. delayed transaction disable. 3 3 r/w diag. diagnostic retry_ext. extends the latency from 16 to 64. 2 3 r/w diag. diagnostic discard_tim_sel_cb. set = 2 10 , reset = 2 15 1 3 r/w diag. diagnostic discard_tim_sel_pci. set = 2 10 , reset = 2 15 0 3 r/w async_csc. asynchronous interrupt generation. 0 = csc interrupt not generated asynchronously 1 = csc interrupt is generated asynchronously (default) these bits are global in nature and should be accessed only through function 0. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 75 post office box 655303 ? dallas, texas 75265 socket dma register 0 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket dma register 0 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 13 03 name socket dma register 0 type r r r r r r r r r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: dma socket register 0 type: read-only, read/write offset: 94h (functions 0, 1) default: 0000 0000h description: this register provides control over the pc card dreq (dma request) signaling. table 41. socket dma register 0 description bit type function 312 r reserved. these bits return 0s when read. 10 3 r/w dreqpin. dma request (dreq ) pin. these bits indicate which pin on the 16-bit pc card interface will as the dreq signal during dma transfers. this field is encoded as: 00 = socket not configured for dma (default) 01 = dreq uses spkr 10 = dreq uses iois16 11 = dreq uses inpack 3 this bit is cleared only by the assertion of g_rst.
PCI1450 gfn/gjg pc card controller scps044 september 1998 76 post office box 655303 ? dallas, texas 75265 socket dma register 1 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket dma register 1 type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 153 143 133 123 113 103 93 83 73 63 53 43 33 23 13 03 name socket dma register 1 type r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: dma socket register 1 type: read-only, read/write offset: 98h (functions 0, 1) default: 0000 0000h description: the contents of this register provide control over the distributed dma (ddma) registers and the pci portion of dma transfers. the dma base address locates the ddma registers in a 16-byte region within the first 64k bytes of pci i/o address space. note that 32-bit transfers to the 16-bit pc card interface are not supported; the maximum transfer possible to the pc card interface is 16-bits. however, 32 bits of data are prefetched from the pci bus, thus allowing back-to-back 16-bit transfers to the pc card interface. table 42. socket dma register 1 description bit type function 3116 r reserved. these bits return 0s when read. 154 3 r/w dmabase. dma base address. locates the socket's dma registers in pci i/o space. this field represents a 16-bit pci i/o address. the upper 16 bits of the address are hard-wired to 0, forcing this window to within the lower 64k bytes of i/o address space. the lower four bits are hard-wired to 0, and are included in the address decode. thus, the window is aligned to a natural 16-byte boundary 3 3 r extmode. extended addressing. this feature is not supported by the PCI1450, and always returns a 0. 21 3 r/w xfersize. transfer size. these bits specify the width of the dma transfer on the pc card interface, and are encoded as: 00 = transfers are 8 bits (default). 01 = transfers are 16 bits. 10 = reserved 11 = reserved 0 3 r/w ddmaen. ddma registers decode enable. enables the decoding of the distributed dma registers based upon the value of dmabase. 0 = disabled (default) 1 = enabled 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 77 post office box 655303 ? dallas, texas 75265 capability id register bit 7 6 5 4 3 2 1 0 name capability id type r r r r r r r r default 0 0 0 0 0 0 0 1 register: capability id type: read-only offset: a0h default: 01h description: this register identifies the linked list item as the register for pci power management. the register returns 01h when read, which is the unique id assigned by the pci sig for the pci location of the capabilities pointer and the value. next item pointer register bit 7 6 5 4 3 2 1 0 name next item pointer type r r r r r r r r default 0 0 0 0 0 0 0 0 register: next item pointer type: read-only offset: a1h default: 00h description: the contents of this register indicate the next item in the linked list of the pci power management capabilities. since the PCI1450 functions only include one capabilities item, this register returns 0s when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 78 post office box 655303 ? dallas, texas 75265 power management capabilities register bit 152 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name power management capabilities type r/w r r r r r r r r r r r r r r r default 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 register: power management capabilities type: read-only, read/write offset: a2h (functions 0, 1) default: fe11h description: this register contains information on the capabilities of the pc card function related to power management. both PCI1450 cardbus bridge functions support d0, d2, and d3 power states. table 43. power management capabilities register description bit type function 152 1411 r/w r pme support. this 5-bit field indicates the power states from which the PCI1450 device functions may assert pme . a 0b (zero) for any bit indicates that the function cannot assert the pme signal while in that power state. these five bits return 0fh when read. each of these bits is described below: bit 15 defaults to the value 1 indicating the pme signal can be asserted from the d3 cold state. this bit is r/w because wake-up support from d3 cold is contingent on the system providing an auxiliary power source to the v cc terminals. if the system designer chooses not to provide an auxiliary power source to the v cc terminals for d3 cold wake-up support, then bios should write a 0 to this bit. bit 14 contains the value 1 indicating that the pme signal can be asserted from the d3 hot state. bit 13 contains the value 1 to indicate that the pme signal can be asserted from the d2 state. bit 12 contains the value 1 to indicate that the pme signal can be asserted from the d1 state. bit 11 contains the value 1 indicating that the pme signal can be asserted from the d0 state. 10 r d2_support. this bit returns a 1 when read, indicating that the function supports the d2 device power state. 9 r d1_support. this bit returns a 1 when read, indicating that the function supports the d1 device power state. 86 r reserved. these bits return 000b when read. 5 r dsi. device specific initialization. this bit returns 0 when read. 4 r aux_pwr. auxiliary power source. this bit is meaningful only if bit 15 (d3 cold supporting pme ) is set. when this bit is set, it indicates that support for pme in d3 cold requires auxiliary power supplied by the system by way of a proprietary delivery vehicle. a 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source. if the function does not support pme while in the d3 cold state (bit 15=0), then this field must always return 0. 3 r pmeclk. when this bit is 1, it indicates that the function relies on the presence of the pci clock for pme operation. when this bit is 0, it indicates that no pci clock is required for the function to generate pme . functions that do not support pme generation in any state must return 0 for this field. 20 r version. these 3 bits return 001b when read, indicating that there are 4 bytes of general-purpose power management (pm) registers as described in the draft revision 1.0 pci bus power management interface specification. 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 79 post office box 655303 ? dallas, texas 75265 power management control/status register bit 152 14 13 12 11 10 9 82 7 6 5 4 3 2 1 0 name power management control/status type r/wc r r r r r r r/w r r r r r r r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: power management control/status type: read-only, read/write , read/write to clear offset: a4h (functions 0, 1) default: 000000h description: this register determines and changes the current power state of the PCI1450 cardbus function. the contents of this register are not affected by the internally generated reset caused by the transition from the d3 hot to d0 state. all pci registers, exca registers, and cardbus registers are reset as a result of a d3 hot -to-d0 state transition, with the exception of the pme context bits (if pme is enabled) and the g_rst only bits. table 44. power management control/status register description bit type function 152 r/wc pmestat. pme status. this bit is set when the cardbus function would normally assert the pme signal, independent of the state of the pme_en bit. this bit is cleared by a write back of 1, and this also clears the pme signal if pme was asserted by this function. writing a 0 to this bit has no effect. 1413 r datascale. this 2-bit field returns 0s when read. the cardbus function does not return any dynamic data, as indicated by the dyn_data bit. 129 r datasel. data select. this 4-bit field returns 0s when read. the cardbus function does not return any dynamic data, as indicated by the dyn_data bit. 82 r/w pme enable. this bit enables the function to assert pme . if this bit is cleared, then assertion of pme is disabled. this bit will not be cleared by the assertion of prst . it will only be cleared by the assertion of g_rst . 72 r reserved. these bits return 0s when read. 10 r/w pwrstate. power state. this 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. this field is encoded as: 00 = d0 01 = d1 10 = d2 11 = d3 hot 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 80 post office box 655303 ? dallas, texas 75265 power management control/status register bridge support extensions bit 7 6 5 4 3 2 1 0 name power management control/status register bridge support extensions type r r r r r r r r default 1 1 0 0 0 0 0 0 register: power management control/status register bridge support extensions type: read-only offset: a6h (functions 0, 1) default: c0h description: this register supports pci bridge specific functionality. it is required for all pci-to-pci bridges. table 45. pmcsr_bse bridge support extensions bit type function 7 r bpcc_enable. bus power/clock control enable. this bit returns 1 when read. this bit is encoded as: 0 = bus power/clock control is disabled. 1 = bus power/clock control is enabled (default). a 0 indicates that the bus power/clock control policies defined in the pci power management specification are disabled. when the bus power/clock control enable mechanism is disabled, the bridge's pmcsr powerstate field cannot be used by the system software to control the power or the clock of the bridge's secondary bus. a 1 indicates that the bus power/clock control mechanism is enabled. when bus power/clock control is disabled, the bridge's pmcsr power state field cannot be used by the system software to control power or the clock of the bridge's secondary bus. 6 r b2_b3 . b2/b3 support for d3 hot . the state of this bit determines the action that is to occur as a direct result of programming the function to d3 hot . this bit is only meaningful if bit 7 (bpcc_enable) is a 1. this bit is encoded as: 0 = when the bridge is programmed to d3 hot , its secondary bus will have its power removed (b3). 1 = when the bridge function is programmed to d3 hot , its secondary bus's pci clock will be stopped (b2). (default) 50 r reserved. these bits return 0s when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 81 post office box 655303 ? dallas, texas 75265 gpe control/status register bit 15 14 13 12 11 103 93 83 7 6 5 4 3 23 13 03 name gpe control/status type r r r r r r/wc r/wc r/wc r r r r r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: gpe control/status type: read-only, read/write, read/write to clear offset: a8h default: 0001h description: if the gpe (general-purpose event) function is programmed onto the irqmux5 pin by writing 0010b to bits 2320 of the multifunction routing register (pci offset 8ch), then this register may be used to program which events will cause gpe to be asserted and report the status. table 46. gpe control/status register description bit type function 1511 r reserved. these bits return 0s when read. 10 3 r/wc zv1_sts. pc card socket 1 status. this bit is set on a change in status of the zvenable bit in function 1. 9 3 r/wc zv0_sts. pc card socket 0 status. this bit is set on a change in status of the zvenable bit in function 0. 8 3 r/wc vpp12_sts. 12 volt v pp request status. this bit is set when software has changed the requested v pp level to or from 12 volts from either socket. 73 r reserved. these bits return 0s when read. 2 3 r/w zv1_en. pc card socket 1 zoomed video event enable. when this bit is set, gpe is signaled on a change in status of the zvenable bit in function 1 of the pc card controller. 1 3 r/w zv0_en. pc card socket 0 zoomed video event enable. when this bit is set, gpe is signaled on a change in status of the zvenable bit in function 0 of the pc card controller. 0 3 r/w vpp12_en. 12 volt v pp request event enable. when this bit is set, a gpe is signaled when software has changed the requested v pp level to or from 12 volts for either socket. 3 this bit is cleared only by the assertion of g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 82 post office box 655303 ? dallas, texas 75265 exca compatibility registers (functions 0 and 1) the exca (exchangeable card architecture) registers implemented in the PCI1450 are register-compatible with the popular intel 82365sl-df pcmcia controller. exca registers are identified by an offset value, which is compatible with the legacy i/o index/data scheme used on the intel 82365 isa controller. the exca registers are accessed through this scheme by writing the register offset value into the index register (i/o base), and reading or writing the data register (i/o base + 1). the i/o base address used in the index/data scheme is programmed in the pc card 16-bit i/f legacy mode base address register , which is shared by both card sockets. the offsets from this base address run contiguous from 00h to 3fh for socket a, and from 40h to 7fh for socket b. refer to figure 19 for an exca i/o mapping illustration. table 47 identifies each exca register and its respective exca offset. the ti PCI1450 also provides a memory mapped alias of the exca registers by directly mapping them into pci memory space. they are located through the cardbus socket registers/exca registers base address register (pci register 10h) at memory offset 800h. each socket has a separate base address programmable by function. refer to figure 20 for an exca memory mapping illustration. note that memory offsets are 800h844h for both functions 0 and 1. this illustration also identifies the cardbus socket register mapping, which is mapped into the same 4k window at memory offset 0h. the interrupt registers, as defined by the 82365sl specification, in the exca register set control such card functions as reset, type, interrupt routing, and interrupt enables. special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI1450 to ensure that all possible PCI1450 interrupts can potentially be routed to the programmable interrupt controller. the exca registers that are critical to the interrupt signaling are at memory address exca offset 803h and 805h. access to i/o mapped 16-bit pc cards is available to the host system via two exca i/o windows. these are regions of host i/o address space into which the card i/o space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. i/o windows have byte granularity. access to memory mapped 16-bit pc cards is available to the host system via five exca memory windows. these are regions of host memory space into which the card memory space is mapped. these windows are defined by start, end, and offset addresses programmed in the exca registers described in this section. memory windows have 4k byte granularity. a bit location followed by a 3 means that this bit is not cleared by the assertion of prst . this bit will only be cleared by the assertion of g_rst . this is necessary to retain device context when transitioning from d3 to d0.
PCI1450 gfn/gjg pc card controller scps044 september 1998 83 post office box 655303 ? dallas, texas 75265 PCI1450 configuration registers 10h card bus socket / exca base address 16bit legacy mode base address note: the 16bit legacy mode base address register is shared by function 0 and 1 as indicated by the shading. 44h index data host i/o space pc card a exca registers pc card b exca registers 00h offset 3fh 40h 7fh offset of desired register is placed in the index register and the data from that location is returned in the data register. figure 19. exca register access through i/o PCI1450 configuration registers 16-bit legacy-mode base address cardbus socket/exca base address . . . . . . . . 10h 44h cardbus socket a registers exca registers card a offset 00h 20h 800h 844h host memory space cardbus socket b registers exca registers card b offset 00h 20h 800h 844h host memory space note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. offset address register's base address offsets are from the cardbus socket/exca base figure 20. exca register access through memory
PCI1450 gfn/gjg pc card controller scps044 september 1998 84 post office box 655303 ? dallas, texas 75265 table 47. exca registers and offsets register name pci memory address offset exca offset (card a) exca offset (card b) identification and revision 800 00 40 interface status 801 01 41 power control 2 8022 02 42 interrupt and general control 2 8032 03 43 card status change 2 8042 04 44 card status change interrupt configuration 2 8052 05 45 address window enable 806 06 46 i / o window control 807 07 47 i / o window 0 start-address low-byte 808 08 48 i / o window 0 start-address high-byte 809 09 49 i / o window 0 end-address low-byte 80a 0a 4a i / o window 0 end-address high-byte 80b 0b 4b i / o window 1 start-address low-byte 80c 0c 4c i / o window 1 start-address high-byte 80d 0d 4d i / o window 1 end-address low-byte 80e 0e 4e i / o window 1 end-address high-byte 80f 0f 4f memory window 0 start-address low-byte 810 10 50 memory window 0 start-address high-byte 811 11 51 memory window 0 end-address low-byte 812 12 52 memory window 0 end-address high-byte 813 13 53 memory window 0 offset-address low-byte 814 14 54 memory window 0 offset-address high-byte 815 15 55 card detect and general control 816 16 56 reserved 817 17 57 memory window 1 start-address low-byte 818 18 58 memory window 1 start-address high-byte 819 19 59 memory window 1 end-address low-byte 81a 1a 5a memory window 1 end-address high-byte 81b 1b 5b memory window 1 offset-address low-byte 81c 1c 5c memory window 1 offset-address high-byte 81d 1d 5d global control 81e 1e 5e reserved 81f 1f 5f memory window 2 start-address low-byte 820 20 60 memory window 2 start-address high-byte 821 21 61 memory window 2 end-address low-byte 822 22 62 memory window 2 end-address high-byte 823 23 63 memory window 2 offset-address low-byte 824 24 64 memory window 2 offset-address high-byte 825 25 65 reserved 826 26 66 reserved 827 27 67 2 one or more bits in this register are cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 85 post office box 655303 ? dallas, texas 75265 table 47. exca registers and offsets (continued) register name pci memory address offset exca offset (card a) exca offset (card b) memory window 3 start-address low-byte 828 28 68 memory window 3 start-address high-byte 829 29 69 memory window 3 end-address low-byte 82a 2a 6a memory window 3 end-address high-byte 82b 2b 6b memory window 3 offset-address low-byte 82c 2c 6c memory window 3 offset-address high-byte 82d 2d 6d reserved 82e 2e 6e reserved 82f 2f 6f memory window 4 start-address low-byte 830 30 70 memory window 4 start-address high-byte 831 31 71 memory window 4 end-address low-byte 832 32 72 memory window 4 end-address high-byte 833 33 73 memory window 4 offset-address low-byte 834 34 74 memory window 4 offset-address high-byte 835 35 75 i/o window 0 offset-address low-byte 836 36 76 i/o window 0 offset-address high-byte 837 37 77 i/o window 1 offset-address low-byte 838 38 78 i/o window 1 offset-address high-byte 839 39 79 reserved 83a 3a 7a reserved 83b 3b 7b reserved 83c 3c 7c reserved 83d 3d 7d reserved 83e 3e 7e reserved 83f 3f 7f memory window page register 0 840 - - memory window page register 1 841 - - memory window page register 2 842 - - memory window page register 3 843 - - memory window page register 4 844 - -
PCI1450 gfn/gjg pc card controller scps044 september 1998 86 post office box 655303 ? dallas, texas 75265 exca identification and revision register (index 00h) bit 7 6 5 4 3 2 1 0 name exca identification and revision type r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 0 0 0 1 0 0 register: exca identification and revision type: read/write offset: cardbus socket address + 800h: card a exca offset 00h card b exca offset 40h default: 84h description: this register provides host software with information on 16-bit pc card support and 82365sl-df compatibility. note: if bit 5 (subsyrw) in the system control register is 1, then this register is read-only. table 48. exca identification and revision register description bit type function 76 r/w iftype. interface type. these bits, which are hardwired as 10b, identify the 16-bit pc card support provided by the PCI1450. the PCI1450 supports both i/o and memory 16-bit pc cards. 54 r/w reserved. these bits can be used for 82365sl emulation. 3 0 r/w 365rev. 82365sl revision. this field stores the 82365sl revision supported by the PCI1450. host software may read this field to determine compatibility to the 82365sl register set. this field defaults to 0100b upon reset.
PCI1450 gfn/gjg pc card controller scps044 september 1998 87 post office box 655303 ? dallas, texas 75265 exca interface status register (index 01h) bit 7 6 5 4 3 2 1 0 name exca interface status type r r r r r r r r default 0 0 x x x x x x register: exca interface status type: read-only offset: cardbus socket address + 801h: card a exca offset 01h card b exca offset 41h default: 00xx xxxxb description: this register provides information on current status of the pc card interface. an x in the default bit values indicates that the value of the bit after reset depends on the state of the pc card interface. table 49. exca interface status register description bit type function 7 r reserved. this bit returns 0 when read. a write has no effect. 6 r cardpwr. card power. this bit indicates the current power status of the pc card socket. this bit reflects how the exca power control register has been programmed. the bit is encoded as: 0 = v cc and v pp to the socket is turned off (default). 1 = v cc and v pp to the socket is turned on. 5 r ready. this bit indicates the current status of the ready signal at the pc card interface. 0 = pc card is not ready for a data transfer. 1 = pc card is ready for a data transfer. 4 r cardwp. card write protect. this bit indicates the current status of the wp signal at the pc card interface. this signal reports to the PCI1450 whether or not the memory card is write protected. further, write protection for an entire PCI1450 16-bit memory window is available by setting the appropriate bit in the exca memory window offset-address high byte register . 0 = wp signal is 0. pc card is r/w. 1 = wp signal is 1. pc card is read-only. 3 r cdetect2. card detect 2. this bit indicates the status of the cd2 signal at the pc card interface. software may use this and cdetect1 to determine if a pc card is fully seated in the socket. 0 = cd2 signal is 1. no pc card inserted. 1 = cd2 signal is 0. pc card at least partially inserted. 2 r cdetect1. card detect 1. this bit indicates the status of the cd1 signal at the pc card interface. software may use this and cdetect2 to determine if a pc card is fully seated in the socket. 0 = cd1 signal is 1. no pc card inserted. 1 = cd1 signal is 0. pc card at least partially inserted. 10 r bvdstat. battery voltage detect. when a 16-bit memory card is inserted, the field indicates the status of the battery voltage detect signals (bvd1, bvd2) at the pc card interface, where bit 0 reflects the bvd1 status, and bit 1 reflects bvd2. 00 = battery is dead. 01 = battery is dead. 10 = battery is low; warning. 11 = battery is good. when a 16-bit i/o card is inserted, this field indicates the status of the spkr (bit 1) signal and the stschg (bit 0) at the pc card interface. in this case, the two bits in this field directly reflect the current state of these card outputs.
PCI1450 gfn/gjg pc card controller scps044 september 1998 88 post office box 655303 ? dallas, texas 75265 exca power control register (index 02h) bit 7 6 5 42 32 2 12 02 name exca power control type r/w r r r/w r/w r r/w r/w default 0 0 0 0 0 0 0 0 register: exca power control type: read-only, read/write offset: cardbus socket address + 802h: card a exca offset 02h card b exca offset 42h default: 00h description: this register provides pc card power control. bit 7 of this register controls the 16-bit output enables on the socket interface, and can be used for power management in 16-bit pc card applications. table 50. exca power control register description bit type function 7 r/w coe. card output enable. this bit controls the state of all of the 16-bit outputs on the PCI1450. this bit is encoded as: 0 = 16-bit pc card outputs are disabled (default). 1 = 16-bit pc card outputs are enabled. 65 r reserved. these bits return 0s when read. writes have no effect. 432 r/w excavcc. v cc . these bits are used to request changes to card v cc . this field is encoded as: 00 = 0 v (default) 01 = 0 v reserved 10 = 5 v 11 = 3 v 2 r reserved. this bit returns 0 when read. a write has no effect. 102 r/w excavpp. v pp . these bits are used to request changes to card v pp . the PCI1450 ignores this field unless v cc to the socket is enabled (i.e., 5 vdc or 3.3 vdc). this field is encoded as: 00 = 0 v (default) 01 = v cc 10 = 12 v 11 = 0 v reserved 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 89 post office box 655303 ? dallas, texas 75265 exca interrupt and general control register (index 03h) bit 7 62 5 4 3 2 1 0 name exca interrupt and general control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca interrupt and general control type: read/write offset: cardbus socket address + 803h: card a exca offset 03h card b exca offset 43h default: 00h description: this register controls interrupt routing for i/o interrupts as well as other critical 16-bit pc card functions. table 51. exca interrupt and general control register description bit type function 7 r/w ringen. card ring indicate enable. enables the ring indicate function of the bvd1/ri pins. this bit is encoded as: 0 = ring indicate disabled (default) 1 = ring indicate enabled 62 r/w card reset. this bit controls the 16-bit pc card reset signal, and allows host software to force a card reset. this bit affects 16-bit cards only. this bit is encoded as: 0 = reset signal asserted (default) 1 = reset signal deasserted. 5 r/w cardtype. card type. this bit indicates the pc card type. this bit is encoded as: 0 = memory pc card is installed (default) 1 = i/o pc card is installed 4 r/w cscroute. pci interrupt csc routing enable bit. this bit has meaning only if the csc interrupt routing control bit (pci offset 93h, bit 5) is 0b. in this case, when this bit is set (high), the card status change interrupts are routed to pci interr upts. when low the card status change interrupts are routed, using bits 74 in the exca card status change interrupt configuration register . this bit is encoded as: 0 = csc interrupts routed by exca registers (default) 1 = csc interrupts routed to pci interrupts if the csc interrupt routing control bit (pci offset 93h, bit 5) is set to 1b, this bit has no meaning which is the default cas e. 30 r/w intselect. card interrupt select for i/o pc card functional interrupts. these bits select the interrupt routing for i/o pc card functional interrupts. this field is encoded as: 0000 = no isa interrupt routing (default). csc interrupts routed to pci interrupts. 0001 = irq1 enabled 0010 = smi enabled 0011 = irq3 enabled 0100 = irq4 enabled 0101 = irq5 enabled 0110 = irq6 enabled 0111 = irq7 enabled 1000 = irq8 enabled 1001 = irq9 enabled 1010 = irq10 enabled 1011 = irq11 enabled 1100 = irq12 enabled 1101 = irq13 enabled 1110 = irq14 enabled 1111 = irq15 enabled 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 90 post office box 655303 ? dallas, texas 75265 exca card status-change register (index 04h) bit 7 6 5 4 32 22 12 02 name exca card status-change type r r r r r r r r default 0 0 0 0 0 0 0 0 register: exca card status - change type: read-only offset: cardbus socket address + 804h: card a exca offset 04h card b exca offset 44h default: 00h description: this register reflects the status of pc card csc interrupt sources. the exca card status change interrupt configuration register enables these interrupt sources to generate an interrupt to the host. when the interrupt source is disabled, the corresponding bit in this register always reads as 0. when an interrupt source is enabled and that particular event occurs, the corresponding bit in this register is set to indicate the interrupt source. after generating the interrupt to the host, the interrupt service routine must read this register to determine the source of the interrupt. the interrupt service routine is responsible for resetting the bits in this register, as well. resetting a bit is accomplished by one of two methods: a read of this register, or an explicit write back of 1 to the status bit. the choice of these two methods is based on the interrupt flag clear mode select, bit 2, in the exca global control register . table 52. exca card status-change register description bit type function 74 r reserved. these bits return 0s when read. writes have no effect. 32 r cdchange. card detect change. this bit indicates whether a change on the cd1 or cd2 signals occurred at the pc card interface. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = no change detected on either cd1 or cd2 1 = a change was detected on either cd1 or cd2 22 r readychange. ready change. when a 16-bit memory is installed in the socket, this bit includes whether the source of a PCI1450 interrupt was due to a change on the ready signal at the pc card interface indicating that pc card is now able ready to accept new data. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = no low-to-high transition detected on ready (default) 1 = detected a low-to-high transition on ready when a 16-bit i/o card is installed, this bit is always 0. 12 r batwarn. battery warning change. when a 16-bit memory card is installed in the socket, this bit indicates whether the source of a PCI1450 interrupt was due to a battery low warning condition. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = no battery warning condition (default) 1 = detected a battery warning condition when a 16-bit i/o card is installed, this bit is always 0. 02 r batdead. battery dead or status change. when a 16-bit memory card is installed in the socket, this bit indicates whether the source of a PCI1450 interrupt was due to a battery dead condition. a read of this bit or writing a 1 to this bit clears it. this bit is encoded as: 0 = stschg deasserted (default) 1 = stschg asserted ring indicate. when the PCI1450 is configured for ring indicate operation this bit indicates the status of the ri pin. 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 91 post office box 655303 ? dallas, texas 75265 exca card status-change interrupt configuration register (index 05h) bit 7 6 5 4 32 22 12 02 name exca card status-change interrupt configuration type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca card status-change interrupt configuration type: read/write offset: cardbus socket address + 805h: card a exca offset 05h card b exca offset 45h default: 00h description: this register controls interrupt routing for csc interrupts, as well as masks/unmasks csc interrupt sources. table 53. exca card status-change interrupt register description bit type function 74 r/w cscselect. interrupt select for card status change. these bits select the interrupt routing for card status change interrupts. this field is encoded as: 0000 = csc interrupts routed to pci interrupts if bit 5 of the diagnostic register (pci offset 93h) is set to 1b. in this case bit 4 of exca 803 is a adon't care.o this is the default setting. 0000 = no isa interrupt routing if bit 5 of the diagnostic register (pci offset 93h) is set to 0b. in this case, csc interrupts are routed to pci interrupts by setting bit 4 of exca 803h to 1b 0001 = irq1 enabled 0010 = smi enabled 0011 = irq3 enabled 0100 = irq4 enabled 0101 = irq5 enabled 0110 = irq6 enabled 0111 = irq7 enabled 1000 = irq8 enabled 1001 = irq9 enabled 1010 = irq10 enabled 1011 = irq11 enabled 1100 = irq12 enabled 1101 = irq13 enabled 1110 = irq14 enabled 1111 = irq15 enabled 32 r/w cden. card detect enable. enables interrupts on cd1 or cd2 changes. this bit is encoded as: 0 = disables interrupts on cd1 or cd2 line changes (default) 1 = enable interrupts on cd1 or cd2 line changes 22 r/w readyen. ready enable. this bit enables/disables a low-to-high transition on the pc card ready signal to generate a host interrupt. this interrupt source is considered a card status change. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 12 r/w batwarnen. battery warning enable. this bit enables/disables a battery warning condition to generate a csc interrupt. this bit is encoded as: 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 02 r/w batdeaden. battery dead enable. this bit enables/disables a battery dead condition on a memory pc card or assertion of the stschg i/o pc card signal to generate a csc interrupt. 0 = disables host interrupt generation (default) 1 = enables host interrupt generation 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 92 post office box 655303 ? dallas, texas 75265 exca address window enable register (index 06h) bit 7 6 5 4 3 2 1 0 name exca address window enable type r/w r/w r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca address window enable type: read-only, read/write offset: cardbus socket address + 806h: card a exca offset 06h card b exca offset 46h default: 00h description: this register enables/disables the memory and i/o windows to the 16-bit pc card. by default, all windows to the card are disabled. the PCI1450 will not acknowledge pci memory or i/o cycles to the card if the corresponding enable bit in this register is 0, regardless of the programming of the exca memory and i/o window start/end/offset address registers . table 54. exca address window enable register description bit type function 7 r/w iowin1en. i/o window 1 enable. this bit enables/disables i/o window 1 for the card. this bit is encoded as: 0 = i/o window 1 disabled (default) 1 = i/o window 1 enabled 6 r/w iowin0en. i/o window 0 enable. this bit enables/disables i/o window 0 for the card. this bit is encoded as: 0 = i/o window 0 disabled (default) 1 = i/o window 0 enabled 5 r reserved. this bit returns 0 when read. a write has no effect. 4 r/w memwin4en. memory window 4 enable. this bit enables/disables memory window 4 for the card. this bit is encoded as: 0 = memory window 4 disabled (default) 1 = memory window 4 enabled 3 r/w memwin3en. memory window 3 enable. this bit enables/disables memory window 3 for the card. this bit is encoded as: 0 = memory window 3 disabled (default) 1 = memory window 3 enabled 2 r/w memwin2en. memory window 2 enable. this bit enables/disables memory window 2 for the card. this bit is encoded as: 0 = memory window 2 disabled (default) 1 = memory window 2 enable 1 r/w memwin1en. memory window 1 enable. this bit enables/disables memory window 1 for the pc card. this bit is encoded as: 0 = memory window 1 disabled (default) 1 = memory window 1 enabled 0 r/w memwin0en. memory window 0 enable. this bit enables/disables memory window 0 for the pc card. this bit is encoded as: 0 = memory window 0 disabled (default) 1 = memory window 0 enabled
PCI1450 gfn/gjg pc card controller scps044 september 1998 93 post office box 655303 ? dallas, texas 75265 exca i/o window control register (index 07h) bit 7 6 5 4 3 2 1 0 name exca i/o window control type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window control type: read/write offset: cardbus socket address + 807h: card a exca offset 07h card b exca offset 47h default: 00h description: this register contains parameters related to i/o window sizing and cycle timing. table 55. exca i/o window control register description bit type function 7 r/w waitstate1. i/o window 1 wait-state. this bit controls the i/o window 1 wait-state for 16-bit i/o accesses. this bit has no effect on 8-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent isa wait state 6 r/w zerows1. i/o window 1 zero wait-state. this bit controls the i/o window 1 wait-state for 8-bit i/o accesses. note: this bit has no effect on 16-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. 0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three isa cycles 5 r/w iosis16w1. i/o window 1 iois16 source. this bit controls the i/o window automatic data sizing feature which used the iois16 signal from the pc card to determine the data width of the i/o data transfer. 0 = data width determined by datasize1, bit 4 (default) 1 = window data width determined by iois16 4 r/w datasize1. i/o window 1 data size. this bit controls the i/o window 1 data size. this bit is ignored if the i/o window 1 iois16 source bit (bit 5) is set. this bit is encoded as: 0 = window data width is 8 bits (default) 1 = window data width is 16 bits 3 r/w waitstate0. i/o window 0 wait-state. this bit controls the i/o window 0 wait-state for 16-bit i/o accesses. this bit has no effect on 8-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. this bit is encoded as: 0 = 16-bit cycles have standard length (default) 1 = 16-bit cycles extended by one equivalent isa wait state 2 r/w zerows0. i/o window 0 zero wait-state. this bit controls the i/o window 0 wait-state for 8-bit i/o accesses. note: this bit has no effect on 16-bit accesses. this wait-state timing emulates the isa wait-state used by the 82365sl-df. 0 = 8-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three isa cycles 1 r/w iois16w0. i/o window 0 iois16 source. this bit controls the i/o window automatic data sizing feature which used the iois16 signal from the pc card to determine the data width of the i/o data transfer. 0 = data width determined by datasize0, bit 0 (default) 1 = window data width determined by iois16 0 r/w datasize0. i/o window 0 data size. this bit controls the i/o window 1 data size. this bit is ignored if the i/o window 1 iois16 source bit (bit 1) is set. this bit is encoded as: 0 = window data width is 8 bits (default) 1 = window data width is 16 bits
PCI1450 gfn/gjg pc card controller scps044 september 1998 94 post office box 655303 ? dallas, texas 75265 exca i/o window 0 & 1 start-address low-byte register (index 08h, 0ch) bit 7 6 5 4 3 2 1 0 name exca i/o window 0 & 1 start-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address low-byte offset: cardbus socket address + 808h: card a exca offset 08h card b exca offset 48h register: exca i/o window 1 start-address low-byte offset: cardbus socket address + 80ch: card a exca offset 0ch card b exca offset 4ch type: read/write default: 00h size: one byte description: these registers contain the low-byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the start address. exca i/o window 0 & 1 start-address high-byte register (index 09h, odh) bit 7 6 5 4 3 2 1 0 name exca i/o window 0 & 1 start-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 start-address high-byte offset: cardbus socket address + 809h: card a exca offset 09h card b exca offset 49h register: exca i/o window 1 start-address high-byte offset: cardbus socket address + 80dh: card a exca offset 0dh card b exca offset 4dh type: read/write default: 00h size: one byte description: these registers contain the high-byte of the 16-bit i/o window start address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the start address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 95 post office box 655303 ? dallas, texas 75265 exca i/o window 0 & 1 end-address low-byte register (index 0ah, 0eh) bit 7 6 5 4 3 2 1 0 name exca i/o window 0 & 1 end-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 end-address low-byte offset: cardbus socket address + 80ah: card a exca offset 0ah card b exca offset 4ah register: exca i/o window 1 end-address low-byte offset: cardbus socket address + 80eh: card a exca offset 0eh card b exca offset 4eh type: read/write default: 00h size: one byte description: these registers contain the low-byte of the 16-bit i/o window end address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the start address. exca i/o window 0 & 1 end-address high-byte register (index 0bh, 0fh) bit 7 6 5 4 3 2 1 0 name exca i/o window 0 & 1 end-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 end-address high-byte offset: cardbus socket address + 80bh: card a exca offset 0bh card b exca offset 4bh register: exca i/o window 1 end-address high-byte offset: cardbus socket address + 80fh: card a exca offset 0fh card b exca offset 4fh type: read/write default: 00h size: one byte description: these registers contain the high-byte of the 16-bit i/o window end address for i/o windows 0 and 1. the eight bits of these registers correspond to the upper eight bits of the end address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 96 post office box 655303 ? dallas, texas 75265 exca memory window 04 start-address low-byte register (index 10h/18h/20h/28h/30h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 start-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address low-byte offset: cardbus socket address + 810h: card a exca offset 10h card b exca offset 50h register: exca memory window 1 start-address low-byte offset: cardbus socket address + 818h: card a exca offset 18h card b exca offset 58h register: exca memory window 2 start-address low-byte offset: cardbus socket address + 820h: card a exca offset 20h card b exca offset 60h register: exca memory window 3 start-address low-byte offset: cardbus socket address + 828h: card a exca offset 28h card b exca offset 68h register: exca memory window 4 start-address low-byte offset: cardbus socket address + 830h: card a exca offset 30h card b exca offset 70h type: read/write default: 00h size: one byte description: these registers contain the low-byte of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the start address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 97 post office box 655303 ? dallas, texas 75265 exca memory window 04 start-address high-byte register (index 11h/19h/21h/29h/31h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 start-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 start-address high-byte offset: cardbus socket address + 811h: card a exca offset 11h card b exca offset 51h register: exca memory window 1 start-address high-byte offset: cardbus socket address + 819h: card a exca offset 19h card b exca offset 59h register: exca memory window 2 start-address high-byte offset: cardbus socket address + 821h: card a exca offset 21h card b exca offset 61h register: exca memory window 3 start-address high-byte offset: cardbus socket address + 829h: card a exca offset 29h card b exca offset 69h register: exca memory window 4 start-address high-byte offset: cardbus socket address + 831h: card a exca offset 31h card b exca offset 71h type: read/write default: 00h size: one byte description: these registers contain the high-nibble of the 16-bit memory window start address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23a20 of the start address. in addition, the memory window data width and wait states are set in this register. table 56. exca memory window 04 start-address high-byte register description bit type function 7 r/w datasize. this bit controls the memory window data width. this bit is encoded as: 0 = window data width is 8 bits (default) 1 = window data width is 16 bits 6 r/w zerowait. zero wait-state. this bit controls the memory window wait state for 8- and 16-bit accesses. this wait state timing emulates the isa wait-state used by the 82365sl-df. this bit is encoded as: 0 = 8- and 16-bit cycles have standard length (default) 1 = 8-bit cycles reduced to equivalent of three isa cycles 16-bit cycles reduce to the equivalent of two isa cycles. 54 r/w scratch. scratch pad bits. these bits have no effect on memory window operation. 30 r/w stahn. start address high-nibble. these bits represent the upper address bits a23a20 of the memory window start address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 98 post office box 655303 ? dallas, texas 75265 exca memory window 04 end-address low-byte register (index 12h/1ah/22h/2ah/32h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 end-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address low-byte offset: cardbus socket address + 812h: card a exca offset 12h card b exca offset 52h register: exca memory window 1 end-address low-byte offset: cardbus socket address + 81ah: card a exca offset 1ah card b exca offset 5ah register: exca memory window 2 end-address low-byte offset: cardbus socket address + 822h: card a exca offset 22h card b exca offset 62h register: exca memory window 3 end-address low-byte offset: cardbus socket address + 82ah: card a exca offset 2ah card b exca offset 68h register: exca memory window 4 end-address low-byte offset: cardbus socket address + 832h: card a exca offset 32h card b exca offset 72h type: read/write default: 00h size: one byte description: these registers contain the low-byte of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the end address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 99 post office box 655303 ? dallas, texas 75265 exca memory window 04 end-address high-byte register (index 13h/1bh/23h/2bh/33h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 end-address high-byte type r/w r/w r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 end-address high-byte offset: cardbus socket address + 813h: card a exca offset 13h card b exca offset 53h register: exca memory window 1 end-address high-byte offset: cardbus socket address + 81bh: card a exca offset 1bh card b exca offset 5bh register: exca memory window 2 end-address high-byte offset: cardbus socket address + 823h: card a exca offset 23h card b exca offset 63h register: exca memory window 3 end-address high-byte offset: cardbus socket address + 82bh: card a exca offset 2bh card b exca offset 6bh register: exca memory window 4 end-address high-byte offset: cardbus socket address + 833h: card a exca offset 33h card b exca offset 73h type: read/write default: 00h size: one byte description: these registers contain the high-nibble of the 16-bit memory window end address for memory windows 0, 1, 2, 3, and 4. the lower 4 bits of these registers correspond to bits a23a20 of the end address. in addition, the memory window wait states are set in this register. table 57. exca memory window 04 end-address high-byte register description bit type function 76 r/w memws. wait state. these bits specify the number of equivalent isa wait states to be added to 16-bit memory accesses. the number of wait states added is equal to the binary value of these two bits. 54 r reserved. these bits return 0s when read. writes have no effect. 30 r/w endhn. end address high-nibble. these bits represent the upper address bits a23a20 of the memory window and address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 100 post office box 655303 ? dallas, texas 75265 exca memory window 04 offset-address low-byte register (index 14h/1ch/24h/2ch/34h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 offset-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address low-byte offset: cardbus socket address + 814h: card a exca offset 14h card b exca offset 54h register: exca memory window 1 offset-address low-byte offset: cardbus socket address + 81ch: card a exca offset 1ch card b exca offset 5ch register: exca memory window 2 offset-address low-byte offset: cardbus socket address + 824h: card a exca offset 24h card b exca offset 64h register: exca memory window 3 offset-address low-byte offset: cardbus socket address + 82ch: card a exca offset 2ch card b exca offset 6ch register: exca memory window 4 offset-address low-byte offset: cardbus socket address + 834h: card a exca offset 34h card b exca offset 74h type: read/write default: 00h size: one byte description: these registers contain the low-byte of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the 8 bits of these registers correspond to bits a19a12 of the offset address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 101 post office box 655303 ? dallas, texas 75265 exca memory window 04 offset-address high-byte register (15h/1dh/25h/2dh/35h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 offset-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 0 offset-address high-byte offset: cardbus socket address + 815h: card a exca offset 15h card b exca offset 55h register: exca memory window 1 offset-address high-byte offset: cardbus socket address + 81dh: card a exca offset 1dh card b exca offset 5dh register: exca memory window 2 offset-address high-byte offset: cardbus socket address + 825h: card a exca offset 25h card b exca offset 65h register: exca memory window 3 offset-address high-byte offset: cardbus socket address + 82dh: card a exca offset 2dh card b exca offset 6dh register: exca memory window 4 offset-address high-byte offset: cardbus socket address + 835h: card a exca offset 35h card b exca offset 75h type: read/write default: 00h size: one byte description: these registers contain the high 6 bits of the 16-bit memory window offset address for memory windows 0, 1, 2, 3, and 4. the lower 6 bits of these registers correspond to bits a25a20 of the offset address. in addition, the write protection and common/attribute memory configurations are set in this register. table 58. exca memory window 04 offset-address high-byte register description bit type function 7 r/w winwp. write protect. this bit specifies whether write operations to this memory window are enabled. this bit is encoded as: 0 = write operations are allowed (default) 1 = write operations are not allowed 6 r/w reg. this bit specifies whether this memory window is mapped to card attribute or common memory. this bit is encoded as: 0 = memory window is mapped to common memory (default) 1 = memory window is mapped to attribute memory 50 r/w offhb. offset address high-byte. these bits represent the upper address bits a25a20 of the memory window offset address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 102 post office box 655303 ? dallas, texas 75265 exca i/o window 0 & 1 offset-address low-byte register (index 36h, 38h) bit 7 6 5 4 3 2 1 0 name exca i/o window 0 & 1 offset-address low-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address low-byte offset: cardbus socket address + 836h: card a exca offset 36h card b exca offset 76h register: exca memory window 1 offset-address low-byte offset: cardbus socket address + 838h: card a exca offset 38h card b exca offset 78h type: read/write default: 00h size: one byte description: these registers contain the low-byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the lower 8 bits of the offset address, and bit 0 is always 0. exca i/o window 0 & 1 offset-address high-byte register (index 37h, 39h) bit 7 6 5 4 3 2 1 0 name exca i/o window 0 & 1 offset-address high-byte type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca i/o window 0 offset-address high-byte offset: cardbus socket address + 837h: card a exca offset 37h card b exca offset 77h register: exca memory window 1 offset-address high-byte offset: cardbus socket address + 839h: card a exca offset 39h card b exca offset 79h type: read/write default: 00h size: one byte description: these registers contain the high-byte of the 16-bit i/o window offset address for i/o windows 0 and 1. the 8 bits of these registers correspond to the upper 8 bits of the offset address.
PCI1450 gfn/gjg pc card controller scps044 september 1998 103 post office box 655303 ? dallas, texas 75265 exca card detect and general control register (index 16h) bit 7 6 5 4 3 2 1 0 name exca card detect and general control type r r w r/w r r r/w r default x x 0 0 0 0 0 0 register: exca card detect and general control type: read-only, write-only, read/write offset: cardbus socket address + 816h: card a exca offset 16h card b exca offset 56h default: xx00 0000b description: this register controls how the exca registers for the socket respond to card removal. it also reports the status of the vs1 and vs2 signals at the pc card interface. table 59 describes each bit in the exca card detect and general control register . table 59. exca card detect and general control register description bit type function 7 r vs2stat. vs2. this bit reports the current state of the vs2 signal at the pc card interface, and, therefore, does not have a default value. 0 = vs2 is low 1 = vs2 is high 6 r vs1stat. vs1. this bit reports the current state of the vs1 signal at the pc card interface, and, therefore, does not have a default value. 0 = vs1 is low 1 = vs1 is high 5 w swcsc. software card detect interrupt. if the card detect enable bit in the exca card status change interrupt configuration register is set, then writing a 1 to this bit causes a card detect card status change interrupt for the associated card socket. if the card detect enable bit is cleared to 0 in the exca card status change interrupt configuration register , then writing a 1 to the software card detect interrupt bit has no effect. this bit is write-only. a read operation of this bit always returns 0. writing a 1 to this bit also clears it. if bit 2 of the exca global control register is set and a 1 is written to clear bit 3 of the exca card status change interrupt register , then this bit also gets cleared. 4 r/w cdresume. card detect resume enable. if this bit is set to 1 and once a card detect change has been detected on the cd1 and cd2 inputs, then the ri_out output will go from high to low. the ri_out remains low until the card status change bit in the exca card status change register is cleared. if this bit is a 0, then the card detect resume functionality is disabled. 0 = card detect resume disabled (default) 1 = card detect resume enabled 32 r reserved. these bits return 0s when read. writes have no effect. 1 r/w regconfig. register configuration upon card removal. this bit controls how the exca registers for the socket react to a card removal event. this bit is encoded as: 0 = no change to exca registers upon card removal (default) 1 = reset exca registers upon card removal 0 r reserved. this bit returns 0 when read. a write has no effect.
PCI1450 gfn/gjg pc card controller scps044 september 1998 104 post office box 655303 ? dallas, texas 75265 exca global control register (index 1eh) bit 7 6 5 4 3 2 1 0 name exca global control type r r r r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca global control type: read-only, read/write offset: cardbus socket address + 81eh: card a exca offset 1eh card b exca offset 5eh default: 00h description: this register controls both pc card sockets, and is not duplicated for each socket. the host interrupt mode bits in this register are retained for 82365sl compatibility. table 60. exca global control register description bit type function 75 r reserved. these bits return 0s when read. writes have no effect. 4 r/w intmodeb. level/edge interrupt mode select card b. this bit selects the signaling mode for the PCI1450 host interrupt for card b interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default) 1 = host interrupt is level mode 3 r/w intmodea. level/edge interrupt mode select card a. this bit selects the signaling mode for the PCI1450 host interrupt for card a interrupts. this bit is encoded as: 0 = host interrupt is edge mode (default) 1 = host interrupt is level mode 2 r/w ifcmode. interrupt flag clear mode select. this bit selects the interrupt flag clear mechanism for the flags in the exca card status change register . this bit is encoded as: 0 = interrupt flags cleared by read of csc register (default) 1 = interrupt flags cleared by explicit write back of 1 1 r/w cscmode. card status change level/edge mode select. this bit selects the signaling mode for the PCI1450 host interrupt for card status changes. this bit is encoded as: 0 = host interrupt is edge mode (default) 1 = host interrupt is level mode 0 r/w pwrdwn. pwrdwn mode select. when the bit is set to 1 the PCI1450 is in power-down mode. in power-down mode the PCI1450 card outputs are 3-stated until an active cycle is executed on the card interface. following an active cycle the outputs are again 3-stated. the PCI1450 still receives dma requests, functional interrupts and/or card status change interrupts; however, an actual card access is required to awake upo the interface. this bit is encoded as: 0 = power-down mode disabled (default) 1 = power-down mode enabled
PCI1450 gfn/gjg pc card controller scps044 september 1998 105 post office box 655303 ? dallas, texas 75265 exca memory window 04 page register (index 40h, 41h, 42h, 43h, 44h) bit 7 6 5 4 3 2 1 0 name exca memory window 04 page type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: exca memory window 04 page type: read/write offset: cardbus socket address + 840h, 841h, 842h, 843h, 844h default: 00h description: the upper 8 bits of a 4-byte pci memory address are compared to the contents of this register when decoding addresses for 16-bit memory windows. each window has its own page register, all of which default to 00h. by programming this register to a nonzero value, host software may locate 16-bit memory windows in any one of 256 16m-byte regions in the 4 gigabyte pci address space. these registers are only accessible when the exca registers are memory mapped, that is, these registers may not be accessed using the index/data i/o scheme.
PCI1450 gfn/gjg pc card controller scps044 september 1998 106 post office box 655303 ? dallas, texas 75265 cardbus socket registers (functions 0 and 1) the pcmcia cardbus specification requires a cardbus socket controller to provide five 32-bit registers which report and control the socket-specific functions. the PCI1450 provides the cardbus socket/exca base address register (pci offset 10h) to locate these cardbus socket registers in pci memory address space. each socket has a separate base address register for accessing the cardbus socket registers, see figure 21 below. table 61 illustrates the location of the socket registers in relation to the cardbus socket/exca base address. table 61. cardbus socket registers register name offset socket event 2 00h socket mask 2 04h socket present state 2 08h socket force event 0ch socket control 2 10h reserved 14h reserved 18h reserved 1ch socket power management 20h 2 one or more bits in this register are cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst . PCI1450 configuration registers 16-bit legacy-mode base address cardbus socket/exca base address . . . . . . . . 10h 44h cardbus socket a registers exca registers card a offset 00h 20h 800h 844h host memory space cardbus socket b registers exca registers card b offset 00h 20h 800h 844h host memory space note: the cardbus socket/exca base address mode register is separate for functions 0 and 1. figure 21. accessing cardbus socket registers through pci memory
PCI1450 gfn/gjg pc card controller scps044 september 1998 107 post office box 655303 ? dallas, texas 75265 socket event register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 32 22 12 02 name socket event type r r r r r r r r r r r r r/wc r/wc r/wc r/wc default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket event type: read-only, read/write to clear offset: cardbus socket address + 00h default: 0000 0000h description: this register indicates a change in socket status has occurred. these bits do not indicate what the change is, only that one has occurred. software must read the socket present state register for current status. each bit in this register can be cleared by writing a 1 to that bit. the bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register . all bits in this register are cleared by pci reset. they may be immediately set again, if, when coming out of pc card reset, the bridge finds the status unchanged (i.e., cstschg reasserted or card detect is still true). software needs to clear this register before enabling interrupts. if it is not cleared and interrupts are enabled, then an interrupt is generated based on any bit set and not masked. table 62. socket event register description bit type function 314 r reserved. these bits return 0s when read. 32 r/wc pwrevent. power cycle. this bit is set when the PCI1450 detects that the pwrcycle bit in the socket present state register has changed. this bit is cleared by writing a 1. 22 r/wc cd2event. ccd2 . this bit is set when the PCI1450 detects that the cdetect2 field in the socket present state register has changed. this bit is cleared by writing a 1. 12 r/wc cd1event. ccd1 . this bit is set when the PCI1450 detects that the cdetect1 field in the socket present state register has changed. this bit is cleared by writing a 1. 02 r/wc cstsevent. cstschg. this bit is set when the cardsts field in the socket present state register has changed state. for cardbus cards, this bit is set on the rising edge of the cstschg signal. for 16-bit pc cards, this bit is set on both transitions of the cstschg signal. this bit is reset by writing a 1. 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 108 post office box 655303 ? dallas, texas 75265 socket mask register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket mask type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 32 22 12 02 name socket mask type r r r r r r r r r r r r r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket mask type: read-only, read/write offset: cardbus socket address + 04h default: 0000 0000h description: this register allows software to control the cardbus card events which generate a status change interrupt. table 63 below describes each bit in this register. the state of these mask bits does not prevent the corresponding bits from reacting in the socket event register . table 63. socket mask register description bit type function 314 r reserved. these bits return 0s when read. 32 r/w pwrmask. power cycle. this bit masks the pwrcycle bit in the socket present state register from causing a status change interrupt. 0 = pwrcycle event will not cause a csc interrupt (default) 1 = pwrcycle event will cause a csc interrupt 212 r/w cdmask. card detect mask. these bits mask the cdetect1 and cdetect2 bits in the socket present state register from causing a csc interrupt. 00 = insertion/removal will not cause csc interrupt (default) 01 = reserved (undefined) 10 = reserved (undefined) 11 = insertion/removal will cause csc interrupt 02 r/w cstsmask. cstschg mask. this bit masks the cardsts field in the socket present state register from causing a csc interrupt. 0 = cardsts event will not cause csc interrupt (default) 1 = cardsts event will cause csc interrupt 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 109 post office box 655303 ? dallas, texas 75265 socket present state register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket present state type r r r r r r r r r r r r r r r r default 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket present state type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 x 0 0 0 x x x register: socket present state type: read-only offset: cardbus socket address + 08h default: 3000 00xxh description: this register reports information about the socket interface. writes to the socket force event register are reflected here as well as general socket interface status. information about pc card v cc support and card type is only updated at each insertion. also note that the PCI1450 uses the ccd1 and ccd2 signals during card identification, and changes on these signals during this operation are not reflected in this register. table 64. socket present state register description bit type function 31 r yvsocket. yv socket. this bit indicates whether or not the socket can supply v cc = y.yv to pc cards. the PCI1450 does not support y.yv v cc ; therefore, this bit is always reset unless overridden by the socket force event register . this bit is hardwired to 0. 30 r xvsocket. xv socket. this bit indicates whether or not the socket can supply v cc = x.xv to pc cards. the PCI1450 does not support x.xv v cc ; therefore, this bit is always reset unless overridden by the socket force event register . this bit is hardwired to 0. 29 r 3vsocket. 3-v socket. this bit indicates whether or not the socket can supply v cc = 3.3 vdc to pc cards. the PCI1450 does support 3.3 v v cc ; therefore, this bit is always set unless overridden by the socket force event register . 28 r 5vsocket. 5-v socket. this bit indicates whether or not the socket can supply v cc = 5.0 vdc to pc cards. the PCI1450 does support 5.0 v v cc ; therefore, this bit is always 1 unless overridden by the device control register (bit 6). 2714 r reserved. these bits return 0s when read. 13 r yvcard. yv card. this bit indicates whether or not the pc card inserted in the socket supports v cc = y.y vdc. this bit can be set by writing to the corresponding bit in the socket force event register . 12 r xvcard. xv card. this bit indicates whether or not the pc card inserted in the socket supports v cc = x.x vdc. this bit can be set by writing to the corresponding bit in the socket force event register . 11 r 3vcard. 3-v card. this bit indicates whether or not the pc card inserted in the socket supports v cc = 3.3 vdc. this bit can be set by writing to the corresponding bit in the socket force event register . 10 r 5vcard. 5-v card. this bit indicates whether or not the pc card inserted in the socket supports v cc = 5.0 vdc. 9 r badvccreq. bad v cc request. this bit indicates that the host software has requested that the socket be powered at an invalid voltage. 0 = normal operation (default) 1 = invalid v cc request by host software
PCI1450 gfn/gjg pc card controller scps044 september 1998 110 post office box 655303 ? dallas, texas 75265 table 64. socket present state register description (continued) bit type function 8 r datalost. data lost. this bit indicates that a pc card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI1450. 0 = normal operation (default) 1 = potential data loss due to card removal 7 r notacard. not a card. this bit indicates that an unrecognizable pc card has been inserted in the socket. this bit is not updated until a valid pc card is inserted into the socket. 0 = normal operation (default) 1 = unrecognizable pc card detected 6 r ireqcint. ready(ireq )//cint . this bit indicates the current status of the ready(ireq )//cint signal at the pc card interface. 0 = ready(ireq )//cint is low 1 = ready(ireq )//cint is high 5 r cbcard. cardbus card detected. this bit indicates that a cardbus pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 4 r 16bitcard. 16-bit card detected. this bit indicates that a 16-bit pc card is inserted in the socket. this bit is not updated until another card interrogation sequence occurs (card insertion). 3 r pwrcycle. power cycle. this bit indicates that the status of each card powering request. this bit is encoded as: 0 = socket is powered down (default) 1 = socket is powered up 2 r cdetect2. ccd2 . this bit reflects the current status of the ccd2 signal at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd2 is low (pc card may be present) 1 = ccd2 is high (pc card not present) 1 r cdetect1. ccd1 . this bit reflects the current status of the ccd1 signal at the pc card interface. changes to this signal during card interrogation are not reflected here. 0 = ccd1 is low (pc card may be present) 1 = ccd1 is high (pc card not present) 0 r cardsts. cstschg. this bit reflects the current status of the cstschg signal at the pc card interface. 0 = cstschg is low 1 = cstschg is high
PCI1450 gfn/gjg pc card controller scps044 september 1998 111 post office box 655303 ? dallas, texas 75265 socket force event register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket force event type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket force event type r w w w w w w w w r w w w w w w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket force event type: read-only, write-only offset: cardbus socket address + 0ch default: 0000 xxxxh description: this register is used to force changes to the socket event register and the socket present state register . the cvstest bit in this register must be written when forcing changes that require card interrogation. table 65. socket force event register description bit type function 3115 r reserved. these bits return 0s when read. 14 w cvstest. card vs test. when this bit is set, the PCI1450 re-interrogates the pc card, updates the socket present state register , and re-enables the socket power control. 13 w fyvcard. force yv card. writes to this bit cause the yvcard bit in the socket present state register to be written. when set, this bit disables the socket power control. 12 w fxvcard. force xv card. writes to this bit cause the xvcard bit in the socket present state register to be written. when set, this bit disables the socket power control. 11 w f3vcard. force 3-v card. writes to this bit cause the 3vcard bit in the socket present state register to be written. when set, this bit disables the socket power control. 10 w f5vcard. force 5-v card. writes to this bit cause the 5vcard bit in the socket present state register to be written. when set, this bit disables the socket power control. 9 w fbadvccreq. force badvccreq. changes to the badvccreq bit in the socket present state register can be made by writing this bit. 8 w fdatalost. force data lost. writes to this bit cause the datalost bit in the socket present state register to be written. 7 w fnotacard. force not a card. writes to this bit cause the notacard bit in the socket present state register to be written. 6 r reserved. this bit returns 0 when read. 5 w fcbcard. force cardbus card. writes to this bit cause the cbcard bit in the socket present state register to be written. 4 w f16bitcard. force 16-bit card. writes to this bit cause the 16bitcard bit in the socket present state register to be written. 3 w fpwrcycle. force power cycle. writes to this bit cause the pwrevent bit in the socket event register to be written, and the pwrcycle bit in the socket present state register is unaffected. 2 w fcdetect2. force ccd2 . writes to this bit cause the cd2event bit in the socket event register to be written, and the cdetect2 bit in the socket present state register is unaffected. 1 w fcdetect1. force ccd1 . writes to this bit cause the cd1event bit in the socket event register to be written, and the cdetect1 bit in the socket present state register is unaffected. 0 w fcardsts. force cstschg. writes to this bit cause the cstsevent bit in the socket event register to be written. the cardsts bit in the socket present state register is unaffected.
PCI1450 gfn/gjg pc card controller scps044 september 1998 112 post office box 655303 ? dallas, texas 75265 socket control register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket control type r r r r r r r r r r r r r r r r default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 62 52 42 3 22 12 02 name socket control type r r r r r r r r r/w r/w r/w r/w r r/w r/w r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket control type: read-only, read/write offset: cardbus socket address + 10h default: 0000 0000h description: this register provides control of the voltages applied to the socket's v pp and v cc . the PCI1450 ensures that the socket is powered up only at acceptable voltages when a cardbus card is inserted. table 66. socket control register description bit type function 318 r reserved. these bits return 0s when read. 7 r/w stopclk. this bit controls how the cardbus clock run state machine decides when to stop the cardbus clock to the cardbus card: 0 = the PCI1450 clock run master will try to stop the clock to the cardbus card under the following two conditions: the cardbus interface is idle for 8 clocks and there is a request from the pci master to stop the pci clock. 1 = the PCI1450 clock run master will try to stop the clock to the cardbus card under the following condition: the cardbus interface is idle for 8 clocks. in summary, if this bit is set to1, then the cardbus controller will try to stop the clock to the cardbus card independent of the pci clock run signal. the only condition that has to be satisfied in this case is the cardbus interface sampled idle for 8 clocks. 642 r/w vccctrl. v cc control. these bits are used to request card v cc changes. 000 = request power off (default) 001 = reserved 010 = request v cc = 5.0 v 011 = request v cc = 3.3 v 100 = request v cc = x.xv 101 = request v cc = y.yv 110 = reserved 111 = reserved 3 r reserved. this bit returns 0 when read. 202 r/w vppctrl. v pp control. these bits are used to request card vpp changes. 000 = request power off (default) 001 = request v pp = 12.0 v 010 = request v pp = 5.0 v 011 = request v pp = 3.3 v 100 = request v pp = x.xv 101 = request v pp = y.yv 110 = reserved 111 = reserved 2 this bit is cleared only by the assertion of g_rst when pme is enabled. if pme is not enabled, then this bit is cleared by the assertion of prst or g_rst .
PCI1450 gfn/gjg pc card controller scps044 september 1998 113 post office box 655303 ? dallas, texas 75265 socket power management register bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 name socket power management type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 name socket power management type r r r r r r r r r r r r r r r r/w default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 register: socket power management type: read-only, read/write offset: cardbus socket address + 20h default: 0000 0000h description: this register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle. table 67. socket power management register description bit type function 3126 r reserved. these bits return 0s when read. 25 r sktacces. socket access status. this bit provides information on when a socket access has occurred. this bit is cleared by a read access. 0 = no pc card access has occurred (default) 1 = pc card has been accessed 24 r sktmode. socket mode status. this bit provides clock mode information. 0 = normal clock operation 1 = clock frequency has changed 2317 r reserved. these bits return 0s when read. 16 r/w clkctrlen. cardbus clock control enable. this bit, when set, enables clock control according to bit 0 (clkctrl). 0 = clock control disabled (default) 1 = clock control enabled 151 r reserved. these bits return 0s when read. 0 r/w this bit determines whether the cardbus clock run master stops the cclk or slows the clock when it detects idle activity on the cardbus interface. 0 = stop the cardbus clock using the clock run protocol when there is no activity on the cardbus interface (default). 1 = divide pci clock by 16 using the clock run protocol when there is no activity on the cardbus interface.
PCI1450 gfn/gjg pc card controller scps044 september 1998 114 post office box 655303 ? dallas, texas 75265 distributed dma (ddma) registers the dma base address, programmable in pci configuration space at offset 98h, points to a 16-byte region in pci i/o space where the ddma registers reside. table 68 summarizes the names and locations of these registers. these registers are identical in function, but different in location from the intel 8237 dma controller. the similarity between the register models retains some level of compatibility with legacy dma and simplifies the translation required by the master dma device when forwarding legacy dma writes to dma channels. these PCI1450 dma register definitions are identical to those registers of the same name in the 8237 dma controller; however, some register bits defined in the 8237 do not apply to distributed dma in a pci environment. in such cases, the PCI1450 will implement these obsolete register bits as nonfunctional, read-only bits. the reserved registers shown in table 68 are implemented as read-only, and return 0s when read. writes to reserved registers have no effect. table 68. distributed dma registers type register name dma base address offset r reserved page current address 00h w reser v ed page base address r reserved reserved current count 04h w reser v ed reser v ed base count r n/a reserved n/a status 08h w mode reser v ed request command r multichannel reserved n/a reserved 0ch w mask reser v ed master clear reser v ed
PCI1450 gfn/gjg pc card controller scps044 september 1998 115 post office box 655303 ? dallas, texas 75265 dma current address / base address register bit 15 14 13 12 11 10 9 8 name dma current address/base address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name dma current address/base address type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma current address/base address type: read/write offset: dma base address + 00h default: 00 0000h size: two bytes description: this register is used to set the starting (base) memory address of a dma transfer. reads from this register indicate the current memory address of a direct memory transfer. for the 8-bit dma transfer mode, the dma current address register contents are presented on ad150 of the pci bus during the address phase. bits 70 of the dma page register are presented on ad23ad16 of the pci bus during the address phase. for the 16-bit dma transfer mode, the dma current address register contents are presented on ad16ad1 of the pci bus during the address phase, and ad0 is driven to logic `0'. bits 71 of the dma page register are presented on ad23ad17 of the pci bus during the address phase, and bit 0 is ignored. dma page register bit 7 6 5 4 3 2 1 0 name dma page type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma page type: read/write offset: dma base address + 02h default: 0000h size: one byte description: this register is used to set the upper byte of the address of a dma transfer. details of the address represented by this register are explained in the dma current address/base address register , above.
PCI1450 gfn/gjg pc card controller scps044 september 1998 116 post office box 655303 ? dallas, texas 75265 dma current count / base count register bit 15 14 13 12 11 10 9 8 name dma current count/base count type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 name dma current count/base count type r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 0 0 0 0 register: dma current count/base count type: read/write offset: dma base address + 04h default: 0000h size: two bytes description: this register is used to set the total transfer count, in bytes, of a direct memory transfer. reads from this register indicate the current count of a direct memory transfer. in the 8-bit transfer mode, the count is decremented by 1 after each transfer. likewise, the count is decremented by 2 in 16-bit transfer mode. dma command register bit 7 6 5 4 3 2 1 0 name dma command type r r r r r r/w r r default 0 0 0 0 0 0 0 0 register: dma command type: read-only, read/write offset: dma base address + 08h default: 0000h size: one byte description: this register is used to enable and disable the controller; all other bits are reserved. table 69. ddma command register description bit type function 73 r reserved. these bits return 0s when read. 2 r/w dma controller enable. this bit enables and disables the distributed dma slave controller in the PCI1450, and defaults to the enabled state. 0 = dma controller enabled (default) 1 = dma controller disabled 10 r reserved. these bits return 0s when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 117 post office box 655303 ? dallas, texas 75265 dma status register bit 7 6 5 4 3 2 1 0 name dma status type r r r r r r r r default 0 0 0 0 0 0 0 0 register: dma status type: read-only offset: dma base address + 08h default: 0000h size: one byte description: this register indicates the terminal count and dma request (dreq ) status. table 70. dma status register description bit type function 74 r dreqstat. channel request. in the 8237, these bits indicate the status of the dreq signal of each dma channel. in the PCI1450, these bits indicate the dreq status of the single socket being serviced by this register. all four bits are set when the pc card asserts its dreq signal, and are reset when dreq is deasserted. the status of the mask bit in the dma multichannel mask register has no effect on these bits. 30 r tc. channel terminal count. the 8327 uses these bits to indicate the tc status of each of its four dma channels. in the PCI1450, these bits report information about just a single dma channel; therefore, all four of these register bits indicate the tc status of the single socket being serviced by this register. all four bits are set when the terminal count (tc) is reached by the dma channel. these bits are reset when read or when the dma channel is reset dma request register bit 7 6 5 4 3 2 1 0 name dma request type w w w w w w w w default 0 0 0 0 0 0 0 0 register: dma request type: write-only offset: dma base address + 09h default: 0000h size: one byte description: this register is used to request a ddma transfer through software. any write to this register enables software requests. this register is to be used in block mode only.
PCI1450 gfn/gjg pc card controller scps044 september 1998 118 post office box 655303 ? dallas, texas 75265 dma mode register bit 7 6 5 4 3 2 1 0 name dma mode type r/w r/w r/w r/w r/w r/w r/w r default 0 0 0 0 0 0 0 0 register: dma mode type: read-only, read/write offset: dma base address + 0bh default: 0000h size: one byte description: this register is used to set the dma transfer mode. table 71. ddma mode register description bit type function 76 r/w dmamode. mode select bits. the PCI1450 uses these bits to determine the transfer mode. 00 = demand mode select (default) 01 = single mode select 10 = block mode select 11 = reserved 5 r/w incdec. address increment/decrement. the PCI1450 uses this register bit to select the memory address in the dma current address/base address register to increment or decrement after each data transfer. this is in accordance with the 8237 use of this register bit, and is encoded as follows: 0 = addresses increment (default) 1 = addresses decrement 4 r/w autoinit. auto-initialization bit. 0 = auto-initialization disabled (default) 1 = auto-initialization enabled 32 r/w xfertype. transfer type. these bits select the type of direct memory transfer to be performed. a memory write transfer moves data from the PCI1450 pc card interface to memory, and a memory read transfer moves data from memory to the PCI1450 pc card interface. the field is encoded as: 00 = no transfer selected (default) 01 = write transfer 10 = read transfer 11 = reserved 10 r reserved. these bits return 0s when read.
PCI1450 gfn/gjg pc card controller scps044 september 1998 119 post office box 655303 ? dallas, texas 75265 dma master clear register bit 7 6 5 4 3 2 1 0 name dma master clear type w w w w w w w w default 0 0 0 0 0 0 0 0 register: dma master clear type: write-only offset: dma base address + 0dh default: 0000h size: one byte description: this register is used to reset the ddma controller, and resets all ddma registers. dma multichannel mask register bit 7 6 5 4 3 2 1 0 name dma multichannel mask type r r r r r r r r/w default 0 0 0 0 0 0 0 1 register: dma multichannel mask type: read-only, read/write offset: dma base address + 0fh default: 0000h size: one byte description: the PCI1450 uses only the least-significant bit of this register to mask the pc card dma channel. the PCI1450 sets the mask bit when the pc card is removed. host software is responsible for either resetting the socket's dma controller or re-enabling the mask bit. table 72. ddma multichannel mask register description bit type function 71 r reserved. these bits return 0s when read. 0 r/w maskbit. mask select bit. this bit masks incoming dreq signals from the pc card. when set, the socket ignores dma requests from the card. when cleared (or when reset), incoming dreq assertions are serviced normally. 0 = ddma service provided on card dreq 1 = socket dreq signal ignored (default)
PCI1450 gfn/gjg pc card controller scps044 september 1998 120 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating temperature ranges (unless otherwise noted) 2 supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . clamping voltage range, v ccp, v cca, v ccb, v ccz, v cci 0.5 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i : pci 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a 0.5 v to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b 0.5 v to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . zv 0.5 v to v ccz + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . misc 0.5 v to v cci + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fail safe 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output voltage range, v o : pci 0.5 v to v ccp + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card a 0.5 v to v cca + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . card b 0.5 v to v ccb + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . zv 0.5 v to v ccz + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . misc 0.5 v to v cci + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . fail safe 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 2) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . virtual junction temperature, t j 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. applies for external input and bidirectional buffers. v i > v cc does not apply to fail-safe terminals. pci terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . zv terminals are measured with respect to v ccz , and miscellaneous signals are measured with respect to v cci . the limit specified applies for a dc condition. 2. applies for external output and bidirectional buffers. v o > v cc does not apply to fail-safe terminals. pci terminals are measured with respect to v ccp instead of v cc . pc card terminals are measured with respect to v cca or v ccb . zv terminals are measured with respect to v ccz , and miscellaneous signals are measured with respect to v cci . the limit specified applies for a dc condition.
PCI1450 gfn/gjg pc card controller scps044 september 1998 121 post office box 655303 ? dallas, texas 75265 recommended operating conditions (see note 3) operation min nom max unit v cc core voltage commercial 3.3 v 3 3.3 3.6 v v ccp pci i/o voltage commercial 3.3 v 3 3.3 3.6 v v ccp pci i/o v oltage commercial 5 v 4.75 5 5.25 v v cca/b pc card i/o voltage commercial 3.3 v 3 3.3 3.6 v v cca/b pc card i/o v oltage commercial 5 v 4.75 5 5.25 v v ccz zv port i/o voltage commercial 3.3 v 3 3.3 3.6 v v ccz zv port i/o v oltage commercial 5 v 4.75 5 5.25 v v cci miscellaneous i/o voltage commercial 3.3 v 3 3.3 3.6 v v cci miscellaneo u s i/o v oltage commercial 5 v 4.75 5 5.25 v 2 pci 3.3 v 0.5 v ccp v ccp v 2 pci 5 v 2 v ccp v v 2 hi h l l i t lt pc card 3.3 v 0.475 v cca/b v cca/b v v ih 2 high-level input voltage pc card 5 v 2.4 v cca/b v zv 2 v ccz v misc 3 5 v 2 v cci v fail safe 3.3 v 2.4 v cc v 2 pci 3.3 v 0 0.3 v ccp v 2 pci 5 v 0 0.8 v v 2 lllitlt pc card 3.3 v 0 0.325 v cca/b v v il 2 low-level input voltage pc card 5 v 0 0.8 v zv 0 0.8 v misc 3 5 v 0 0.8 v fail safe 3.3 v 0 0.8 v pci 3.3 v 0 v ccp pc card 5 v 0 v cca/b v i input voltage zv 0 v ccz v misc 3 5 v 0 v cci fail safe 3.3 v 0 v cc ? pci 3.3 v 0 v ccp ? pc card 5 v 0 v cca/b v v o ? output voltage zv 0 v ccz v misc 3 5 v 0 v cci fail safe 3.3 v 0 v cc v t t in p ut transition times (t and t f ) pci and pc card 1 4 ns t t inp u t transition times (t r and t f ) zv, misc, and fail safe 0 6 ns t a operating ambient temperature range 0 25 70 c t j # virtual junction temperature 0 25 115 c 2 applies to external inputs and bidirectional buffers without hysteresis 3 miscellaneous pins are v13, w13, y13, u12, v12, w12, u11, v11, w11, y11, y10, w10, y09, w09, v09, u09, y08, all irqmuxx pins, l edax pins, suspend , spkrout, ri_out , inta , intb , and power switch control pins. fail-safe pins are a11, b14, c09, g03, h20, u03, w06, and y03 (card detect and voltage sense pins). ? applies to external output buffers # these junction temperatures reflect simulation conditions. the customer is responsible for verifying junction temperature. note 3: unused pins (input or i/o) must be held high or low to prevent them from floating.
PCI1450 gfn/gjg pc card controller scps044 september 1998 122 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) parameter pins operation test conditions min max unit pci 3.3 v i oh = 0.5 ma 0.9 v cc pci 5 v i oh = 2 ma 2.4 v oh high level out p ut voltage (see note 4) pc card 3.3 v i oh = 0.15 ma 0.9 v cc v v oh hi g h - l eve l ou t pu t vo lt age ( see n o t e 4) pc c ar d 5 v i oh = 0.15 ma 2.4 v zv i oh = 4 ma v cc 0.6 misc i oh = 4 ma v cc 0.6 pci 3.3 v i ol = 1.5 ma 0.1 v cc pci 5 v i ol = 6 ma 0.55 pc card 3.3 v i ol = 0.7 ma 0.1 v cc v ol low-level output voltage pc c ar d 5 v i ol = 0.7 ma 0.55 v zv i ol = 4 ma 0.5 misc i ol = 4 ma 0.5 serr i ol = 12 ma 0.5 i ozl 3-state output, hi g h-impedance state out p ut p ins 3.6 v v i = v cc 1 m a i ozl ,g current (see note 4) o u tp u t pins 5.25 v v i = v cc 1 m a i ozh 3-state output, hi g h-impedance state out p ut p ins 3.6 v v i = v cc 2 10 m a i ozh ,g current o u tp u t pins 5.25 v v i = v cc 2 25 m a input pins v i = gnd 1 i il low-level input current i/o pins v i = gnd 10 m a latch v i = gnd 2 in p ut p ins 3.6 v v i = v cc 3 10 inp u t pins 5.25 v v i = v cc 3 20 i ih high-level input current (see note 5) i/o p ins 3.6 v v i = v cc 3 10 m a i/o pins 5.25 v v i = v cc 3 25 fail-safe pins 3.6 v v i = v cc 10 2 for pci pins, v i = v ccp . for pc card pins, v i = v cc(a/b) . for zv pins, v i = v ccz . for miscellaneous pins, v i = v cci . 3 for i/o pins, input leakage (i il and i ih ) includes i oz leakage of the disabled output. notes: 4. v oh and i ol are not tested on serr (gfn pin u19, gjg pin u19)and ri_out (gfn pin y13, gjg pin p12) because they are open-drain outputs. 5. i ih is not tested on latch (gfn pin w12, gjg pin v11) because it is pulled up with an internal resistor.
PCI1450 gfn/gjg pc card controller scps044 september 1998 123 post office box 655303 ? dallas, texas 75265 pci clock/reset timing requirements over recommended ranges of supply voltage and operating free-air temperature (see figure 23 and figure 24) parameter alternate symbol test conditions min max unit t c cycle time, pclk t cyc 30 ns t wh pulse duration, pclk high t high 11 ns t wl pulse duration, pclk low t low 11 ns d v/ d t slew rate, pclk t r , t f 1 4 v/ns t w pulse duration, rstin t rst 1 ms t su setup time, pclk active at end of rstin t rst-clk 100 s pci timing requirements over recommended ranges of supply voltage and operating free-air temperature (see note 7, figure 22, and figure 25) parameter alternate symbol test conditions min max unit t d propa g ation dela y time, pclk-to-shared signal valid delay time t val c l = 50 pf, 11 ns t pd gy, see note 6 pclk-to-shared signal invalid delay time t inv l , see note 7 2 ns t en enable time, high impedance-to-active delay time from pclk t on 2 ns t dis disable time, active-to-high impedance delay time from pclk t off 28 ns t su setup time before pclk valid t su 7 ns t h hold time after pclk high t h 0 ns notes: 6. pci shared signals are ad310, c/be30 , frame , trdy , irdy , stop , idsel, devsel , and par. 7. this data sheet uses the following conventions to describe time ( t ) intervals. the format is t a , where subscript a indicates the type of dynamic parameter being represented. one of the following is used: t pd = propagation delay time, t d = delay time, t su = setup time, and t h = hold time.
PCI1450 gfn/gjg pc card controller scps044 september 1998 124 post office box 655303 ? dallas, texas 75265 parameter measurement information 2 c load includes the typical load-circuit distributed capacitance. c load test point timing input (see note a) out-of-phase output t pd 50% v cc 50% v cc v cc 0 v 0 v 0 v 0 v 0 v v ol t h t su v oh v oh v ol high-level input low-level input t w voltage waveforms propagation delay times load circuit voltage waveforms setup and hold times input rise and fall times voltage waveforms pulse duration t pd t pd t pd v load i oh i ol from output under test 90% v cc 10% v cc t f t r output control (low-level enabling) waveform 1 (see notes b and c) waveform 2 (see notes b and c) v ol v oh v oh 0.3 v t pzl t pzh t plz t phz voltage waveforms enable and disable times, 3-state outputs v ol + 0.3 v 0 v 0 v @ 50% v cc @ 50% v cc t en t dis t pd t pzh t pzl t phz t plz c load 2 (pf) i ol (ma) timing parameter 50 8 8 0 3 1.5 3 50 8 8 8 8 load circuit parameters = 50 w , where v ol = 0.6 v, i ol = 8 ma i ol 50 3 v load v ol i oh (ma) v load 3 (v) data input in-phase output input (see note a) v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc 50% v cc notes: a. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by pulse generators having the following characteristics: prr = 1 mhz, z o = 50 w , t r = 6 ns. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. for t plz and t phz , v ol and v oh are measured values. 50% v cc figure 22. load circuit and voltage waveforms
PCI1450 gfn/gjg pc card controller scps044 september 1998 125 post office box 655303 ? dallas, texas 75265 pci bus parameter measurement information t high 2 v 0.8 v t r t f t cyc t low 2 v min peak-to-peak figure 23. pclk timing waveform t rst t srst-clk pclk rstin figure 24. rstin timing waveforms 1.5 v t val t inv valid 1.5 v t on t off valid t su t h pclk pci output pci input figure 25. shared signals timing waveforms
PCI1450 gfn/gjg pc card controller scps044 september 1998 126 post office box 655303 ? dallas, texas 75265 pc card cycle timing the pc card cycle timing is controlled by the wait-state bits in the intel 82365sl-df compatible memory and i/o window registers. the pc card cycle generator uses the pci clock to generate the correct card address setup and hold times and the pc card command active (low) interval. this allows the cycle generator to output pc card cycles that are as close to the intel 82365sl-df timing as possible, while always slightly exceeding the intel 82365sl-df values. this ensures compatibility with existing software and maximizes throughput. the pc card address setup and hold times are a function of the wait-state bits. table 73 shows address setup time in pclk cycles and nanoseconds for i/o and memory cycles. table 74 and table 75 show command active time in pclk cycles and nanoseconds for i/o and memory cycles. table 76 shows address hold time in pclk cycles and nanoseconds for i/o and memory cycles. table 73. pc card address setup time, t su(a) , 8-bit and 16-bit pci cycles wait-state bits ts1 0 = 01 (pclk/ns) i/o 3/90 memory ws1 0 2/60 memory ws1 1 4/120 table 74. pc card command active time, t c(a) , 8-bit pci cycles wait-state bits ts1 0 = 01 ws zws (pclk/ns) 0 0 19/570 i/o 1 x 23/690 0 1 7/210 00 0 19/570 01 x 23/690 memory 10 x 23/690 11 x 23/690 00 1 7/210 table 75. pc card command active time, t c(a) , 16-bit pci cycles wait-state bits ts1 0 = 01 ws zws (pclk/ns) 0 0 7/210 i/o 1 x 11/330 0 1 n/a 00 0 9/270 01 x 13/390 memory 10 x 17/510 11 x 23/630 00 1 5/150
PCI1450 gfn/gjg pc card controller scps044 september 1998 127 post office box 655303 ? dallas, texas 75265 table 76. pc card address hold time, t h(a) , 8-bit and 16-bit pci cycles wait-state bits ts1 0 = 01 (pclk/ns) i/o 2/60 memory ws1 0 2/60 memory ws1 1 3/90 timing requirements over recommended ranges of supply voltage and operating free-air temperature, memory cycles (for 100-ns common memory) (see note 8 and figure 26) alternate symbol min max unit t su setup time, ce1 and ce2 before we /oe low t1 60 ns t su setup time, ca25ca0 before we /oe low t2 t su(a) +2pclk ns t su setup time, reg before we /oe low t3 90 ns t pd propagation delay time, we /oe low to wait low t4 ns t w pulse duration, we /oe low t5 200 ns t h hold time, we /oe low after wait high t6 ns t h hold time, ce1 and ce2 after we /oe high t7 120 ns t su setup time (read), cdata15cdata0 valid before oe high t8 ns t h hold time (read), cdata15cdata0 valid after oe high t9 0 ns t h hold time, ca25ca0 and reg after we /oe high t10 t h(a) +1pclk ns t su setup time (write), cdata15cdata0 valid before we low t11 60 ns t h hold time (write), cdata15cdata0 valid after we low t12 240 ns note 8: these times are dependent on the register settings associated with isa wait states and data size. they are also dependen t on cycle type (read/write, memory/i/o) and wait from pc card. the times listed here represent absolute minimums (the times that would be observed if programmed for zero wait state, 16-bit cycles) with a 33-mhz pci clock. timing requirements over recommended ranges of supply voltage and operating free-air temperature, i/o cycles (see figure 27) alternate symbol min max unit t su setup time, reg before iord /iowr low t13 60 ns t su setup time, ce1 and ce2 before iord /iowr low t14 60 ns t su setup time, ca25ca0 valid before iord /iowr low t15 t su(a) +2pclk ns t pd propagation delay time, iois16 low after ca25ca0 valid t16 35 ns t pd propagation delay time, iord low to wait low t17 35 ns t w pulse duration, iord /iowr low t18 t ca ns t h hold time, iord low after wait high t19 ns t h hold time, reg low after iord high t20 0 ns t h hold time, ce1 and ce2 after iord /iowr high t21 120 ns t h hold time, ca25ca0 after iord /iowr high t22 t h(a) +1pclk ns t su setup time (read), cdata15cdata0 valid before iord high t23 10 ns t h hold time (read), cdata15cdata0 valid after iord high t24 0 ns t su setup time (write), cdata15cdata0 valid before iowr low t25 90 ns t h hold time (write), cdata15cdata0 valid after iowr high t26 90 ns
PCI1450 gfn/gjg pc card controller scps044 september 1998 128 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, miscellaneous (see figure 28) parameter alternate symbol min max unit bvd2 low to spkrout low t27 30 t d pro p agation delay time bvd2 high to spkrout high t27 30 ns t pd propagation dela y time ireq to irq15irq3 t28 30 ns stschg to irq15irq3 t28 30 pc card parameter measurement information t8 t6 ca25ca0 reg ce1 , ce2 we , oe wait cdata15cdata0 (write) t1 t7 cdata15cdata0 (read) t2 t3 t11 t10 t12 t4 with no wait state with wait state t5 t9 figure 26. pc card memory cycle
PCI1450 gfn/gjg pc card controller scps044 september 1998 129 post office box 655303 ? dallas, texas 75265 pc card parameter measurement information t16 t23 t19 ca25ca0 reg ce1 , ce2 iord , iowr wait cdata15cdata0 (write) t14 t21 cdata15cdata0 (read) t15 t13 t25 t22 t26 t17 with no wait state with wait state t18 t24 t20 iois16 figure 27. pc card i/o cycle bvd2 t27 spkrout ireq t28 irq15irq3 figure 28. miscellaneous pc card delay times
PCI1450 gfn/gjg pc card controller scps044 september 1998 130 post office box 655303 ? dallas, texas 75265 mechanical data gfn (s-pbga-n256) plastic ball grid array 0,635 19 15 17 13 11 9 y v t u p n r w 7 5 l j k h f g 3 1 d b c a e m 24,13 typ seating plane 4040185-2/b 11/97 10 12 14 16 18 20 8 6 4 2 27,20 24,00 24,70 sq sq 26,80 0,80 0,60 0,50 0,70 1,92 2,32 0,30 0,40 0,635 1,27 0,15 m 0,10 1,27 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice.
PCI1450 gfn/gjg pc card controller scps044 september 1998 131 post office box 655303 ? dallas, texas 75265 mechanical data gjg (s-pbga-n257) plastic ball grid array 19 14,40 typ 17 16 13 14 15 11 12 9 8 10 v u w r n p l m k t 7 5 6 3 4 h f g e c d 1 a b 2 j 18 seating plane 4173511/a 08/98 sq 16,10 15,90 0,95 0,45 0,35 0,55 0,45 0,12 0,08 0,85 1,40 max 0,80 m 0,08 0,10 0,80 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. microstar ? bga configuration micro star is a trademark of texas instruments incorporated.
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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