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s3c72n8/p72n8/c72n5/p72n5 product overview 1- 1 1 product overview overview the s3c72n8/c72n5 single-chip cmos microcontroller has been designed for high perfo rmance using samsung's newest 4- bit cpu core, sam47 (samsung arrangeable microcontrollers). with features such as lcd direct drive capability, 8-bit timer/counter, and serial i/o, the s3c72n8/c72n5 offer an excellent design solution for a wide variety of applications that require lcd functions. up to 40 pins of the 80-pin qfp package can be dedicated to i/o. six vectored interrupts provide fast response to internal and external events. in addition, the s3c72n8/c72n5 's advanced cmos technology provides for low power consumption and a wide operat ing voltage range. otp the s3c72n8/c72n5 microcontroller is also available in otp (one time programmable) version, s3p72n8/p72n5. s3p72n8/p72n5 microcontroller has an on-chip 8/16-kbyte one-time-programmable eprom instead of masked rom. the s3p72n8/p72n5 is comparable to s3c72n8/c72n5, both in function and in pin configuration.
product overview s3c72n8/p72n8/c72n5/p72n5 1- 2 features memory ? 512 4-bit ram ? 8 k 8-bit rom (s3c72n8/p72n8) ? 16 k 8-bit rom (s3c72n5/p72n5) i/o pins ? input only: 8 pins ? i/o: 24 pins ? output: 8 pins sharing with segment driver outputs lcd controller/driver ? maximum 16-digit lcd direct drive capability ? 32 segment, 4 common pins ? display modes: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias) 8-bit basic timer ? programmable interval timer ? watchdog timer 8-bit timer/counter 0 ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? serial i/o interface clock generator watch timer ? real-time and interval time measurement ? four frequency outputs to buz pin ? clock source generation for lcd 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive only mode ? lsb-first or msb-first transmission selectable ? in ternal or external clock source bit sequential carrier ? support 16-bit serial data transfer in arbitrary format interrupts ? three internal vectored interrupts ? three external vectored interrupts ? two quasi-interrupts memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main or sub system oscillation stops) oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal or external oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.95, 1.91, 15.3 m s at 4.19 mhz (main) ? 122 m s at 32.768 khz (subsystem) operating temperature ? ? 40 c to 85 c operating voltage range ? 1.8 v to 5.5 v package type ? 80 -pin qfp
s3c72n8/p72n8/c72n5/p72n5 product overview 1- 3 block diagram program status word arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block instruction register clock 8/16-kbyte program memory 512 x 4-bit data memory x in xt in 4-bit accumulator flags p1.3/tcl0 x out xt out 8-bit timer/ counter 0 p8.0-p8.7/ seg24-seg31 lcd driver/ controller i/o port 8 i/o port 4 i/o port 5 i/o port 7 i/o port 6 p2.0/tclo0 p4.0-p4.3 p5.0-p5.3 p6.0-p6.3/ ks0-ks3 p7.0-p7.3/ ks4-ks7 int0, int1, int2 program counter stack pointer serial i/o port bias v lc0 -v lc2 lcdck/p3.0 lcdsy/p3.1 com0-com3 seg0-seg23 p8.0-p8.7/ seg24-seg31 i/o port 0 i/o port 2 i/o port 3 p0.1 / sck p0.2 /so p0.3 /si p3.0/lcdck p3.1/lcdsy p3.2 p3.3 p2.0/tclo0 p2.1 p2.2/clo p2.3/buz i/o port 1 p1.0/int0 p1.1/int1 p1.2/int2 p1.3/tcl0 p0.0/int4 p0.1/ sck p0.2/so p0.3/si watchdog timer basic timer watch timer p2.3/buz figure 1 -1 . s3c72n8/c72n5 simplified block diagram
product overview s3c72n8/p72n8/c72n5/p72n5 1- 4 pin assignments s3c72n8/c72n5 (top view) seg2 seg1 seg0 com0 com1 com2 com3 bias v lc0 v lc1 v lc2 v dd v ss x out x in test xt in xt out reset p0.0/int4 p0.1/ sck p0.2/so p0.3/si p1.0/int0 seg19 seg20 seg21 seg22 seg23 p8.0/seg24 p8.1/seg25 p8.2/seg26 p8.3/seg27 p8.4/seg28 p8.5/seg29 p8.6/seg30 p8.7/seg31 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p5.0 p4.3 p4.2 p4.1 p4.0 p3.3 p3.2 p3.1/lcdsy p3.0/lcdck p2.3/buz p2.2/clo p2.1 p2.0/tclo0 p1.3/tcl0 p1.2/int2 p1.1/int1 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 figure 1 -2 . s3c72n8/c72n5 80 - qfp pin assignment diagram
s3c72n8/p72n8/c72n5/p72n5 product overview 1- 5 pin descriptions table 1 - 1. s3c72n8/c72n5 pin descriptions pin name pin type description number share pin reset value circuit type p0.0 p0.1 p0.2 p0.3 i i/o i/o i 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up res istors are software assignable. 20 21 22 23 int4 sck so si input a-1 d * d * a-1 p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test are possible. 4-bit pull-up resistors are software assignable. 24 25 26 27 int0 int1 int2 tcl0 input a-1 p2.0 p2.1 p2.2 p2.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. 28 29 30 31 tclo0 ? clo buz input d p3.0 p3.1 p3.2 p3.3 i/o 4-bit i/o port. 1-bit and 4-bit read/write and test are possible. each individual pin can be specified as input or output. 4-bit pull-up resistors are software assignable. 32 33 34 35 lcd ck lcdsy input d p4.0 ? p4.3 p5.0? p5.3 i/o 4-bit i/o ports. n-channel open-drain output up to 5 v. 1-, 4-, and 8-bit read/write and test are possible. ports 4 and 5 can be paired to support 8-bit data transfer. 4-bit pull-up resistors are software assignable. 36?43 ? input e p6.0? p6.3 p7.0? p7.3 i/o 4-bit i/o ports. port 6 pins are individually software configurable as input or output. 1-bit and 4-bit read/write and test are possible. 4-bit pull-up resistors are software assignable. ports 6 and 7 can be paired to enable 8-bit data transfer. 44?51 ks0?ks3 ks4?ks7 input d * p8.0? p8.7 o output port for 1-bit data (for use as cmos driver only) 59?52 seg24? seg31 output h-16 seg0? seg23 o lcd segment signal output 3?1, 80?60 ? output h-15 seg24? seg31 o lcd segment signal output 59?52 p8.0?p8.7 output h-16 com0? com3 o lcd common signal output 4?7 ? output h-15 v lc0 ?v lc2 ? lcd power supply. voltage dividing resistors are assignable by mask option 9?11 sclk sdat ? ? bias ? lcd power control 8 ? ? ? lcdck i/o lcd clock output for display expansion 32 p3.0 input d
product overview s3c72n8/p72n8/c72n5/p72n5 1- 6 table 1 - 1. s3c72n8/c72n5 pin descriptio ns (continued) pin name pin type description number share pin reset value circuit type lcdsy i/o lcd synchronization clock output for lcd display expan sion 33 p3.1 input d tcl0 i/o e xternal clock input for timer/counter 0 27 p1.3 input a-1 tclo0 i/ o timer/counter 0 clock output 28 p 2.0 input d si i serial interface data input 23 p0.3 input a-1 so i/ o serial interface data output 22 p0.2 input d * sck i/o serial i/o interface clock signal 21 p0.1 input d * int0 int1 i external interrupts . the triggering edge for int0 and int1 is selectable. only int0 is synchronized with the system clock. 24 25 p1.0 p1.1 input a-1 int2 i quasi-interrup t with detection of rising edge signals. 26 p1.2 input a-1 int4 i external interrupt input with detection of rising or falling edge 20 p0.0 input a-1 k s 0?k s7 i/o quasi-interrupt inputs with falling edge detection. 44?51 p6 .0? p7 .3 input d * clo i/ o c pu c lock output 30 p2.2 input d buz i/ o 2, 4, 8 or 16 k hz frequency output for buzzer sound with 4.19 mhz main system clock or 32.768 khz subsystem clock. 31 p2.3 input d x in, x out ? crystal, ceramic or rc oscillator pins for main system clock. (for external clock input, use x in and input x in ?s reverse phase to x out ) 15,14 ? ? ? xt in, xt out ? crystal oscillator pins for subsystem clock. (for external clock input, use xt in and input xt in 's reverse phase to xt out ) 17,18 ? ? ? v dd ? main power supply 12 ? ? ? v ss ? ground 13 ? ? ? reset ? reset signal 19 ? input b test ? test signal input (must be connected to v ss ) 16 ? ? ? note s : 1. pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode. 2. d * type has a schmitt trigger circuit at input.
s3c72n8/p72n8/c72n5/p72n5 product overview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a in v dd pull-up resistor enable p-channel pull-up resistor schmitt trigger figure 1 -4 . pin circuit type a-1 (p1, p0.0, p0.3) schmitt trigger in v dd pull-up resistor figure 1 -5 . pin circuit type b ( reset reset ) p-channel n-channel v dd out output disable data figure 1 -6 . pin circuit type c
product overview s3c72n8/p72n8/c72n5/p72n5 1- 8 p-channel i/o output disable data circuit type c resistor enable v dd pull-up resistor circuit type a figure 1 -7 . pin circuit type d (p0.1, p0.2, p2, p3, p6, p7) n-ch v dd resistor enable v dd i/o pne pull-up resistor p-ch output enable data circuit type a figure 1 -8 . pin circuit type e (p4, p5)
s3c72n8/p72n8/c72n5/p72n5 product overview 1- 9 out lcd segment / common data v lc0 v lc1 v lc2 figure 1 -9 . pin circuit type h-15 (seg/com) out lcd segment & port 8 data v lc0 v lc1 v dd v lc2 figure 1 -10 . pin circuit type h-16 (p8)
product overview s3c72n8/p72n8/c72n5/p72n5 1- 10 notes
s3c72n8/p72n8/c72n5/p72n5 electrical data 14- 1 14 electrical data overview in this section, information on s3c72n8/c72n5 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c72n8/p72n8/c72n5 /p72n5 14- 2 table 14- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i all i/o ports ? 0.3 to v dd + 0.3 output voltage v o ? ? 0.3 to v dd + 0.3 output current high i oh one i/o p in active ? 15 ma all i/o ports active ? 35 output current low i ol one i/o pin active + 30 (peak value) + 15 (note) total value for ports 0, 2, 3, and 5 + 100 (peak value) + 60 (note) total value for ports 4, 6, and 7 + 100 + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 note : the values for output current low (i ol ) are calculated as peak value duty . table 14- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below for v ih2 , v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 6, 7 and reset 0.8 v dd ? v dd v ih3 x in , x out , xt in and xt out v dd ? 0.1 ? v dd input l ow v il1 ports 2, 3, 4 and 5 ? ? 0.3 v dd v v oltage v il2 ports 0, 1, 6, 7 and reset ? ? 0.2 v dd v il3 x in , x out , xt in and xt out ? ? 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v ports 0, 2, 3 , 4, 5, 6, 7 and bias i oh = ? 1 ma v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v port 8 only i oh = ? 100 a v dd ? 2.0 ? ?
s3c72n8/p72n8/c72n5/p72n5 electrical data 14- 3 table 14- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v , ports 0, 2 ?7 i ol = 1 5 ma ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v , port 8 only i ol = 100 a ? ? 1 input h igh leakage c urrent i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v in = v dd x in , x out , xt in and xt out ? ? 20 input low leakage c urrent i lil1 v in = 0 v all input pins except x in , x out , xt in and xt out ? ? ? 3 i lil2 v in = 0 v x in , x out , xt in and xt out ? 20 output h igh l eakage c urrent i loh 1 v out = v dd all output pins ? ? 3 m a output l ow l eakage c urrent i lol v o ut = 0 v all output pins ? 3 pull-up r esistor r l1 ports 0? 7 v in = 0 v; v dd = 5 v 25 47 100 k w v dd = 3 v 50 95 200 r l2 v in = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing r esistor r lcd t a = 25 c 50 93 140 com output r com v dd = 5 v ? 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 ? comi) io = 15ua (i = 0?3) ? 45 90 mv seg output voltage deviation v ds v dd = 5 v (v lc0 -segi) io = 15 m a (i = 0?31) ? ? 45 ? 90 mv
electrical data s3c72n8/p72n8/c72n5 /p72n5 14- 4 table 14- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units v lc0 output voltage v lc0 t a = 25 ? c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 ? c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 ? c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2 supply current (1) i dd1 (2) main operating: v dd = 5 v 10% cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22pf 6.0 mhz 4.19 mhz ? 3.5 2.5 8 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.6 1.2 4 3 i dd2 (2) main idle mode; v dd = 5 v 10% cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22pf 6.0 mhz 4.19 mhz ? 1.0 0.9 2.5 2.0 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.0 0.8 i dd3 sub operating: v dd = 3 v 10% cpu = fxt/4 scmod = 1001b 32 khz crystal o scillator ? 15 30 m a i dd4 sub idle mode; v dd = 3 v 10% cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 6 15 i dd5 stop mode; v dd = 5 v 10%, xt in = 0 v cpu = fxt/4, scmod = 0000b ? 2.5 5 i dd 6 (3) stop mode; v dd = 5 v 10% cpu = fx/4, scmod = 0100b ? 0.5 3 notes: 1. d.c. electrical values for supply current (i dd1 to i dd6 ) do not include current drawn through internal pull-up resistors and through lcd voltage dividing resistors. 2. data includes the power consumption for sub - system clock oscillation. 3. when the system clock mode register, scmod, is set to 0100b, the sub-system clock oscillation stops. the main-system clock oscillation stops by the stop instruction.
s3c72n8/p72n8/c72n5/p72n5 electrical data 14- 5 table 14- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator x in x out r frequency (1) v dd = 5 v r = 20 k w , v dd = 5 v r = 38 k w , v dd = 3 v 0.4 ? 2.0 1.0 2 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c72n8/p72n8/c72n5 /p72n5 14- 6 table 14- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillato r clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. table 14- 5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf
s3c72n8/p72n8/c72n5/p72n5 electrical data 14- 7 table 14-6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5 .5 v 0.95 ? 64 with subsystem clock (fxt) 114 122 125 tcl0 input f ti0 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz f requency v dd = 1.8 v to 5 .5v 1 m hz tcl0 i nput h igh, t tih0 , t til0 v dd = 2.7 v to 5.5 v 0.48 ? ? m s low w idth v dd = 1.8 v to 5 .5 v 1.8 sck c ycle t ime t kcy v dd = 2.7 v to 5 . 5 v external sck source 800 ? ? ns internal sck source 6 50 v dd = 1.8 v to 5 .5 v external sck source 3200 internal sck source 3800 sck h igh, l ow w idth t kh , t kl v dd = 1.8 v to 5.5 v external sck source 400 ? ? ns internal sck source t kcy /2 ? 50 v dd = 1.8 v to 5 .5 v external sck source 1600 internal sck source t kcy / 2 ? 150 si setup time to t sik external sck source 100 ? ? ns sck h igh internal sck source 150 si h old t ime to t ksi external sck source 400 ? ? ns sck h igh internal sck source 400 output d elay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 1.8 v to 5 .5 v external sck source 1000 internal sck source 1000 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0? ks7 10 reset input low width t rsl input 10 ? ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock (fx) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
electrical data s3c72n8/p72n8/c72n5 /p72n5 14- 8 1.5 mhz cpu clock 250 khz 15.6 khz main oscillator frequency 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1.8 v 500 khz 750 khz 1.0475 mhz 1.00 mhz 4.19 mhz figure 14- 1. standard operating voltage range table 14-7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 6.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m a release signal set time t srel normal operation 0 ? ? m s oscillator stabilization wait t wait released by reset ? 2 17 /fx ? ms time (1) released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid ins tability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c72n8/p72n8/c72n5/p72n5 electrical data 14- 9 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 14- 2. stop mode release timing when initiated by reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 14- 3. stop mode release timing when initiated by interrupt request
electrical data s3c72n8/p72n8/c72n5 /p72n5 14- 10 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 14- 4. a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 14- 5. clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 14- 6. clock timing measurement at xt in
s3c72n8/p72n8/c72n5/p72n5 electrical data 14- 11 tcl0 t tih0 t til0 1/f ti0 0.8 v dd 0.2 v dd figure 14- 7. tcl 0 timing reset t rsl 0.2 v dd figure 14- 8. input timing for reset reset signal int0, 1, 2, 4, k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 14- 9. input timing for external interrupts and quasi-interrupts
electrical data s3c72n8/p72n8/c72n5 /p72n5 14- 12 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 14- 10. serial data transfer timing
s3c72n8/p72n8/c72n5/p72n5 mechanical data 15- 1 15 mechanical data overview this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table
mechanical data s3c72n8/p72n8/c72n5/p72n5 15- 2 80-qfp-1420c #80 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 0.80 0.35 0.10 note : dimensions are in millimeters. 0.15 max 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 (0.80) (1.00) figure 15-1. 80 -qfp-14 20c package dimensions
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 1 1 6 s3p72n8/p72n5 otp overview the s3p72n8/p72n5 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c72n8/c72n5 microcontroller. it has an on-chip eprom instead of masked rom. the eprom is accessed by a serial data format. the s3p72n8/p72n5 is fully compatible with the s3c72n8/c72n5, both in function and in pin configuration. because of its simple programming requirements, the s3p72n8/p72n5 is ideal for use as an evaluation chip for the s3c72n8/c72n5.
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 2 s3p72n8 S3P72N5 (80-qfp-1420c) seg2 seg1 seg0 com0 com1 com2 com3 bias v lc0 sdat /v lc1 sclk /v lc2 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset p0.0/int4 p0.1/ sck p0.2/so p0.3/si p1.0/int0 seg19 seg20 seg21 seg22 seg23 p8.0/seg24 p8.1/seg25 p8.2/seg26 p8.3/seg27 p8.4/seg28 p8.5/seg29 p8.6/seg30 p8.7/seg31 p7.3/ks7 p7.2/ks6 p7.1/ks5 p7.0/ks4 p6.3/ks3 p6.2/ks2 p6.1/ks1 p6.0/ks0 p5.3 p5.2 p5.1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 p5.0 p4.3 p4.2 p4.1 p4.0 p3.3 p3.2 p3.1/lcdsy p3.0/lcdck p2.3/buz p2.2/clo p2.1 p2.0/tclo0 p1.3/tcl0 p1.2/int2 p1.1/int1 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 figure 16-1. s3p72n8/p72n5 pin assignments (80-qfp)
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 3 table 16-1. pin descriptions used to read/write the eprom main chip during programming pin name pin name pin no. i/o function v lc1 sdat 10 i/o serial data pin. output port when reading and input port when writing can be assigned as input/push-pull output port respectively. v lc2 sclk 11 i/o serial clock pin. input only pin. test v pp (test) 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 19 i chip initialization v dd / v ss v dd / v ss 12/13 i logic power supply pin. v dd should be tied to +5 v during programming. table 16-2. comparison of s3p72n8/p72n5 and s3c72n8/c72n5 features characteristic s3p72n8/p72n5 s3c72n8/c72n5 program memory 8 k/16 k-byte eprom 8 k/16-kbyte mask rom operating voltage (v dd ) 1.8 v to 5.5 v 1.8 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5 v ? pin configuration 80 qfp 80 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72n8/p72n5, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 16-3 below. table 16-3. operating mode selection criteria v dd v pp (test) reg/ mem mem address (a15-a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note: "0" means low level; "1" means high level.
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 4 table 16-4 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 output voltage v o ? ? 0.3 to v dd + 0.3 output current high i oh one i/o p in active ? 15 ma all i/o ports active ? 35 output current low i ol one i/o pin active + 30 (peak value) + 15 (note) total value for ports 0, 2, 3, and 5 + 100 (peak value) + 60 (note) total value for ports 4, 6, and 7 + 100 + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 note : the values for output current low (i ol ) are calculated as peak value duty . table 16-5 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units input high v oltage v ih1 all input pins except those specified below for v ih2 , v ih3 0.7 v dd ? v dd v v ih2 ports 0, 1, 6, 7 and reset 0.8 v dd ? v dd v ih3 x in , x out , xt in and xt out v dd ? 0.1 ? v dd input l ow v il1 ports 2, 3, 4 and 5 ? ? 0.3 v dd v v oltage v il2 ports 0, 1, 6, 7 and reset ? ? 0.2 v dd v il3 x in , x out , xt in and xt out ? ? 0.1 output high v oltage v oh1 v dd = 4.5 v to 5.5 v ports 0, 2, 3 , 4, 5, 6, 7 and bias i oh = ? 1 ma v dd ? 1 .0 ? ? v v oh2 v dd = 4.5 v to 5 . 5 v port 8 only i oh = ? 100 a v dd ? 2.0 ? ?
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 5 table 16-5 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5.5 v) parameter symbol conditions min typ max units output l ow v oltage v ol1 v dd = 4.5 v to 5.5 v , ports 0, 2 ?7 i ol = 1 5 ma ? 0.4 2 v v ol2 v dd = 4.5 v to 5.5 v , port 8 only i ol = 100 a ? ? 1 input h igh leakage c urrent i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v in = v dd x in , x out , xt in and xt out ? ? 20 input low leakage c urrent i lil1 v in = 0 v all input pins except x in , x out , xt in and xt out ? ? ? 3 i lil2 v in = 0 v x in , x out , xt in and xt out ? 20 output h igh l eakage c urrent i loh 1 v out = v dd all output pins ? ? 3 m a output l ow l eakage c urrent i lol v o ut = 0 v all output pins ? 3 pull-up r esistor r l1 ports 0- 7 v in = 0 v; v dd = 5 v 25 47 100 k w v dd = 3 v 50 95 200 r l2 v in = 0 v; v dd = 5 v , reset 100 220 400 v dd = 3 v 200 450 800 lcd voltage dividing r esistor r lcd t a = 25 c 50 93 140 com output r com v dd = 5 v ? 3 6 impedance v dd = 3 v 5 15 seg output r seg v dd = 5 v 3 6 impedance v dd = 3 v 5 15 com output voltage deviation v dc v dd = 5 v (v lc0 -comi) io = 15ua (i = 0?3) ? 45 90 mv seg output voltage deviation v ds v dd = 5 v (v lc0 -segi) io = 15 m a (i = 0?31) ? ? 45 ? 90 mv
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 6 table 16-5 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units v lc0 output voltage v lc0 t a = 25 ? c 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v v lc1 output voltage v lc1 t a = 25 ? c 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc2 output voltage v lc2 t a = 25 ? c 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2 supply current (1) i dd1 (2) main operating: v dd = 5 v 10% cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22pf 6.0 mhz 4.19 mhz ? 3.5 2.5 8 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.6 1.2 4 3 i dd2 (2) main idle mode; v dd = 5 v 10% cpu = fx/4 scmod = 0000b crystal oscillator c1 = c2 = 22pf 6.0 mhz 4.19 mhz ? 1.0 0.9 2.5 2.0 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.0 0.8 i dd3 sub operating: v dd = 3 v 10% cpu = fxt/4 scmod = 1001b 32 khz crystal oscillator ? 15 30 m a i dd4 sub idle mode; v dd = 3 v 10% cpu = fxt/4, scmod = 1001b 32 khz crystal oscillator ? 6 15 i dd5 stop mode; v dd = 5 v 10%, xt in = 0 v cpu = fxt/4, scmod = 0000b ? 2.5 5 i dd 6 (3) stop mode; v dd = 5 v 10% cpu = fx/4, scmod = 0100b ? 0.5 3 notes: 1. d.c. electrical values for supply current (i dd1 to i dd6 ) do not include current drawn through internal pull-up resistors and through lcd voltage dividing resistors. 2. data includes the power consumption for sub - system clock oscillation. 3. when the system clock mode register, scmod, is set to 0100b, the sub-system clock oscillation stops. the main-system clock oscillation stops by the stop instruction.
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 7 table 16-6 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 4.5 v to 5 . 5 v ? ? 10 ms v dd = 1.8 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? ? ns rc oscillator x in x out r frequency (1) v dd = 5 v r = 20 k w , v dd = 5 v r = 38 k w , v dd = 3 v 0.4 ? 2.0 1.0 2 mhz notes: 1. oscillation frequency and x in in put frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillat or stabilization after a power-on occurs, or when stop mode is terminated.
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 8 table 16-7 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 1.8 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 1.8 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval requir ed for oscillating stabilization after a power-on occurs. table 16-8 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input c apacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output c apacitance c out ? ? 15 pf i/o c apacitance c io ? ? 15 pf
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 9 table 16-9 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 1.8 v to 5 . 5 v) parameter symbol conditions min typ max units instruction c ycle t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s t ime (1 ) v dd = 1.8 v to 5.5 v 0.95 ? 64 with subsystem clock (fxt) 114 122 125 tcl0 input f ti0 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz f requency v dd = 1.8 v to 5 .5v 1 m hz tcl0 i nput h igh, t tih0 , t til0 v dd = 2.7 v to 5.5 v 0.48 ? ? m s low w idth v dd = 1.8 v to 5 .5 v 1.8 sck c ycle t ime t kcy v dd = 2.7 v to 5 . 5 v external sck source 800 ? ? ns internal sck source 6 50 v dd = 1.8 v to 5 .5 v external sck source 3200 internal sck source 3800 sck h igh, l ow w idth t kh , t kl v dd = 1.8 v to 5.5 v external sck source 400 ? ? ns internal sck source t kcy /2 ? 50 v dd = 1.8 v to 5 .5 v external sck source 1600 internal sck source t kcy / 2 ? 150 si setup time to t sik external sck source 100 ? ? ns sck h igh internal sck source 150 si h old t ime to t ksi external sck source 400 ? ? ns sck h igh internal sck source 400 output d elay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 1.8 v to 5 .5 v external sck source 1000 internal sck source 1000 interrupt input t inth , t intl int0 ( 2 ) ? ? m s h igh, l ow w idth int1, int2, int4, k s 0 -ks7 10 reset input low width t rsl input 10 ? ? m s notes: 1. u nless otherwise specified, instruction cycle time condition values assume a m ain system clock (fx) source. 2. minimum value for int0 is based on a clock of 2t cy or 128/fx as assigned by the imod0 register setting.
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 10 1.5 mhz cpu clock 250 khz 15.6 khz main oscillator frequency 3 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1.8 v 500 khz 750 khz 1.0475 mhz 1.00 mhz 4.19 mhz figure 16-2 . standard operating voltage range table 16-10 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr normal operation 1.8 ? 6.5 v data retention supply current i dddr v dddr = 1.8 v ? 0.1 10 m s release signal set time t srel normal operation 0 ? ? m s oscillator stabilization wait t wait released by reset ? 2 17 /fx ? ms time (1) released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 11 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 16-3 . stop mode release timing when initiated by reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 16-4 . stop mode release timing when initiated by interrupt request
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 12 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 16-5 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 16-6 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 16-7 . clock timing measurement at xt in
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 13 tcl0 t tih0 t til0 1/f ti0 0.8 v dd 0.2 v dd figure 16-8 . tcl 0 timing reset t rsl 0.2 v dd figure 16-9 . input timing for reset reset signal int0, 1, 2, 4, k0 to k7 t inth t intl 0.8 v dd 0.2 v dd figure 16-10 . input timing for external interrupts and quasi-interrupts
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 14 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 16-11 . serial data transfer timing
s3c72n8/p72n8/c72n5/p72n5 s3p72n8/p72n5 otp 16- 15 start address = first location v dd = 5 v, v pp = 12.5 v x = 0 program one 1 ms pulse increment x v dd = v pp = 5 v compare all byte device passed pass verify 1 byte last address fail no increment address x = 10 no yes verify byte fail fail device faild figure 16-12. otp programming algorithm
s3p72n8/p72n5 otp s3c72n8/p72n8/c72n5 /p72n5 16- 16 notes

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