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tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 high-efficiency integrated dimming led lighting controller check for samples: tps92070 1 features description the tps92070 is an advanced pwm controller ideal ? advanced integrated dimming interface for use in low-power, offline, led lighting ? non-dissipative triac dimmer management applications. the integrated dimming interface circuit ? lamp-to-lamp uniformity during dimming of the tps92070 features a non-dissipative dimmer trigger control circuit. the tps92070 controller ? no low-frequency photometric ripple provides dc led current with no photometric ripple ? exponential dimming profile effects. the dc current also results in higher efficacy ? innovative secondary-side feedback of the leds. the tps92070 provides exponentially eliminates optocoupler devices controlled light output based on the external dimmer position. high power factor is achieved with a valley ? led current regulation better than 5% fill circuit. once a leading-edge dimmer is detected, ? programmable minimum led current the tps92070 sets an output to disable the pfc ? valley switching and dcm operation for circuit and thus optimizes driver operation. the led reduced emi and improved efficiency current sense precision error amplifier implements deep dimming. the tps92070 current sensing ? leading edge dimmer detection scheme provides tight current regulation and ? power factor > 0.8 eliminates the need for an optocoupler. the tight ? cycle-by-cycle current limit protection current regulation allows for strong color and intensity matching amongst individual bulbs or luminaires. ? low start-up and standby currents ? integrated pwm mosfet driver the tps92070 also contains a variety of protection features including cycle-by-cycle peak-current limit, ? thermal shutdown overcurrent protection, open-led (output ? 16-pin, tssop package overvoltage) protection, undervoltage lockout, and thermal shutdown. applications ? led light bulb replacement ? led luminaires ? led downlights ? led wall washers 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com application diagram 2 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070 udg-11185 bp vdd gnd vd gate tdd pcs pgnd tps92070 dtc vz sen min iso cs comp lp + C or
tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) (2) temperature transport orderable package pins units range (t j ) material number tube 70 tps92070pw C 40 c to 140 c plastic tssop 16 tape and reel 2000 TPS92070PWR (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . (2) package drawings, thermal data, and symbolization are available at www.ti.com/packaging absolute maximum ratings (1) (2) (3) all voltages are with respect to gnd, C 40 c < t j = t a < 125 c, all currents are positive into and negative out of the specified terminal (unless otherwise noted) value units min max supply voltage vdd (4) C 0.3 25.0 iso, cs, comp, lp, min, sen, pcs C 0.3 7.0 bp, gate, tdd C 0.3 7.2 input voltages vd C 1.4 7.0 vz, dtc (5) C 0.3 20.0 vz (pulse < 1 ms) 5 bp C 0.5 0 input current peak 30 ma dtc average 16 vdd 5 operating junction temperature (6) C 40 140 c storage temperature (6) C 65 150 c lead temperature (10 seconds) 260 c (1) these are stress ratings only. stress beyond these limits may cause permanent damage to the device. functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods of time may affect device reliability (2) all voltages are with respect to gnd. (3) all currents are positive into the terminal, negative out of the terminal. (4) vdd clamped at approximately 23 v. see electrical characteristics table. (5) vz clamped at approximately 12.5 v. see electrical characteristics table. (6) higher temperature may be applied during board soldering process according to the current jedec j-std-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. copyright ? 2011, texas instruments incorporated submit documentation feedback 3 product folder link(s) : tps92070
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com recommended operating conditions unless otherwise noted, all voltages are with respect to gnd, C 40 c < t j = t a < 125 c. min typ max unit vdd input voltage 9 21.5 v vz current 1 100 a r min resistor from min to gnd (1) 25 75 k r vd1 valley detect resistor from aux winding to vd pin 50 200 k c vz vz bypass capacitor 1 4.7 nf c bp bp capacitor 0.47 1 f c vdd vdd capacitor 10 c bp7 4.7 f c vdd,bp vdd bypass capacitor, ceramic (2) 0.1 f (1) r min values greater than 75k will produce lower minimum current values. however accuracy of the minimum current will degrade, and there may be flickering at very low values of imin. (2) if a ceramic capacitor is used for c vdd then this capacitor is not needed. electrostatic discharge (esd) protection max unit esd rating, human body model (hbm) 1.5 kv esd rating, charged device model (cdm) 500 v electrical characteristics unless otherwise stated, ? 40 c < t a < 125 c, t j = t a , v vdd = 12 v, gnd =0 v, i vz = 50 a, r min = 71.5 k , c vdd = 4.7 f, c bp = 1 f, c lp = 220nf parameter test conditions min typ max units bias and startup i start vz startup current v vdd = 7 v, measured i vz 1.0 10 a v vz vz voltage v vdd = 7 v, 15 a < i vz < 100 a 11.5 12.5 13.5 v vdd startup current v vdd = 7.5 v 134 240 i vdd standby current v lp = 0 v, v sen = 0 v 750 1500 a switching current fg ate = 138 khz, gate C unloaded 1880 2500 v vdd(uvlo) vdd uvlo threshold measured at vdd (falling) 7 7.88 8.4 v v vdd(ovp) vdd clamp and ovp measured at vdd (rising) 21.5 23.5 25 v r vz(ovp) ovp vz discharge resistance v vdd = v vdd(ovp) , vz = 3 v 4.8 k v bp bp regulation voltage 9 v < v vdd < 19v, i bp = C 0 a 6.7 7 7.2 v dimmer trigger circuit v sen(hi) measured at sen (rising) 4.75 5 5.25 dimmer sense thresholds v v sen(lo) measured at sen (falling) 0.9 1 1.10 v sen(clamp) sen clamp voltage i sen = 100 a 5.75 6 6.25 v i dtc(lkg) dtc to pgnd leakage current v dtc = 12 v, v sen > v sen(hi) 40 100 na v dtc = 3 v, v sen (falling), v sen(lo) < v sen < 16 20 25 k v sen(hi) r dtc(pgnd) dtc to pgnd resistance v dtc = 3 v, v sen (rising), v sen < v sen(hi) 100 156 300 v sen < v sen(lo) 100 156 300 current setpoint v min min regulation voltage 2.5 r out(lp) lp output resistance 500 k v oh(lp) lp maximum voltage level v sen = 6 v, i lp = 0 a 2.9 3 3.1 v C 0.02 v ol(lp) lp minimum voltage level v sen = 0 v, i lp = 0 a 0 0.025 v 5 4 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070
tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 electrical characteristics (continued) unless otherwise stated, ? 40 c < t a < 125 c, t j = t a , v vdd = 12 v, gnd =0 v, i vz = 50 a, r min = 71.5 k , c vdd = 4.7 f, c bp = 1 f, c lp = 220nf parameter test conditions min typ max units error amplifier v ios input offset voltage 5 mv < v cs < 100 mv, v comp = 3 v 500 v v comp(min) minimum comp clamp voltage v cs = 150 mv, v lp < 3 v 1.45 1.53 1.60 v v comp(max) maximum comp clamp voltage v cs < 100 mv, v lp > 2.1 v 3.6 3.7 3.8 v v cs(min) minimum cs reference voltage v lp = 0, r min = 71.5 k , t a = 25 c 2.835 3.15 3.465 mv v cs(max) maximum cs reference voltage v lp > 2.1 v, t a = 25 c 97 100 103 mv modulation f clamp(max) maximum frequency clamp measured at gate, v comp = 3.5 v, t a = 25 c 132 138 146 khz measure at gate, v comp = 1.53 v, v vd = 0 v, f clamp(min) minimum frequency clamp 10 20 30 t a = 25 c valley detect measured when gate is high, i vd = C 15 a C 560 vd clamp vd clamp mv measured when gate is low and vd is falling C 125 v vd(en) vd enable threshold minimum peak of resonant valley, v comp = 1.8 v 600 mv v vd(zc) zero-crossing detect threshold measured at vd (falling) 80 100 135 mv v comp > v minf_det , v vd = 0 v, wait time for next t vd(vw) valley wait timer 10 12.7 14 s pwm pulse with zero-crossing detected i vd(min) current required for valley detection C 50 a overcurrent protection v pcs(oc) over current limit measure at pcs (rising), v comp = 4 v 670 700 750 mv t pcs_g1(oc) propagation delay measured between pcs and gate falling 10 64 190 ns pwm comparator t leb leading edge blanking measured at gate, v comp = 3.5 v 180 220 300 ns v pwm(max) v comp = v comp(max) 600 650 v pwm pwm thresholds v comp = 3.5 v 460 500 550 mv v pwm(min) measured at pcs rising, comp 2 v 40 65 80 t pcs_g1(cl) propagation delay measured between pcs and gate falling 10 54 120 ns led isolated current sense r iso(pd) pull down resistance gate is high 240 270 350 pwm outputs v gate(oh) output voltage high 6.7 7 7.2 measured at gate v v gate(ol) output voltage low C 0.01 0 0.01 t fall(pwm) fall time c gate = 1 nf, t a = 25 c 43 70 ns t rise(pwm) rise time cg ate = 1 nf, t a = 25 c 105 155 triac dimmer detection v tdd(oh) output voltage high measured at tdd 6.7 7 7.2 v v tdd(ol) output voltage low C 0.01 0 0.01 t fall(tdd) fall time c tdd = 1 nf 120 190 ns t rise(tdd) rise time c tdd = 1 nf 130 220 minimum delay from 1v to 5v sen t dly_1v_5v signal transitions for no dimmer 105 135 170 s detection copyright ? 2011, texas instruments incorporated submit documentation feedback 5 product folder link(s) : tps92070
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com device information functional block diagram 6 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070 udg-11186 vz sen dtc gnd + + s q q r 1 v 5 v 20 k w 160 w lp set-point filter exponential dimming control min + 2.5 v + 2.5 v r max 100 k w control to period translator + pwm and fault logic r gm 500 w + tdd pcs iso comp cs v ios < 500 m v control to peak current translator + 0.7 v ocp triac dimmer detection gate bp vd gnd vdd 7 v 7 v + 7 v vdd valley detect + + 8 v uvlo 23 v ovp 155c 140c 12.5 v 6 v i set from pwm similar to gate tsd valley pwmcomparator v pwm tps92070
tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 tps92070 pw (tssop) package (top view) pin descriptions pin description name no. bp 1 connect a 1-uf ceramic capacitor to gnd to bypass the internal voltage regulator. comp 7 loop compensation output. connect the loop compensation components between this pin and gnd cs 6 led current sense feedback and positive input terminal of the error amplifier. dimmer trigger control input. connect this pin to thesource of the hv n-channel mosfet cascode device of the dtc dtc 12 circuit. gate 16 pwm drive signal output. connect to flyback power mosfet. gnd 3 ground for internal circuitry inverting input of secondary side current sense comparator and isolation transformer buffer. connect to gnd for iso 5 non-isolated applications. lp 8 pole for dtc low pass filter. connect a capacitor to gnd to set the response time of the dimming level detection circuit. min 9 minimum current programming input. connect a resistor to gnd to set the minimum led current. pcs 14 primary current sense input. connected to shunt resistor for primary side current sense. pgnd 13 power ground for gate driver. connected to gnd (1) sen 10 dimmer sense input. an internal window comparator continuously monitors this pin to determine the dimmer setting. triac dimmer detect. drives bypass fet in valley fill pfc when dimmer is detected. for non pfc applications, leave tdd 15 this pin open vd 4 valley detect input. connect to the aux winding through a resistor divider. provides power to the device. connect a bypass capacitor directly to gnd. see recommended operating vdd 2 conditions for suggested values. vz 11 voltage clamp. this pin clamps the maximum voltage on the gate of the external hv dtc n-channel mosfet. (1) see application section for layout recommendations copyright ? 2011, texas instruments incorporated submit documentation feedback 7 product folder link(s) : tps92070 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 bp vdd gnd vd iso cs comp lp gate tdd pcs pgnd dtc vz sen min
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com typical characteristics unless otherwise stated, C 40 c t a = t j +125 c, v vdd = 12 v, gnd =0v, i vz = 50 a, r min = 71.5 k , c vdd = 10 f, c vz = 1 nf, c lp = 220 nf figure 1. maximum clamp frequency vs. temperature figure 2. minimum clamp frequency vs. temperature figure 3. maximum current sense voltage vs. figure 4. minimum current sense voltage vs. temperature temperature 8 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070 130 132 134 136 138 140 142 144 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) maximum clamp frequency (khz) g000 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) minimum clamp freqency (khz) g000 95 97 99 101 103 105 107 109 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) maximum current sense voltage (mv) g000 3.00 3.05 3.10 3.15 3.20 3.25 3.30 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 temperature (c) minimum current sense voltage (mv) g000
tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 applications startup bias and uvlo during powerup when vdd is less than the uvlo threshold of 8 v, the vz pin is trickle charged with i vz(start) of approximately 10 a through the startup-resistor connected to the bulk rectified voltage. as vz is being charged, vdd tracks vz (less v gsth ) through the external cascode hv mosfet (q1) supplying a vdd startup current of 135 a. once vz reaches the tps92070 zener clamp regulation level of 12.5 v, the device enters into a stand-by mode during which the dimmer trigger circuit (dtc), set-point filter, 7-v bias regulator, and a minimal amount of housekeeping circuitry is active. the tps92070 remains in this state until the sen pin exceeds 5 v indicating that adequate line voltage is present, either through triac firing, or line voltage presence. the typical start-up waveforms are shown in figure 5 . figure 5. typical startup waveforms for a triac triggered v in(ac) input copyright ? 2011, texas instruments incorporated submit documentation feedback 9 product folder link(s) : tps92070 udg-11187 vdd vz 12.5 v bp sen lp gate pwm switching 0 v 0 v i out i min 7 v 0 v 0 v 6 v
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com dtc and phase detection the dtc pin is a current sink which loads the dimmer with approximately 20 ma during the zero-crossing of the ac line to ensure that the triac is reliably triggered. this current sink is switched on when the voltage on the sen pin is below 5 v. the setpoint filter in conjunction with the sen and lp pins is used to determine the firing angle of the triac dimmer (if any) connected to the input of the led driver. an internal window comparator monitors the sen (dimmer sense input) pin and the resulting duty-cycle is transformed into a voltage at the lp pin using the lp filter. the relation between the triac firing angle and the lp voltage is shown in figure 6 . it illllustrates the conversion of the triac firing angle to lp voltage and exponential dimming control of i set based on internal control voltage. as the voltage on the lp varies from 0 v to 3 v based on the mapping of 0% to 100% sen duty-cycle, an internal control voltage is linearly modulated by tps92070 from 400 mv to 200 mv. figure 6. triac firing angle vs. low-pass filter voltage 10 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070 udg-11188 33% sen duty-cycle 66% 200 400 internal control voltage (mv) low-pass filter voltage (v) 0 3 1.98 current sense voltage (mv) v cs(min) v cs(max) 100 1
tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 the internal control voltage, v ctrl is clamped to 0.4 v for lp < 1 v and clamped to 0.2 v for lp > 1.98v . as the control voltage is linearly modulated between 0.4 v and 0.2 v, the current sense reference voltage v cs is exponentially controlled between the pre-set maximum of 100 mv and the externally programmed minimum limit of v cs_min . the current setpoint level, v cs_min is programmed by r min . (1) the exponential control of the set-point current extends the dimming control range and enables up to two decades of led current-programming between the v cs(min) and v cs(max) = 100 mv levels. led current sense the secondary-side led current is sensed using the cs pin and tightly regulated using the low-offset (500 v) transconductance amplifier. the transconductance (g m ) of the amplifier is internally set to approximately g m = 1/500 s. in the direct current-sense mode (non-isolated), the iso pin is connected to gnd. in the isolated-mode, the secondary-side led current is sensed using a small transformer with the secondary of the transformer connected between cs and iso pins as shown in figure 7 . the iso pin has a switched pull-down resistance of 270 . figure 7. isolated current sense modulation the internal i set current and rgm sets a reference input for the transconductance current sense amplifier which controls the voltage on the comp pin. the comp pin is used for loop compensation. the voltage on the comp pin modulates the peak of the primary current and the switching frequency (frequency modulation) of the flyback converter. the modulation on the primary current and the switching frequency are shown in figure 8 . the peak of the primary current is modulated by varying the threshold on the pwm comparator. the threshold is modulated from 0.6 v to 0.065 v while the switching frequency varies between 20 khz and 138 khz as comp pin varies from 3.7 v to 2.6 v. the maximum comp pin voltage is clamped at 3.7 v allowing the maximum cycle-by-cycle peak current limit pwm threshold to be 0.6 v. the switching frequency is linearly modulated from 138 khz to 20 khz with the pwm threshold clamped at 0.065 v as the comp pin varies from 2.6 v to 1.63 v. the minimum frequency is clamped at 20 khz and tps92070 enters the minimum frequency detect state for comp < 1.6 v. the minimum voltage on the comp is clamped at 1.53 v. the pwm threshold is related to the comp pin voltage as shown in equation 2 and equation 3 . for 2.6 v comp 3.7, (2) for v comp < 2.6 v, (3) copyright ? 2011, texas instruments incorporated submit documentation feedback 11 product folder link(s) : tps92070 ( ) cs min min 225 v r = udg-11189 csiso gate r ds(on) 270 w v p comp pwm v 2.5 v 2 - = pwm v 0.065 =
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com figure 8. switching period and pwm threshold modulation based on comp pin voltage primary current sense the primary current is sensed by monitoring the voltage developed across an external current-sense resistor connected between the source of the external hv mosfet and pgnd. the pcs pin is used for monitoring the voltage and it is then compared with the pwm threshold (v pwm ). the pwm comparator has a leading-edge blanking time of 220 ns to avoid any false-tripping of the comparator due to capacitive charge spikes on the pcs pin. the gate output is pulled low once the pcs pin reaches the pwm threshold. 12 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070 udg-11194 1.63 loop compensation voltage (v) t period(min) t period(max) t period pwm threshold voltage v pwm(min) v pwm(max) 2.6 v comp(max)
tps92070 www.ti.com slusan1 C draft 6 * august 30, 2011 valley detect tps92070 ensures that the flyback converter always operates in either dcm or qr mode of operation and initiates a new pwm switching cycle only after the energy in the flyback transformer is completely reset to zero. this is accomplished by monitoring the auxiliary winding waveform using a resistive divider connected to the vd pin. the tps92070 initiates a new switching cycle based on the following conditions: ? for normal operation with 1.63 v v comp 3.7 v, a new pwm switching cycle is initiated when the internal timer t period has expired and the next valley is detected. the vd pin must go below 100 mv (v vd(zc) ) prior to valley detection to enable the valley detector circuit. ? in the minimum frequency clamp state when v comp < 1.63 v, the switching period is fixed at t period(max) (corresponding to f clamp(min) ) and the valley detector is disabled. ? the relationship of t period to the switching frequency is shown in equation 4 and equation 5 . (4) (5) by turning on the flyback power switch at the resonant valley, the switching losses are reduced thereby enabling higher efficiency. the voltage at the vd pin is clamped at C 0.56 v during the negative excursions on the aux winding when gate is high. when gate is low and during the resonant valley detection, the vd pin is clamped at C 0.2 v. the interface to the vd pin to the aux winding is shown in figure 9 . the tps92070 requires that the positive peak of the resonant ring at the vd pin is higher than 0.6 v (v vd(en) ) to ensure that the valley-detect circuit is enabled for detection on the falling edge when v comp > 1.63 v. hence, r vd2 need to be selected in such a way that this condition is met for all aux voltages when v comp > 1.63 v. a current i vd(min) of at least 50 a must be drawn from the vd pin when the gate is high to ensure proper valley detection. this requirement determines the value of r vd1 . the waveforms associated with the valley detect are shown in figure 10 . if the voltage at the aux winding is not sufficient for valley detection when v comp > 1.63 v, an internal valley wait timer of 12.7 s (t vd(vw) ) expires after the t period times out. the time out of the valley wait timer would initiate a new pwm switching pulse following the 100 mv threshold crossing on the vd pin. spacer (do not translate) figure 9. auxiliary winding interface to vd figure 10. hv mosfet drain and vd waveforms copyright ? 2011, texas instruments incorporated submit documentation feedback 13 product folder link(s) : tps92070 ( ) ( ) clamp max period min 1 f t = ( ) ( ) clamp min period max 1 f t = udg-11191 vd resonant valley detect r vd1 n p n s n b r vd2 udg-11192 time t period t period valley switching (1) (2) (3) . (1) resonanat ring at vd pin (2) resonant clamp at -0.2 v (3) on-time clamp at -0.56 v
tps92070 slusan1 C draft 6 * august 30, 2011 www.ti.com triac dimmer detect the tdd pin is used to drive an external by-pass fet that disables valley-fill pfc when a dimmer is detected by tps92070. the tdd pin is set to logic high state (v tdd(oh) = 7 v) as the part is powered up and if no dimmer is detected by continuously sensing the sen pin, the tdd pin is then reset to logic low (v tdd(ol) = 0 v). the presence of a dimmer is detected by monitoring the time delay in a window between 1 v and 5 v comparators that are monitoring the sen pin. if the rise time from 1 v to 5 v is greater than 135 s for four consecutive half-line cycles, direct connection to the ac line without dimmer is assumed, and the tdd output goes low. otherwise the tdd pin remains high. if the tdd pin is low and the delay time (t dly_1v_5v ) is detected to be less than 135 s, for four consecutive half-line cycles, the tdd pin goes high once the sen pin falls below 1 v indicating dimmer detection. protection features output over voltage protection (ovp) output (secondary-side) overvoltage protection / open led detection is achieved by disabling the controller whenever the vdd voltage rises enough to trigger its internal 23 v clamp. upon ovp detection, gate is pulled low and the tdd pin is reset to logic-high state. the tps92070 is disabled and an internal pull-down resistor (r vz(ovp) ) discharges the vz pin, until the vdd voltage drops below the uvlo threshold when a restart is triggered. overcurrent protection (ocp) overcurrent faults are detected when the pcs pin exceeds the internal 700-mv threshold. upon the detection of an ocp condition, the gate signal is pulled low, and the lp pin voltage is reset to 0 v corresponding to the minimum led output condition. gate switching and current regulation resumes from the minimum led light setting once the sen pin crosses the 5 v. thermal shutdown (tsd) tps92070 is disabled if the junction temperature of the part exceeds approximately 155 c and enters into the restart mode where the vz pin is discharged until vdd falls below the uvlo threshold. the device stays in this restart mode until the junction temperature falls below approximately 140 c when it resumes normal operation with the light output preset to the minimum setting. pcb layout use good layout practices when constructing the pcb. maintain the location of bypass components close to the pins being bypassed. route power ground (pgnd) separate from signal ground (gnd) to keep the high current paths and the small signal paths separate. connect pgnd to gnd at a single point, preferably under the device. 14 submit documentation feedback copyright ? 2011, texas instruments incorporated product folder link(s) : tps92070
package option addendum www.ti.com 17-sep-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) tps92070pw active tssop pw 16 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim TPS92070PWR active tssop pw 16 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS92070PWR tssop pw 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 q1 package materials information www.ti.com 16-sep-2011 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS92070PWR tssop pw 16 2000 346.0 346.0 29.0 package materials information www.ti.com 16-sep-2011 pack materials-page 2

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