spice device model sup/sub85n04-03 vishay siliconix this document is intended as a spice modeling guideline and does not constitute a commercial product data sheet. designers sho uld refer to the appropriate data sheet of the same number for guaranteed specification limits. document number: 71615 www.vishay.com 18-apr-01 1 n-channel 40-v (d-s) 175c mosfet characteristics ? n- and p-channel vertical dmos ? macro model (subcircuit model) ? level 3 mos ? apply for both linear and switching application ? accurate over the ? 55 to 125 c temperature range ? model the gate charge, transient, and diode reverse recovery characteristics description the attached spice model describes the typical electrical characteristics of the n-channel vertical dmos. the subcircuit model is extracted and optimized over the ? 55 to 125 c temperature ranges under the pulsed 0-to-10v gate drive. the saturated output impedance is best fit at the gate bias near the threshold voltage. a novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched c g d model. all model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. subcircuit model schematic
spice device model sup/sub85n04-03 vishay siliconix www.vishay.com document number: 71615 2 18-apr-01 specifications (t j = 25 c unless otherwise noted) parameter symbol test condition simulated data measured data unit static gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 1.9 v on-state drain current a i d(on) v ds = 5 v, v gs = 10 v 1410 a v gs = 10v, i d = 30a 0.0026 0.0029 v gs = 4.5v, i d = 20a 0.0040 0.0044 v gs = 10v, i d = 30a, t j = 125c 0.0037 drain-source on-state resistance a r ds(on) v gs = 10v, i d = 30a, ,t j = 175c 0.0043 ? forward transconductance a g fs v ds = 15v, i d = 30 a 87 s forward voltage a v sd i s = 85a, v gs = 0 v 0.92 1.1 v dynamic b input capacitance c iss 6809 6860 output capacitance c oss 1347 1320 reverse transfer capacitance c rss v gs = 0v, v ds = 25v, f = 1 mhz 823 800 pf total gate charge b q g 165 165 gate-source charge b q gs 25 25 gate-drain charge b q gd v ds = 30v, v gs = 10v, i d = 85a 55 55 nc turn-on delay time b t d(on) 57 15 rise time b t r 103 90 turn-off delay time b t d(off) 120 95 fall time b t f v dd = 30v, r l = 0.35 ? i d ? 85a, v gen = 10v, r g = 2.5 ? 193 125 reverse recovery time t rr i f = 85a, di/dt = 100 a/ s 65 60 ns notes a. pulse test; pulse width 300 s, duty cycle 2%. b. guaranteed by design, not subject to production testing.
spice device model sup/sub85n04-03 vishay siliconix document number: 7xxxx www.vishay.com dd-mon-yr 3 comparison of model with measured data (t j =25 c unless otherwise noted)
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