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document no. a13761ej1v1um00 (1st edition) date published january 2002 ns cp(n) printed in japan 1998 ? preliminary user?s manual V30MZ? 16-bit microprocessor core hardware
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3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. V30MZ, v30hl, v30mx, and v series are trademarks of nec corporation.
4 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. ? the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? not all devices/types available in every country. please check with local nec representative for availability and additional information. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5d 98. 12
5 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.12 nec electronics (europe) gmbh duesseldorf, germany tel: 0211-65 03 01 fax: 0211-65 03 327 ? branch the netherlands eindhoven, the netherlands tel: 040-244 58 45 fax: 040-244 45 80 ? branch sweden taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (france) s.a. v?lizy-villacoublay, france tel: 01-3067-58-00 fax: 01-3067-58-99 nec electronics (france) s.a. representaci?n en espa?a madrid, spain tel: 091-504-27-87 fax: 091-504-28-60
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7 introduction readers : this manual is intended for users who have an understanding of the V30MZ hardware which is the cpu core of cbic functions and wish to design an application system using the V30MZ functions. purpose : this manual is intended for users to understand the V30MZ hardware functions described in the organization below. organization : this V30MZ users manual mainly consists of the following chapters. ? general description ? interrupt functions ? pin functions ? standby functions ? cpu functions ? reset functions ? bus control functions ? test functions how to read this manual : this manual assumes that users have a general understanding of electric circuits, logical circuits, and microcontrollers. to understand the overall functions of the V30MZ functions ? read this manual in the order of the table of contents . to find the differences between v30hl? and v30mx? ? refer to section 1.3 differences between V30MZ and v30hl, v30mx. to find the details of instruction functions ? refer to the separate volume of the 16-bit v series tm instruction users manual . conventions : data significance : higher digits on the left and lower digits on the right active low representation : xxxb (b after pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numerical representation : binary xxxx or xxxxb decimal xxxx hexadecimal xxxxh prefixes indicating power of 2 (address space, memory capacity) : k (kilo) : 2 10 = 1024 m (mega) : 2 20 = 1024 2 g (giga) : 2 30 = 1024 3
8 related documents : note that the related documents may be preliminary versions, but there are not indicated as such in this document. ? 16-bit v series instruction users manual (u11301e) ? cb-c9 family vx/vm type design manual users manual (a12745e) ? cb-c9 family vx/vm type core library cpu core users manual (a13195e)
9 contents chapter 1 general description .............................................................................................. .. 13 1.1 features................................................................................................................. ........................................ 13 1.2 symbol diagram ........................................................................................................... ................................. 13 1.3 differences between V30MZ and v30hl, v30mx............................................................................... .......... 14 chapter 2 pin functions.................................................................................................... ............ 17 2.1 pin list ................................................................................................................. .......................................... 17 2.2 pin statuses................................................................................................................ ................................... 18 2.3 description of pin statuses.............................................................................................. .............................. 19 2.3.1 normal pins............................................................................................................ ............................. 19 2.3.2 test pins .............................................................................................................. ............................... 22 2.3.3 reserved pins .......................................................................................................... ........................... 22 2.4 handling of unused pins .................................................................................................. ............................. 23 chapter 3 cpu functions .................................................................................................... .......... 25 3.1 register configuration ................................................................................................... ................................ 25 3.1.1 general-purpose registers (aw, bw, cw, dw) ............................................................................. .... 25 3.1.2 segment registers (ps, ss, ds0, ds1) ................................................................................... ........... 25 3.1.3 pointer (sp, bp)....................................................................................................... ........................... 25 3.1.4 program counter (pc)................................................................................................... ...................... 26 3.1.5 program status word (psw) .............................................................................................. ................. 26 3.1.6 index register (ix, iy) ................................................................................................ .......................... 30 3.2 address space ............................................................................................................ .................................. 31 3.2.1 memory space ........................................................................................................... ......................... 31 3.2.2 i/o space.............................................................................................................. ............................... 32 3.3 instruction prefetch..................................................................................................... ................................... 33 3.4 logical address and physical address..................................................................................... ..................... 34 3.4.1 segment system ......................................................................................................... ........................ 34 3.4.2 segment configuration .................................................................................................. ...................... 35 3.4.3 dynamic relocation ..................................................................................................... ........................ 37 3.5 effective address........................................................................................................ ................................... 39 3.6 instruction set.......................................................................................................... ...................................... 40 3.6.1 list of instruction sets by function................................................................................... .................... 40 3.6.2 format of object code .................................................................................................. ....................... 41 3.7 addressing mode.......................................................................................................... ................................. 42 3.7.1 instruction address .................................................................................................... ......................... 42 3.7.2 data address........................................................................................................... ............................ 43 chapter 4 bus control functions .......................................................................................... 4 7 4.1 interface between V30MZ and memory....................................................................................... .................. 47 4.1.1 cautions on accessing word data ........................................................................................ ............... 48 4.2 interface between V30MZ and i/o .......................................................................................... ....................... 49 4.3 read/write timing of memory and i/o ...................................................................................... .................... 50 4.3.1 read timing of memory and i/o .......................................................................................... ................ 50 4.3.2 write timing of memory and i/o ......................................................................................... ................. 52 4.4 bus hold function ........................................................................................................ ................................. 54
10 chapter 5 interrupt functions .............................................................................................. ... 55 5.1 hardware interrupt ....................................................................................................... .................................. 58 5.1.1 non-maskable interrupt (nmi) ........................................................................................... .................. 58 5.1.2 maskable interrupt (int) ............................................................................................... ...................... 58 5.2 software interrupts...................................................................................................... ................................... 60 5.3 timing at which interrupt is not acknowledged ............................................................................ ................. 61 5.4 interrupt servicing in execution of block processing instruction ......................................................... .......... 62 chapter 6 standby functions ................................................................................................ .... 65 6.1 setting of standby mode.................................................................................................. .............................. 65 6.2 standby mode............................................................................................................. ................................... 65 6.3 release of standby mode.................................................................................................. ............................ 66 6.3.1 release by hardware interrupt request .................................................................................. ............. 66 6.3.2 release by reset input ................................................................................................. ................... 67 chapter 7 reset functions.................................................................................................. ........ 69 chapter 8 test functions................................................................................................... .......... 71 8.1 test pins ................................................................................................................ ........................................ 71 8.1.1 test bus pins (tbi22 to tbi0, tbo42 to tbo0)........................................................................... ....... 71 8.1.2 bunri, test pins ....................................................................................................... ....................... 71 8.2 normal mode.............................................................................................................. .................................... 72 8.3 unit test mode and standby test mode..................................................................................... ................... 72 8.3.1 unit test mode ......................................................................................................... ............................ 72 8.3.2 standby test mode ...................................................................................................... ........................ 72 appendix a list of instruction execution clock counts........................................... 73 appendix b index ............................................................................................................ .................... 85
11 list of figures figure no. title page 3-1 program status word (psw)................................................................................................... ..............27 3-2 memory map.................................................................................................................. ........................31 3-3 configuration of word data and double word data............................................................................. .32 3-4 i/o map ..................................................................................................................... .............................32 3-5 conceptual diagram of segment system........................................................................................ ......34 3-6 relationship between segment register, offset address and physical address .................................35 3-7 relationship between each segment register, segment and memory space .....................................36 3-8 dynamic relocation......................................................................................................... ......................38 3-9 memory address calculation................................................................................................. ................39 3-10 object code format ........................................................................................................ ......................41 4-1 interface between V30MZ and memory.......................................................................................... .......47 4-2 read timing of memory and i/o............................................................................................... .............50 4-3 write timing of memory and i/o.............................................................................................. ..............52 4-4 bus hold timing ............................................................................................................. .......................54 5-1 interrupt vector table configuration ........................................................................................ .............56 5-2 interrupt acknowledge cycle................................................................................................. ................59 6-1 timing to enter standby mode ................................................................................................ ..............65
12 list of tables table no. title page 2-1 relationship among operand and ubeb, a0, and bus cycles ............................................................ 19 2-2 relationship between bs3 to bs0 signal and bus cycle..................................................................... 20 3-1 address and data configuration of each memory element ................................................................. 31 3-2 segment registers and offset addressing..................................................................................... ...... 36 3-3 list of instruction sets by function........................................................................................ ............... 40 4-1 V30MZ data access ........................................................................................................... .................. 48 5-1 interrupt source list ....................................................................................................... ...................... 55 5-2 number of bus cycles required until interrupt is acknowledged......................................................... 62 7-1 status of output pins after reset ........................................................................................... .............. 69 7-2 initial value of registers after reset ...................................................................................... .............. 69 8-1 test mode selection list .................................................................................................... .................. 71 a-1 list of number of instruction execution clocks .............................................................................. ...... 74
13 chapter 1 general description the V30MZ is a cpu core that is an improved version of the v30mx, which itself enhances the bus efficiency of the m pd70116h (other name: v30hl), an original nec microprocessor. the V30MZ raises the bus efficiency by realizing 1 clock/bus cycle. the incorporation of an internal pipeline considerably raises the instruction execution time, enabling fast processing comparable to that of risc microprocessors. compared to the v30mx's 4.3 mips (33-mhz operation, no wait), the V30MZ realizes a processing performance of 35 mips (66-mhz operation, no wait). 1.1 features (1) processing performance: 35 mips (66-mhz operation, no wait) (2) cmos static design (internal system clock can be fully stopped) (3) 1 bus cycle: 1 clock (4) external bus interface ? address bus: 20 bits ? data bus: 16 bits (separate input/output buses) (5) bus hold function (6) standby function (halt mode) 1.2 symbol diagram ubeb bs (3:0) do (15:0) di (15:0) a (19:0) out hldak nmi int clk tbo (42:0) tbi (22:0) test bunri in in in out pollb reset buslockb out out out out in in in in in in in readyb in out dbnmim dbmode dbint dba20 out in in out dbrd dbwr out out dbhltst tbra out out tinta teoi out out tilen (3:0) out hldrq
chapter 1 general description 14 1.3 differences between V30MZ and v30hl, v30mx (1/3) item V30MZ v30hl v30mx address/data bus a19 to a0, di15 to di0, do15 to do0 a19 to a16, ad15 to ad0 a23 to a0, d15 to d0 large-scale mode/small-scale mode not provided provided not provided pin functions following pins of v30hl are removed note : astb, ps3 to ps0, bufen, qs1, qs0, bufr/w, rd, ic, rq/ak1, rq/ak0, intak, s/lg, lbs0, wr, nc m pd8080af emulation function not provided provided not provided connection to numerical operation co-processor not possible possible lim ems4.0 function not provided not provided provided test function as cbic core provided (tbi22 to tbi0, tbo42 to tbo0, bunri, test) not provided provided buslockb pin status in case of buslock instruction execution prior to halt instruction high-level output low-level output status of ubeb pin during interrupt acknowledge cycle high-level output low-level output status of output pins during bus hold see section 2.2. pin statuses high impedance relationship between buslock instruction and bus hold request bus hold request is acknowledged even if buslock instruction is executed immediately before an instruction that does not perform access to memory or i/o. the buslockb output remains high. buslock instruction effective for all instructions bus hold request acknowledged between first and second bus cycle w hen odd address word data is accessed not possible possible bus status output at recovery from bus hold status to standby mode no (remains in idle status) provided instruction execution time the number of instruction clocks for each instruction and the cpu operating frequency of the V30MZ have been improved, so that the instruction execution time is considerably reduced. note that programs that depend on the number of instruction execution clo cks, such as consecutive i/o accesses, may not function normally. interrupt response time the V30MZ performs pipeline processing internally, executing multiple instruction in parallel. therefore, in cases such as when a hardware interrupt synchronized with a given bus cycle is r equested, the V30MZ may acknowledge the interrupt request after performing a larger number of instructions than the v30hl and v30mx. however, this does not apply with regard to i/o accesses undefined flag change if an arithmetic operation defined as an indefinite flag change is executed, the contents of the flag immediately after the execution may differ from the v30hl and v30mx. this is especially likely to occur in the case of multiply and divide instruction. interrupt request acknowledge disable timing the timing at which interrupt requests are not acknowledged differs. (refer to section 5.3 timing at which interrupt is not acknowledged .) note the bs3 pin of the V30MZ has the same functions as the io/m pin of the v30hl, except for the output timing. remark active low pins are indicated with xxx (overscore added) in the case of the v30hl, whereas they are indicated with xxxb (b added) in the case of the V30MZ.
chapter 1 general description 15 (2/3) item V30MZ v30hl v30mx supported instructions the V30MZ does not support the following instructions supported by the v30hl and v30mx. an undefined result is obtained by executing these instructions. add4s, brkem, calln, clr1 note 1 , cmp4s, ext, fpo2, ins, not1 note 2 , repc, repnc, retem, rol4, ror4, set1 note 3 , sub4s, test1 moreover, the fpo1 instruction is handled as an nop instruction. number of instruction prefixes up to 7 instruction prefixes can be used (for all instructions). even if instruction prefixes are used redundantly, normal processing is performed as long as their total number doesn't exceed 7. if there are more than 7 prefixes for one instruction, the execution result of the instruction (to which prefixes have been attached) is not guaranteed. furthermore, normal recovery from interrupt processing is not possible. for repeat string instructions (rep, movbk, etc.), 3 types of prefixes max. can be used (rep is also counted as 1 type). if there are redundant instruction prefixes, repeat string instructions cannot be performed normally after the end of interrupt processing. in the case of instructions other than string instructions, the number of instruction prefixes is not limited. decimal correction instruction performs a correction operation for the second byte of cvtdb and dvtbd instructions. decimal correction operation is performed regardless of the value of the second byte of the cvtdb and cvtbd instructions. multiple bit shift and rotate instructions only the lower 5 bits of the number of shifts are valid. all 8 bits of the number of shifts (immediate, or specification by cl register) are valid. prepare instruction only the lower 5 bits of the second operand are valid. all 8 bits of the second operand are valid. pop r instruction executes memory read cycle 8 times. however, data corresponding to sp is not used. except for sp, 7 memory read cycles are performed. repeat prefixed cmpbk, cmpbkb, and cmpbkw instructions memory read is performed in the order ix ? iy memory read is performed in the order iy ? ix. call memptr32 instruction reads new pc, ps values after saving current pc, ps values to the stack. current pc and ps values are saved on to the stack after the new pc and ps values are read. when number of shifts = 0 for shift, and rotate instructions executes also write cycle of memory operand. z flag, p flag, and s flag change for shl, shr, and sara instructions. these flags are set/cleared depending on the execution result of shift instruction. if the operand is memory, only the read cycle is performed, and the write cycle of the shift result is not performed. for the shl, shr, and sara instructions, the z flag, p flag, and s flag do not change. these flags retain the status prior to instruction execution. notes 1. excluding clr1 cy and clr1 dir. 2. excluding not1 cy. 3. excluding set1 cy and set1 dir.
chapter 1 general description 16 (3/3) item V30MZ v30hl v30mx buslock instruction only valid for instruction performing memory or i/o access, and not valid for other instructions. moreover, during bus lock period, code fetch bus cycle is not performed. effective for all instructions. during execution of the instructions following the buslock instruction, the buslock output is low level, and during this period, bus hold requests are not accepted. moreover, during the bus lock period, a code fetch bus cycle may be performed.
17 chapter 2 pin functions 2.1 pin list pin input/output function a19 to a0 output address signal output di15 to di0 input data signal input do15 to do0 output data signal output ubeb output data bus upper byte enable signal output bs3 to bs0 output bus status signal output readyb input wait state generation signal input buslockb output bus lock signal output pollb input external system period sense si gnal input reset input system reset signal input hldrq input bus hold request signal input hldak output bus hold acknowledge signal output nmi input non-maskable interrupt request signal input int input maskable interrupt request signal input clk input system clock input bunri input pin for performing test using test bus test input tbi22 to tbi0 input tbo42 to tbo0 output dbint input reserved for nec dbmode output dba20 output dbrd output dbwr output dbnmim input dbhltst output teoi output tilen3 to tilen0 output tbra output tinta output
chapter 2 pin functions 18 2.2 pin statuses the status of each output pin in the different operation modes is listed in the table below. pin status normal mode test mode pin bus hold standby (halt) mode reset standby test mode unit test mode a19 to a0 hhhu ndefined undefined do15 to do0 undefined undefined undefined undefined undefined ubeb hhhu ndefined undefined bs3 to bs0 hhhu ndefined undefined buslockb hhhu ndefined undefined hldak h l l undefined undefined tbo42 to tbo0 hi-z hi-z hi-z hi-z operating remark h : high-level output l : low-level output hi-z : high impedance operating : outputs valid signal
chapter 2 pin functions 19 2.3 description of pin statuses 2.3.1 normal pins (1) a19 to a0 (address)...output bus for outputting 20-bit address. none of the pins ever go into high impedance. (2) di15 to di0 (data input)...input dedicated input bus for inputting 16-bit data. always input high-level or low-level signal (do not make signal high impedance). (3) do15 to do0 (data output)...output dedicated output bus for outputting 16-bit data. none of the pins ever go into high impedance. (4) ubeb (upper byte enable)...output outputs low-active signal indicating that higher 8 bits of 16-bit data bus are to be used with memory or i/o access cycle. this pin does not go into high impedance. the bus cycles for which this signal becomes active are as follows. ? bus cycle through byte access of odd address ? bus cycle through first byte access of odd address for word data ? bus cycle through access of even address for word data combined with the a0 signal, the bus cycle can be identified as follows. table 2-1. relationship among operand and ubeb, a0, and bus cycles operand ubeb pin output level a0 pin output level number of bus cycles even address word l l 1 1st bus cycle l h 2 odd address word 2nd bus cycle h l even address byte h l 1 odd address byte l h 1 remark l: low level h: high level (5) bs3 to bs0 (bus status)...output outputs status signal to external to notify state of the bus cycle. during reset and bus hold acknowledge, go into idle state (high-level output).
chapter 2 pin functions 20 this pin does not go into high-impedance. the bs3 pin has the same functions as the io/m pin of the v30hl, except for output timing (only names differ). table 2-2. relationship between bs3 to bs0 signal and bus cycle pin output level bs3 bs2 bs1 bs0 bus cycle (status) llllinterrupt acknowl edge l h l h i/o read l h h l i/o write hlllst andby (halt) mode h l l h memory data read h l h l memory data write h h l h code fetch hhhhidle status remarks 1. l: low level h: high level 2. no output with combinations other than above. (6) readyb (ready)...input performs wait control. when memory or i/o data read/write operation cannot be completed within the basic bus cycle (1 clock), the bus cycle can be extended by inputting an inactive level (high level) to this pin. (7) buslockb (bus lock)...output it outputs a low-active signal to other bus masters requesting that they do not use the system bus during execution of 1 instruction following the buslock instruction. it also outputs the signal during interrupt acknowledge. it does not go into high impedance. (8) pollb (poll)...input it is used to synchronize between program execution by the V30MZ and operation of an external device. input to this pin are checked by the poll instruction: if a low level is input, the next instruction is processed; if a high level is input, program execution is halted until this pin is driven low. input of a low level to this pin should be done for at least 9 clocks. (9) reset (reset)...input inputs a reset signal. following reset release, the V30MZ starts program execution from memory address ffff0h (segment value: ffffh, offset value: 0000h). (10) hldrq (hold request)...input inputs a signal to the V30MZ to request that the external bus master release the address bus, data bus, and control bus (bus hold). inputting a high level to this pin causes the bus hold acknowledge status to be entered upon completion of the currently executing bus cycle, and while the high level is input, the bus hold acknowledge status continues. input a high level for at least 3 clock cycles.
chapter 2 pin functions 21 (11) hldak (hold acknowledge)...output outputs a signal indicating that the hldrq signal has been acknowledged and that the bus hold acknowledge status is entered. (12) nmi (non-maskable interrupt)...input inputs a non-maskable interrupt signal by software. the nmi signal is active at the rising edge and detected in any clock cycle, however, it starts interrupt servicing after the end of the instruction being executed. the interrupt start address for this interrupt is determined by interrupt vector 2. input an active level (high level) for at least 5 cycles after a rising edge. when inputting nmi requests consecutively, keep nmi low for at least one clock cycle. the priority order of interrupt request signals is as follows. int < nmi < hldrq remark the standby mode can also be released by an nmi signal. (13) int (interrupt request)...input inputs an interrupt request signal that can be masked by software. input an active level (high level) to this until the interrupt acknowledge status is output from the bs3-bs0 pins. (14) clk (clock)...input inputs a clock signal. input to this clk pin and internal operation of the V30MZ are performed at the same frequency. when the clk input is stopped, the supply current enters 0a.
chapter 2 pin functions 22 2.3.2 test pins (1) tbi22 to tbi0 (test bus input)...input input test bus pin. (2) tbo42 to tbo0 (test bus output)...output output test bus pin. (3) test (test bus control)...input test bus control input pin. (4) bunri (test bus control)...input input pin for selecting normal mode/test mode. remark for details on the functions of each pin, see chapter 8 test functions . 2.3.3 reserved pins the following each pin is reserved for nec. according to section 2.4 handling of unused pins , connect each pin. ? dbint ? dbmode ? dba20 ? dbrd ? dbwr ? dbnmim ? dbhltst ? teoi ? tilen3 to tilen0 ? tbra ? tinta
chapter 2 pin functions 23 2.4 handling of unused pins pin input/output recommended handling a19 to a0 output leave open. do15 to do0 output ubeb output bs3 to bs0 output readyb input input low level. buslockb output leave open. pollb input input low level. hldrq input hldak output leave open. nmi input input low level. int input dbint input dbmode output leave open. dba20 output dbrd output dbwr output dbnmim input input low level. dbhltst output leave open. teoi output tilen3 to tilen0 output tbra output tinta output
24 [memo]
25 chapter 3 cpu functions 3.1 register configuration 3.1.1 general-purpose registers (aw, bw, cw, dw) there are four 16-bit registers. these can be not only used as 16-bit registers, but also accessed as 8-bit registers (ah, al, bh, bl, ch, cl, dh, dl) by dividing each register into the higher 8 bits and the lower 8 bits. therefore, these registers are used as 8-bit registers or 16-bit registers for a wide range of instructions such as transfer instruction, arithmetic operation instruction, logical operation instruction. furthermore, the following registers are used as the default registers for specific instruction processing. ? aw : word multiplication/division, word input/output, data conversion ? al : byte multiplication/division, byte input/output, bcd rotate, data conversion ? ah : byte multiplication/division ? bw : data conversion (table reference) ? cw : loop control branch, repeat, and prefix ? cl : shift instruction, rotation instruction ? dw : word multiplication/division, indirect addressing input/output 3.1.2 segment registers (ps, ss, ds0, ds1) the V30MZ can divide the memory space into logical segments in 64 k-byte units and control up to 4 segments simultaneously (segment system). the start address of each segment is specified by the following 4 segment registers. ? program segment register (ps) : specifies the base address of the segment that stores instructions. ? stack segment register (ss) : specifies the base address of the segment that performs stack operations. ? data segment 0 register (ds0) : specifies the base address of the segment that stores data. ? data segment 1 register (ds1) : specifies the base address of the segment that is used as a data destination by data transfer instructions. for details of the segment system and segment registers, refer to section 3.4 logical address and physical address . 3.1.3 pointer (sp, bp) the pointer consists of two 16-bit registers (stack pointer (sp) and base pointer (bp)). each register is used as a pointer to specify a memory address and can be referenced in an instruction and is also used as an index register during a memory data reference. the sp indicates the address in the stack segment at which the latest data is stored and is used as the default register during stack operation. the bp is used to fetch the data stored on the stack.
chapter 3 cpu functions 26 3.1.4 program counter (pc) the pc is a 16-bit binary counter that holds the offset information of the memory address of the program that the execution unit (exu) is about to execute. the pc value is automatically incremented (+1) every time the microprogram fetches an instruction code from an instruction queue. furthermore, in execution of a branch instruction with branch or condition, subroutine control instruction, and interrupt instruction, a new location is loaded and the pc value becomes the same as that of the prefetch pointer (pfp). 3.1.5 program status word (psw) the psw consists of 6 kinds of status flag and 4 kinds of control flag. (1) status flag ? overflow flag (v) ? sign flag (s) ? zero flag (z) ? auxiliary carry flag (ac) ? parity flag (p) ? carry flag (cy) (2) control flag ? mode flag (md) ? direction flag (dir) ? interrupt enable flag (ie) ? break flag (brk) the status flag is automatically set (1) and cleared (0) according to the execution result (data value) of each instruction. the cy flag can directly be set/ cleared or inverted by an instruction. the control flag is set/cleared by an instruction and controls the operation of the V30MZ. the ie flag and brk flag are cleared (0) when interrupt servicing is started. reset input clears (0) all flags (except md flag). the psw is manipulated in byte units or word units by the processing shown below. processing in byte units is only carried out on the lower 8 bits (including the status flags except the v flag).
chapter 3 cpu functions 27 figure 3-1. program status word (psw) md 1 v ie s 0 0 1 1 1 dir brk z ac p cy 15131197531 14121086420 bits 7 to 0 can be stored or restored in ah by a mov instruction. all bits of the psw are saved to the stack when an interrupt is generated or in execution of a call instruction (call) and restored by a return instruction (ret, reti). the psw can be saved or restored to the stack independently by a push psw instruction or pop psw instruction. the flags are set to the states shown below after execution of each instruction. (a) carry flag (cy) <1> binary addition/subtraction in the case of processing in byte units, cy is set when there is a carry or borrow from operation result bit 7, and cleared otherwise. in the case of word operation, cy is set when there is a carry or borrow from operation result bit 15, and cleared otherwise. it is not changed by an increment or decrement instruction. <2> logical operation cy is cleared without regard to the operation result. <3> binary multiplication cy is cleared if ah is other than 0 as a result of an unsigned byte operation. cy is cleared if ah is al sign extension as a result of a signed byte operation and set otherwise. cy is cleared if dw is 0 as a result of an unsigned word operation and set otherwise. cy is cleared if dw is aw sign extension as a result of an unsigned word operation and set otherwise. in the case of an 8-bit immediate operation, cy is cleared when the product is within 16 bits and set otherwise. <4> binary division undefined. <5> shift/rotate in the case of a shift or rotate including the cy flag, cy is set when the bit shifted to the cy flag is 1 and cleared if 0. (b) parity flag (p) <1> binary addition/subtraction, logical operation, shift set when the number of 1 bits of the lower 8 bits of the operation result is even and cleared when it is odd. set when the result is all 0.
chapter 3 cpu functions 28 <2> binary multiplication/subtraction undefined. (c) auxiliary carry flag (ac) <1> binary addition/subtraction in the case of processing in byte units, it is set when there is a carry from the lower 4 bits to the higher 4 bits or a borrow from the higher 4 bits to the lower 4 bits, and cleared otherwise. in a word operation, it performs the same operation as for a byte operation with respect to the lower bytes. <2> logical operation, binary multiplication/division, shift/rotate undefined. (d) zero flag (z) <1> binary addition/subtraction, logical operation, shift/rotate it is set when the 8 bits and 16 bits of the result are all 0 for a byte operation and word operation, respectively, and cleared otherwise. <2> binary multiplication/division undefined. (e) sign flag (s) <1> binary addition/subtraction, logical operation, shift/rotate set when bit 7 of the result is 1 and cleared when it is 0 in the case of a byte operation. set when bit 15 of the result is 1 and cleared when it is 0 in the case of a word operation. <2> binary multiplication/division undefined. (f) overflow flag (v) <1> binary addition/subtraction set when carries from bit 7 and bit 6 are different and cleared when they are the same in the case of a byte operation. set when carries from bit 15 and bit 14 are different and cleared when they are the same in the case of a word operation. <2> binary multiplication as a result of an unsigned byte operation, cleared if ah is 0 and set otherwise. as a result of a signed byte operation, cleared if ah is sign extension of al and set otherwise. as a result of an unsigned word operation, cleared if dw is 0 and set otherwise. as a result of a signed word operation, cleared if dw is sign extension of aw and set otherwise. in the case of an 8-bit immediate operation, cleared if the product is within 16 bits and set if the product exceeds 16 bits.
chapter 3 cpu functions 29 <3> binary division cleared. <4> logical operation cleared. < 5 > shift/rotate in the case of a left 1-bit shift/rotate, the status of the overflow flag is as follows depending on the operation result. ? when cy = msb: cleared ? when cy 1 msb: set in the case of a right 1-bit shift/rotate, its status is as follows depending on the operation result. ? when msb = next lower bit of msb: cleared ? when msb 1 next lower bit of msb: set in the case of a multi-bit shift/rotate, it is undefined. (g) break flag (brk) only when it is saved to the stack as part of the psw, it can be set by a memory manipulation instruction, and becomes valid when restored to the psw after it is set. if the brk flag is set, executing one instruction automatically generates a software interrupt (interrupt vector 1) allowing tracing of one instruction at a time. (h) interrupt enable flag (ie) ie is set by an ei instruction and the maskable interrupt (int) is enabled. it is cleared by a di instruction and the maskable interrupt (int) is disabled. (i) direction flag (dir) when the dir flag is set, processing is carried out from the higher addresses to the lower addresses in block transfer and/or i/o system instructions. when it is cleared, processing is carried out from the lower addresses to the higher addresses. (j) mode flag (md) this is a m pd8080af emulation function related flag that conforms to the previous v30hl. since the V30MZ is not provided with the emulation function, this flag is invalid.
chapter 3 cpu functions 30 3.1.6 index register (ix, iy) this consists of two 16-bit registers (ix, iy). in a memory data reference, it is used as an index register to generate effective addresses (each register can also be referenced in an instruction). furthermore, in specific instruction processing, it has the following special roles. ix: address register for source operand in block data manipulation instruction address register for source operand in bcd string operation instruction iy: address register for destination operand in block data manipulation address register for destination operand in bcd string operation instruction
chapter 3 cpu functions 31 3.2 address space 3.2.1 memory space the V30MZ uses 20-bit address information and can access 1 m bytes (512 k words) of memory. figure 3-2 shows the memory map. the 1 k byte from 00000h to 003ffh is allocated to the interrupt vector table. however, the table area that is not used by the system can be used for other purposes. the start address after a reset is ffff0h. the 12 bytes from ffff0h to ffffbh are automatically used for a reset start, etc., and cannot be used for other purposes. the 4 bytes from ffffch to fffffh are also reserved for future use and are not available for users. figure 3-2. memory map reserved area fffffh ffffch ffffbh ffff0h area for general use fffefh 00400h interrupt vector table 003ffh 00000h refer to figure 5-1. interrupt vector table configuration dedicated area the elements stored in the memory area include operation codes, interrupt start addresses, stack data, general variables, and consist of two kinds; byte units and word units. addresses generated by an instruction for these elements can be even (a0 = 0) or odd (a0 = 1). word data in the V30MZ is designed to be accessible for both even and odd addresses. both even and odd addresses are possible for generation of an instruction. for the access method, refer to section 4.1 interface between V30MZ and memory . table 3-1 shows the address and data configuration of each memory element. table 3-1. address and data configuration of each memory element memory element address data configuration operation code even/odd 1 to 6 bytes interrupt vector table even 2 words/vector stack even/odd word general variable even/odd byte/word/double word
chapter 3 cpu functions 32 the word data configuration and double word data configuration are as follows. figure 3-3. configuration of word data and double word data (a) word data configuration (b) double word data configuration higher byte lower byte higher address lower address higher byte lower byte higher address lower address higher byte lower byte higher word lower word 3.2.2 i/o space the V30MZ can access an i/o space of up to 64 k bytes (32 k words) in an area independent of the memory space. the i/o space is addressed by i/o address information output from the lower 16 bits of the address bus. figure 3- 4 shows the i/o map. the 256 bytes of ff00h to ffffh are reserved for future use and are not available for users. for the access method, refer to section 4.2 interface between V30MZ and i/o . figure 3-4. i/o map reserved ffffh ff00h feffh 0000h
chapter 3 cpu functions 33 3.3 instruction prefetch the V30MZ performs pipeline processing internally, performing instruction fetch (prefetch), instruction decode, and instruction execution in parallel. for this reason, it is difficult to determine what part of the program is currently being executed by monitoring the output of the address bus for the instruction code fetch. if there are conditional branch instructions, even in case branching does not occur, the address of the branch destination is prefetched (only one time), so that further monitoring of the program is difficult. the V30MZ has 8 prefetch queues (16 bytes).
chapter 3 cpu functions 34 3.4 logical address and physical address there are two kinds of memory space address; logical address and physical address. the physical address means an address that directly corresponds to hardware. the V30MZ can access a 1 m- byte memory space and so the range of a physical address value is 00000h to fffffh. a physical address is generated every time the bus control unit (bcu) is started which fetches an instruction and transfers data, etc. the logical address means an address used for addressing in the segment system. 3.4.1 segment system the segment means an address space in small units (max. 64 k bytes) which do not directly depend on program creation. each segment consists of continuous memory and can be specified individually. physical addresses cannot be controlled directly in program creation in machine language. the V30MZ specifies memory addresses in a segment system. addressing in the segment system uses the following two types of address. ? segment base address : start address of segment (address in 1 m-byte memory space) ? offset address : address allocated to each segment in the segment system, the segment base address is fixed as a reference point and only the offset address is treated as an address in processing within each segment. figure 3-5. conceptual diagram of segment system fffffh 00000h xxxxxh segment ffffh 0000h (maximum) offset address segment base address memory space the segment base address is specified by the segment register. the physical address is a sum of the segment base address and offset address. figure 3-6 shows the relationship between the segment register and offset address, and physical address.
chapter 3 cpu functions 35 figure 3-6. relationship between segment register, offset address and physical address 0 0 segment register (16 bits) 0 31 420 19 0 0 15 offset address (16 bits) 0 19 physical address (20 bits) + as shown in figure 3-6, the physical address is a sum of 16 times the segment register content (4 bits shifted to left) and offset value. at this time, the segment register content and offset value are treated as unsigned data. in a program which is created as a set of multiple segments for which allocation addresses are specified by physical addresses, each segment is compiled and assembled individually and becomes one or a number of object modules. each object module has a segment name, size, content classification, control information, etc., and becomes a parameter in execution of link processing. multiple object modules are linked and the segment base addresses corresponding the physical addresses are specified and become ready to be loaded to actual memory. 3.4.2 segment configuration the V30MZ can distinguish 4 kinds of segment (program, stack, data 0, data 1) and define them. for each segment the start address is specified by one of the following 4 segment registers. the bcu uses different segment registers for generation of physical addresses depending on the type of memory bus cycle. ? program segment register (ps) ? stack segment register (ss) ? data segment 0 register (ds0) ? data segment 1 register (ds1) the offset address within each segment is specified by a specific register or effective address. table 3-2 shows correspondence between each segment register and offset addressing.
chapter 3 cpu functions 36 table 3-2. segment registers and offset addressing segment register offset default override pfp ps disabled sp ss disabled effective address (bp base) ps, ds0, ds1 effective address (non-bp base) ds0 ps, ss, ds1 ix in instruction group a (primitive block transfer instruction, primitive output instruction, bcd string instruction) iy in instruction group b (primitive block transfer instruction, primitive input instruction, bcd string instruction) ds1 disabled when the default offset is a prefetch pointer (pfp), stack pointer (sp) and index register (iy) in instruction group b, the segment registers that can be combined are fixed at ps, ss, and ds1 respectively, and other segment registers cannot be used. for other default offsets, any segment registers other than the default segment register can be specified by the segment override prefix. figure 3-7 shows the relationship between each segment register, segment and memory space. figure 3-7. relationship between each segment register, segment and memory space fffffh 00000h memory space program segment ffffh 0000h stack segment ffffh 0000h data segment 0 ffffh 0000h data segment 1 ffffh 0000h ps ss ds0 ds1 V30MZ each segment has the following meaning.
chapter 3 cpu functions 37 (1) program segment the start address of this segment is determined by the program segment register (ps) and the offset from the start address is specified by the prefetch pointer (pfp). in this segment, an operation code, table data, etc., are placed. by using the segment override prefix (ps:), the program segment can be used as the general variable area and source data area in execution of instruction group a. (2) stack segment the start address of this segment is determined by the stack segment register (ss) and the offset from the start address is specified by the effective address when the stack pointer (sp) and base pointer (bp) as the base address are used. this is used as an area to save the contents of the return address (ps, pc content), program status word (psw), general register, etc., as a parameter transfer area and local variable area. by using the segment override prefix (ss:), the stack segment can be used as a general variable area and source data area in execution of instruction group a. (3) data segment 0 the start address of this segment is determined by the data segment 0 register (ds0) and the offset from the start address is specified by the effective address when bp is not used as a base address. this segment is used as an area to store general variables. when executing instruction group a, it is used as a source data area. however, in this case, the content of the index register (ix) becomes the offset. for the effective address when bp is used as the base address, the stack segment is used as the default, but data segment 0 can be used if the segment override prefix (ds0:) is used. (4) data segment 1 the start address of this segment is determined by the data segment 1 register (ds1). this can be used as a destination data area when executing instruction group b. in this case, the content of the index register (iy) becomes the offset. if the segment override prefix (ds1:) is used, data segment 1 can be used as a general variable area or source data area in execution of instruction group a. 3.4.3 dynamic relocation relocating programs that are stored in two or more files separately in empty memory spaces for each execution is called dynamic relocation. figure 3-8 shows a conceptual diagram of dynamic relocation. for the V30MZ, memory addressing of a program can be determined only with the offset value for the base address of each segment (specified by each segment register). therefore, it is possible to allocate the program in an arbitrary memory space by only adjusting to the physical address of the memory at which it is to be allocated (however, this is only possible if the base address of each segment is not changed in the program). this increases the degree of freedom of program allocation in the memory (addressing is possible in 16-byte units), enabling more effective utilization of memory and making it easier to implement a system that executes multiple jobs and tasks. this can be applied to executing a program in a file on an external storage medium such as a floppy disk and hard disk with the os controlling the memory allocation area, type, and segment registers, and loading the program in any empty memory area.
chapter 3 cpu functions 38 figure 3-8. dynamic relocation (a) before relocation (b) after relocation fffffh 00000h memory space program segment stack segment data segment 0 data segment 1 ps ss ds0 ds1 V30MZ fffffh 00000h memory space program segment stack segment data segment 0 data segment 1 ps ss ds0 ds1 V30MZ
chapter 3 cpu functions 39 3.5 effective address the effective address (ea) is an unsigned 16-bit number and is the memory address to be processed by an instruction represented by the offset value for the base address of the corresponding segment. this is calculated by the execution unit (exu) according to the specification of an instruction operand. the exu calculates ea in several different methods (addressing mode). the method is selected by the 2nd byte operand of the instruction. the information encoded in the 2nd byte of the instruction indicates how the effective address of the memory indicated by the operand is calculated by the exu. this operand code is automatically generated by a compiler or assembler from a program statement or instruction description. all addressing modes are available in assembly language (refer to section 3.7 addressing mode ). the method of calculation of ea is shown below. figure 3-9 indicates that the exu calculates ea by adding the displacement, base register contents, and index register contents. for any instruction, these three elements can be combined arbitrarily. the displacement is an 8-bit or 16-bit immediate number indicated by an operand. figure 3-9. memory address calculation 00 00 ps or 00 00 ss 00 00 ds0 or 00 00 ds1 or displacement (16 bits) iy or ix or bp or bw physical address (20 bits) bp or bw iy or ix effective address encoded in instruction determined by instruction uniformity determined unless it is denied by segment override prefix
chapter 3 cpu functions 40 3.6 instruction set 3.6.1 list of instruction sets by function the V30MZ instruction sets by function are generally classified as follows: table 3-3. list of instruction sets by function instruction group mnemonic data transfer instruction ldea, mov, trans, transb, xch repeat prefix rep, repe, repne, repnz, repz primitive block transfer instruction cmpbk, cmpbkb, cmpbkw, cmpm, cmpmb, cmpmw, ldm, ldmb, ldmw, movbk, movbkb, movbkw, stm, stmb, stmw input/output instruction in, out primitive input/output instruction inm, outm addition/subtraction instruction add, addc, sub, subc increment/decrement instruction dec, inc multiplication instruction mul, mulu division instruction div, divu bcd adjustment instruction adj4a, adj4s, adjba, adjbs data conversion instruction cvtbd, cvtbw, cvtdb, cvtwl comparison instruction cmp complement operation instruction neg, not logical operation instruction and, or, test, xor bit manipulation instruction clr1 cy,clr1 dir, set1 cy, set1 dir, not1 cy shift instruction shl, shr, shra rotate instruction rol, rolc, ror, rorc subroutine control instruction call, ret stack manipulation instruction dispose, pop, prepare, push branch instruction br conditional branch instruction bc, bcwz, be, bge, bgt, bh, bl, ble, blt, bn, bnc, bne, bnh, bnl, bnv, bnz, bp, bpe, bpo, bz, bv, dbnz, dbnze, dbnzne interrupt instruction brk, brkv, chkind, reti cpu control instruction buslock, di, ei, fpo1 note , halt, nop, poll segment override prefix ds0:, ds1:, ps:, ss: note treated as a nop instruction. remarks 1. the following instructions are not supported among the instructions that v30hl supports. executing these instructions causes undefined. add4s, brkem, calln, clr1 (except clr1 cy, clr1 dir), cmp4s, ext, fpo2, ins, not1 (except not1 cy), repc, repnc, retem, rol4, ror4, set1 (except set1 cy, set1 dir), sub4s, test1 2. for details of each instruction, refer to the 16-bit v series instruction users manual .
chapter 3 cpu functions 41 3.6.2 format of object code object codes are basically indicated by the following format. figure 3-10. object code format op-code operand remark op-code : 8-bit code indicating type of instruction operand : field indicating register, memory address to be processed by instruction. indicated by field of 0 to 5 bytes
chapter 3 cpu functions 42 3.7 addressing mode 3.7.1 instruction address the instruction address refers to the address at which an operation code is read and, normally it is automatically incremented every time an operation code is read. however, in an instruction that controls the instruction execution sequence such as a jump instruction, subroutine call instruction, the branch destination instruction address is specified by an operand. (1) direct addressing the 4-byte data in an operation code becomes an instruction address and is loaded into the ps and pc registers. this mode is used by the following instructions. call far_proc br far_label (2) pc relative addressing the 1-byte or 2-byte data in an operation code becomes a displacement from the start address (pc value) of the next instruction and is added to the pc. this mode is used by the following instructions. call near_proc br near_label br short_label bcondition short_label ; example bz short_label bnc short_label (3) register indirect addressing the content of any 16-bit register specified by the register specification field in an operation code becomes the instruction address and is loaded into the pc. this mode is used by the following instructions. call regptr16 ; example call aw br regptr16 ; example br ix (4) memory indirect addressing the 2-byte or 4-byte data in memory specified by the memory addressing (refer to section 3.7.2 data address ) indicated by the addressing mode specification field in an operation code becomes the instruction address and is directly loaded into the pc or both ps and pc. this mode is used by the following instructions. call memptr16 ; example call word_var [bw] call memptr32 ; example call dword_var [bw+ix] br memptr16 ; example br word_var [br+2] br memptr32 ; example br dword_var [bp+iy]
chapter 3 cpu functions 43 3.7.2 data address the data address is an address for reading/writing the operand data of each instruction. normally, an address is a concept used for memory or i/o, but this operand address includes data in registers, immediate data and i/o data. (1) non-memory addressing non-memory addressing specifies data in registers, immediate data and i/o data. (a) register addressing specifies the register from/to which the register specification field in an operation code reads/writes the operand data. the register addressing is shown in the following description. general description register that can be described reg, reg' aw, bw, cw, dw, sp, bp, ix, iy, al, ah, bl, bh, cl, ch, dl, dh reg8, reg8' al, ah, bl, bh, cl, ch, dl, dh reg16, reg16' aw, bw, cw, dw, sp, bp, ix, iy sreg ps, ss, ds0, ds1 acc aw, al example of usage: reg16 : mov aw, ix ; aw ? ix reg8 : add al, ch ; al ? al + ch (b) immediate addressing 1-byte or 2-byte data in an operation code becomes read-only operand data. immediate addressing cannot be used for the destination operand of an instruction. immediate addressing is shown in the following description. general description value that can be described imm8 0 to ffh (0 to 255 or - 128 to +127) imm16 0 to ffffh (0 to 65535 or - 32768 to +32767) imm 0 to ffffh (0 to 65535 or - 32768 to +32767) pop_value 0 to ffffh (0 to 65535) normally even example of usage: imm16 : mov aw, 216 ; aw ? 216 imm8 : shl al, 5 ; shifts al to left by 5 bits. pop_value : ret 16 ; deletes unnecessary 16 bytes on stack. (c) i/o addressing i/o addressing specifies data in a 64-k byte i/o space. there are two kinds of specification method in i/o addressing as shown below, and these are used by an input/ output instruction.
chapter 3 cpu functions 44 <1> imm8 8-bit data in an operation code specifies the i/o address. in this method, specification is limited to a 256-byte space on the lower side of the 64-k byte i/o space. this specification method is used by the following two instructions. in acc, imm8 out imm8, acc <2> dw the content of dw indicates the i/o address. this method can be used to specify across the entire 64-k byte i/o space. this specification method is used by the following four instructions. in acc, dw inm dst_block, dw out dw, acc outm dw, src_block (2) memory addressing memory addressing specifies the operand data in memory. this memory addressing is further divided into several modes by the 5-bit memory addressing specification field placed after an op-code. in all memory addressing modes, a 16-bit offset address from the segment base specified by the default or segment override is specified. memory addressing is shown in the following description. description data length dme m note 8/16-bit data mem 8/16-bit data mem8 8-bit data mem16 16-bit data note description in an instruction that has no memory addressing specification field (a) direct addressing indicates the memory address at which 2-byte data in an operation code is the read/write target of operand data. example of usage: mov byte_var, 216 ; bytemem (offset (byte_var)) ? 216 (b) register indirect addressing indicates the memory address at which the 16-bit register (bw or ix or iy) specified by the memory addressing specification field in an operation code is the read/write target of operand data. example of usage: mov word ptr [bw], 10 ; wordmem (bw) ? 10 add al, byte ptr [ix] ; al ? al + bytemem (ix)
chapter 3 cpu functions 45 (c) based addressing indicates the memory address at which the value of the 16-bit base register (bw or bp) specified by the memory addressing specification field in an operation code added to a sign extended displacement value indicated by 1-byte or 2-byte data in an operation code is the read/write target of operand data. when bp is selected as the base register, the default segment register becomes ss, and it can be used when the data pushed to the stack as an argument in procedure calling is accessed from the procedure. example of usage: mov word_var [bw+2], aw ; wordmem (offset (word_var)+bw+2) ? aw sub aw, [bp+6] ; aw ? aw C wordmem (bp+6) (d) indexed addressing indicates the memory address at which the value of the 16-bit indexed register (ix or iy) specified by the memory addressing specification field in an operation code added to a sign extended displacement value indicated by 1-byte or 2-byte data in an operation code is the read/write target of operand data. example of usage: mov word_var [iy+2], 0 ; wordmem (offset (word_var)+iy+2) ? 0 sub aw, [ix+6] ; aw ? aw C wordmem (ix+6) (e) addressing with based index indicates the memory address at which the value of the 16-bit base register (bw or bp) specified by the memory addressing specification field in an operation code added to a sign extended displacement indicated by 1-byte or 2-byte data in an operation code plus the value of the 16-bit index register (ix or iy) is the read/write target of operand data. that is, it performs addressing similar to a combination of based addressing and indexed addressing. this addressing can be used to access data that has a 2-dimensional array structure, etc. example of usage: mov word_var [bw+6] [iy+2],0 ; wordmem (offset (word_var)+bw+6+iy+2) ? 0 sub aw, [bp+6+ix] ; aw ? aw C wordmem (bp+ix+6)
46 [memo]
47 chapter 4 bus control functions the V30MZ executes 1 bus cycle in 1 clock. since accessing memory integrated on the same chip is possible in just 1 clock, it is possible to configure systems that take advantage of both small-capacity, high-speed on-chip memory and large-capacity, low-cost external memory by combining a wait insertion function. 4.1 interface between V30MZ and memory as the V30MZ uses a 16-bit data bus, it is capable of transferring 16-bit word data in 1 bus cycle. however, this applies only when an address generated by an instruction is even (a0 = 0), and if it is odd (a0 = 1) a word data transfer requires 2 bus cycles. figure 4-1 shows the interface between the V30MZ and memory. figure 4-1. interface between V30MZ and memory a19 to a1 V30MZ a0 ubeb di15 to di0 do15 to do0 memory upper bank (512 k bytes) csb memory lower bank (512 k bytes) di15 to di8 address bus (19) do15 to do8 di7 to di0 do7 to do0 8 8 8 8 data input bus (16) data output bus (16) csb in figure 4-1, a0, when active low, enables the lower bank byte data of memory. furthermore, aside from the information from the address bus, the ubeb signal is output and when active low this also enables the byte data of the memory higher bank. (1) when accessing word data at odd address in the first bus cycle, ubeb = 0 and a0 = 1, and only the higher byte is accessed and then ubeb = 1 is automatically set, the lower 16 bits (a15 to a0) of the address information is incremented (+1). that is, a0 = 0 is set, and the lower byte at the next address is accessed.
chapter 4 bus control functions 48 (2) when accessing word data at even address word data is accessed in 1-bus cycle with ubeb = 0 and a0 = 0. table 4-1 shows the relationship between the type of operand and the number of ubeb, a0 pins, and bus cycles. table 4-1. V30MZ data access operand ubeb pin output level a0 pin output level number of bus cycles word at even address l l 1 word at odd address 1st bus cycle l h 2 2nd bus cycle h l byte at even address h l 1 byte at odd address l h 1 remark l : low level h : high level normally, the V30MZ performs an access (prefetch) of an operation code in word units. however, when a branch to an odd address takes place, only 1 byte at that odd address is fetched and subsequent bytes are fetched again in word units again. when a vector table address is generated from the vector number (0 to 225), an even address is always generated, and so an access to the interrupt vector table is always performed as word data at an even address. therefore, a vector table access to one interrupt is always performed in 2 bus cycles for the 2 words of the segment base and offset. 4.1.1 cautions on accessing word data when accessing word data by the V30MZ, ensure that all the data that can be checked by the program may be placed at an even address. when it is placed at an odd address, the result will be as follows. one bus cycle for a memory access requires 1 clock. therefore, every time word data at an odd address is accessed, one extra clock of the instruction execution time are required compared to accessing word data at an even address. this applies when executing an instruction that has more than one word data access. in the case of a word data transfer from memory to memory, 2 memory accesses are required for a read from the source and a write to the destination and so the execution time becomes the maximum when both are odd addresses. this problem of odd addresses also happens in stack manipulation. registers, etc. are automatically saved to the stack by interrupt servicing, but these are all word data and so when processed at an odd address, note that the number of bus cycles is doubled and the interrupt response time is delayed. example: number of execution clocks of mov reg, mem instruction byte data : 1 word data : 2 (for odd address) : 1 (for even address) this is an example in which one word data access is performed.
chapter 4 bus control functions 49 4.2 interface between V30MZ and i/o the segment system is not applied to an i/o address like memory. in i/o address output timing, 0 is output to all the higher 4 bits (a19 to a16) of the address bus. data can be transferred between the V30MZ and i/o in either byte units or word units and both an 8-bit i/o device and 16-bit i/o device can be connected. however, like memory for a word data access, 1 bus cycle for an even address and 2 bus cycles for an odd address are used. when accessing an 8-bit i/o device, a0 of the i/o address information is only used for device selection and values higher than a1 are used for device selection and selection of several registers within one device. that is, all the internal registers of the i/o device at an even address are also even and all the internal registers of the i/o device at an odd address are selected with an odd number. use of a memory mapped i/o configuration (using the memory area by allocating it for i/o) allows the i/o to be placed in a 1 m-byte memory space not in the i/o space. using the memory mapped i/o configuration, it is possible to perform a variety of addressing modes and operation processing for the memory directly to the i/o device. caution however, with the memory mapped i/o, all control signals output from the V30MZ are for the memory and so the i/o device is distinguished only by address information. therefore, special care is required to avoid contention between the addresses of variables and static data, etc., and the addresses allocated to the i/o.
chapter 4 bus control functions 50 4.3 read/write timing of memory and i/o the V30MZ executes one bus cycle in at least 1 clock. 4.3.1 read timing of memory and i/o the V30MZ outputs the addresses (a19 to a0), ubeb signal, and bus status (bs3 to bs0) in synchronization with the rising edge of the clock (clk). data (di15 to di0) is read at the rising edge of the next clk signal, and the readyb signal is sampled at the same time. if the readyb signal is low at this time, the operation goes to the next bus cycle, and if the readyb signal is high, the operation goes to the wait cycle (tw), and the current bus cycle is extended. in the tw state, the a19 to a0 signals and the ubeb signal maintain their output value, but the bs3 to bs0 signals become high level. figure 4-2. read timing of memory and i/o (1/2) (a) with no wait clk (input) a19 to a0 (output) ubeb (output) bs3 (output) di15 to di0 (input) readyb (input) t x don't care don't care bs2 (output) bs1 (output) bs0 (output) h during memory read: h during i/o read: l during memory read: l during i/o read: h remark { indicates the sampling timing.
chapter 4 bus control functions 51 figure 4-2. read timing of memory and i/o (2/2) (b) with 1 wait clk (input) a19 to a0 (output) ubeb (output) bs3 (output) di15 to di0 (input) t x tw don't care don't care don't care bs2 (output) bs1 (output) bs0 (output) during memory read: h during i/o read: l during memory read: l during i/o read: h h readyb (input) remark { indicates the sampling timing.
chapter 4 bus control functions 52 4.3.2 write timing of memory and i/o the V30MZ outputs the address (a19 to a0), ubeb signal, bus status (bs3 to bs0), and data (do15 to do0) in synchronization with the rising edge of the clock (clk). then at the next rising edge of the clk signal, it samples the readyb signal. if the readyb signal is low at this time, the operation goes to the next bus cycle, and if the readyb signal is high, the operation goes to the wait cycle (tw), and the current bus cycle is extended. in the tw state, invalid data is output from the do15 to do0 pins. therefore, if a tw state is inserted to extend the bus cycle, latch the data from the do15 to do0 pins output at the first bus cycle using an external circuit. moreover, in the tw state, the a19 to a0 signals and the ubeb signal maintain their output value, but the bs3 to bs0 signals become high level. figure 4-3. write timing of memory and i/o (1/2) (a) with no wait clk (input) bs3 (output) do15 to do0 (output) readyb (input) t x don't care don't care bs2 (output) bs1 (output) bs0 (output) h during memory write: h during i/o write: l during memory write: l during i/o write: h a19 to a0 (output) ubeb (output) remark { indicates the sampling timing.
chapter 4 bus control functions 53 figure 4-3. write timing of memory and i/o (2/2) (b) with 1 wait clk (input) a19 to a0 (output) ubeb (output) bs3 (output) do15 to do0 (output) readyb (input) t x tw valid invalid don't care don't care don't care bs2 (output) bs1 (output) bs0 (output) during memory write: h during i/o write: l during memory write: l during i/o write: h h remark { indicates the sampling timing.
chapter 4 bus control functions 54 4.4 bus hold function when a high level is input to the hldrq pin, the hldak signal becomes high level at the end of the bus cycle that is currently being executed, and the V30MZ enters the bus hold state (th). however, an idle cycle (ti) lasting 1 clock is always inserted immediately before the th state. in the th state, the a19 to a0 signals, the ubeb signal, and the bs3 to bs0 signal become high level, but the do15 to do0 signals output undefined data. next, when a low level is input to the hldrq pin, the hldak signal becomes low level, and the V30MZ returns to the normal bus cycle. however, a ti state lasting 1 clock is always inserted immediately after the th state. in the th state, no code fetch cycle is generated. figure 4-4. bus hold timing clk (input) a19 to a0 (output) ubeb (output) bs3 to bs0 (output) do15 to do0 (output) readyb (input) tx ti tw valid don't care don't care th th th hldrq (input) hldak (output) t x don't care ti th invalid remark { indicates the sampling timing.
55 chapter 5 interrupt functions interrupts of the V30MZ are roughly divided into two kinds; hardware interrupts and software interrupts. these interrupts are all vectored interrupts that reference a vector table. an interrupt vector table stores the start address of an interrupt service routine. when an interrupt is generated, the V30MZ references the fixed 4 bytes (fixed vector) in the vector table corresponding to the interrupt source or any 4 bytes (variable vector) specified each time and branches to the address stored there (start address of the interrupt service routine). the interrupt vector table is assigned to a 1 k-byte area 000h to 3ffh of the memory space and can define a maximum of 256 vectors. table 5-1 shows the number of interrupt source clocks processed, vector numbers and priority order. figure 5-1 shows the interrupt vector table configuration. table 5-1. interrupt source list interrupt source number of clocks processed note vector no. priority order nmi input (rising edge active) 26 2 2 hardware interrupt int input (high level active) 32 32 to 255 3 div or divu instruction divide error 0 chkind instruction boundary over 5 brkv instruction 4 brk 3 instruction 3 brk imm8 instruction 32 to 255 1 software interrupt brk flag (single-step) 25 14 note the number of clocks after execution of an instruction is aborted by an interrupt until the program branches to the start address of the interrupt service routine (progression of the wait state into the memory bus cycle and bus hold request are not taken into account). remark the following three instructions have a relatively long execution time, and even if an interrupt request is generated during their execution, their execution is not interrupted, and the interrupt request is acknowledged after the execution is completed. this point should be paid attention to in the case of systems for which the interrupt response time is particularly crucial. instruction number of execution clocks remarks divu 24 when divide error not generated due to divu instruction div 25 when divide error not generated due to div instruction prepare 139 when 2nd operand = 31
chapter 5 interrupt functions 56 figure 5-1. interrupt vector table configuration vector 0 000h 003h vector 1 004h 007h vector 2 008h 00bh vector 3 00ch 00fh vector 4 010h 013h vector 5 014h 017h vector 6 018h 02bh 02ch 07bh vector 31 07ch 07fh vector 32 080h 083h 084h 3fbh vector 255 3fch 3ffh div or divu instruction divide error brk flag (single-step) nmi input brk 3 instruction brkv instruction chkind instruction boundary over reserved general use ? brk imm8 instruction ? int input dedicated use for vectors 0 to 5, the interrupt sources to be used are specified and vectors 6 to 31 are reserved and are not available for general use. for vectors 32 to 255, brk imm8 instruction, and int input are available for general use. one interrupt vector consists of 4 bytes and the higher address 2 bytes are loaded to the program segment register (ps) as a base address pointer (program segment value) and the lower address 2 bytes are loaded to the program counter (pc) as an offset value. example: vector 0 003h 002h 001h 000h ps ? (003h, 002h) pc ? (001h, 000h) when creating a program, initialize the content of each vector used based on the example above in the beginning of the program.
chapter 5 interrupt functions 57 the following are the basic steps when jumping to an interrupt service routine. ta ? vector lower word data (offset value) tc ? vector higher word data (program segment value) sp ? spC2, (sp+1, sp) ? psw ie ? 0, brk ? 0, md ? 1 sp ? spC2, (sp+1, sp) ? ps ps ? tc sp ? spC2, (sp+1, sp) ? pc pc ? ta caution since the interrupt enable flag (ie) and break flag (brk) of the program status word (psw) are cleared (0) when interrupt servicing is started, no maskable interrupt (int) or brk flag (single- step) interrupt is acknowledged any longer.
chapter 5 interrupt functions 58 5.1 hardware interrupt there are two kinds of hardware interrupt. ? non-maskable interrupt (nmi) ? maskable interrupt (int) 5.1.1 non-maskable interrupt (nmi) nmi is a non-maskable interrupt and cannot be disabled by software. whenever there is an input to the nmi pin from a peripheral device, it is always acknowledged and detected on a rising edge. nmi takes precedence over int and is used to cope with abrupt variation of the normal power supply (instantaneous power failure) and memory error, bus error, etc. no interrupt acknowledge cycle is issued by nmi and no interrupt acknowledge is output, either. caution nmi requests are acknowledged even immediately after reset (int requests are not acknowledged), but until the correct value is loaded to the stack pointer (ss:sp), normal nmi processing cannot be performed. therefore, implement measures such as masking the nmi input with an external circuit. 5.1.2 maskable interrupt (int) maskable interrupts (int) are acknowledged with the following response sequence. prepare the interrupt acknowledge signal by decoding the bs3 to bs0 signals (when bs3 to bs0 are all low level).
chapter 5 interrupt functions 59 figure 5-2. interrupt acknowledge cycle clk (input) a19 to a0 (output) bs0 (output) di15 to di0 (input) 1st bus cycle ti ti invalid invalid invalid ti ti buslockb (output) 2nd bus cycle invalid interrupt vector number bs3 (output) bs2 (output) bs1 (output) ubeb (output) h (1) the 1st bus cycle is activated to obtain synchronization with the external interrupt controller. the values read from the data bus (di15 to di0) are not used. at this time, address 00000h is output to the address bus (a19 to a0), but this value has no meaning. moreover, a wait cycle can be inserted by using the readyb signal. (2) four clocks of idle cycle (ti) are inserted between the 1st bus cycle and the 2nd bus cycle. during this interval, the buslockb signal remains low. no code fetch cycle is generated between the 1st bus cycle and the 2nd bus cycle. (3) the V30MZ reads the vector number from the interrupt controller during the 2nd bus cycle (only lower byte of data bus is valid). at this time, address 00000h is output to the address bus, but this value is meaningless. moreover, similarly to the 1st bus cycle, a wait cycle can be inserted by using the readyb signal. remark whereas in the case of the v30hl, ube output is always low level during the interrupt acknowledge cycle, in the case of the V30MZ, ubeb output is always high level. (ubeb output becomes low level only when the start address of the interrupt processing routine is read.)
chapter 5 interrupt functions 60 5.2 software interrupts software interrupts take precedence over hardware interrupts except a brk flag (single-step) interrupts. they can be divided as follows. (1) interrupt by instruction result ? divide error by div instruction or divu instruction ? boundary over detection by chkind instruction when the processing result of an instruction is invalid, an interrupt is automatically generated to allow exception handling. (2) interrupt by conditional break (execution of brkv instruction) in execution of a brkv instruction, if the v flag is set (1), an interrupt is generated. it is used for processing an overflow of the operation result. (3) interrupt by unconditional break instruction ? 1-byte break instruction (brk 3) ? 2-byte break instruction (brk imm8 ( 1 3)) this interrupt is used when branching to a subroutine by a system call or inter-segment call without being aware of the branch destination. (4) brk flag (single-step) interrupt this is a useful function for program debugging, etc. this interrupt is controlled by the brk flag of psw. however, it is manipulated with the psw saved to the stack, not by an instruction which directly sets/clears the brk flag and set/cleared processing is indirectly performed by restoring it to the psw. when the brk flag is set (1), after the next one instruction is executed, the interrupt routine (monitor program, etc.) specified by vector 1 is started and the brk flag is also cleared (0) together with the ie flag at that time. therefore, once the vector 1 interrupt is started, interrupt routine instructions are not executed one by one but continuously in the same way as for other interrupts. here, the internal registers, flag state, memory content, etc., can be checked and dumped. in this interrupt routine, the number of single-steps is checked and if it is possible to terminate the single- step operation, the brk flag in the stack is cleared (0) by a memory manipulation instruction and returned. this allows instructions to be executed continuously after returning to the main routine. when returning without manipulating the brk flag, brk = 1 saved in the stack is restored to the psw and after execution of one instruction in the main routine a vector 1 interrupt is generated again.
chapter 5 interrupt functions 61 5.3 timing at which interrupt is not acknowledged in the timing shown in (1) to (4) below, that is, between an instruction in which data is directly set in the segment register or 3 types of prefix and the following one instruction, no hardware interrupt or brk flag (single-step) interrupt is acknowledged. furthermore, only the int interrupt is not acknowledged in the timing shown in (5). with the following 5 timings, no interrupt is acknowledged. (1) between each of mov ss, reg 16; mov ss, mem16; pop ss instructions and the next instruction (2) between segment override prefix (ps:, ss:, ds0:, ds1:) and the next instruction (3) between repeat prefix (rep, repe, repne) and the next instruction (4) between buslock instruction and the next instruction (5) between each of ei, reti, and pop psw instructions (in case an ie flag of the psw register is set (1) by executing the instruction) and the next instruction (only int interrupt) however, an nmi request signal generated in interrupt disable timings in (1) to (4) is held pending internally and acknowledged after execution of the next one instruction is completed. moreover, if the timing of (5) is generated with an ie flag set, the int interrupt is acknowledged even immediately after the execution of these instructions.
chapter 5 interrupt functions 62 5.4 interrupt servicing in execution of block processing instruction when a hardware interrupt request is generated in execution of a primitive block transfer/comparison, or input instruction, the V30MZ acknowledges it and branches to the corresponding interrupt address. however, in a block processing instruction, immediately after completion of the bus cycle in which an interrupt is generated, the interrupt may not be acknowledged. in that case, it takes several bus cycles after generation of the interrupt until the V30MZ can acknowledge the interrupt. table 5-2 shows the number of bus cycles. in this table, the bus cycle in which an interrupt is generated is counted as the first bus cycle. table 5-2. number of bus cycles required until interrupt is acknowledged instruction ix register iy register number of bus cycles required until interrupt is acknowledged movbkw even even 2 to 4 even odd 3 to 6 odd even 2 to 5 odd odd 3 to 7 movbkb C C 2 to 4 cmpbkw even even 1, 2 even odd 1 to 3 odd even 1 to 3 odd odd 1 to 4 cmpbkb C C 1, 2 cmpmw C even 1 C odd 1, 2 cmpmb C C 1 ldmw even C 1 odd C 1, 2 ldmb C C 1 stmw C even 3, 4 C odd 3 to 5 stmb C C 3, 4 example 1. when an interrupt request is generated in execution of movbkb instruction movbkb bus cycle interrupt servicing int input or nmi input
chapter 5 interrupt functions 63 example 2. when an interrupt request is generated in execution of stmb instruction stmb bus cycle interrupt servicing int input or nmi input if at the start of an interrupt service routine started in this way the cw register operating as a counter for the block data is saved to the stack and the saved cw register is restored at the end of the interrupt service routine and then the original routine is returned to by an reti instruction, the suspended block processing can be restarted. at this time, if a prefix is placed before the block processing instruction, the return address is modified (C1 address for one kind of prefix) and saved so that up to 3 kinds of prefix are stored and can be returned to the address at which the prefix is placed when returning from the interrupt service routine. in order to use these functions effectively, set the sum of prefixes placed before a block processing instruction to three or less.
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65 chapter 6 standby functions 6.1 setting of standby mode executing a halt instruction sets the standby (halt) mode. in the standby mode, the clock is supplied only to the circuit related to the function required for releasing the standby mode and the circuit related to the bus hold function, and its supply to all other circuits is stopped. as a result, the system's power consumption is considerably reduced. 6.2 standby mode when the V30MZ enters the standby mode, the bs3 to bs0 signals output the halt status for 1 clock. then the a19 to a0 signals, the ubeb signal, and the bs3 to bs0 signals become high level. do15 to do0 outputs become undefined. figure 6-1. timing to enter standby mode the bus hold function is also valid in the standby mode, but when the bus hold acknowledge period ends, the system returns to the standby mode. however, when the system returns to the standby mode, there is no halt status output from the bs3 to bs0 pins (the idle status continues). clk (input) a19 to a0 (output) ubeb (output) bs3 (output) do15 to do0 (output) undefined bs2 (output) bs1 (output) bs0 (output) h
chapter 6 standby functions 66 6.3 release of standby mode there are two ways to release the standby mode: release by a hardware interrupt (nmi input or int input) and release by reset input. when both inputs become active at the same time, the normal interrupt priority order applies. 6.3.1 release by hardware interrupt request cautions 1. when the bus hold request and hardware interrupt request are issued at the same time, the bus hold request takes priority, and after the bus hold cycle ends, the standby mode is released by hardware interrupt request. 2. when the halt instruction and the hardware interrupt request are issued at the same time, the halt status is output from the bs3 to bs0 pins, but the V30MZ does not enter the standby mode, and instead immediately performs interrupt processing (or the instruction following the halt instruction). (1) release by nmi input upon detection of the rising edge of nmi input, the standby mode is released and the interrupt processing (nmi routine) starts. then, when the reti instruction is executed upon completion of the nmi routine, program execution resumes from the instruction following the halt instruction. (2) release by int input the operation after release of the standby mode differs depending on whether the system is in the interrupt enable status (ie flag of psw = 1) or in the interrupt disable status (ie flag of psw = 0). (a) interrupt enable status when there is an int input, the standby mode is released and interrupt processing (int routine) starts. then, when the reti instruction is executed upon completion of the int routine, program execution resumes from the instruction following the halt instruction. caution input the high level to the int pin until the 1st bus cycle of the interrupt acknowledge cycle. (b) interrupt disable status when there is an int input, the standby mode is released and program execution resumes from the instruction following the halt instruction. caution input the high level to the int pin for the interval of one clock or longer.
chapter 6 standby functions 67 6.3.2 release by reset input when the reset signal is input in the standby mode, the standby mode is released unconditionally, and the system starts normal reset operation. therefore, the status that was held in the standby mode becomes invalid, and the program that was stopped by the standby mode cannot be resumed.
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69 chapter 7 reset functions when a high level is input to the reset pin for 4 clocks or more, each output pin of the V30MZ changes to the statuses shown in table 7-1. they retain these values while the high level is input. a setup time and hold time are prescribed for the rising edge of the clk pin for reset input. be sure to perform reset input so as to satisfy these prescriptions. table 7-1. status of output pins after reset pin status after reset a19 to a0 high-level output do15 to do0 undefined ubeb high-level output buslockb bs3 to bs0 hldak low-level output tbo42 to tbo0 high impedance each register is initialized to the value shown in table 7-2 following reset. table 7-2. initial value of registers after reset register initial value pc 0000h pfp ps ffffh ss, ds0, ds1 0000h aw, bw, cw, dw undefined sp, bp ix, iy md v dir ie brk higher 1 1 1 1 0 0 0 0 sz ac p cy lower 0 0 0 0 0 0 1 0 psw when the signal input to the reset pin goes back to low level, the V30MZ starts instruction prefetch from address ffff0h (segment value: ffffh, offset value: 0000h).
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71 chapter 8 test functions the V30MZ has unit test functions using the test bus like other cbic cores. 8.1 test pins the V30MZ has the following test pins. ? tbi22 to tbi0 ? tbo42 to tbo0 ? bunri ? test 8.1.1 test bus pins (tbi22 to tbi0, tbo42 to tbo0) the test bus pins are used instead of normal pins in the unit test mode. for details, see the design manual user's manual of each cell-based ic family. 8.1.2 bunri, test pins these pins are used to select the normal, unit test, or standby test mode. table 8-1. test mode selection list bunri pin input level test pin input level mode low level don't care normal mode high level low level standby test mode high level high level unit test mode
chapter 8 test functions 72 8.2 normal mode this is the mode normally used by the user. when the low level is input to the bunri pin, pins other than test pins become valid and the normal mode is entered. at this time, inputs to the tbi22 to tbi0 pins are ignored, and the tbo42 to tbo0 pins go into high impedance. 8.3 unit test mode and standby test mode when the high level is input to the bunri pin, inputs to pins other than test pins are ignored (become invalid), and the system enters the test mode. there are two test modes, the unit test mode and the standby test mode. perform circuit design so that the bus configuration pins (except test pins) do not become floating level or cause bus contention during the unit test mode and the standby test mode. (for details on the status of pins in each mode, see section 2.2 pin statuses .) 8.3.1 unit test mode when the high level is input to the bunri pin and the test pin, the system enters the unit test mode. in the unit test mode, inputs to pins other than test pins are ignored, and inputs to the tbi22 to tbi0 pins become valid instead. moreover, values for the pins other than test pins are output to the tbo42 to tbo0 pins. caution the unit test mode is a mode for testing performed by nec. 8.3.2 standby test mode when the high level is input to the bunri pin and the low level is input to the test pin, the system enters the standby test mode. this mode is used for cores that are not tested during test circuit verification simulation and user logic separation simulation. inputs to the tbi22 to tbi0 pins are ignored and the tbo42 to tbo0 pins go into high impedance.
73 appendix a list of instruction execution clock counts this appendix shows the number of execution clocks for each instruction under conditions (1) to (7) listed below. for details on the functions of each instruction, refer to the 16-bit v series instruction users manual . (1) instruction decoding is completed. (2) no wait state occurs during memory access or i/o access. note 1 (3) there is no bus hold request. (4) word data is allocated to even addresses. note 2 (5) registers required for calculating effective addresses (bw, bp, sp, ix, iy, etc.) do not change at immediately preceding instruction. note 3 (6) there is only 1 register required for calculating effective addresses. note 4 (7) the branching destination of a branch instruction is an even address. note 5 notes 1. if a wait state is generated, add the number of clocks of the wait state to the number of instruction execution clocks. 2. when access to word data allocated to odd addresses is performed, add 1 clock. 3. when using a register that changed in the immediately preceding instruction for calculating the effective address, add 1 clock. (however, 1 clock does not increase in the case of the ldea instruction and the repeat prefetch instruction.) moreover, in the case of consecutive push or pop instruction, the number of execution clocks does not increase (they are all executed in 1 clock.) 4. if there are two registers required for calculating the effective address (for example mov aw,[bw+ix]), add 1 clock. 5. if branching to an odd address is performed, add 1 clock.
appendix a list of instruction execution clock counts 74 table a-1. list of instruction execution clock counts (1/11) operation code mnemonic, operand 7654321076543210 clocks 0000010w imm8 or imm16-low add acc, imm imm16-high 1 100000swmod 000 mem (disp-low) (disp-high) add mem, imm imm8 or imm16-low imm16-high 3 0000000wmod reg mem add mem, reg (disp-low) (disp-high) 3 100000sw11000 reg add reg, imm imm8 or imm16-low imm16-high 1 0000001wmod reg mem add reg, mem (disp-low) (disp-high) 2 add reg, reg' 0 0 0 0 0 0 1 w 1 1 reg reg' 1 add reg, reg' 0 0 0 0 0 0 0 w 1 1 reg reg' 1 0001010w imm8 or imm16-low addc acc, imm imm16-high 1 100000swmod 010 mem (disp-low) (disp-high) addc mem, imm imm8 or imm16-low imm16-high 3 0001000wmod reg mem addc mem, reg (disp-low) (disp-high) 3 100000sw11010 reg addc reg, imm imm8 or imm16-low imm16-high 1 0001001wmod reg mem addc reg, mem (disp-low) (disp-high) 2 addc reg, reg' 0 0 0 1 0 0 1 w 1 1 reg reg' 1 addc reg, reg' 0 0 0 1 0 0 0 w 1 1 reg reg' 1 adj4a 00100111 10 adj4s 00101111 10 adjba 00110111 9 adjbs 00111111 9 0010010w imm8 or imm16-low and acc, imm imm16-high 1 1000000wmod 100 mem (disp-low) (disp-high) and mem, imm imm8 or imm16-low imm16-high 3 0010000wmod reg mem and mem, reg (disp-low) (disp-high) 3 1000000w11100 reg and reg, imm imm8 or imm16-low imm16-high 1 0010001wmod reg mem and reg, mem (disp-low) (disp-high) 2
appendix a list of instruction execution clock counts 75 table a-1. list of instruction execution clock counts (2/11) operation code mnemonic, operand 7654321076543210 clocks and reg, reg' 0 0 1 0 0 0 1 w 1 1 reg reg' 1 and reg, reg' 0 0 1 0 0 0 0 w 1 1 reg reg' 1 bc short-label 0 1 1 1 0 0 1 0 disp8 1 (when cy = 0) bc short-label 0 1 1 1 0 0 1 0 disp8 4 (when cy = 1) bcwz short-label 1 1 1 0 0 0 1 1 disp8 1 (when cw 1 0) bcwz short-label 1 1 1 0 0 0 1 1 disp8 4 (when cw = 0) be short-label 0 1 1 1 0 1 0 0 disp8 1 (when z = 0) be short-label 0 1 1 1 0 1 0 0 disp8 4 (when z = 1) bge short-label 0 1 1 1 1 1 0 1 disp8 1 (when s " v = 1) bge short-label 0 1 1 1 1 1 0 1 disp8 4 (when s " v = 0) bgt short-label 0 1 1 1 1 1 1 1 disp8 1 (when (s " v) z = 1) bgt short-label 0 1 1 1 1 1 1 1 disp8 4 (when (s " v) z = 0) bh short-label 0 1 1 1 0 1 1 1 disp8 1 (when cy z = 1) bh short-label 0 1 1 1 0 1 1 1 disp8 4 (when cy z = 0) bl short-label 0 1 1 1 0 0 1 0 disp8 1 (when cy = 0) bl short-label 0 1 1 1 0 0 1 0 disp8 4 (when cy = 1) ble short-label 0 1 1 1 1 1 1 0 disp8 1 (when (s " v) z = 0) ble short-label 0 1 1 1 1 1 1 0 disp8 4 (when (s " v) z = 1) blt short-label 0 1 1 1 1 1 0 0 disp8 1 (when s " v = 0) blt short-label 0 1 1 1 1 1 0 0 disp8 4 (when s " v = 1) bn short-label 0 1 1 1 1 0 0 0 disp8 1 (when s = 0) bn short-label 0 1 1 1 1 0 0 0 disp8 4 (when s = 1) bnc short-label 0 1 1 1 0 0 1 1 disp8 1 (when cy = 1) bnc short-label 0 1 1 1 0 0 1 1 disp8 4 (when cy = 0) bne short-label 0 1 1 1 0 1 0 1 disp8 1 (when z = 1) bne short-label 0 1 1 1 0 1 0 1 disp8 4 (when z = 0) bnh short-label 0 1 1 1 0 1 1 0 disp8 1 (when cy z = 0) bnh short-label 0 1 1 1 0 1 1 0 disp8 4 (when cy z = 1) bnl short-label 0 1 1 1 0 0 1 1 disp8 1 (when cy = 1) bnl short-label 0 1 1 1 0 0 1 1 disp8 4 (when cy = 0) bnv short-label 0 1 1 1 0 0 0 1 disp8 1 (when v = 1) bnv short-label 0 1 1 1 0 0 0 1 disp8 4 (when v = 0) bnz short-label 0 1 1 1 0 1 0 1 disp8 1 (when z = 1) bnz short-label 0 1 1 1 0 1 0 1 disp8 4 (when z = 0) bp short-label 0 1 1 1 1 0 0 1 disp8 1 (when s = 1) bp short-label 0 1 1 1 1 0 0 1 disp8 4 (when s = 0) bpe short-label 0 1 1 1 1 0 1 0 disp8 1 (when p = 0) bpe short-label 0 1 1 1 1 0 1 0 disp8 4 (when p = 1) bpo short-label 0 1 1 1 1 0 1 1 disp8 1 (when p = 1) bpo short-label 0 1 1 1 1 0 1 1 disp8 4 (when p = 0)
appendix a list of instruction execution clock counts 76 table a-1. list of instruction execution clock counts (3/11) operation code mnemonic, operand 7654321076543210 clocks 11101010 offset-low offset-high seg-low br far-label seg-high 7 11111111 mod 100 mem br memptr16 (disp-low) (disp-high) 5 11111111 mod 101 mem br memptr32 (disp-low) (disp-high) 10 11101001 disp-low br near-label disp-high 4 br regptr16 1 1 1 1 1 1 1 1 1 1 1 0 0 reg 4 br short-label 1 1 1 0 1 0 1 1 disp8 4 brk 3 11001100 9 brk imm8 ( 1 3) 11001101 imm8 10 brkv 1 1 0 0 1 1 1 0 6 (when v = 0) brkv 1 1 0 0 1 1 1 0 13 (when v = 1) buslock 11110000 1 bv short-label 0 1 1 1 0 0 0 0 disp8 1 (when v = 0) bv short-label 0 1 1 1 0 0 0 0 disp8 4 (when v = 1) bz short-label 0 1 1 1 0 1 0 0 disp8 1 (when z = 0) bz short-label 0 1 1 1 0 1 0 0 disp8 4 (when z = 1) 10011010 offset-low offset-high seg-low call far-proc seg-high 10 11111111 mod 010 mem call memptr16 (disp-low) (disp-high) 6 11111111 mod 011 mem call memptr32 (disp-low) (disp-high) 12 11101000 disp-low call near-proc disp-high 5 call regptr16 1 1 1 1 1 1 1 1 1 1 0 1 0 reg 5 01100010 mod reg mem chkind reg16, mem32 (disp-low) (disp-high) 13 (when interrupt condition is not satisfied) 01100010 mod reg mem chkind reg16, mem32 (disp-low) (disp-high) 20 (when interrupt condition is satisfied) clr1 cy 11111000 4 clr1 dir 1 1 1 1 1 1 0 0 4 0011110w imm8 or imm16-low cmp acc, imm imm16-high 1 100000swmod 111 mem (disp-low) (disp-high) cmp mem, imm imm8 or imm16-low imm16-high 2
appendix a list of instruction execution clock counts 77 table a-1. list of instruction execution clock counts (4/11) operation code mnemonic, operand 7654321076543210 clocks 0011100wmod reg mem cmp mem, reg (disp-low) (disp-high) 2 100000sw11111 reg cmp reg, imm imm8 or imm16-low imm16-high 1 0011101wmod reg mem cmp reg, mem (disp-low) (disp-high) 2 cmp reg, reg' 0 0 1 1 1 0 1 w 1 1 reg reg' 1 cmp reg, reg' 0 0 1 1 1 0 0 w 1 1 reg reg' 1 cmpbk [ds1-spec:]dst-block 1 0 1 0 0 1 1 w 6 cmpbk [seg-spec:]src-block, [ds1-spec:]dst-block 1010011w 6 cmpbkb 1 0 1 0 0 1 1 w 6 cmpbkw 1 0 1 0 0 1 1 w 6 cmpm [ds1-spec:]dst-block 1010111w 4 cmpmb 1010111w 4 cmpmw 1010111w 4 cvtbd 1101010000001010 17 cvtbw 10011000 1 cvtdb 1101010100001010 6 cvtwl 10011001 1 dbnz short-label 1 1 1 0 0 0 1 0 disp8 2 (when cw = 0) dbnz short-label 1 1 1 0 0 0 1 0 disp8 5 (when cw 1 0) dbnze short-label 1 1 1 0 0 0 0 1 disp8 6 (w hen cw 1 0 and z = 1) dbnze short-label 1 1 1 0 0 0 0 1 disp8 3 (in cases ot her than above) dbnzne short-label 1 1 1 0 0 0 0 0 disp8 6 (w hen cw 1 0 and z = 0) dbnzne short-label 1 1 1 0 0 0 0 0 disp8 3 (in cases ot her than above) 1111111wmod 001 mem dec mem (disp-low) (disp-high) 3 dec reg16 0 1 0 0 1 reg 1 dec reg8 1111111w11001 reg 1 di 11111010 4 dispose 11001001 2 1111011wmod 111 mem div mem16 (disp-low) (disp-high) 25 1111011wmod 111 mem div mem8 (disp-low) (disp-high) 18 div reg16 1 1 1 1 0 1 1 w 1 1 1 1 1 reg 24 div reg8 1111011w11111 reg 17 1111011wmod 110 mem divu mem16 (disp-low) (disp-high) 24 1111011wmod 110 mem divu mem8 (disp-low) (disp-high) 16
appendix a list of instruction execution clock counts 78 table a-1. list of instruction execution clock counts (5/11) operation code mnemonic, operand 7654321076543210 clocks divu reg16 1 1 1 1 0 1 1 w 1 1 1 1 0 reg 23 divu reg8 1111011w11110 reg 15 ds0: 00111110 1 ds1: 00100110 1 ei 11111011 4 11011xxx mod yyy mem fpo1 fp-op, mem (disp-low) (disp-high) 1 halt 11110100 9 in acc, dw 1110110w 6 in acc, imm8 1110010w imm8 6 1111111wmod 000 mem inc mem (disp-low) (disp-high) 3 inc reg16 0 1 0 0 0 reg 1 inc reg8 1111111w11000 reg 1 inm [ds1-spec:]dst-block, dw 0 1 1 0 1 1 0 w 6 10001101 mod reg mem ldea reg16, mem16 (disp-low) (disp-high) 1 ldm [seg-spec:]src-block 1 0 1 0 1 1 0 w 3 ldmb 1010110w 3 ldmw 1010110w 3 1010000w addr-low mov acc, dmem addr-high 1 mov ah, psw 10011111 2 1010001w addr-low mov dmem, acc addr-high 1 11000101 mod reg mem mov ds0, reg16, mem32 (disp-low) (disp-high) 6 11000100 mod reg mem mov ds1, reg16, mem32 (disp-low) (disp-high) 6 1100011wmod 000 mem (disp-low) (disp-high) mov mem, imm imm8 or imm16-low imm16-high 1 1000100wmod reg mem mov mem, reg (disp-low) (disp-high) 1 10001100 mod 0 sreg mem mov mem16, sreg (disp-low) (disp-high) 3 mov psw, ah 10011110 4 1 0 1 1 w reg imm8 or imm16-low mov reg, imm imm16-high 1 1100011w11000 reg mov reg, imm imm8 or imm16-low imm16-high 1
appendix a list of instruction execution clock counts 79 table a-1. list of instruction execution clock counts (6/11) operation code mnemonic, operand 7654321076543210 clocks 1000101wmod reg mem mov reg, mem (disp-low) (disp-high) 1 mov reg, reg' 1 0 0 0 1 0 1 w 1 1 reg reg' 1 mov reg, reg' 1 0 0 0 1 0 0 w 1 1 reg reg' 1 mov reg16, sreg 1 0 0 0 1 1 0 0 1 1 0 sreg reg 1 10001110 mod 0 sreg mem mov sreg, mem16 (disp-low) (disp-high) 3 mov sreg, reg16 1 0 0 0 1 1 1 0 1 1 0 sreg reg 2 movbk [ds1-spec:]dst-block, [seg-spec:]src-block 1010010w 5 movbk [seg-spec:]src-block 1 0 1 0 0 1 0 w 5 movbkb 1 0 1 0 0 1 0 w 5 movbkw 1 0 1 0 0 1 0 w 5 1111011wmod 101 mem mul mem16 (disp-low) (disp-high) 4 1111011wmod 101 mem mul mem8 (disp-low) (disp-high) 4 mul reg16 1 1 1 1 0 1 1 w 1 1 1 0 1 reg 3 011010s111 reg reg' mul reg16, imm16 imm16-low imm16-high 3 011010s111 reg reg' mul reg16, imm8 imm8 3 011010s1 mod reg mem (disp-low) (disp-high) mul reg16, mem16, imm16 imm16-low imm16-high 4 011010s1 mod reg mem (disp-low) (disp-high) mul reg16, mem16, imm8 imm8 4 011010s111 reg reg' mul reg16, reg16' , imm16 imm16-low imm16-high 3 011010s111 reg reg' mul reg16, reg16' , imm8 imm8 3 mul reg8 1111011w11101 reg 3 1111011wmod 100 mem mulu mem16 (disp-low) (disp-high) 4 1111011wmod 100 mem mulu mem8 (disp-low) (disp-high) 4 mulu reg16 1 1 1 1 0 1 1 w 1 1 1 0 0 reg 3 mulu reg8 1111011w11100 reg 3 1111011wmod 011 mem neg mem (disp-low) (disp-high) 3 neg reg 1111011w11011 reg 1
appendix a list of instruction execution clock counts 80 table a-1. list of instruction execution clock counts (7/11) operation code mnemonic, operand 7654321076543210 clocks nop 10010000 1 1111011wmod 010 mem not mem (disp-low) (disp-high) 3 not reg 1111011w11010 reg 1 not1 cy 11110101 4 0000110w imm8 or imm16-low or acc, imm imm16-high 1 1000000wmod 001 mem (disp-low) (disp-high) or mem, imm imm8 or imm16-low imm16-high 3 0000100wmod reg mem or mem, reg (disp-low) (disp-high) 3 1000000w11001 reg or reg, imm imm8 or imm16-low imm16-high 1 0000101wmod reg mem or reg, mem (disp-low) (disp-high) 2 or reg, reg' 0 0 0 0 1 0 1 w 1 1 reg reg' 1 or reg, reg' 0 0 0 0 1 0 0 w 1 1 reg reg' 1 out dw, acc 1110111w 6 out imm8, acc 1 1 1 0 0 1 1 w imm8 6 outm dw, [seg-spec:]src-block 0 1 1 0 1 1 1 w 7 poll 10011011 number of 9 + 9 pollb pin samplings 10001111 mod 000 mem pop mem16 (disp-low) (disp-high) 3 pop psw 10011101 3 pop r 01100001 8 pop reg16 0 1 0 1 1 reg 1 pop reg16 1 0 0 0 1 1 1 1 1 1 0 0 0 reg 1 pop sreg 000 sreg 111 3 11001000 imm16-low prepare imm16, imm8 (when imm8 = 0) imm16-high imm8 8 11001000 imm16-low prepare imm16, imm8 (when imm8 = 1) imm16-high imm8 14 11001000 imm16-low prepare imm16, imm8 (when imm8 > 1) imm16-high imm8 15 + 4 imm8 ps: 00101110 1 011010s0 imm16-low push imm16 imm16-high 1 push imm8 0 1 1 0 1 0 s 0 imm8 1 11111111 mod 110 mem push mem16 (disp-low) (disp-high) 2
appendix a list of instruction execution clock counts 81 table a-1. list of instruction execution clock counts (8/11) operation code mnemonic, operand 7654321076543210 clocks push psw 10011100 2 push r 01100000 9 push reg16 0 1 0 1 0 reg 1 push reg16 1 1 1 1 1 1 1 1 1 1 1 1 0 reg 1 push sreg 000 sreg 110 2 rep inm 111100110110110w5 + 6 rep rep ldm/ldmb/ldmw 111100111010110w5 + 6 rep rep movbk 111100111010010w5 + 7 rep rep outm 111100110110111w5 + 6 rep rep stm/stmb/stmw 111100111010101w5 + 6 rep repe cmpm/cmpmb/cmpmw 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 w 5 + 9 rep repne cmpm/cmpmb/cmpmw 111100101010111w5 + 9 rep repnz cmpbk/cmpbkb/cmpbkw 111100101010011w5 + 9 rep repz cmpbk/cmpbkb/cmpbkw 111100111010011w5 + 10 rep 1 1 0 0 1 0 1 0 pop-value-low ret pop-value (segment-external call) pop-value-high 9 1 1 0 0 0 0 1 0 pop-value-low ret pop-value (segment-internal call) pop-value-high 6 ret (segment-external call) 1 1 0 0 1 0 1 1 8 ret (segment-internal call) 1 1 0 0 0 0 1 1 6 reti 11001111 10 1101000wmod 000 mem rol mem, 1 (disp-low) (disp-high) 3 1101001wmod 000 mem rol mem, cl (disp-low) (disp-high) 5 1100000wmod 000 mem (disp-low) (disp-high) rol mem, imm8 imm8 5 rol reg, 1 1101000w11000 reg 1 rol reg, cl 1101001w11000 reg 3 1100000w11000 reg rol reg, imm8 imm8 3 1101000wmod 010 mem rolc mem, 1 (disp-low) (disp-high) 3 1101001wmod 010 mem rolc mem, cl (disp-low) (disp-high) 5 1100000wmod 010 mem (disp-low) (disp-high) rolc mem, imm8 imm8 5 rolc reg, 1 1101000w11010 reg 1 rolc reg, cl 1101001w11010 reg 3
appendix a list of instruction execution clock counts 82 table a-1. list of instruction execution clock counts (9/11) operation code mnemonic, operand 7654321076543210 clocks 1100000w11010 reg rolc reg, imm8 imm8 3 1101000wmod 001 mem ror mem, 1 (disp-low) (disp-high) 3 1101001wmod 001 mem ror mem, cl (disp-low) (disp-high) 5 1100000wmod 001 mem (disp-low) (disp-high) ror mem, imm8 imm8 5 ror reg, 1 1101000w11001 reg 1 ror reg, cl 1101001w11001 reg 3 1100000w11001 reg ror reg, imm8 imm8 3 1101000wmod 011 mem rorc mem, 1 (disp-low) (disp-high) 3 1101001wmod 011 mem rorc mem, cl (disp-low) (disp-high) 5 1100000wmod 011 mem (disp-low) (disp-high) rorc mem, imm8 imm8 5 rorc reg, 1 1101000w11011 reg 1 rorc reg, cl 1101001w11011 reg 3 1100000w11011 reg rorc reg, imm8 imm8 3 set1 cy 11111001 4 set1 dir 11111101 4 1101000wmod 100 mem shl mem, 1 (disp-low) (disp-high) 3 1101001wmod 100 mem shl mem, cl (disp-low) (disp-high) 5 1100000wmod 100 mem (disp-low) (disp-high) shl mem, imm8 imm8 5 shl reg, 1 1101000w11100 reg 1 shl reg, cl 1101001w11100 reg 3 1100000w11100 reg shl reg, imm8 imm8 3 1101000wmod 101 mem shr mem, 1 (disp-low) (disp-high) 3 1101001wmod 101 mem shr mem, cl (disp-low) (disp-high) 5
appendix a list of instruction execution clock counts 83 table a-1. list of instruction execution clock counts (10/11) operation code mnemonic, operand 7654321076543210 clocks 1100000wmod 101 mem (disp-low) (disp-high) shr mem, imm8 imm8 5 shr reg, 1 1101000w11101 reg 1 shr reg, cl 1101001w11101 reg 3 1100000w11101 reg shr reg, imm8 imm8 3 1101000wmod 111 mem shra mem, 1 (disp-low) (disp-high) 3 1101001wmod 111 mem shra mem, cl (disp-low) (disp-high) 5 1100000wmod 111 mem (disp-low) (disp-high) shra mem, imm8 imm8 5 shra reg, 1 1101000w11111 reg 1 shra reg, cl 1101001w11111 reg 3 1100000w11111 reg shra reg, imm8 imm8 3 ss: 00110110 1 stm [ds1-spec:]dst-block 1010101w 3 stmb 1010101w 3 stmw 1010101w 3 0010110w imm8 or imm16-low sub acc, imm imm16-high 1 100000swmod 101 mem (disp-low) (disp-high) sub mem, imm imm8 or imm16-low imm16-lhigh 3 0010100wmod reg mem sub mem, reg (disp-low) (disp-high) 3 100000sw11101 reg sub reg, imm imm8 or imm16-low imm16-high 1 0010101wmod reg mem sub reg, mem (disp-low) (disp-high) 2 sub reg, reg' 0 0 1 0 1 0 1 w 1 1 reg reg' 1 sub reg, reg' 0 0 1 0 1 0 0 w 1 1 reg reg' 1 0001110w imm8 or imm16-low subc acc, imm imm16-high 1 100000swmod 011 mem (disp-low) (disp-high) subc mem, imm imm8 or imm16-low imm16-lhigh 3
appendix a list of instruction execution clock counts 84 table a-1. list of instruction execution clock counts (11/11) operation code mnemonic, operand 7654321076543210 clocks 0001100wmod reg mem subc mem, reg (disp-low) (disp-high) 3 100000sw11011 reg subc reg, imm imm8 or imm16-low imm16-high 1 0001101wmod reg mem subc reg, mem (disp-low) (disp-high) 2 subc reg, reg' 0 0 0 1 1 0 1 w 1 1 reg reg' 1 subc reg, reg' 0 0 0 1 1 0 0 w 1 1 reg reg' 1 1010100w imm8 or imm16-low test acc, imm imm16-high 1 1111011wmod 000 mem (disp-low) (disp-high) test mem, imm imm8 or imm16-low imm16-lhigh 2 1000010wmod reg mem test mem,reg (disp-low) (disp-high) 2 1111011w11000 reg test reg, imm imm8 or imm16-low imm16-high 1 1000010wmod reg mem test reg, mem (disp-low) (disp-high) 2 test reg, reg' 1 0 0 0 0 1 0 w 1 1 reg reg' 1 trans 11010111 5 trans src-table 11010111 5 transb 11010111 5 xch aw, reg16 1 0 0 1 0 reg 3 1000011wmod reg mem xch mem, reg (disp-low) (disp-high) 5 1000011wmod reg mem xch reg, mem (disp-low) (disp-high) 5 xch reg, reg' 1 0 0 0 0 1 1 w 1 1 reg reg' 3 xch reg16, aw 1 0 0 1 0 reg 3 0011010w imm8 or imm16-low xor acc, imm imm16-high 1 1000000wmod 110 mem (disp-low) (disp-high) xor mem, imm imm8 or imm16-low imm16-lhigh 3 0011000wmod reg mem xor mem, reg (disp-low) (disp-high) 3 1000000w11110 reg xor reg, imm imm8 or imm16-low imm16-high 1 0011001wmod reg mem xor reg, mem (disp-low) (disp-high) 2 xor reg, reg' 0 0 1 1 0 0 1 w 1 1 reg reg' 1 xor reg, reg' 0 0 1 1 0 0 0 w 1 1 reg reg' 1
85 appendix b index [a] a19 to a0................................................................. 19 ac............................................................................ 28 addressing mode..................................................... 42 addressing with based index................................... 45 ah............................................................................ 25 al ............................................................................ 25 auxiliary carry flag ................................................... 28 aw........................................................................... 25 [b] based addressing.................................................... 45 bh............................................................................ 25 bl ............................................................................ 25 bp............................................................................ 25 break flag ................................................................ 29 brk ......................................................................... 29 bs3 to bs0 .............................................................. 19 bunri ..................................................................... 22 bus control functions ................................. 47 bus hold function ................................................... 54 buslockb ............................................................. 20 bw........................................................................... 25 [c] carry flag ................................................................. 27 ch ........................................................................... 25 cl ............................................................................ 25 clk.......................................................................... 21 control flag .............................................................. 26 cpu functions ................................................... 25 cw........................................................................... 25 cy............................................................................ 27 [d] data address ........................................................... 43 data segment 0 ....................................................... 37 data segment 1 ....................................................... 37 description of pin statuses ..................................... 19 dh ........................................................................... 25 di15 to di0 .............................................................. 19 differences between V30MZ and v30 hl, v30mx.. 14 dir .......................................................................... 29 direct addressing............................................... 42, 44 direction flag ............................................................ 29 dl ............................................................................ 25 do15 to do0 ........................................................... 19 double word data configuration ............................... 32 ds0 .......................................................................... 25 ds1 .......................................................................... 25 dw ........................................................................... 25 dynamic relocation .................................................. 37 [e] effective address ..................................................... 39 [f] format of object code .............................................. 41 [g] general-purpose registers ....................................... 25 [h] handling of unused pins ......................................... 23 hardware interrupt ................................................... 58 hldak ..................................................................... 21 hldrq..................................................................... 20 [i] ie.............................................................................. 29 immediate addressing.............................................. 43 indexed addressing.................................................. 45 index register ........................................................... 30 initial value of registers after reset........................ 69 instruction address................................................... 42 instruction prefetch .................................................. 33 instruction set .......................................................... 40 int ........................................................................... 21 interface between V30MZ and i/o ........................... 49 interface between V30MZ and memory ................... 47 interrupt acknowledge cycle ................................... 59 interrupt enable flag ................................................. 29 interrupt functions....................................... 55 interrupt servicing in execution of block processing instruction ................................................................ 62 interrupt vector table configuration ........................ 56 i/o addressing.......................................................... 43 i/o map .................................................................... 32 i/o space.................................................................. 32
appendix b index 86 ix ............................................................................. 30 iy ............................................................................. 30 [l] list of instruction execution clock counts.................................................................. 73 logical address ....................................................... 34 [m] maskable interrupt ................................................... 58 md ........................................................................... 29 memory address calculation................................... 39 memory addressing ................................................. 44 memory indirect addressing..................................... 42 memory map ............................................................ 31 memory space ......................................................... 31 mode flag ................................................................. 29 [n] nmi .......................................................................... 21 non-maskable interrupt (nmi).................................. 58 non-memory addressing ......................................... 43 normal mode ........................................................... 72 [o] overflow flag............................................................ 28 [p] p .............................................................................. 27 parity flag................................................................. 27 pc............................................................................ 26 pc relative addressing............................................. 42 physical address ..................................................... 34 pin functions ..................................................... 17 pin list ..................................................................... 17 pin statuses............................................................. 18 pointer ..................................................................... 25 pollb ..................................................................... 20 program counter ...................................................... 26 program segment .................................................... 37 program status word................................................ 26 ps ............................................................................ 25 psw......................................................................... 26 [r] read timing of memory and i/o.............................. 50 readyb...................................................................20 register addressing .................................................43 register configuration..............................................25 register indirect addressing...............................42, 44 release of standby mode ........................................66 reset .....................................................................20 reset functions...............................................69 [s] s ...............................................................................28 segment configuration .............................................35 segment registers ....................................................25 segment system.......................................................34 setting of standby mode ..........................................65 sign flag ...................................................................28 software interrupts ...................................................60 sp.............................................................................25 ss.............................................................................25 stack segment..........................................................37 standby functions...........................................65 standby mode ..........................................................65 standby test mode ...................................................72 status flag ................................................................26 status of output pin after reset...............................69 symbol diagram.......................................................13 [t] tbi22 to tbi0 .....................................................22, 71 tbo42 to tbo0..................................................22, 71 test ........................................................................22 test bus pins............................................................71 test functions .................................................71 timing at which interrupt is not acknowledged .......61 [u] ubeb........................................................................19 unit test mode ..........................................................72 [v] v ...............................................................................28 [w] word data configuration ...........................................32 write timing of memory and i/o ..............................52
appendix b index 87 [z] z .............................................................................. 28 zero flag .................................................................. 28
88 [memo]
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