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tl/dd12527 cop87l88gw one-time programmable (otp) microcontroller preliminary may 1996 cop87l88gw one-time programmable (otp) microcontroller general description the cop87l88gw is a member of the cop8 tm 8-bit otp microcontroller family. it is pin and software compatible to the mask rom cop888gw product family. (continued) features y low cost 8-bit microcontroller y fully static cmos, with low current drain y two power saving modes: halt and idle y 1 m s instruction cycle time y 16 kbytes on-board otp eprom with security feature note: up to 32 kbytes of otp eprom is available on request. y 512 bytes on-board ram y single supply operation: 2.7v 5.5v y full duplex uart y microwire/plus tm serial i/o y idle timer y two 16-bit timers, each with two 16-bit registers supporting: e processor independent pwm mode e external event counter mode e input capture mode y four pulse train generators with 16-bit prescalers y two 16-bit input capture modules with 8-bit prescalers y multi-input wake up (miwu) with optional interrupts (8) y 8-bit stack pointer sp (stack in ram) y two 8-bit register indirect data memory pointers (b and x) y fourteen multi-source vectored interrupts servicing e external interrupt e idle timer t0 e two timers (each with 2 interrupts) e microwire/plus e multi-input wake up e software trap e uart (2) e default vis e capture timers e counters (one vector for all four counters) y versatile instruction set y true bit manipulation y memory mapped i/o y bcd arithmetic instructions y multiply/divide functions y package: 68-pin plcc y software selectable i/o options e tri-state output e push-pull output e weak pull-up input e high impedance input y schmitt trigger inputs on ports g and l y temperature range: b 40 cto a 85 c y form fit and function emulation device for the cop888gw y real time emulation and full program debug offered by metalink development system block diagram tl/dd/12527 1 figure 1. cop87l88gw block diagram tri-state is a registered trademark of national semiconductor corporation. microwire/plus tm , cops tm microcontrollers, microwire tm and cop8 tm are trademarks of national semiconductor corporation. ibm ,pc , pc-at and pc/xt are registered trademarks of international business machines corporation. icemaster tm is a trademark of metalink corporation. c 1996 national semiconductor corporation rrd-b30m96/printed in u. s. a. http://www.national.com
general description (continued) it is a fully static part, fabricated using double-metal silicon gate microcmos technology. the device is available as one-time programmable (otp). features include an 8-bit memory mapped architecture, microwire/plus serial i/o, two 16-bit timer/counters supporting three modes (processor independent pwm generation, external event counter and input capture mode capabilities), four indepen- dent 16-bit pulse train generators with 16-bit prescalers, two independent 16-bit input capture modules with 8-bit prescal- ers, multiply and divide functions, full duplex uart, and two power savings modes (halt and idle), both with a multi- sourced wake up/interrupt capability. this multi-sourced in- terrupt capability may also be used independent of the halt or idle modes. each i/o pin has software selectable configurations. the devices operate over a voltage range of 2.7v 5.5v. high throughput is achieved with an efficient, regular instruction set operating at a maximum of 1 m s per instruction rate. connection diagram tl/dd/12527 2 top view note: -x crystal oscillator -e halt enable order number COP87L88GWV-XE see ns plastic chip package number v68a figure 2. connection diagram http://www.national.com 2
absolute maximum ratings (note) suppiy voltage (v cc )7v voltage at any pin b 0.3v to v cc a 0.3v total current into v cc pin (source) 100 ma total current out of gnd pin (sink) 110 ma storage temperature range b 65 cto a 150 c note: absolute maximum ratings indicate limits beyond which damage to the device may occur. dc and ac electri- cal specifications are not ensured when operating the de- vice at absolute maximum ratings. dc electrical characteristics b 40 c s t a s a 85 c unless otherwise specified parameter conditions min typ max units operating voltage 2.7 5.5 v power supply ripple (note 1) peak-to-peak 0.1 v cc v supply current (note 2) cki e 10 mhz v cc e 5.5v, t c e 1 m s14ma halt current (note 3) v cc e 5.5v, cki e 0 mhz 12 m a idle current cki e 10 mhz v cc e 5.5v 1.7 ma input levels (v ih ,v il ) reset , cki logic high 0.8 v cc v logic low 0.2 v cc v all other inputs logic high 0.7 v cc v logic low 0.2 v cc v hi-z input leakage v cc e 5.5v b 2 a 2 m a input pullup current v cc e 5.5v, v in e 0v 40 b 250 m a g port input hysteresis (note 6) 0.05 v cc 0.35 v cc v output current levels d outputs source v cc e 4.5v, v oh e 3.3v b 0.4 ma sink (note 4) v cc e 4.5v, v ol e 1v 10 ma all others source (weak pull-up mode) v cc e 4.5v, v oh e 2.7v b 10 b 100 m a source (push-pull mode) v cc e 4.5v, v oh e 3.3v b 0.4 ma sink (push-pull mode) v cc e 4.5v, v ol e 0.4v 1.6 ma tri-state leakage v cc e 5.5v b 2 a 2 m a allowable sink/source current per pin d outputs (sink) 15 ma all others 3ma maximum input current room temp g 200 ma without latchup (note 5, 7) ram retention voltage, v r (note 6) 500 ns rise and fall time (min) 2 v input capacitance (note 7) 7 pf load capacitance on d2 (note 7) 1000 pf http://www.national.com 3
ac electrical characteristics b 40 c s t a s a 85 c unless otherwise specified parameter conditions min typ max units instruction cycle time (t c ) crystal, resonator 1.0 dc m s ceramic cki clock duty cycle (note 6) f e max 40 60 % rise time (note 6) f e 10 mhz ext clock 5 m s fall time (note 6) f e 10 mhz ext clock 5 m s inputs t setup v cc t 4.5v 200 ns t hold v cc t 4.5v 60 ns output propagation delay (note 9) r l e 2.2k, c l e 100 pf t pd1 ,t pd0 so, sk v cc t 4.5v 0.7 m s all others v cc t 4.5v 1 m s microwire tm setup time (t uws ) (note 7) v cc t 4.5v 20 microwire hold time (t uwh ) (note 7) v cc t 4.5v 56 ns microwire output propagation delay (t upd )v cc t 4.5v 220 input pulse width (note 8) interrupt input high time 1 interrupt input low time 1 t c timer 1, 2 input high time 1 timer 1, 2 input low time 1 capture timer high time 1 cki capture timer low time 1 cki reset pause width 1 m s note 1: maximum rate of voltage change to be defined. note 2: supply current is measured after running 2000 cydes with a square wave cki input, cko open, inputs at rails and outputs open. note 3: the halt mode will stop cki from oscillatng. test conditions: all inputs tied to v cc , l, c, e, f, and g port i/o's configured as outputs and programmed low and not driving a load; d outputs programmed low and not driving a load. parameter refers to halt mode entered via setting bit 7 of the g port data register. part will pull up cki during halt in crystal clock mode. note 4: the user must guarantee that d2 pin does not source more than 10 ma during reset. if d2 sources more than 10 ma during reset, the device will go into programming mode. note 5: pins g6 and reset are designed with a high voltage input network. these pins allow input voltages greater than v cc and the pins will have sink current to v cc when biased at voltages greater than v cc (the pins do not have source current when biased at a voltage below v cc .) the effective resistance to v cc is 750 x (typical). these two pins will not latch up. the voltage at the pins must be limited to less than 14v. warning: voltages in excess of 14v will cause damage to the pins. this warning excludes esd transients. note 6: condition and parameter valid only for part in halt mode. note 7: parameter characterized but not tested. note 8: t c e instruction cycle time note 9: the output propagation delay is referenced to the end of the instruction cycle where the output change occurs. tl/dd/12527 3 figure 3. microwire/plus timing http://www.national.com 4
pin descriptions v cc and gnd are the power supply pins. all v cc and gnd pins must be connected. cki is the clock input. this comes from a crystal oscillator (in conjunction with cko). see oscillator description sec- tion. reset is the master reset input. see reset description section. the device contains five bidirectional 8-bit i/o ports (c, e, f, g and l), where each individual bit may be independently configured as an input (schmitt trigger inputs on ports l and g), output or tri-state under program control. three data memory address locations are allocated for each of these i/o ports. each i/o port has two associated 8-bit memory mapped registers, the configuration register and the output data register. a memory mapped address is also reserved for the input pins of each i/o port. (see the memo- ry map for the various addresses associated with the i/o ports.) figure 4 shows the i/o port configurations. the data and configuration registers allow for each port bit to be individually configured under software control as shown below: configuration data port set-up register register 0 0 hi-z input (tri-state output) 0 1 input with weak pull-up 1 0 push-pull zero output 1 1 push-pull one output port l is an 8-bit i/o port. all l-pins have schmitt triggers on the inputs. the port l supports multi-input wake up on all eight pins. l1 is used for the uart external clock. l2 and l3 are used for the uart transmit and receive. l4 and l5 are used for the timer input functions t2a and t2b. l6 and l7 are used for the capture timer input functions cap1 and cap2. the port l has the following alternate features: l0 miwu l1 miwu or ckx l2 miwu or tdx l3 miwu or rdx l4 miwu or t2a l5 miwu or t2b l6 miwu or cap1 l7 miwu or cap2 port g is an 8-bit port with 6 i/o pins (g0 g5), an input pin (g6), and a dedicated output pin (g7). pins g0 g6 all have schmitt triggers on their inputs. pin g7 serves as the dedi- cated output pin for the cko clock output. there are two registers associated with the g port, a data register and a configuration register. therefore, each of the 6 i/o bits (g0 g5) can be individually configured under software con- trol. tl/dd/12527 4 figure 4. i/o port configurations http://www.national.com 5
pin descriptions (continued) since g6 is an input only pin and g7 is dedicated cko clock output pin, the associated bits in the data and configuration registers for g6 and g7 are used for special purpose func- tions as outlined below. reading the g6 and g7 data bits will return zeros. note that the chip will be placed in the halt mode by writ- ing a ``1'' to bit 7 of the port g data register. similarly the chip will be placed in the idle mode by writing a ``1'' to bit 6 of the port g data register. writing a ``1'' to bit 6 of the port g configuration register enables the microwire/plus to operate with the alter- nate phase of the sk clock. config reg. data reg. g7 not used halt g6 alternate sk idle port g has the following alternate features: g0 intr (externai interrupt input) g2 t1b (timer t1 capture input) g3 t1a (timer t1 i/o) g4 so (microwire serial data output) g5 sk (microwire seriai clock) g6 si (microwire serial data input) port g has the following dedicated functions: g7 cko osciilator dedicated output ports c and f are 8-bit i/o ports. port e is an 8-bit i/o port. it has the following alternate features: e0 ct1 (output for counter1, puise train generator) e1 ct2 (output for counter2, pulse train generator) e2 ct3 (output for counter3, puise train generator) e3 ct4 (output for counter4, pulse train generator) port i is an eight-bit hi-z input port. port d is an 8-bit output port that is preset high when reset goes iow. the user can tie two or more d port out- puts (except d2) together in order to get a higher drive. note: care must be exercised with the d2 pin operation. at reset, the external loads on this pin must ensure that the output voltages stay above 0.8 v cc to prevent the chip from entering special modes. also keep the external loading on d2 to k 1000 pf. functional description the architecture of the device is modified harvard architec- ture. with the harvard architecture, the control store pro- gram memory (rom) is separated from the data store mem- ory (ram). both rom and ram have their own separate addressing space with separate address buses. the archi- tecture, though based on harvard architecture, permits transfer of data from rom to ram. cpu registers the cpu can do an 8-bit addition, subtraction, logical or shift operation in one instruction (t c ) cycle time. there are six cpu registers: a is the 8-bit accumulator register pc is the 15-bit program counter register pu is the upper 7 bits of the program counter (pc) pl is the lower 8 bits of the program counter (pc) b is an 8-bit ram address pointer, which can be optionally post auto incremented or decremented. x is an 8-bit alternate ram address pointer, which can be optionally post auto incremented or decremented. sp is the 8-bit stack pointer, which points to the subroutine/ interrupt stack (in ram). the sp is initialized to ram ad- dress 06f with reset. s is the 8-bit data segment address register used to ex- tend the iower haif of the address range (00 to 7f) into 256 data segments of 128 bytes each. all the cpu registers are memory mapped with the excep- tion of the accumuiator (a) and the program counter (pc). program memory the program memory consists of 16 kbytes of otp eprom. these bytes may hoid program instructions or con- stant data (data tables for the laid instruction, jump vectors for the jid instruction, and interrupt vectors for the vis in- struction). the program memory is addressed by the 15-bit program counter (pc). all interrupts in the devices vector to program memory location 0ff hex. the device can be configured to inhibit external reads of the program memory. this is done by programming the security byte. security feature the program memory array has an associate security byte that is located outside of the program address range. this byte can be addressed only from programming mode by a programmer tool. security is an optional feature and can only be asserted after the memory array has been programmed and verified. a secured part will read all 00(hex) by a programmer. the part will fail blank check and will fail verify operations. a read operation will fill the programmer's memory with 00(hex). the security byte itself is always readable with val- ue of 00(hex) if unsecure and ff(hex) if secure. data memory the data memory address space includes the on-chip ram and data registers, the i/o registers (configuration, data and pin), the control registers, the microwire/plus sio shift register, and the various registers, and counters asso- ciated with the timers (with the exception of the idle timer). data memory is addressed directly by the instruction or indi- rectly by the b, x, sp pointers and s register. the data memory consists of 512 bytes of ram. sixteen bytes of ram are mapped as ``registers'' at addresses 0f0 to 0ff hex. these registers can be loaded immediately, and also decremented and tested with the drsz (decre- ment register and skip if zero) instruction. the memory pointer registers x, sp, b and s are memory mapped into this space at address locations 0fc to 0ff hex respective- ly, with the other registers being available for general usage. the instruction set permits any bit in memory to be set, reset or tested. all i/o and registers (except a and pc) are memory mapped; therefore, i/o bits and register bits can be directly and individually set, reset and tested. the accumu- lator (a) bits can also be directly and individually tested. note: ram contents are undefined upon power-up. data memory segment ram extension data memory address 0ff is used as a memory mapped location for the data segment address register (s). http://www.national.com 6
data memory segment ram extension (continued) the data store memory is either addressed directly by a single-byte address within the instruction, or indirectly rela- tive to the reference of the b, x, or sp pointers (each con- tains a single-byte address). this single-byte address allows an addressing range of 256 locations from 00 to ff hex. the upper bit of this single-byte address divides the data store memory into two separate sections as outlined previ- ously. with the exception of the ram register memory from address locations 00f0 to 00ff, all ram memory is memo- ry mapped with the upper bit of the single-byte address be- ing equal to zero. this allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 to 00ff) is extended. if this upper bit equals one (representing address range 0080 to 00ff), then address extension does not take place. alternatively, if this upper bit equals zero, then the data segment extension register s is used to extend the base address range (from 0000 to 007f) from xx00 to xx7f, where xx represents the 8 bits from the s register. thus the 128-byte data segment extensions are located from addresses 0100 to 017f for data segment 1, 0200 to 027f for data segment 2, etc., up to ff00 to ff7f for data segment 255. the base address range from 0000 to 007f represents data segment 0. figure 5 illustrates how the s register data memory exten- sion is used in extending the lower half of the base address range (00 to 7f hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from xx00 to xx7f. this organization allows a total of 256 data seg- ments of 128-bytes each with an additional upper base seg- ment of 128 bytes. furthermore, all addressing modes are availabie for all data segments. the s register must be changed under program control to move from one data seg- ment (128 bytes) to another. however, the upper base seg- ment (containing the 16 memory registers, i/o registers, controi registers, etc.) is always available regardless of the contents of the s register, since the upper base segment (address range 0080 to 00ff) is independent of data seg- ment extension. the instructions that utilize the stack pointer (sp) always reference the stack as part of the base segment (segment 0), regardless of the contents of the s register. the s regis- ter is not changed by these instructions. consequently, the stack (used with subroutine linkage and interrupts) is always located in the base segment. the stack pointer will be initial- ized to point at data memory location 006f as a result of reset. the 128 bytes of ram contained in the base segment are split between the iower and upper base segments. the first 112 bytes of ram are resident from address 0000 to 006f in the iower base segment, while the remaining 16 bytes of ram represent the 16 data memory registers located at ad- dresses 00f0 to 00ff of the upper base segment. no ram is located at the upper sixteen addresses (0070 to 007f) of the lower base segment. additional ram beyond these initial 128 bytes, however, will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (xx00 to xx7f) of the lower base segment. the additional 384 bytes of ram in this device are memory mapped at address locations 0100 to 017f 0200 to 027f, and 0300 to 037f hex. tl/dd/12527 5 * reads as all ones. figure 5. ram organization http://www.national.com 7
reset this device enters a reset state immediately upon detecting a logic low on the reset pin. the reset pin must be held low for a minimum of one instruction cycle to guarantee a valid reset. during power-up initialization, the user must in- sure that the reset pin is held low until this device is within the specified v cc voltage. an r/c circuit on the reset pin with a delay 5 times (5x) greater than the power supply rise time is recommended. when the reset input goes low, the i/o ports are initial- ized immediately, with any observed delay being only propa- gation delay. when the reset pin goes high, this device comes out of the reset state synchronously. this device will be running within two instruction cycles of the reset pin going high. reset may also be used to exit this device from the halt mode. some registers are reset to a known state, whereas other registers and ram are ``unchanged'' by reset. when the controller goes into reset state while it is performing a write operation to one of these registers or ram that are ``un- changed'' by reset, the register or ram value will become unknown (i.e. not unchanged). this is because the write op- eration is terminated prematurely by reset and the results become uncertain. these registers and ram locations are unchanged by reset only if they are not written to when the controller resets. the following initializations occur with reset : port l: tri-state port c: tri-state port g: tri-state port e: tri-state port f: tri-state port d: high pc: cleared psw, cntrl and icntrl registers: cleared sior: unaffected after reset with power already applied random after reset at power-on t1cntrl: cleared t2cntrl: cleared txra, txrb: random ccmr1, ccmr2: cleared cm1psc, cm1crl, cm1crh, cm2psc, cm2crl, and cm2crh: unaffected after reset with power already applied random after reset at power-on ccr1 and ccr2: cleared cxprh, cxprl, cxcth, and cxctl: random after reset at power-on psr, enur and enui: cleared enu: cleared except bit 1 (tbmt) e 1 accumulator, timer 1 and timer 2: random after reset with crystal clock option (power al- ready applied) unaffected after reset with rc clock option (power already applied) random after reset at power-on mdcr: cleared mdr1, mdr2, mdr3, mdr4, mdr5: random wken, wkedg: cleared wkpnd: random s register: cleared sp (stack pointer): loaded with 6f hex b and x pointers: unaffected after reset with power already applied random after reset at power-on ram: unaffected after reset with power already applied random after reset at power-on the external rc network shown in figure 6 should be used to ensure that the reset pin is held low until the power supply to the chip stabilizes. tl/dd/12527 6 rc l 5 c power supply rise time figure 6. recommended reset circuit oscillator circuits the chip can be driven by a clock input on the cki input pin which can be between dc and 10 mhz. the cko output clock is on pin g7 (crystal configuration), the cki input fre- quency is divided down by 10 to produce the instruction cycle clock (t c ). figure 7 shows the crystal diagram tl/dd/12527 7 figure 7. crystal diagram crystal oscillator cki and cko can be connected to make a closed loop crystal (or resonator) controlled oscillator. http://www.national.com 8
oscillator circuits (continued) table i shows the component values required for various standard crystal values. table i. crystai oscillator configuration, t a e 25 c r1 r2 c1 c2 cki freq conditions (k x )(m x ) (pf) (pf) (mhz) 0 1 30 30 36 10 v cc e 5v 0 1 30 30 36 4 v cc e 5v 0 1 200 100 150 0.455 v cc e 5v current drain the total current drain of the chip depends on: 1. oscillator operation modeei1 2. internal switching currentei2 3. internal leakage currentei3 4. output source currentei4 5. dc current caused by external input not at v cc or gndei5 thus the total current drain, it, is given as: it e i1 a i2 a i3 a i4 a i5 to reduce the total current drain, each of the above compo- nents must be minimum. the chip will draw more current as the cki input frequency increases up to the maximum 10 mhz value. operating with a crystal network will draw more current than an external square-wave. switching current, governed by the equation below, can be reduced by lowering voltage and frequency. leakage current can be reduced by lowering voltage and temperature. the other two items can be reduced by care- fully designing the end-user's system. i2 e c c v c f where c e equivalent capacitance of the chip v e operating voltage f e cki frequency control registers cntrl register (address x'00ee) the timer1 (t1) and microwire/plus control register contains the following bits: sl1 & select the microwire/plus clock divide by (00 e sl0 2, 01 e 4, 1x e 8) iedg external interrupt edge polarity select (0 e rising edge, 1 e falling edge) msel selects g5 and g4 as microwire/plus signals sk and so respectively t1c0 timer t1 start/stop control in timer modes 1 and 2 t1 underflow interrupt pending flag in timer mode 3 t1c1 timer t1 mode control bit t1c2 timer t1 mode control bit t1c3 timer t1 mode control bit t1c3 t1c2 t1c1 t1c0 msel iedg sl1 sl0 bit 7 bit 0 psw register (address x'00ef) the psw register contains the following select bits: gie giobai interrupt enable (enables interrupts) exen enabie externai interrupt busy microwire/plus busy shifting flag expnd externai interrupt pending t1ena timer t1 interrupt enable for timer underflow or t1a input capture edge t1pnda timer t1 interrupt pending flag (autoreload ra in mode 1, t1 underflow in mode 2, t1a capture edge in mode 3) c carry fiag hc half carry flag hc c t1pnda t1ena expnd busy exen gie bit 7 bit 0 the half-carry fiag is aiso affected by aii the instructions that affect the carry fiag. the sc (set carry) and rc (reset carry) instructions wili respectiveiy set or clear both the car- ry flags. in addition to the sc and rc instructions, adc, subc, rrc and rlc instructions affect the carry and half carry fiags. icntrl register (address x'00e8) the icntrl register contains the foilowing bits: t1enb timer t1 interrupt enable for t1b input capture edge t1pndb timer t1 interrupt pending flag for t1b capture edge m wen enabie microwire/plus interrupt m wpnd microwire/plus interrupt pending t0en timer t0 interrupt enable (bit 12 toggle) t0pnd timer t0 interrupt pending lpen l port interrupt enable (multi-input wake up/in- terrupt) bit 7 couid be used as a flag unused lpen t0pnd t0en m wpnd m wen t1pndb t1enb bit 7 bit 0 t2cntrl register (address x'00c6) the t2cntrl register contains the following bits: t2enb timer t2 interrupt enable for t2b input capture edge t2pndb timer t2 interrupt pending flag for t2b capture edge t2ena timer t2 interrupt enable for timer underflow or t2a input capture edge t2pnda timer t2 interrupt pending flag (auto reload ra in mode 1, t2 underflow in mode 2, t2a capture edge in mode 3) t2c0 timer t2 start/stop control in timer modes 1 and 2 timer t2 underflow interrupt pending flag in timer mode 3 t2c1 timer t2 mode control bit t2c2 timer t2 mode control bit t2c3 timer t2 mode control bit t2c3 t2c2 t2c1 t2c0 t2pnda t2ena t2pndb t2enb bit 7 bit 0 http://www.national.com 9
timers the device contains a very versatile set of timers (t0, t1, t2). all timers and associated autoreload/capture registers power up containing random data. timer t0 (idle timer) the device supports applications that require maintaining reai time and iow power with the idle mode. this idle mode support is furnished by the idle timer t0, which is a 16-bit timer. the timer t0 runs continuously at the fixed rate of the instruction cycle ciock, t c . the user cannot read or write to the idle timer t0, which is a count down timer. the timer t0 supports the following functions: # exit out of the idle mode (see idle mode description) # start up delay out of the halt mode the idle timer t0 can generate an interrupt when the thir- teenth bit toggies. this toggle is iatched into the t0pnd pending flag, and wiil occur every 4 ms at the maximum clock frequency (t c e 1 m s). a control flag t0en allows the interrupt from the thirteenth bit of timer t0 to be enabled or disabied. setting t0en will enable the interrupt, while reset- ting it will disable the interrupt. timer t1 and timer t2 the device has a set of two powerful timer/counter blocks, t1 and t2. the associated features and functioning of a timer block are described by referring to the timer block tx. since the two timer blocks, t1 and t2 are identical, all com- ments are equally applicable to either of the two timer blocks. each timer block consists of a 16-bit timer, tx, and two supporting 16-bit autoreload/capture registers, rxa and rxb. each timer block has two pins associated with it, txa and txb. the pin txa supports i/o required by the timer block, while the pin txb is an input to the timer block. the powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. the timer block has three operating modes: processor inde- pendent pwm mode, external event counter mode, and input capture mode. the control bits txc3, txc2, and txc1 allow selection of the different modes of operation. mode 1. processor independent pwm mode as the name suggests, this mode allows the device to gen- erate a pwm signal with very minimal user intervention. the user only has to define the parameters of the pwm signal (on time and off time). once begun, the timer block will continuously generate the pwm signal completely indepen- dent of the microcontroller. the user software services the timer block only when the pwm parameters require updat- ing. in this mode the timer tx counts down at a fixed rate of tc. upon every underflow the timer is alternately reloaded with the contents of supporting registers, rxa and rxb. the very first underflow of the timer causes the timer to reload from the register rxa. subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register rxb. the tx timer control bits, txc3, txc2 and txc1 set up the timer for pwm mode operation. figure 8 shows a block diagram of the timer in pwm mode. the underfiows can be programmed to toggle the txa out- put pin. the underfiows can also be programmed to gener- ate interrupts. underfiows from the timer are alternately latched into two pending flags, txpnda and txpndb. the user must reset these pending fiags under software control. two control en- abie fiags, txena and txenb, aliow the interrupts from the timer underflow to be enabled or disabled. setting the timer enable flag txena wili cause an interrupt when a timer un- derflow causes the rxa register to be reloaded into the tim- er. setting the timer enable flag txenb will cause an inter- rupt when a timer underflow causes the rxb register to be reloaded into the timer. resetting the timer enable flags will disable the associated interrupts. either or both of the timer underflow interrupts may be en- abled. this gives the user the flexibility of interrupting once per pwm period on either the rising or falling edge of the pwm output. alternatively, the user may choose to interrupt on both edges of the pwm output. mode 2. externai event counter mode this mode is quite similar to the processor independent pwm mode described above. the main difference is that the timer, tx, is ciocked by the input signal from the txa pin. the tx timer control bits, txc3, txc2 and txc1 allow the timer to be clocked either on a positive or negative edge from the txa pin. underflows from the timer are iatched into the txpnda pending flag. setting the txena control flag will cause an interrupt when the timer underflows. tl/dd/12527 8 figure 8. timer in pwm mode http://www.national.com 10
timers (continued) tl/dd/12527 9 figure 9. timer in external event counter mode in this mode the input pin txb can be used as an indepen- dent positive edge sensitive interrupt input if the txenb control flag is set. the occurrence of a positive edge on the txb input pin is latched into the txpndb flag. figure 9 shows a block diagram of the timer in external event counter mode. note: the pwm output is not available in this mode since the txa pin is being used as the counter input clock. mode 3. input capture mode the device can precisely measure external frequencies or time external events by placing the timer block, tx, in the input capture mode. in this mode, the timer tx is constantly running at the fixed t c rate. the two registers, rxa and rxb, act as capture registers. each register acts in conjunction with a pin. the register rxa acts in conjunction with the txa pin and the register rxb acts in conjunction with the txb pin. the timer value gets copied over into the register when a trigger event occurs on its corresponding pin. control bits, txc3, txc2 and txc1, allow the trigger events to be speci- fied either as a positive or a negative edge. the trigger con- dition for each input pin can be specified independently. the trigger conditions can also be programmed to generate interrupts. the occurrence of the specified trigger condition on the txa and txb pins will be respectively iatched into the pending flags, txpnda and txpndb. the control flag txena allows the interrupt on txa to be either enabled or disabled. setting the txena flag enables interrupts to be generated when the selected trigger condi- tion occurs on the txa pin. similarly, the flag txenb con- trols the interrupts from the txb pin. underflows from the timer can also be programmed to gen- erate interrupts. underflows are latched into the timer txc0 pending flag (the txc0 control bit serves as the timer under- flow interrupt pending flag in the input capture mode). con- sequently, the txc0 control bit should be reset when enter- ing the input capture mode. the timer underflow interrupt is enabled with the txena control flag. when a txa interrupt occurs in the input capture mode, the user must check both the txpnda and txc0 pending flags in order to determine whether a txa input capture or a timer underflow (or both) caused the interrupt. figure 10 shows a block diagram of the timer in input cap- ture mode. tl/dd/12527 10 figure 10. timer in input capture mode http://www.national.com 11
timers (continued) timer control flags the timers t1 and t2 have identical control structures. the control bits and their functions are summarized below. txc0 timer start/stop control in modes 1 and 2 (proc- essor independent pwm and external event counter), where 1 e start, 0 e stop timer un- derfiow interrupt pending flag in mode 3 (input capture) txpnda timer interrupt pending flag txpndb timer interrupt pending flag txena timer interrupt enable flag txenb timer interrupt enable flag 1 e timer interrupt enabled 0 e timer interrupt disabled txc3 timer mode control txc2 timer mode control txc1 timer mode control capture timer this device contains two independent capture timers, cap- ture timer 1 and capture timer 2. each capture timer con- tains an 8-bit programmable prescaler register, a 16-bit down counter, a 16-bit input capture register, and capture edge select logic. the 16-bit down counter is clocked at a specific frequency determined by the value loaded into the prescaler register. a selected positive or negative edge transition on the capture input causes the contents of the down counter to be latched into the capture register. the values captured in the registers reflect the elapsed time be- tween two positive or two negative transitions on the cap- ture input. the time between a positive and negative edge (a pulse width) may be measured if the selected capture edge is switched after the first edge is captured. each cap- ture timer may be stopped/started under software control, and each capture timer may be configured to interrupt the microcontroller on an underflow or input capture. figure 11 shows the capture timer 1 block diagram. the timer mode control bits (txc3, txc2 and txc1) are detailed below: table ii. timer mode control txc3 txc2 txc1 timer mode interrupt a interrupt b timer source source counts on 0 0 0 mode 2 (external event counter) timer underflow positive txb edge txa positive edge 0 0 1 mode 2 (external event counter) timer underflow positive txb edge txa negative edge 1 0 1 mode 1 (pwm) txa toggle autoreload ra autoreload rb t c 1 0 0 mode 1 (pwm) no txa toggle autoreload ra autoreload rb t c 0 1 0 mode 3 (capture) captures: positive txa edge or positive txb edge t c txa positive edge timer underflow txb positive edge 1 1 0 mode 3 (capture) captures: positive txa edge or negative txb edge t c txa positive edge timer underflow txb negative edge 0 1 1 mode 3 (capture) captures: negative txb edge or positive txb edge t c txa negative edge timer underflow txb positive edge 1 1 1 mode 3 (capture) captures: negative txa edge or negative txb edge t c txa negative edge timer underflow txb negative edge http://www.national.com 12
timers (continued) tl/dd/12527 11 figure 11. capture timer 1 block diagram the registers shown in the block diagram include those for capture timer 1 (cm1), as well as, the capture timer 1 con- trol register. these registers are read/writable (with the ex- ception of the capture registers, which are read-only) and may be accessed through the data memory address/data bus. the registers are designated as: cm1psc capture timer 1 prescaler (8-bit) cm1crl capture timer 1 capture register (low-byte), read-only cm1crh capture timer 1 capture register (high-byte), read-only cm2psc capture timer 2 prescaler (8-bit) cm2crl capture timer 2 capture register (low-byte), read-only cm2crh capture timer 2 capture register (high-byte), read-only ccmr1 control register for capture timer 1 ccmr2 control register for capture timer 2 control register bits the control bits for capture timer 1 (cm1) and capture timer 2 (cm2) are contained in ccmr1 and ccmr2. the ccmr1 register bits are: cm1run cm1 start/stop control bit (1 e start; 0 e stop) cm1ien cm1 interrupt enable control bit (1 e enable irq) cm1ip1 cm1 interrupt pending bit 1 (1 e cm1 under- flowed) cm1ip2 cm1 interrupt pending bit 2 (1 e cm1 captured) cm1ec select the active edge for capture on cm1 (0 e rising, 1 e falling) cm1tm cm1 test mode control bit (1 e special test path in test mode. this bit is reserved during normal operation, and must never be set to one.) cm1 un- un- cm1 cm1 cm1 cm1 cm1 tm used used ec ip2 ip1 ien run bit 7 bit 0 all interrupt pending bits must be reset by software. http://www.national.com 13
timers (continued) the ccmr2 register bits are: cm2run cm2 start/stop control bit (1 start; 0 e stop) cm2ien cm2 interrupt enable control bit (1 e enable irq) cm2ip1 cm2 interrupt pending bit 1 (1 e cm2 under- flowed) cm2ip2 cm2 interrupt pending bit 2 (1 e cm2 captured) cm2ec select the active edge for capture on cm2 (0 e rising, 1 e falling) cm2tm cm2 test mode control bit (1 e speciai test path in test mode. this bit is reserved during normal operation, and must never be set to one.) cm2 un- un- cm2 cm2 cm2 cm2 cm2 tm used used ec ip2 ip1 ien run bit 7 bit 0 aii interrupt pending bits must be reset by software. functional description the capture timer is used to determine the time between events, where an event is simply a selected edge transition on the capture input. the resolution of the time measure- ment is dependent on the frequency at which the down counter is clocked. the vaiue ioaded into the prescaler con- trols this frequency. the prescaier is clocked by cki, while the down counter is clocked on every underfiow of the prescaler. this means the prescaier simpiy divides the cki ciock before it is fed into the down counter. the prescaler register must be ioad- ed with a vaiue corresponding to the cki divisor needed to produce the desired down counter clock. the appropriate prescaler vaiue can be determined using the following equation: down counter clock frequency e cki/(cmxpsc a 1) the capture input signai is set up by configuring the port pin associated with the capture timer as an input. the edge seiect bit for the capture input is then set or reset according to the desired transition. if the pin is configured as an input, the appropriate externai transition will cause a capture. if the pin is configured as an output, toggling the data register bit wiil cause a capture. if interrupts are used, the capture timer interrupt pending bits are cieared and the capture tim- er interrupt enable bit is set. both interrupt sources, down counter underflow and input capture edge, are enabled/dis- abled with the same cmxien bit. the gie bit must also be set to enable interrupts. the interrupt signals from the two capture timers are gated to a single 16-bit interrupt vector located at addresses 0xe6 and 0xe7. the capture timer is started by writing a ``1'' to the capture timer start/stop bit. setting this bit also enables the port pin to be the capture input to the capture timer. the internal prescaler is loaded with the contents of the prescaler regis- ter, and begins counting down. setting the start/stop bit also loads the down counter with 0ffff hex. the prescaler is clocked by cki. an underflow of the prescaler decre- ments the 16-bit down counter, and reloads the value from the prescaler register into the prescaler. each additional un- derflow of the prescaler decrements the down counter, and reloads the prescaler from the prescaler register. if a selected edge transition on the input capture pin occurs, the contents of the down counter are immediately latched into the capture register, the down counter is re-initialized to 0ffff hex, and the capture input pending flag is set. the prescaler counter is not loaded. (in order for an input tran- sition to be guaranteed recognized, the signal on the cap- ture input pin must have a low pulse width and a high pulse width of at least one cki period.) if interrupts are enabled, the capture timer generates an interrupt. the prescaler and down counter continue to operate until a reset condition occurs or the capture timer start/stop bit is reset. the user must process capture interrupts faster than the capture in- put frequency, otherwise input captures may be lost or erro- neous values may be read. if the down counter underflows (changes state from 0000 to ffff) before a capture input is detected, the underflow in- terrupt pending flag is set. if interrupts are enabled, the cap- ture timer generates an interrupt. the capture timer may be stopped at any time under soft- ware control by resetting the capture timer start/stop bit. a capture may occur before the start/stop bit is physically cieared, due to the fully asynchronous nature of the input capture signal. the user must ensure that the software han- dles this situation correctly. if the user wishes to process this capture and interrupts are being used, the capture timer interrupts should not be disabied prior to stopping the timer. if interrupts are not being used, the user should poll the capture timer pending bits after stopping the timer. if the user wishes to ignore this capture and interrupts are being used, the capture timer interrupt service routine should check that the timer is still running prior to processing cap- ture interrupts. if the user is polling the pending flags, these flags should be cleared after the timer is stopped. the con- tents of the prescaler and down counter remain unchanged while the capture timer is stopped. the capture edge detect logic is disabled, and no capture takes place even if an external capture signal occurs. the capture timer may be restarted under software control by writing a ``1'' to the start/stop bit. this causes the prescaler and down counter to be re-initialized. the prescaler is loaded from the prescal- er register, and the down counter is loaded with 0ffff hex. reset state a reset signal applied to the counter block during normal operation has the following effects: # clear ccmr1 register # clear ccmr2 register # cm1psc, cmicrl, cm1crh, cm2psc, cm2crl and cm2crh are unaffected. (at power-on, the contents of these registers are undefined.) the bi-directional port pins are initialized during reset as hi-z inputs. setting the start/stop bits connects the pins to the capture timers. http://www.national.com 14
timers (continued) initialization the user should perform the following initialization prior to starting the capture timer: 1. reset the cmxrun bit 2. configure the corresponding port bits as inputs 3. set the edge control bits cmxec 4. reset cmxip1 (cmxip1 e 0) 5. reset cmxip2 (cmxip2 e 0) 6. load the 8-bit prescaler register cmxpsc with the de- sired value (from 0 to 255) 7. set cmxien (if interrupts are to be used) 8. set the global interrupt enable (gie) bit (if interrupts are to be used) 9. set cmxrun bit to start the capture timer warning in order to avoid erroneous interrupts, the capture timer in- terrupts must be disabled prior to setting/resetting the cap- ture edge control bits (cmxec). in addition, after selecting the interrupt edge, the pending flags must be reset before the capture interrupts are enabled or re-enabled. if the ini- tialization sequence outlined above is followed each time the user aiters the edge control bits, the user is guaranteed to avoid erroneous interrupts. pulse train generators this device contains four independent pulse train genera- tors. each individual generator is controlled by a corre- sponding 16-bit counter. each counter has a 16-bit prescal- er and a 16-bit count register. each counter may be config- ured to output a selected number of 50% duty cycle pulses. the contents of the prescaler determine the width of the output pulses, and the value of the count register deter- mines the number of pulses. each counter may be stopped/ started under software control, and each counter may be configured to interrupt the microcontroller on an underflow. figure 12 shows the pulse train generator 1 block diagram. tl/dd/12527 12 figure 12. pulse train generator 1 block diagram http://www.national.com 15
pulse train generators (continued) the four 8-bit registers shown in each individual counter in the block diagram constitute a 16-bit prescaler and a 16-bit count register. these registers are all read/writable and may be accessed through the data memory address/data bus. the registers are designated as: cxprl low-byte of the prescaler cxprh high-byte of the prescaler cxctl low-byte of the count register cxcth high-byte of the count register control register bits the control bits for counter 1 and counter 2 are contained in the ccr1 register. the ccr1 register bits are: c1run counter1 start/stop control bit (1 e start; 0 e stop) c1ien counter1 interrupt enable control bit (1 e en- able irq) c1ipnd counter1 interrupt pending bit (1 e counter 1 underflowed) c1tm counter1 test mode control bit (1 e special test path in test mode. this bit is reserved during nor- mal operation, and must never be set to one.) c2run counter2 start/stop control bit (1 e start; 0 e stop) c2ien counter2 interrupt enable control bit (1 e en- able irq) c2ipnd counter2 interrupt pending bit (1 e counter 2 underflowed) c2tm counter2 test mode control bit (1 e special test path. this bit is reserved during normal operation, and must never be set to one.) all interrupt pending bits must be reset by software. c2tm c2 c2 c2 c1tm c1 c1 c1 ipnd ien run ipnd ien run bit 7 bit 0 the control bits for counter 3 and counter 4 are contained in the ccr2 register. the ccr2 register bits are: c3run counter3 start stop control bit (1 e start; 0 e stop) c3ien counter3 interrupt enable control bit (1 e en- able irq) c3ipnd counter3 interrupt pending bit (1 e counter 3 underflowed) c3tm counter3 test mode control bit (1 e special test path. this bit is reserved during normal operation, and must never be set to one.) c4run counter4 start/stop control bit (1 e start; 0 e stop) c4ien counter4 interrupt enable control bit (1 e en- able irq) c4ipnd counter4 interrupt pending bit (1 e counter 4 underflowed c4tm counter4 test mode control bit (1 e special test path. this bit is reserved during normal operation, and must never be set to one.) c4tm c4 c4 c4 c3tm c3 c3 c3 ipnd ien run ipnd ien run bit 7 bit 0 all interrupt pending bits must be reset by software. functional description the pulse train generator may be used to produce a series of output pulses of a given width. the high/low time of a pulse is determined by the contents of the prescaler. the number of pulses in a series is determined by the contents of the count register. the prescaler is loaded with a value corresponding to the desired width of the output pulse (t w ). the high time and low time of the output signal are each equal to t w , therefore the output signal produced has a 50% duty cycle and a period equal to 2 * t w . the appropriate prescaler value can be determined using the following equation: t w e [ (prh * 256) a prl a 1 ] * t c since prh and prl are both 8-bit registers, this equation allows a maximum t w of 65536 t c and a minimum t w of one t c . the internal prescaler is automatically loaded from prh and prl when the counter start/stop bit is set. the count register is loaded with a value corresponding to the desired number of output pulses. the appropriate count value is calculated with the following equation: number of pulses e cth * 256 a ctl a 1 the port pin associated with the counter out signal is con- figured in software as an output, and preset to the desired start logic level. lf interrupts are to be used, the counter interrupt pending bit is cleared and the interrupt enable bit is set. the gie bit must also be set to enable interrupts. the interrupt signals from the four counters are gated to a single interrupt vector located at addresses 0xf0 0xf1. the counter is started by writing a ``1'' to the counter start/ stop bit. this resets the divide-by-2 counter which produces the clock signal for the counter register from the prescaler underflow (see figure 12 ). it also reloads the internal pre- scaler and starts the prescaler counting down on the next rising edge of t c . the prescaler is clocked on the rising edge of t c to ensure synchronization. each subsequent rising edge of t c causes the prescaler to be decremented. when the prescaler underflows, ufl1 is generated (see figure 13 ). this signal causes the port pin to toggle. in addition, the internal prescaler is reloaded with the value from the prh and prl registers. each additional underflow of the prescal- er causes the port pin to toggle and reloads the internal prescaler. every second underflow of the prescaler generates the sig- nal ufl2. (ufl2 occurs at half the frequency of ufl1, or once per output pulse.) this signal, ufl2, decrements the count register. therefore, the count registers are decre- mented once per output pulse. http://www.national.com 16
pulse train generators (continued) the underflow of the counter register produces the signal ufl3. this signal stops the counter by resetting the counter start/stop bit, and sets the counter interrupt pending flag. if the counter interrupt is enabled, an interrupt occurs. the counter may be stopped at any time under software control by resetting the counter start/stop bit. the contents of the count register and the output on the associated port pin are frozen. the counter may be restarted under software control by setting the start/stop bit. the internal prescaler is automatically reloaded from prh and prl when the coun- ter start/stop bit is set, therefore a full width pulse will be generated before the output is toggled. the user may also choose to alter the logic level on the port pin before restart- ing. this is done by initializing the associated port pin data register bit. a counter underflow may occur before the start/ stop bit is physically cleared by software. the user must ensure that the software handles this situation correctly. if the user wishes to process this underflow and interrupts are being used, the counter interrupts should not be disabled prior to stopping the timer. if interrupts are not being used, the user should poll the counter pending bits after stopping the timer. if the user wishes to ignore this underflow and interrupts are being used, the counter interrupt should be disabled prior to stopping the timer. if the user is polling the pending flags, these flags should be cleared after the timer is stopped. if the default level of the output pin is high (associated port data register bit is set to ``1'') and the counter is stopped during a low level, the low level becomes the default level. the software must reinitialize the port pin to a high level before restarting if necessary. the programmer may also have to adjust the counter value (see figure 13 ). reset state a reset signal applied to the pulse train generator block during normal operation has the following effects: # counting stops immediately # interrupt enable bit is reset to zero # counter start/stop bit is reset to zero # interrupt pending bit is reset to zero # test mode controi bit is reset to zero # prl, prh, ctl and cth are unaffected (at power-on reset, the contents of the prescaler and count register are undefined.) # divide-by-2 counter is reset # the bi-directional port pins are initialized during reset as hi-z inputs. the appropriate bits must be initialized as outputs, in order to route the counter out signals to the port pins. initialization the user should perform the following initialization prior to starting the counter: 1. load prl register 2. load prh register 3. load ctl register 4. load cth register 5. reset cxipnd bit 6. set cxien (if interrupt is to be used) 7. configure the associated port bit as an output (if out is to be used) 8. set the global interrupt enable (gie) bit (if interrupt is to be used) 9. set cxrun bit to start counter multiply/divide this device contains a multiply/divide block. this block sup- port s a 1 byte x 2 bytes (3 bytes result) multiply o r a 3 bytes/ 2 bytes (2 bytes result) divide operation. the multiply or divide operation is executed by setting control bits located in the multiply/divide control register. the multiply or divide operands must be placed into the appropriate memory mapped locations before the operation is initiated. figure 14 contains the block diagram of the multiply/divide block. it shows the registers contained within the multiply/ divide block. the registers shown in the block diagram are assigned ac- cording to table iii. tl/dd/12527 13 figure 13. timing diagram for prl e 1, prh e 0, ctl e 3, cth e 0 http://www.national.com 17
multiply/divide (continued) table iii. multiply/divide registers register name (address) multiplication assignment division assignment before operation after operation before operation after operation mdr1 (xx98) unused unchanged low byte of dividend low byte of result mdr2 (xx99) multiplier low byte of result middle byte of dividend high byte of result mdr3 (xx9a) middle byte of result high byte of dividend undefined mdr4 (xx9b) low byte of multiplicand high byte of result low byte of divisor low byte of divisor mdr5 (xx9c) high byte of multiplicand unchanged high byte of divisor high byte of divisor http://www.national.com 18
multiply/divide (continued) control register bits the multiply/divide control register (mdcr) is located at address xx9d. it has the following bit assignments: mult start multiplication operation (1 e start) div start division operation (1 e start) divovf division overflow (if the result of a division is greater than 16 bits or the user attempted to divide by zero; 1 e error) rsvd rsvd rsvd rsvd rsvd div div mult ovf bit 7 bit 0 after the appropriate mdr registers are loaded, the mult and div start bits are set by the user to start a multiply or divide operation. the division operation has priority, if both bits are set simultaneously. the mult and div bits are both automatically cleared by hardware at the end of a divide or multiply operation. each division operation causes the divovf flag to be set/reset as appropriate. the divovf flag is cleared following a multiplication operation. divovf is a read-only bit. the mult and div bits are read/ writable. bits 3 7 in mdcr should not be used, as the mult and div operations will change their values. multiply/divide operation for the multiply operation, the muitiplicand is placed at ad- dresses xx9b and xx9c. the multiplier is placed at address xx99. for the divide operation, the dividend is placed at ad- dresses xx98 to xx9a and the divisor is placed at addresses xx9b to xx9c. in both operations, all operands are interpret- ed as unsigned values. the divide or multiply operation is started by setting the appropriate mdcr bit. if both the mult and div bits are set, the microcontroller performs a divide operation. (the user is not required to read or clear the divovf error bit prior to beginning a new multiply/di- vide operation. this bit is ignored during subsequent opera- tions. however, the next divide operation will overwrite the error flag as appropriate, and the next multiply operation will clear it.) the multiply operation requires 1 instruction cycle to com- plete. the divide operation requires 2 instruction cycles to complete. a divide by zero or a division which produces an overflow requires only 1 instruction cycle to execute. the mdr1 through mdr5 registers and the mdcr register can not be read from or written to during a multiply or divide operation. any attempt to write into these registers will be ignored. any attempt to read these registers will return un- defined data. the result of a multiply is placed in addresses xx99-xx9b. the result of a divide is placed in addresses xx98-xx99. if a division by zero is attempted or if the resulting quotient of a divide operation is more than 16 bits long, then the divovf bit is set in the multiply/divide control register. the dividend and the divisor are left unchanged. the divide operation al- ways causes the divovf flag to be set or reset as appropri- ate. the divovf flag is cleared following a multiply opera- tion. reset state a reset signal applied to the device during normal operation has the following affects: mdcr is cleared, and any operation in progress is stopped. mdr1 through mdr5 are undefined. power save modes the device offers the user two power save modes of opera- tion: halt and idle. in the halt mode, all microcontroller activities are stopped. in the idle mode, the on-board oscil- lator circuitry and timer t0 are active but all other microcon- troller activities are stopped. in either mode, all on-board ram, registers, i/o states, and timers (with the exception of t0) are unaltered. halt mode the device can be placed in the halt mode by writing a ``1'' to the halt flag (g7 data bit). all microcontroller activi- ties, including the clock and timers, are stopped. in the halt mode, the power requirements of the device are mini- mal and the applied voltage (v cc ) may be decreased to v r (v r e 2.0v) without altering the state of lhe machine. the device supports two different ways of exiting the halt mode. the first method of exiting the halt mode is with the multi-input wakeup feature on the l port. the second meth- od of exiting the halt mode is by pulling the reset pin low. since a crystal or ceramic resonator may be selected as the oscillator, the wakeup signal is not allowed to start the chip running immediately since crystal oscillators and ceramic resonators have a delayed start up time to reach full ampli- tude and frequency stability. the idle timer is used to gen- erate a fixed deiay to ensure that the osciliator has indeed stabilized before allowing instruction execution. in this case, upon detecting a valid wakeup signal, only the oscillator circuitry is enabled. the idle timer is loaded with a value of 256 and is clocked with the t c instruction cycle clock. the t c clock is derived by dividing the oscillator clock down by a factor of 10. the schmitt trigger following the cki inverter on the chip ensures that the idle timer is clocked only when the oscillator has a sufficiently large amplitude to meet the schmitt trigger specifications. this schmitt trigger is not part of the oscillator closed loop. the startup timeout from the idle timer enables the clock signals to be routed to the rest of the chip. the devices have two mask options associated with the halt mode. the first mask option enables the halt mode feature, while the second mask option disables the halt mode. with the halt mode enable mask option, the device will enter and exit the halt mode as described above. with the halt disable mask option, the device cannot be placed in the halt mode (writing a ``1'' to the halt flag will have no effect, the halt flag will remain ``0''). idle mode the device is placed in the idle mode by writing a ``1'' to the idle flag (g6 data bit). in this mode, all activities, except the associated on-board oscillator circuitry and the idle timer t0, are stopped. http://www.national.com 19
power save modes (continued) as with the halt mode, the device can be returned to nor- mal operation with a reset, or with a multi-input wake up from the l port. alternately, the microcontroller resumes normal operation from the idle mode when the thirteenth bit (representing 4.096 ms at internal clock frequency of 10 mhz, t c e 1 m s) of the idle timer toggles. this toggle condition of the thirteenth bit of the idle timer t0 is latched into the t0pnd pending flag. the user has the option of being interrupted with a transition on the thirteenth bit of the idle timer t0. the interrupt can be enabled or disabled via the t0en control bit. setting the t0en flag enables the interrupt and vice versa. the user can enter the idle mode with the timer t0 inter- rupt enabled. in this case, when the t0pnd bit gets set, the device will first execute the timer t0 interrupt service rou- tine and then return to the instruction following the ``enter idle mode'' instruction. alternatively, the user can enter the idle mode with the idle timer t0 interrupt disabled. in this case, the device will resume normal operation with the instruction immediate- ly following the ``enter idle mode'' instruction. note: it is necessary to program two nop instructions following both the set halt mode and set idle mode instructions. these nop instructions are necessary to allow clock resynchronization following the halt or idle modes. multi-input wakeup the multi-input wake up feature is used to return (wake up) the device from either the halt or idle modes. alternately multi-input wake up/interrupt feature may also be used to generate up to 8 edge selectable external interrupts. figure 14 shows the multi-input wake up logic. tl/dd/12527 15 figure 14. multi-input wake up logic http://www.national.com 20
multi-input wakeup (continued) the multi-input wake up feature utilizes the l port. the user selects which particular l port bit (or combination of l port bits) will cause the device to exit the halt or idle modes. the selection is done through the register wken. the register wken is an 8-bit read/write register, which contains a control bit for every l port bit. setting a particular wken bit enables a wake up from the associated l port pin. the user can select whether the trigger condition on the selected l port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition). this selection is made via the register wkedg, which is an 8-bit control register with a bit assigned to each l port pin. setting the control bit will select the trigger condition to be a negative edge on that particular l port pin. resetting the bit selects the trigger condition to be a positive edge. changing an edge select entails several steps in order to avoid a wake up condition as a result of the edge change. first, the associated wken bit should be reset, followed by the edge select change in wkedg. next, the associated wkpnd bit should be cleared, followed by the associated wken bit being reenabled. an example may serve to clarify this procedure. suppose we wish to change the edge select from positive (low going high) to negative (high going low) for l port bit 5, where bit 5 has previously been enabled for an input interrupt. the pro- gram would be as follows: rbit 5, wken sbit 5, wkedg rbit 5, wkpnd sb1t 5, wken if the l port bits have been used as outputs and then changed to inputs with multi-input wake up/lnterrupt, a safety procedure should also be followed to avoid wakeup conditions. after the selected l port bits have been changed from output to input but before the associated wken bits are enabled, the associated edge select bits in wkedg should be set or reset for the desired edge selects, followed by the associated wkpnd bits being cleared, this same procedure should be used following reset, since the l port inputs are left floating as a result of reset. the occurrence of the selected trigger condition for multi-in- put wake up is latched into a pending register called wkpnd. the respective bits of the wkpnd register will be set on the occurrence of the selected trigger edge on the corresponding port l pin. the user has the responsibility of clearing these pending flags. since wkpnd is a pending register for the occurrence of selected wake up conditions, the device will not enter the halt mode if any wake up bit is both enabled and pending. consequently, the user must clear the pending flags before attempting to enter the halt mode. wken, wkpnd and wkedg are all read/write registers, and are cleared at reset. port l interrupts port l provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service subroutine. the interrupt from port l shares logic with the wake up cir- cuitry. the register wken allows interrupts from port l to be individually enabled or disabled. the register wkedg specifies the trigger condition to be either a positive or a negative edge. finally, the register wkpnd latches in the pending trigger conditions. the gie (global interrupt enable) bit enables the interrupt function. a control flag, lpen, functions as a global interrupt enable for port l interrupts. setting the lpen flag will enable inter- rupts and vice versa. a separate global pending flag is not needed since the register wkpnd is adequate. since port l is also used for waking the device out of the halt or ldle modes, the user can elect to exit the halt or idle modes either with or without the interrupt enabled. if he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the in- struction that placed the microcontroller in the halt or idle modes. in the other case, the device will first execute the interrupt service routine and then revert to normal oper- ation. (see halt mode for clock option wake up informa- tion.) http://www.national.com 21
uart the device contains a full-duplex software programmable uart. the uart ( figure 15 ) consists of a transmit shift register, a receive shift register and seven addressable reg- isters, as follows: a transmit buffer register (tbuf), a receiv- er buffer register (rbuf), a uart control and status regis- ter (enu), a uart receive control and status register (enur), a uart interrupt and clock source register (enui), a prescaler select register (psr) and baud (baud) register. the enu register contains flags for transmit and receive functions; this register also determines the length of the data frame (7, 8 or 9 bits), the value of the ninth bit in trans- mission, and parity selection bits. the enur register flags framing, data overrun and parity errors while the uart is receiving. other functions of the enur register include saving the ninth bit received in the data frame, enabling or disabling the uart's attention mode of operation and providing addition- al receiver/transmitter status information via rcvg and xmtg bits. the determination of an internal or external clock source is done by the enui register, as well as select- ing the number of stop bits and enabling or disabling trans- mit and receive interrupts. a control flag in this register can also select the uart mode of operation: asynchronous or synchronous. tl/dd/12527 16 figure 15. uart block diagram http://www.national.com 22
uart (continued) uart control and status registers the operation of the uart is programmed through three registers: enu, enur and enui. the function of the individ- ual bits in these registers is as follows: enu-uart control and status register (address at 0ba) pen psel1 xbit9/ chl1 chl0 err rbfl tbmt psel0 0rw 0rw 0rw 0rw 0rw 0r 0r ir bit 7 bit 0 enur-uart receive control and status register (address at 0bb) doe fe pe spare rblt9 attn xmtg rcvg 0rd 0rd 0rd 0rw * 0r 0rw 0r 0r bit 7 bit 0 enui-uart interrupt and clock source register (address at 0bc) stp2 stp78 etdx ssel xrclk xtclk eri eti 0rw 0rw 0rw 0rw 0rw 0rw 0rw 0rw bit 7 bit 0 * bit is not used. 0 bit is cleared on reset. 1 bit is set to one on reset. r bit is read-only; it cannot be written by software. rw bit is read/write. d bit is cleared on read; when read by software as a one, it is cleared automatically. writing to the bit does not affect its state. description of uart register bits enueuart control and status register tbmt: this bit is set when the uart transfers a byte of data from the tbuf register into the tsft register for trans- mission. it is automatically reset when software writes into the tbuf register. rbfl: this bit is set when the uart has received a com- plete character and has copied it into the rbuf register. it is automatically reset when software reads the character from rbuf. err: this bit is a global uart error flag which gets set if any or a combination of the errors (doe, fe, pe) occur. chl1, chl0: these bits select the character frame format. parity is not included and is generated/verified by hardware. chl1 e 0, chl0 e 0 the frame contains eight data bits. chl1 e 0, chl0 e 1 the frame continues seven data bits. chl1 e 1, chl0 e 0 the frame continues nine data bits. chl1 e 1, chl0 e 1 loopback mode selected. transmit- ter output internally looped back to receiver input. nine bit framing for- mat is used. xbit9/psel0: programs the ninth bit for transmission when the uart is operating with nine data bits per frame. for seven or eight data bits per frame, this bit in conjunction with psel1 selects parity. psel1, psel0: parity select bits. psel1 e 0, psel0 e 0 odd parity (if parity enabled) psel1 e 0, psel1 e 1 odd parity (if parity enabled) psel1 e 1, psel0 e 0 mark(1) (if parity enabled) psel1 e 1, psel1 e 1 space(0) (if parity enabled) pen: this bit enables/disables parity (7- and 8-bit modes only). pen e 0 parity disabled. pen e 1 parity enabled. enureuart receive control and status register rcvg: this bit is set high whenever a framing error occurs and goes low when rdx goes high. xmtg: this bit is set to indicate that the uart is transmit- ting. it gets reset at the end of the last frame (end of last stop bit). attn: attention mode is enabled while this bit is set. this bit is cleared automatically on receiving a character with data bit nine set. rbit9: contains the ninth data bit received when the uart is operating with nine data bits per frame. spare: reserved for future use. pe: flags a parity error. pe e 0 indicates no parity error has been detected since the last time the enur register was read. pe e 1 indicates the occurrence of a parity error. fe: flags a framing error. fe e 0 indicates no framing error has been detected since the last time the enur register was read. fe e 1 indicates the occurrence of a framing error. doe: flags a data overrun error. doe e 0 indicates no data overrun error has been detect- ed since the last time the enur register was read. doe e 1 indicates the occurrence of a data overrun error. enuieuart interrupt and clock source register eti: this bit enables/disables interrupt from the transmitter section. eti e 0 interrupt from the transmitter is disabled. eti e 1 interrupt from the transmitter is enabled. http://www.national.com 23
uart (continued) eri: this bit enables/disables interrupt from the receiver section. eri e 0 interrupt from the receiver is disabled. eri e 1 interrupt from the receiver is enabled. xtclk: this bit selects the clock source for the transmitter section. xtclk e 0 the clock source is selected through the psr and baud registers. xtclk e 1 signal on ckx (l1) pin is used as the clock. xrclk: this bit selects the clock source for the receiver section. xrclk e 0 the clock source is selected through the psr and baud registers. xrclk e 1 signal on ckx (l1) pin is used as the clock. ssel: uart mode select. ssel e 0 asynchronous mode. ssel e 1 synchronous mode. etdx: tdx (uart transmit pin) is the alternate function assigned to port l pin l2; it is selected by setting etdx bit. to simulate line break generation, software should reset etdx bit and output logic zero to tdx pin through port l data and configuration registers. stp78: this bit is set to program the last stop bit to be 7/8th of a bit in length. stp2: this bit programs the number of stop bits to be trans- mitted. stp2 e 0 one stop bit transmitted. stp2 e 1 two stop bits transmitted. associated i/o pins data is transmitted on the tdx pin and received on the rdx pin. tdx is the alternate function assigned to port l pin l2; it is selected by setting etdx (in the enui register) to one. rdx is an inherent function of port l pin l3, requiring no setup. the baud rate clock for the uart can be generated on- chip, or can be taken from an external source. port l pin l1 (ckx) is the external clock i/o pin. the ckx pin can be either an input or an output, as determined by port l config- uration and data registers (bit 1). as an input, it accepts a clock signal which may be selected to drive the transmitter and/or receiver. as an output, it presents the internal baud rate generator output. uart operation the uart has two modes of operation: asynchronous mode and synchronous mode. asynchronous mode this mode is selected by resetting the ssel (in the enui register) bit to zero. the input frequency to the uart is 16 times the baud rate. the tsft and tbuf registers double-buffer data for trans- mission. while tsft is shifting out the current character on the tdx pin, the tbuf register may be loaded by software with the next byte to be transmitted. when tsft finishes transmitting the current character the contents of tbuf are transferred to the tsft register and the transmit buffer empty flag (tbmt in the enu register) is set. the tbmt flag is automatically reset by the uart when software loads a new character into the tbuf register. there is also the xmtg bit which is set to indicate that the uart is transmit- ting. this bit gets reset at the end of the last frame (end of last stop bit). tbuf is a read/write register. the rsft and rbuf registers double-buffer data being re- ceived. the uart receiver continually monitors the signal on the rdx pin for a low level to detect the beginning of a start bit. upon sensing this low level, it waits for half a bit time and samples again. if the rdx pin is still low, the re- ceiver considers this to be a valid start bit, and the remain- ing bits in the character frame are each sampled a single time, at the mid-bit position. serial data input on the rdx pin is shifted into the rsft register. upon receiving the com- plete character, the contents of the rsft register are cop- ied into the rbuf register and the received buffer full flag (rbfl) is set. rbfl is automatically reset when software reads the character from the rbuf register. rbuf is a read only register. there is also the rcvg bit which is set high when a framing error occurs and goes low once rdx goes high. tbmt, xmtg, rbfl and rcvg are read only bits. synchronous mode in this mode data is transferred synchronously with the clock. data is transmitted on the rising edge and received on the falling edge of the synchronous clock. this mode is selected by setting ssel bit in the enui regis- ter. the input frequency to the uart is the same as the baud rate. when an external clock input is selected at the ckx pin, data transmit and receive are performed synchronously with this clock through tdx/rdx pins. if data transmit and receive are selected with the ckx pin as clock output, the device generates the synchronous clock output at the ckx pin. the internal baud rate genera- tor is used to produce the synchronous clock. data transmit and receive are performed synchronously with this clock. framing formats the uart supports several serial framing formats (figure 16) . the format is selected using control bits in the enu, enur and enui registers. the first format (1,1a, 1b, 1c) for data transmission (chl0 e 1, chl1 e 0) consists of start bit, seven data bits (ex- cluding parity) and 7/8, one or two stop bits. in applications using parity, the parity bit is generated and verified by hard- ware. the second format (chl0 e 0, chl1 e 0) consists of one start bit, eight data bits (excluding parity) and 7/8, one or two stop bits. parity bit is generated and verified by hard- ware. the third format for transmission (chl0 e 0, chl1 e 1) consists of one start bit, nine data bits and 7/8, one or two stop bits. this format also supports the uart ``atten- tion'' feature. when operating in this format, all eight bits of tbuf and rbuf are used for data. the ninth data bit is transmitted and received using two bits in the enu and enur registers, called xbit9 and rbit9. rbit9 is a read only bit. parity is not generated or verified in this mode. http://www.national.com 24
uart operation (continued) tl/dd/12527 17 figure 16. framing formats for any of the above framing formats, the last stop bit can be programmed to be 7/8th of a bit in length. if two stop bits are selected and the 7/8th bit is set (selected), the second stop bit will be 7/8th of a bit in length. the parity is enabled/disabled by pen bit located in the enu register. parity is selected for 7- and 8-bit modes only. if parity is enabled (pen e 1), the parity selection is then performed by psel0 and psel1 bits located in the enu register. note that the xbit9/psel0 bit located in the enu register serves two mutually exclusive functions. this bit programs the ninth bit for transmission when the uart is operating with nine data bits per frame. there is no parity selection in this framing format. for other framing formats xbit9 is not needed and the bit is psel0 used in conjunction with psel1 to select parity. the frame formats for the receiver differ from the transmit- ter in the number of stop bits required. the receiver only requires one stop bit in a frame, regardless of the setting of the stop bit selection bits in the control register. note that an implicit assumption is made for full duplex uart opera- tion that the framing formats are the same for the transmit- ter and receiver. uart interrupts the uart is capable of generating interrupts. interrupts are generated on receive buffer full and transmit buffer emp- ty. both interrupts have individual interrupt vectors. two bytes of program memory space are reserved for each inter- rupt vector. the two vectors are located at addresses 0xec to 0xef hex in the program memory space. the interrupts can be individually enabled or disabled using enable trans- mit interrupt (etl) and enable receive interrupt (erl) bits in the enui register. the interrupt from the transmitter is set pending, and re- mains pending, as long as both the tbmt and etl bits are set. to remove this interrupt, software must either clear the eti bit or write to the tbuf register (thus clearing the tbmt bit). the interrupt from the receiver is set pending, and remains pending, as long as both the rbfl and eri bits are set. to remove this interrupt, software must either clear the erl bit or read from the rbuf register (thus clearing the rbfl bit). baud clock generation the clock inputs to the transmitter and receiver sections of the uart can be individually selected to come either from an external source at the ckx pin (port l, pin l1) or from a source selected in the psr and baud registers. internally, the basic baud clock is created from the oscillator frequency through a two-stage divider chain consisting of a 1 16 (in- crements of 0.5) prescaler and an 11-bit binary counter (fig- ure 17) .the divide factors are specified through two read/ write registers shown in figure 18 . note that the 11-bit baud rate divisor spills over into the prescaler select register (psr). psr is cleared upon reset. http://www.national.com 25
baud clock generation (continued) tl/dd/12527 18 figure 17. uart baud clock generation tl/dd/12527 19 figure 18. uart baud clock divisor registers http://www.national.com 26
baud clock generation (continued) as shown in table v, a prescaler factor of 0 corresponds to no clock. this condition is the uart power down mode where the uart clock is turned off for power saving pur- pose. the user must also turn the uart clock off when a different baud rate is chosen. the correspondences between the 5-bit prescaler select and prescaler factors are shown in table v. there are many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 mhz fre- quency coming out of the first stage. the 1.8432 mhz pre- scaler output is then used to drive the software programma- ble baud rate counter to create a 16x clock for the following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 (table iv). other baud rates may be created by using appropriate divisors. the 16x clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receivers. table iv. baud rate divisors (1.8432 mhz prescaier output) baud baud rate rate divisor b 1 (n-1) 110 (110.03) 1046 134.5 (134.58) 855 150 767 300 383 600 191 1200 95 1800 63 2400 47 3600 31 4800 23 7200 15 9600 11 19200 5 38400 2 note: the entries in table iv assume a prescaier output of 1.8432 mhz. in asynchronous mode the baud rate could be as high as 625k. table v. prescaler factors prescaler prescaler select factor 00000 no clock 00001 1 00010 1.5 00011 2 00100 2.5 00101 3 00110 3.5 00111 4 01000 4.5 01001 5 01010 5.5 01011 6 01100 6.5 01101 7 01110 7.5 01111 8 10000 8.5 10001 9 10010 9.5 10011 10 10100 10.5 10101 11 10110 11.5 10111 12 11000 12.5 11001 13 11010 13.5 11011 14 11100 14.5 11101 15 11110 15.5 11111 16 http://www.national.com 27
baud clock generation (continued) as an example, considering asynchronous mode and a cki clock of 4.608 mhz, the prescaler factor selected is: 4.608/1.8432 e 2.5 the 2.5 entry is available in table v. the 1.8432 mhz pre- scaler output is then used with proper baud rate divisor (table v) to obtain different baud rates. for a baud rate of 19200 e.g., the entry in table iv is 5. n b 1 e 5(n b 1 is the value from table iv) n e 6 (n is the baud rate divisor) baud rate e 1.8432 mhz/(16 c 6) e 19200 the divide by 16 is performed because in the asynchronous mode, the input frequency to the uart is 16 times the baud rate. the equation to calculate baud rates is given below. the actual baud rate may be found from: br e fc/(16 c n c p) where: br is the baud rate fc is the cki frequency n is the baud rate divisor (table iv). p is the prescaler divide factor selected by the value in the prescaler select register (table v) note: in the synchronous mode, the divisor 16 is replaced by two. example: asynchronous mode: crystal frequency e 5 mhz desired baud rate e 9600 using the above equation n c p can be calculated first. n c p e (5 c 106)/(16 c 9600) e 32.552 now 32.552 is divided by each prescaler factor (table v) to obtain a value closest to an integer. this factor happens to be 6.5 (p e 6.5). n e 32.552/6.5 e 5.008 (n e 5) the programmed value (from table iv) should be 4 (n b 1). using the above values calculated for n and p: br e (5 c 106)/(16 c 5 c 6.5) e 9615.384 % error e (9615.385 b 9600)/9600 e 0.16 effect of halt/idle the uart logic is reinitialized when either the halt or idle modes are entered. this reinitialization sets the tbmt flag and resets all read only bits in the uart control and status registers. read/write bits remain unchanged. the transmit buffer (tbuf) is not affected, but the transmit shift register (tsft) bits are set to one. the receiver regis- ters rbuf and rsft are not affected. the device will exit from the halt/idle modes when the start bit of a character is detected at the rdx (l3) pin. this feature is obtained by using the multi-input wakeup scheme provided on the device. before entering the halt or idle modes the user program must select the wakeup source to be on the rdx pin. this selection is done by setting bit 3 of wken (wakeup enable) register. the wakeup trigger condition is then selected to be high to low transition. this is done via the wkedg regis- ter (bit 3 is one). if the device is halted and crystal oscillator is used, the wake up signal will not start the chip running immediately because of the finite start up time requirement of the crystal oscillator. the idle timer (t0) generates a fixed (256 t c ) de- lay to ensure that the oscillator has indeed stabilized before allowing the device to execute code. the user has to con- sider this delay when data transfer is expected immediately after exiting the halt mode. diagnostic bits charl0 and charl1 in the enu register provide a ioopback feature for diagnostic testing of the uart. when these bits are set to one, the following occur: the receiver input pin (rdx) is internally connected to the transmitter output pin (tdx); the output of the transmitter shift regis- ter is ``looped back'' into the receive shift register input. in this mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit and receive data paths of the uart. note that the framing format for this mode is the nine bit format; one start bit, nine data bits, and 7/8, one or two stop bits. parity is not generated or verified in this mode. attention mode the uart receiver section supports an alternate mode of operation, referred to as attention mode. this mode of operation is selected by the attn bit in the enur register. the data format for transmission must also be selected as having nine data bits and either 7/8, one or two stop bits. the attention mode of operation is intended for use in networking the device with other processors. typically in such environments the messages consists of device ad- dresses, indicating which of several destinations should re- ceive them, and the actual data. this mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1. if the ninth bit is reset to a zero the byte is a data byte. while in attention mode, the uart monitors the com- munication flow, but ignores all characters until an address character is received. upon receiving an address character, the uart signals that the character is ready by setting the rbfl flag, which in turn interrupts the processor if uart receiver interrupts are enabled. the attn bit is also cleared automatically at this point, so that data characters as well as address characters are recognized. software ex- amines the contents of the rbuf and responds by deciding either to accept the subsequent data stream (by leaving the attn bit reset) or to wait until the next address character is seen (by setting the attn bit again). operation of the uart transmitter is not affected by selec- tion of this mode. the value of the ninth bit to be transmitted is programmed by setting xbit9 appropriately. the value of the ninth bit received is obtained by reading rbit9. since this bit is located in enur register where the error flags reside, a bit operation on it will reset the error flags. http://www.national.com 28
interrupts the device supports a vectored interrupt scheme. it sup- ports a total of fourteen interrupt sources. table vi lists all the possible device interrupt sources, their arbitration rank- ings and the memory locations reserved for the interrupt vector for each source. two bytes of program memory space are reserved for each interrupt source. all interrupt sources except the software interrupt are maskable. each of the maskable interrupts have an enable bit and one or more pending bits. a maska- ble interrupt is active if its associated enable and pending bits are set. if gle e 1 and an interrupt is active, then the processor will be interrupted as soon as it is ready to start executing an instruction except if the above conditions hap- pen during the software trap service routine. this excep- tion is described in the software trap sub-section. the interruption process is accomplished with the intr in- struction (opcode 00), which is jammed inside the instruc- tion register and replaces the opcode about to be execut- ed. the following steps are performed for every interrupt: 1. the gie (global interrupt enable) bit is reset. 2. the address of the instruction about to be executed is pushed into the stack. 3. the pc (program counter) branches to address 00ff. this procedure takes 7 t c cycles to execute. at this time, since gie e 0, other maskable interrupts are disabled. the user is now free to do whatever context switching is required by saving the context of the machine in the stack with push instructions. the user would then pro- gram a vis (vector interrupt select) instruction in order to branch to the interrupt service routine of the highest priority interrupt enabled and pending at the time of the vis. note that this is not necessarily the interrupt that caused the branch to address location 00ff hex prior to the context switching. thus, if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the vis, then the interrupt with the higher rank will override any lower ones and will be acknowledged. the lower priority interrupt(s) are still pending, however, and will cause another interrupt im- mediately following the completion of the interrupt service routine associated with the higher priority interrupt just serv- iced. this lower priority interrupt will occur immediately fol- lowing the reti (return from interrupt) instruction at the end of the interrupt service routine just completed. inside the interrupt service routine, the associated pending bit has to be cleared by software. the reti (return from interrupt) instruction at the end of the interrupt service rou- tine will set the gie (global interrupt enable) bit, allowing the processor to be interrupted again if another interrupt is active and pending. the vis instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest rank. the addresses of the different interrupt service routines, called vectors, are chosen by the user and stored in rom in a table starting at 01e0 (assuming that vis is located be- tween 00ff and 01df). the vectors are 15-bit wide and therefore occupy 2 rom locations. table vi. interrupt vector table arbitration source vector * ranking description address (hi-low byte) (1) highest software 0yfe 0yff (2) reserved 0yfc 0yfd (3) external g0 0yfa-0yfb (4) timer t0 underflow 0yf8 0yf9 (5) timer t1 t1a/underflow 0yf6 0yf7 (6) timer t1 t1b 0yf4-0yf5 (7) microwire/plus busy low 0yf2 0yf3 (8) counters 0yf0 0yf1 (9) uart receive 0yee 0yef (10) uart transmit 0yec 0yed (11) timer t2 t2a/underflow 0yea 0yeb (12) timer t2 t2b 0ye8 0ye9 (13) capture timer 1 and 2 0ye6 0ye7 (14) unused 0ye4 0ye5 (15) port l/wakeup 0ye2 0ye3 (16) lowest default vis reserved 0ye0 0ye1 * y is a variable which represents the vis block. vis and the vector table must be located in the same 256-byte block except if vis is located at the last address of a block, in this case, the table must be in the next block. http://www.national.com 29
interrupts (continued) vis and the vector table must be located in the same 256-byte block (0y00 to 0yff) except if vis is located at the last address of a block. in this case, the table must be in the next block. the vector table cannot be inserted in the first 256-byte block (y i 0). the vector of the maskable interrupt with the lowest rank is located at 0ye0 (hi-order byte) and 0ye1 (lo-order byte) and so forth in increasing rank number. the vector of the maskable interrupt with the highest rank is located at 0yfa (hi-order byte) and 0yfb (lo-order byte). the software trap has the highest rank and its vector is located at 0yfe and 0yff. if, by accident, a vis gets executed and no interrupt is ac- tive, then the pc (program counter) will branch to a vector located at 0ye0 0ye1. warning a default vis interrupt handler routine must be present. as a minimum, this handler should confirm that the gie bit is cleared (this indicates that the interrupt sequence has been taken), take care of any required housekeeping, restore ocntext and return. some sort of warm restart procedure should be implemented. these events can occur without any error on the part of the system sesigner or programmer. note: there is always the possibility of an interrupt occurring during an in- struction which is attempting to reset the gie bit or any other interrupt enable bit. if this occurs when a single cycle instruction is being used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. this is because interrupt processing is started at the same time as the interrupt bit is being reset. to avoid this scenario, the user should always use a two, three, or four cycle instruction to reset interrupt enable bits. figure 19 shows the interrupt block diagram. software trap the software trap (st) is a special kind of non-maskable interrupt which occurs when the intr instruction (used to acknowledge interrupts) is fetched from rom and placed inside the instruction register. this may happen when the pc is pointing beyond the available rom address space or when the stack is over-popped. when an st occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization pro- cedures) before restarting. the occurrence of an st is latched into the st pending bit. the gie bit is not affected and the st pending bit ( not accessible by the user ) is used to inhibit other interrupts and to direct the program to the st service routine with the vis instruction. the rpnd instruction is used to clear the software interrupt pending bit. this pending bit is also cleared on reset. the st has the highest rank among all interrupts. nothing (except another st) can interrupt an st being serviced. tl/dd/12527 20 figure 19. interrupt block diagram http://www.national.com 30
detection of illegal conditions the device can detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. reading of undefined rom gets zeroes. the opcode for software interrupt is 00. if the program fetches instructions from undefined rom, this will force a software interrupt, thus signaling that an illegal condition has occurred. the subroutine stack grows down for each call (jump to subroutine), interrupt, or push, and grows up for each re- turn or por the stack pointer is initialized to ram location 06f hex during reset. consequently, if there are more re- turns than calls, the stack pointer will point to addresses 070 and 071 hex (which are undefined ram). undefined ram from addresses 070 to 07f (segment 0), 140 to 17f (segment 1), and all other segments (i.e., segments 3... etc.) is read as all 1's, which in turn will cause the program to return to address 7fff hex. this is an undefined rom location and the instruction fetched (all 0's) from this loca- tion will generate a software interrupt signaling an illegal condition. thus, the chip can detect the following illegal conditions: 1. executing from undefined rom 2. over ``pop''ing the stack by having more returns than calls. when the software interrupt occurs, the user can re-initialize the stack pointer and do a recovery procedure before re- starting (this recovery program is probably similar to that following reset, but might not contain the same program initialization procedures). the recovery program should re- set the software interrupt pending bit using the rpnd in- struction. microwire/plus microwire/plus is a serial synchronous communica- tions interface. the microwire/plus capability enables the device to interface with any of national semiconductor's microwire peripherals (i.e., a/d converters, display driv- ers, e2proms etc.) and with other microcontrollers which support the microwire interface. it consists of an 8-bit serial shift register (sio) with serial data input (si), serial data output (so) and serial shift clock (sk). figure 20 shows a block diagram of the microwire/plus logic. the shift clock can be selected from either an internal source or an external source. operating the mlcrowire/ plus arrangement with the internal clock source is called the master mode of operation. similarly, operating the microwire/plus arrangement with an external shift clock is called the slave mode of operation. the cntrl register is used to configure and control the microwire/plus mode. to use the microwire/plus, the msel bit in the cntrl register is set to one. in the master mode, the sk clock rate is selected by the two bits, sl0 and sl1, in the cntrl register. table vii details the different clock rates that may be selected. table vii. microwire/plus master mode clock select sl1 sl0 sk period 00 2 c t c 01 4 c t c 1x 8 c t c where t c is the instruction cycle clock tl/dd/12527 21 figure 20. microwire/plus block diagram http://www.national.com 31
microwire/plus (continued) microwire/plus operation setting the busy bit in the psw register causes the microwire/plus to start shifting the data. it gets reset when eight data bits have been shifted. the user may reset the busy bit by software to allow less than 8 bits to shift. if enabled, an interrupt is generated when eight data bits have been shifted. the device may enter the microwire/plus mode either as a master or as a slave. figure 21 shows how two devices, microcontrollers and several peripherals may be interconnected using the microwire/plus ar- rangements. warning: the sio register should only be loaded when the sk clock is low. loading the sio register while the sk clock is high will resuit in undefined data in the sio register. sk clock is normally low when not shifting. setting the busy flag when the input sk clock is high in the microwire/plus slave mode may cause the current sk clock for the sio shift register to be narrow. for safety, the busy flag should only be set when the input sk clock is low. microwire/plus master mode operation in the microwire/plus master mode of operation the shift clock (sk) is generated internally by the device. the microwire master always initiates all data exchanges. the msel bit in the cntrl register must be set to enable the so and sk functions onto the g port. the so and sk pins must also be selected as outputs by setting appropriate bits in the port g configuration register. table viii summa- rizes the bit settings required for master mode of operation. microwire/plus slave mode operation in the microwire/plus slave mode of operation the sk clock is generated by an external source. setting the msel bit in the cntrl register enables the so and sk functions onto the g port. the sk pin must be selected as an input and the so pin is selected as an output pin by setting and resetting the appropriate bits in the port g configuration reg- ister. table viii summarizes the settings required to enter the slave mode of operation. this table assumes that the control flag msel is set. table viii. microwire mode settings g4 (so) g5 (sk) g4 g5 operation config. bit config. bit fun. fun. 1 1 so int. microwire/plus sk master 0 1 tri- int. microwlre/plus state sk master 1 0 so ext. mlcrowlre/plus sk slave 0 0 trl- ext. microwlre/plus state sk slave the user must set the busy flag immediately upon entering the slave mode. this will ensure that all data bits sent by the master will be shifted properly. after eight clock pulses the busy flag will be cleared and the sequence may be repeated. alternate sk phase operation the device allows either the normal sk clock or an alternate phase sk clock to shift data in and out of the sio register. in both the modes the sk is normally low. in the normal mode data is shifted in on the rising edge of the sk clock and the data is shifted out on the falling edge of the sk clock. the sio register is shifted on each falling edge of the sk clock. in the alternate sk phase operation, data is shifted in on the falling edge of the sk clock and shifted out on the rising edge of the sk clock. a control flag, sksel, allows either the normal sk clock or the alternate sk clock to be selected. resetting sksel causes the microwire/plus logic to be clocked from the normal sk signal. setting the sksel flag selects the alter- nate sk clock. the sksel is mapped into the g6 configura- tion bit. the sksel flag will power up in the reset condition, selecting the normal sk signal. tl/dd/12527 22 figure 21. microwire/plus application http://www.national.com 32
memory map all ram, ports and registers (except a and pc) are mapped into data memory address space. address contents s/add reg 0000 to 006f 112 on-chip ram bytes 0070 to 007f unused ram address space (reads as all 1's) xx80 to xx8f unused ram address space (reads undefined data) xx90 port e data register xx91 port e configuration register xx92 port e input pins (read only) xx93 reserved xx94 port f data register xx95 port f configuration register xx96 port f input pins (read only) xx97 reserved xx98 dividend or result byte (mdr1) xx99 dividend/multiplier or result byte (mdr2) xx9a dividend/result byte or undefined (mdr3) xx9b divisor/multiplicand or result byte (mdr4) xx9c divisor or multiplicand byte(mdr5) xx9d muitiply/divide control register (mdcr) xx9e counter control 1 register (ccr1) xx9f counter control 2 register (ccr2) xxa0 counter 1 prescaler lower byte (c1prl) xxa1 counter 1 prescaler upper byte (c1prh) xxa2 counter 1 count register lower byte (c1ctl) xxa3 counter 1 count register upper byte (c1cth) xxa4 counter 2 prescaler lower byte (c2prl) xxa5 counter 2 prescaler upper byte (c2prh) xxa6 counter 2 count register lower byte (c2ctl) xxa7 counter 2 count register upper byte (c2cth) xxa8 counter 3 prescaler lower byte (c3prl) xxa9 counter 3 prescaler upper byte (c3prh) xxaa counter 3 count register lower byte (c3ctl) xxab counter 3 count register upper byte (c3cth) xxac counter 4 prescaler lower byte (c4prl) xxad counter 4 prescaler upper byte (c4prh) xxae counter 4 count register lower byte (c4ctl) xxaf counter 4 count register upper byte (c4cth) xxb0 capture timer 1 prescaler register (cm1 psc) xxb1 capture timer 1 lower byte (cm1crl) read-only xxb2 capture timer 1 upper byte (cm1crh) read-only xxb3 capture timer 2 prescaler register (cm2psc) xxb4 capture timer 2 lower byte (cm2crl) read-only xxb5 capture timer 2 upper byte (cm2crh) read-only xxb6 capture timer 1 control register (ccmr1) xxb7 capture timer 2 control register (ccmr2) xxb8 uart transmit buffer (tbuf) xxb9 uart receive buffer (rbuf) xxba uart control and status register (enu) http://www.national.com 33
memory map (continued) address contents s/add reg xxbb uart receive control and status register (enur) xxbc uart interrupt and clock source register (enui) xxbd uart baud register (baud) xxbe uart prescaler select register (psr) xxbf reserved for uart xxc0 timer t2 lower byte xxc1 timer t2 upper byte xxc2 timer t2 autoload register t2ra lower byte xxc3 timer t2 autoload register t2ra upper byte xxc4 timer t2 autoload register t2rb lower byte xxc5 timer t2 autoload register t2rb upper byte xxc6 timer t2 control register xxc7 reserved xxc8 miwu edge select register (wkedg) xxc9 mlwu enable register (wken) xxca mlwu pending register (wkpnd) xxcb reserved xxcc reserved xxcd to xxcf reserved xxd0 port l data register xxd1 port l configuration register xxd2 port l input pins (read only) xxd3 reserved for port l xxd4 port g data register xxd5 port g configuration register xxd6 port g input pins (read only) xxd7 port l input pins (read only) xxd8 port c data register xxd9 port c configuration register xxda port c input pins (read only) xxdb reserved for port c xxdc port d xxdd to xxdf reserved for port d xxe0 to xxe5 reserved for ee control registers xxe6 timer t1 autoload register t1rb lower byte xxe7 timer t1 autoload register t1rb upper byte xxe8 icntrl register xxe9 microwire shift register xxea timer t1 lower byte xxeb timer t1 upper byte xxec timer t1 autoload register t1ra lower byte xxed timer t1 autoload register t1ra upper byte xxee cntrl control register xxef psw register xxf0 to xxfb on-chip ram mapped as registers xxfc x register xxfd sp register xxfe b register xxff s register 0100 to 017f 0200 to 027f on chip ram bytes (384 bytes) 0300 to 037f reading memory locations 0070h-007fh (segment 0) will return all ones. reading unused memory locations between 0080h-00f0 hex (segment 0) will return undefined data. reading memory locations from other segments (i.e., segment 4, segment 5, etc.) will return all ones. http://www.national.com 34
addressing modes there are ten addressing modes, six for operand address- ing and four for transfer of control. operand addressing modes register indirect this is the ``normal'' addressing mode. the operand is the data memory addressed by the b pointer or x pointer. register indirect (with auto post increment or decrement of pointer) this addressing mode is used with the ld and x instruc- tions. the operand is the data memory addressed by the b pointer or x pointer. this is a register indirect mode that automatically post increments or decrements the b or x reg- ister after executing the instruction. direct the instruction contains an 8-bit address field that directly points to the data memory for the operand. immediate the instruction contains an 8-bit immediate field as the op- erand. short immediate this addressing mode is used with the load b immediate instruction. the instruction contains a 4-bit immediate field as the operand. indirect this addressing mode is used with the laid instruction. the contents of the accumuiator are used as a partial address (lower 8 bits of pc) for accessing a data operand from the program memory. transfer of control addressing modes relative this mode is used for the jp instruction, with the instruction field being added to the program counter to get the new program location. jp has a range from b 31 to a 32 to allow a 1-byte relative jump (jp a 1 is implemented by a nop instruction). there are no ``pages'' when using jp, since all 15 bits of pc are used. absolute this mode is used with the jmp and jsr instructions, with the instruction field o f i 2 bits replacing the lower 12 bits of the program counter (pc). this allows jumping to any loca- tion in the current 4k program memory segment. absolute long this mode is used with the jmpl and jsrl instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (pc). this allows jumping to any location up to 32k in the program memory space. indirect this mode is used with the jid instruction. the contents of the accumulator are used as a partial address (lower 8 bits of pc) for accessing a location in the program memory. the contents of this program memory location serve as a partial address (lower 8 bits of pc) for the jump to the next instruc- tion. note: the vis is a special case of the indirect transfer of control address- ing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (pc) in order to jump to the associated interrupt service routine. instruction set register and symbol definition registers a 8-bit accumulator register b 8-bit address register x 8-bit address register sp 8-bit stack pointer register pc 15-bit program counter register pu upper 7 bits of pc pl lower 8 bits of pc c 1 bit of psw register for carry hc 1 bit of psw register for half carry gie 1 bit of psw register for global interrupt enable vu interrupt vector upper byte vl interrupt vector lower byte symbols [ b ] memory indirectly addressed by b register [ x ] memory indirectly addressed by x register md direct addressed memory mem direct addressed memory or [ b ] meml direct addressed memory or [ b ] or immediate data imm 8-bit immediate data reg register memory: addresses f0 to ff (includes b, x and sp) bit bit number (0 to 7) x loaded with y exchanged with http://www.national.com 35
instruction set add a,memi add a w a a memi adc a,meml add with carry a w a a memi a c, c w carry, hc w half carry subc a,meml subtract with carry a w a b memi a c, c w carry, hc w half carry and a,meml logical and a w a and memi andsz a,lmm logical and lmmed., skip if zero skip next if (a and imm) e 0 or a,meml logical or a w a or memi xor a,meml logical exclusive or a w a xor memi ifeq md,lmm if equal compare md and lmm, do next if md e lmm ifeq a,meml if equal compare a and meml, do next if a e meml ifne a,meml if not equal compare a and meml, do next if a i meml ifgt a,meml if greater than compare a and meml, do next if a l meml lfbne y if b not equal do next if lower 4 bits of b i imm drsz reg decrement reg., skip if zero reg w reg b 1, skip if reg e 0 sbit y ,mem set bit 1 to bit, mem (bit e 0 to 7 immediate) rbit y ,mem reset bit 0 to bit, mem lfbit y ,mem if bit if bit y , a or mem is true do next instruction rpnd reset pending flag reset software interrupt pending flag x a,mem exchange a with memory a y mem xa, [ x ] exchange a with memory [ x ] a y [ x ] ld a,meml load a with memory a w memi ld a, [ x ] load a with memory [ x ] a w [ x ] ld b, imm load b with immed. b w imm ld mem, imm load memory immed. mem w imm ld reg, imm load register memory immed. reg w imm xa, [ b g ] exchange a with memory [ b ] a y [ b ] ,(b w b g 1) xa, [ x g ] exchange a with memory [ x ] a y [ x ] ,(x w x g 1) ld a, [ b g ] load a with memory [ b ] a w [ b ] ,(b w b g 1) ld a, [ x g ] load a with memory [ x ] a w [ x ] ,(x w x g 1) ld [ b g ] ,lmm load memory [ b ] lmmed. [ b ] w imm, (b w b g 1) clr a clear a a w 0 inc a increment a a w a a 1 dec a decrement a a w a b 1 laid load a indirect from rom a w rom (pu, a) dcor a decimal correct a a w bcd correction of a (follows adc, subc) rrc a rotate a right thru c c x a7 x ... x a0 x c rlc a rotate a left thru c c w a7 w ... w a0 w c swap a swap nibbles of a a 7...a4 y a3...a0 sc set c c w 1, hc w 1 rc reset c c w 0, hc w 0 ifc if c if c is true, do next instruction ifnc if not c if c is not true, do next instruction pop a pop the stack into a sp w sp a 1, a w [ sp ] push a push a onto the stack [ sp ] w a, sp w sp b 1 vis vector to interrupt service routine pu w [ vu ] ,pl w [ vl ] jmpl addr. jump absolute long pc w ii (ii e 15 bits, 0 to 32k) jmp addr. jump absolute pc 9...0 w i(i e 12 bits) jp disp. jump relative short pc w pc a r(ris b 31 to a 32, except 1) jsrl addr. jump subroutine long [ sp ] w pl, [ sp b 1 ] w pu, sp b 2, pc w ii jsr addr jump subroutine [ sp ] w pl, [ sp b 1 ] w pu, sp b 2,pc9...0 w i jid jump indirect pl w rom (pu, a) ret return from subroutine sp a 2, pl w [ sp ] ,pu w [ sp b 1 ] retsk return and skip sp a 2, pl w [ sp ] ,pu w [ sp b 1 ] , skip next instruction reti return from interrupt sp a 2, pl w [ sp ] ,pu w [ sp b 1 ] , gie w 1 intr generate an interrupt [ sp ] w pl, [ sp b 1 ] w pu, sp b 2, pc w 0ff nop no operation pc w pc a 1 http://www.national.com 36
instruction execution time most instructions are single byte (with immediate addressing mode instructions taking two bytes). most single byte instructions take one cycle time to execute. see the bytes and cycles per instruction table for details. bytes and cycles per instruction the following table shows the number of bytes and cycles for each instruction in the format of byte/cycle. arithmetic and logic instructions [ b ] direct immed. add 1/1 3/4 2/2 adc 1/1 3/4 2/2 subc 1/1 3/4 2/2 and 1/1 3/4 2/2 or 1/1 3/4 2/2 xor 1/1 3/4 2/2 ifeq 1/1 3/4 2/2 ifgt 1/1 3/4 2/2 ifbne 1/1 drsz 1/3 sbit 1/1 3/4 rbit 1/1 3/4 lfbit 1/1 3/4 rpnd 1/1 instructions usin ga&c clra 1/1 inca 1/1 deca 1/1 laid 1/3 dcora 1/1 rrca 1/1 rlca 1/1 swapa 1/1 sc 1/1 rc 1/1 ifc 1/1 ifnc 1/1 pusha 1/3 popa 1/3 andsz 2/2 transfer of control instructions jmpl 3/4 jmp 2/3 jp 1/3 jsrl 3/5 jsr 2/5 jid 1/3 vis 1/5 ret 1/5 retsk 1/5 reti 1/5 intr 1/7 nop 1/1 memory transfer instructions register direct immed. register indirect indirect auto incr. and decr. [ b ][ x ][ b a ,b b ][ x a ,x b ] xa, * 1/1 1/3 2/3 1/2 1/3 ld a, * 1/1 1/3 2/3 2/2 1/2 1/3 ld b, imm 1/1 (if b k 16) ld b, imm 2/2 (if b l 15) ld mem, imm 2/2 3/3 2/2 ld reg, imm 2/3 ifeq md, imm 3/3 note: * e l memory location addressed by b or x or directly. http://www.national.com 37
bits 3 0 opcode list bits 7 4 fe d c b a 9 8 76 5 4 3 2 1 0 jp b 15 jp b 31 ld 0f0, y i drsz 0f0 rrca rc adc a, adc a, [ b ] ifbit andsz ld b, 0f ifbne 0 jsr jmp jp a 17 intr 0 y i0, [ b ] a, y i x000 x0ff x000 x0ff jp b 14 jp b 30 ld 0f1, y i drsz 0f1 * sc subc a, sub a, [ b ] ifbit * ld b, 0e ifbne 1 jsr jmp jp a 18 jp a 21 y i1, [ b ] x100 x1ff x100 x1ff jp b 13 jp b 29 ld 0f2, y i drsz 0f2 x a, x a, ifeq a, ifeq a, [ b ] ifbit * ld b, 0d ifbne 2 jsr jmp jp a 19 jp a 32 [ x a ][ b a ] y i2, [ b ] x200 x2ff x200 x2ff jp b 12 jp b 28 ld 0f3, y i drsz 0f3 x a, x a, ifgt a, ifgt a, [ b ] ifbit * ld b, 0c ifbne 3 jsr jmp jp a 20 jp a 43 [ x b ][ b b ] y i3, [ b ] x300 x3ff x300 x3ff jp b 11 jp b 27 ld 0f4, y i drsz 0f4 vis laid add a, add a, [ b ] ifbit clra ld b, 0b ifbne 4 jsr jmp jp a 21 jp a 54 y i4, [ b ] x400 x4ff x400 x4ff jp b 10 jp b 26 ld 0f5, y i drsz 0f5 rpnd jid and a, and a, [ b ] ifbit swapa ld b, 0a ifbne 5 jsr jmp jp a 22 jp a 65 y i5, [ b ] x500 x5ff x500 x5ff jp b 9jp b 25 ld 0f6, y i drsz 0f6 x a, [ x ] xa, [ b ] xor a, xor a, [ b ] ifbit dcora ld b, 9 ifbne 6 jsr jmp jp a 23 jp a 76 y i6, [ b ] x600 x6ff x600 x6ff jp b 8jp b 24 ld 0f7, y i drsz 0f7 ** or a, y iora, [ b ] ifbit pusha ld b, 8 ifbne 7 jsr jmp jp a 24 jp a 87 7, [ b ] x700 x7ff x700 x7ff jp b 7jp b 23 ld 0f8, y i drsz 0f8 nop rlca ld a, y i ifc sbit rbit ld b, 7 ifbne 8 jsr jmp jp a 25 jp a 98 0, [ b ] 0, [ b ] x800 x8ff x800 x8ff jp b 6jp b 22 ld 0f9, y i drsz 0f9 ifne ifeq ifne ifnc sbit rbit ld b, 6 ifbne 9 jsr jmp jp a 26 jp a 10 9 a, [ b ] md, y ia, y i1, [ b ] 1, [ b ] x900 x9ff x900 x9ff jp b 5jp b 21 ld 0fa, y i drsz 0fa ld a, ld a, ld [ b a ] , inca sbit rbit ld b, 5 ifbne 0a jsr jmp jp a 27 jp a 11 a [ x a ][ b a ] y i2, [ b ] 2, [ b ] xa00 xaff xa00 xaff jp b 4jp b 20 ld 0fb, y i drsz 0fb ld a, ld a, ld [ b b ] , deca sbit rbit ld b, 4 ifbne 0b jsr jmp jp a 28 jp a 12 b [ x b ][ b b ] y i3, [ b ] 3, [ b ] xb00 xbff xb00 xbff jp b 3jp b 19 ld 0fc, y i drsz 0fc ld md, y i jmpl x a,md popa sbit rbit ld b, 3 ifbne 0c jsr jmp jp a 29 jp a 13 c 4, [ b ] 4, [ b ] xc00 xcff xc00 xcff jp b 2jp b 18 ld 0fd, y i drsz 0fd dir jsrl ld a,md retsk sbit rbit ld b, 2 ifbne 0d jsr jmp jp a 30 jp a 14 d 5, [ b ] 5, [ b ] xd00 xdff xd00 xdff jp b 1jp b 17 ld 0fe, y i drsz 0fe ld a, [ x ] ld a, [ b ] ld [ b ] , y i ret sbit rbit ld b, 1 ifbne 0e jsr jmp jp a 31 jp a 15 e 6, [ b ] 6, [ b ] xe00 xeff xe00 xeff jp b 0jp b 16 ld 0ff, y i drsz 0ff ** ld b, y i reti sbit rbit ld b, 0 ifbne 0f jsr jmp jp a 32 jp a 16 f 7, [ b ] 7, [ b ] xf00 xfff xf00 xfff where, y i is the immediate data md is a directly addressed memory location * is an unused opcode note: the opcode 60 hex is also the opcode for ifbit y i,a. http://www.national.com 38
development support in-circuit emulator the metalink icemaster tm -cop8 tm model 400 in-circuit emulator for the cop8 family of microcontrollers features high-performance operation, ease of use, and an extremely flexible user-interface for maximum productivity. inter- changeable probe cards, which connect to the standard common base, support the various configurations and pack- ages of the cop8 family. the icemaster provides real-time, full-speed emulation up to 10 mhz, 32 kbytes of emulation memory and 4k frames of trace buffer memory. the user may define as many as 32k trace and break triggers which can be enabled, dis- abled, set or cleared. they can be simple triggers based on code or address ranges or complex triggers based on code address, direct address, opcode value, opcode class or im- mediate operand. complex breakpoints can be anded and ored together. trace information consists of address bus values, opcodes and user-selectable probe clips status (ex- ternal event lines). the trace buffer can be viewed as raw hex or as disassembled instructions. the probe clip bit val- ues can be displayed in binary, hex or digital waveform for- mats. during single-step operation the dynamically annotated code feature displays the contents of all accessed (read and write) memory locations and registers, as well as flow- of-control direction change markers next to each instruction executed. the icemaster's performance analyzer offers a resolution of better than 6 m s. the user can easily monitor the time spent executing specific portions of code and find ``hot spots'' or ``dead code''. up to 15 independent memory ar- eas based on code address or label ranges can be defined. analysis results can be viewed in bar graph format or as actual frequency count. emulator memory operations for program memory include single line assembler, disassembler, view, change and write to file. data memory operations include fill, move, compare, dump to file, examine and modify. the contents of any memory space can be directly viewed and modified from the corresponding window. the icemaster comes with an easy to use windowed in- terface. each window can be sized, highlighted, color-con- trolled, added, or removed completely. commands can be accessed via pull-down-menus and/or redefinable hot keys. a context sensitive hypertext/hyperlinked on-line help sys- tem explains clearly the options the user has from within any window. the icemaster connects easily to a pc via the standard comm port and its 115.2 kbaud serial link keeps typical program download time to under 3 seconds. the following tables list the emulator and probe cards order- ing information. emulator ordering information part number description im-cop8/400/1 3 metalink base unit in-circuit emulator for all cop8 devices, symbolic debugger software and rs 232 serial interface cable, with 110v @ 60 hz power supply. im-cop8/400/2 3 metalink base unit in-circuit emulator for all cop8 devices, symbolic debugger software and rs 232 serial interface cable, with 220v @ 50 hz power supply. 3 these parts include national's cop8 assembler/linker/librarian package (cop8-dev-ibma). probe card ordering information part number package voltage emulates range mhw-888gw68pwpc 68 plcc 2.5v 6.0v cop87l88gw mhw-888gw68p5pc 68 plcc 4.5v 5.5v cop87l88gw macro cross assembler national semiconductor offers a cop8 macro cross assem- bler. it runs on industry standard compatible pcs and sup- ports all of the full-symbolic debugging features of the metalink icemaster emulators. assembler ordering information part number description manual cop8-dev-ibma cop8 assembler/linker/ 620896 librarian for ibm pc/xt ,at or compatible. current version: 4.6. single chip otp/emulator support the cop8 family is supported by single chip otp emula- tors. for detailed information refer to the emulator specific datasheet and the emulator selection table below: 87l88 otp emulator ordering information device number clock option package emulates COP87L88GWV-XE crystal, 68 plcc cop888gw halt en http://www.national.com 39
development support (continued) programming support cop8 epu programming of these otp devices is supported by the me- talink icemasterecop8 evaluation and programming unit (cop8 epu). the cop8 epu is a low cost unit which can be used to program cop8 otp microcontrollers. the host computer for the cop8 epu is a standard pc (or compatible) running the dos operating system. the interface to the cop8 epu is over the rs 232c serial channel at 115,200 baud. the on-board voltage generator supplies all the voltages required to program the eprom/otp using only the wall mounted power supply provided. user interface: the cop8 epu offers a friendly, pop-up/pull-down win- dow, menu driven user interface featuring programmable function keys, a context sensitive, hyperlinked on-line help system and configurable displays. home computer specification: # ibm pc (or compatible) with minimum 640 bytes of mem- ory # one 3.5 , 1.4 mb floppy diskette drive # one hard drive # rs 232c serial channel # pc-dos/ms-dos version 3.1 or later ordering information: the following table is to provide a list of the epu adapters and their ordering information: cop8eepu ordering information not recommended for volume programming. part number devices supported epu-cop888gg-1 3 epu with 110v power supply epu-cop888gg-2 3 epu with 220v power supply cop8-pgma-68p programming adaptor for 68 plcc packages 3 these parts include national's cop8 assembler/linker/librarian pack- age (cop8-dev-ibma). available literature for more information, please see the cop8 basic family user's manual, literature number 620895, cop8 feature family user's manual, literature number 620897 and na- tional's family of 8-bit microcontrollers cop8 selection guide, literature number 630006. dial-a-helper service dial-a-helper is a service provided by the microcontroller applications group. the dial-a-helper is an electronic infor- mation system that may be accessed as a bulletin board system (bbs) via data modem, as an ftp site on the inter- net via standard ftp client application or as an ftp site on the internet using a standard internet browser such as net- scape or mosaic. the dial-a-helper system provides access to an automated information storage and retrieval system. the system capa- bilities include a message section (electronic mail, when accessed as a bbs) for communications to and from the microcontroller applications group and a file sec- tion which consists of several file areas where valuable application software and utilities could be found. dial-a-helper bbs via a standard modem modem: canada/u.s.: (800) nsc-micro (800) 672-6427 europe: ( a 49) 0-8141-351332 baud: 14.4k set-up: length: 8-bit parity: none stop bit: 1 operation: 24 hrs., 7 days dial-a-helper via ftp ftp nscmicro.nsc.com user: anonymous password: username @ yourhost.site.domain dial-a-helper via a worldwide web browser ftp://nscmicro.nsc.com national semiconductor on the worldwide web see us on the worldwide web at: http://www.national.com customer response center complete product information and technical support is avail- able from national's customer response centers. canada/u.s.: tel: (800) 272-9959 email: support @ tevm2.nsc.com europe: email: europe.support @ nsc.com deutsch tel: a 49 (0) 180-530 85 85 english tel: a 49 (0) 180-532 78 32 fran 3 ais tel: a 49 (0) 180-532 93 58 italiano tel: a 49 (0) 180-534 16 80 japan: tel: a 81-043-299-2309 s. e. asia: beijing tel: ( a 86) 10-865-8601 shanghai tel: ( a 86) 21-6249-6062 hong kong tel: ( a 852) 2737-1600 korea tel: ( a 82) 2-3771-6909 malaysia tel: 011-644-9061 singapore tel: ( a 65) 255-2226 taiwan tel: a 886-2-521-3288 australia: tel: ( a 61) 3-9558-9999 india: tel: ( a 91) 80-559-9467 canada/u.s.: tel (800) 272-9959 http://www.national.com 40
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cop87l88gw one-time programmable (otp) microcontroller physical dimensions inches (millimeters) unless otherwise noted plastic leaded chip carrier (v) order number COP87L88GWV-XE ns plastic chip package number v68a life support policy national's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of national semiconductor corporation. as used herein: 1. life support devices or systems are devices or 2. a critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. national semiconductor national semiconductor national semiconductor national semiconductor corporation europe hong kong ltd. japan ltd. 1111 west bardin road fax: a 49 (0) 180-530 85 86 13th floor, straight block, tel: 81-043-299-2308 arlington, tx 76017 email: europe.support @ nsc.com ocean centre, 5 canton rd. fax: 81-043-299-2408 tel: 1(800) 272-9959 deutsch tel: a 49 (0) 180-530 85 85 tsimshatsui, kowloon fax: 1(800) 737-7018 english tel: a 49 (0) 180-532 78 32 hong kong fran 3 ais tel: a 49 (0) 180-532 93 58 tel: (852) 2737-1600 http://www.national.com italiano tel: a 49 (0) 180-534 16 80 fax: (852) 2736-9960 national does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and national reserves the right at any time without notice to change said circuitry and specifications.

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