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16:1 single-ended multiplexer ICS850S1601I idt? / ics? 16:1, single-ended multiplexer 1 ics850s1601bgi rev. a august 15, 2008 general description the ics850s1061i is a low skew16:1 single-ended clock multiplexer and is a member of the hiperclocks? family of high performance clock solutions from idt. the ics850s1061i has 16 selectable single-ended clock inputs and 1 single-ended clock output. the device operates up to 250mhz and is packaged in a 24 tssop package. features ? 16:1 single-ended multiplexer ? nominal output impedance: 20 ? (v dd = 3.3v) ? maximum output frequency: 250mhz ? propagation delay: 2.7ns (maximum) ? full 3.3v or 2.5v supply modes ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) packages hiperclocks? ic s ICS850S1601I 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package top view pin assignment block diagram clk0 clk_sel3 clk_sel2 clk_sel1 oe clk1 q pulldown pulldown pulldown pulldown pullup pulldown clk15 pulldown pulldown clk14 clk_sel0 pulldown 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 clk8 clk9 clk10 clk11 clk12 clk13 clk14 clk15 v dd clk_sel0 clk_sel1 clk_sel2 clk7 clk6 clk4 clk5 clk2 clk3 clk1 clk0 gnd q oe clk_sel3
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 2 ics850s1601bgi rev. a august 15, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1 clk8 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 2 clk9 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 3 clk10 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 4 clk11 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 5 clk12 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 6 clk13 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 7 clk14 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 8 clk15 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 9v dd power power supply pin. 10, 11. 12, 13 clk_sel0, clk_sel1, clk_sel2, clk_sel3 input pulldown clock select inputs. see tabl e 3. lvcmos / lvttl interface levels. 14 oe input pullup output enable pin for q output. lvcmos/lvttl interface levels. 15 q output single-ended clock output. lvcmos/lvttl interface levels. 16 gnd power power supply ground. 17 clk0 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 18 clk1 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 19 clk2 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 20 clk3 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 21 clk4 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 22 clk5 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 23 clk6 input pulldown single-ended clock input. lvcmos/lvttl interface levels. 24 clk7 input pulldown single-ended clock input. lvcmos/lvttl interface levels. symbol parameter test conditions minimum typical maximum units c in input capacitance 2 pf c pd power dissipation capacitance v dd = 3.465v 10 pf v dd = 2.625v 8 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v dd = 3.3v5% 20 ? v dd = 2.5v5% 25 ?
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 3 ics850s1601bgi rev. a august 15, 2008 function tables table 3. clock input function table inputs input selected to q clk_sel3 clk_sel2 clk_sel1 clk_sel0 0000 clk0 0001 clk1 0010 clk2 0011 clk3 0100 clk4 0101 clk5 0110 clk6 0111 clk7 1000 clk8 1001 clk9 1010 clk10 1011 clk11 1100 clk12 1101 clk13 1110 clk14 1111 clk15
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 4 ics850s1601bgi rev. a august 15, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 82.8 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current output unterminated 49 ma symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v i dd power supply current output unterminated 41 ma
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 5 ics850s1601bgi rev. a august 15, 2008 table 4c. lvcmos/lvttl dc characteristics, v dd = 3.3v 5% or 2.5v 5%, t a = -40c to 85c note 1: output terminated with 50 ? to v dd /2. see parameter measurement information section. load test circuit diagrams. ac electrical characteristics table 5a. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: measured from v dd /2 of the input to v dd /2 of the output. note 2: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the output s are measured at the differential cross points. note 3: this parameter is defined according with jedec standard 65. note 4: input duty cycle must be 50%. symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.465v 2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current clk[0:15], clk_sel[0:3] v dd = v in = 3.465v or 2.625v 150 a oe v dd = v in = 3.465v or 2.625v 10 a i il input low current clk[0:15], clk_sel[0:3] v dd = 3.465v or 2.625v, v in = 0v -10 a oe v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v dd = 3.3v 5%, i oh = -12ma 2.6 v v dd = 2.5v 5%, i oh = -12ma 1.8 v v ol output low voltage; note 1 v dd = 3.3v 5% or 2.5v 5%, i ol = 12ma 0.5 v parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low-to-high; note 1 1.4 2.7 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.35 ps t sk(i) input skew 175 ps t sk(pp) part-to-part skew; note 2, 3 600 ps t r / t f output rise/fall time 20% to 80% 100 500 ps odc output duty cycle; note 4 f 200mhz 46 54 % f = 250mhz 40 60 % mux isolation mux isolation 155.52mhz 43 db
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 6 ics850s1601bgi rev. a august 15, 2008 table 5b. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c note 1: measured from v dd /2 of the input to v dd /2 of the output. note 2: defined as skew between outputs on different devices oper ating at the same supply voltage and with equal load condition s. using the same type of inputs on each device, the output s are measured at the differential cross points. note 3: this parameter is defined according with jedec standard 65. note 4: input duty cycle must be 50%. parameter symbol test conditio ns minimum typical maximum units f max output frequency 250 mhz tp lh propagation delay, low-to-high; note 1 1.5 2.7 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 155.52mhz, integration range: 12khz ? 20mhz 0.32 ps t sk(i) input skew 195 ps t sk(pp) part-to-part skew; note 2, 3 600 ps t r / t f output rise/fall time 20% to 80% 80 600 ps odc output duty cycle; note 4 f 200mhz 46 54 % f = 250mhz 40 60 % mux isolation mux isolation 155.52mhz 43 db
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 7 ics850s1601bgi rev. a august 15, 2008 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the powe r of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specif ied offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental . when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offs et from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on th e desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specific ations, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. offset frequency (hz) ssb phase noise dbc/hz additive phase jitter @ 155.52mhz 12khz to 20mhz = 0.35ps (typical)
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 8 ics850s1601bgi rev. a august 15, 2008 parameter measureme nt information 3.3v output load ac test circuit part-to-part skew output duty cycle/pulse width/period 2.5v output load ac test circuit input skew scope qx lvcmos gnd v dd 1.65v5% -1.65v5% t sk(pp) v dd 2 v dd 2 part 1 part 2 qx qy t period t pw t period odc = v ddo 2 x 100% t pw q scope qx lvcmos gnd v dd 1.25v5% -1.25v5% t pd1 t pd2 tsk(i) = ? t pd2 ? t pd1 ? tsk (i) clk2 q clk1
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 9 ics850s1601bgi rev. a august 15, 2008 parameter measurement in formation, continued mux isolation propagation delay output rise/fall time application information recommendations for unused input pins inputs: clk inputs for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clkx (static) clky clk_sely q spectrum mux _isol clkx clky t pd v dd 2 v dd 2 q clk0: clk15 20% 80% 80% 20% t r t f q
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 10 ics850s1601bgi rev. a august 15, 2008 reliability information table 6. ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ics859s1601i is: 649 package outline and package dimensions package outline - g suffix for 24 lead tssop table 7. package dimensions reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standar d test boards 82.8c/w 78.5 76.3 all dimensions in millimeters symbol minimum maximum n 24 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS850S1601I 16:1, single-ended multiplexer idt? / ics? 16:1, single-ended multiplexer 11 ics850s1601bgi rev. a august 15, 2008 ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 850s1601bgilf ics50s1601bil ?lead-free? 24 lead tssop tube -40 c to 85 c 850s1601bgilft ics50s1601bil ?lead-free? 24 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other ext raordinary environmental requirements are not recommended without additional processing by idt. idt reserves t he right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support device s or critical medical instruments.
iICS850S1601I 16:1, single-ended multiplexer www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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