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d a t a sh eet product speci?cation supersedes data of 1996 oct 02 file under integrated circuits, ic02 1996 oct 09 integrated circuits SAA7206h dvb compliant descrambler
1996 oct 09 2 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h contents 1 features 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 mpeg-2 systems parsing 7.2 pes level descrambling 7.3 descrambler core 7.4 microcontroller interface 7.5 output interfacing 7.6 boundary scan test 7.7 programming the descrambler 8 limiting values 9 handling 10 thermal characteristics 11 dc characteristics 12 ac characteristics 13 package outline 14 soldering 14.1 introduction 14.2 reflow soldering 14.3 wave soldering 14.3.1 qfp 14.3.2 so 14.3.3 method (qfp and so) 14.4 repairing soldered joints 15 definitions 16 life support applications
1996 oct 09 3 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 1 features input data fully compliant with the transport stream (ts) definition of the mpeg-2 systems specification input data signals; [forward error correction (fec) interface] C modem data input bus (8-bit wide) C valid input data indicator C erroneous packet indicator C first packet byte indicator C byte strobe signal (for asynchronous mode only). the interface can be programmed to one of two modes: C asynchronous mode; byte strobe input signal (mbclk) < 9 mhz, for connection to a modem (fec) C synchronous mode; mbclk is not used. data is delivered to the descrambler synchronized with the chip clock (dclk) [9 mhz (typ.) with a 33% duty cycle]. no external memory effective bit rate; f bit 72 mhz control interface; 8-bit multiplexed data/address, memory mapped i/o (90ce201 microcontroller parallel bus compatible), in combination with a microcontroller interrupt signal ( irq) output ports are identical to the input data interface (demultiplexer interface) C except for the packet error indicator ( mb/mb), as the descrambler translates an active mb signal to the transport_error_indicator bit in the transport stream C except for the byte strobe input signal (mbclk), as data is delivered to the demultiplexer, synchronized with the descrambler chip clock which is generated by the demultiplexer descrambler, based on the super descrambler mechanism algorithm with stream decipher and block decipher. the descrambler is initialized with a 64-bit control word (cw) at the beginning of a transport stream packet payload of a selected packet identification (pid). the descrambler operates on transport stream packet or packetized elementary stream (pes) packet payloads microcontroller support; only for control, no specific descrambling tasks are performed by the microcontroller. however, parsing and processing of conditional access information (such as emm and ecm data) is left to the system microcontroller boundary scan test port for boundary scan. 2 general description the SAA7206h (dvb compliant) is designed for use in mpeg-2 based digital tv receivers, incorporating conditional access filters. such receivers are to be implemented in, for instance, a digital video broadcasting top set box, or an integrated digital tv receiver. an example of a demultiplexer/descrambler system configuration, containing a channel decoder module, a demultiplexer, a system controller and a conditional access system is shown in fig.3. the main function of the descrambler is to descramble the payloads of mpeg-2 ts packets or pes packets. in addition, the descrambler retrieves conditional access (ca) data [such as entitlement management messages (emm) and entitlement control messages (ecm) etc.] from the stream and passes it to the system microcontroller for processing. 3 ordering information type number package name description version SAA7206h qfp64 plastic quad ?at package; 64 leads (lead length 1.95 mm); body 14 20 2.8 mm sot319-2
1996 oct 09 4 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 4 quick reference data 5 block diagram symbol parameter conditions min. typ. max. unit v ddd digital supply voltage -- 5.5 v v ddd(core) digital supply voltage for core -- 3.6 v p tot total power dissipation v ddd(core) = 3.3 v, v ddd =5v, c l =15pf -- 250 mw f clk clock frequency duty cycle = 30 to 55% -- 9 mhz t amb operating ambient temperature 0 - 70 c fig.1 block diagram. handbook, full pagewidth mgg313 test control block for boundary scan test and scan test microcontroller interface conditional access filters transport streams and af parser packet identification bank control word bank stream decipher block decipher output interface 7 to 9, 12 to 16 3 63 4 5 1 37 46 20 19 18 47 to 50, 53 to 56 44 45 43 59 62 22 24, 25, 28 to 31, 34, 35 38 39 61 60 36 6, 11, 21, 26, 32, 41, 51, 57, 64 10, 42 2, 17, 23, 27, 33, 52, 58 tc1 tc0 min7 to min0 mdv mb/mb msync mbclk tdi tck tms trst tdo dat7 to dat0 dcs r/w a1 a0 irq v ddd(core) v ddd1 to v ddd9 v ssd1 to v ssd7 v ssd1(core) , v ssd2(core) dclk por dato0 to dato7 dvo synco SAA7206 40 oe
1996 oct 09 5 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 6 pinning symbol pin i/o description irq 1 o interrupt request output for microcontroller (active low, open-drain output) v ssd1 2 gnd digital ground 1 dcs 3 i descrambler chip select input (active low) a1 4 i a1 = address/data indicator input a0 5 i a0 = msbyte indicator input v ddd1 6 supply digital supply voltage 1 (+5 v) dat7 7 i/o microcontroller bidirectional data bus bit 7 dat6 8 i/o microcontroller bidirectional data bus bit 6 dat5 9 i/o microcontroller bidirectional data bus bit 5 v ssd1(core) 10 gnd digital ground 1 for core v ddd2 11 supply digital supply voltage 2 (+5 v) dat4 12 i/o microcontroller bidirectional data bus bit 4 dat3 13 i/o microcontroller bidirectional data bus bit 3 dat2 14 i/o microcontroller bidirectional data bus bit 2 dat1 15 i/o microcontroller bidirectional data bus bit 1 dat0 16 i/o microcontroller bidirectional data bus bit 0 v ssd2 17 gnd digital ground 2 tdi 18 i boundary scan test data input tck 19 i boundary scan test clock input tms 20 i boundary scan test mode select input v ddd3 21 supply digital supply voltage 3 (+5 v) dclk 22 i 9 mhz descrambler chip clock input (duty cycle range: 30 to 55%) v ssd3 23 gnd digital ground 3 dato0 24 o data output to demultiplexer bit 0 dato1 25 o data output to demultiplexer bit 1 v ddd4 26 supply digital supply voltage 4 (+5 v) v ssd4 27 gnd digital ground 4 dato2 28 o data output to demultiplexer bit 2 dato3 29 o data output to demultiplexer bit 3 dato4 30 o data output to demultiplexer bit 4 dato5 31 o data output to demultiplexer bit 5 v ddd5 32 supply digital supply voltage 5 (+5 v) v ssd5 33 gnd digital ground 5 dato6 34 o data output to demultiplexer bit 6 dato7 35 o data output to demultiplexer bit 7 v ddd(core) 36 supply digital supply voltage for core (+3.3 v) tdo 37 o boundary scan test data output dvo 38 o valid output data indicator synco 39 o indicates the ?rst output byte (sync) of a transport packet
1996 oct 09 6 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h oe 40 i output enable (active low), if high, device outputs are high impedance, (connected to logic 0 in normal operation) v ddd6 41 supply digital supply voltage 6 (+5 v) v ssd2(core) 42 gnd digital ground 2 for core msync 43 i indicates the ?rst input byte (sync) of a transport packet mdv 44 i valid input data indicator mb/mb 45 i packet error indicator input (programmable polarity) trst 46 i boundary scan reset input (low in normal operation) min7 47 i 8-bit wide modem data input bit 7 min6 48 i 8-bit wide modem data input bit 6 min5 49 i 8-bit wide modem data input bit 5 min4 50 i 8-bit wide modem data input bit 4 v ddd7 51 supply digital supply voltage 7 (+5 v) v ssd6 52 gnd digital ground 6 min3 53 i 8-bit wide modem data input bit 3 min2 54 i 8-bit wide modem data input bit 2 min1 55 i 8-bit wide modem data input bit 1 min0 56 i 8-bit wide modem data input bit 0 v ddd8 57 supply digital supply voltage 8 (+5 v) v ssd7 58 gnd digital ground 7 mbclk 59 i byte strobe input signal < 9 mhz tc0 60 i test control input 0 (not connected in normal operation) tc1 61 i test control input 1 (not connected in normal operation) por 62 i power-on reset, must be active high during at least 5 dclk pulses r/ w 63 i read/ write input selection v ddd9 64 supply digital supply voltage 9 (+5 v) symbol pin i/o description
1996 oct 09 7 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.2 pin configuration. handbook, full pagewidth SAA7206 mgg312 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 irq v ssd1 dcs a1 a0 v ddd1 dat7 dat6 dat5 v ssd1(core) v ddd2 dat4 dat3 dat2 dat1 dat0 v ssd2 tdi tck v ddd7 min4 min5 min6 min7 trst mb/mb mdv msync v ssd2(core) v ddd6 oe synco dvo tdo v ddd(core) dato7 dato6 v ssd5 tms v ddd3 dclk v ssd3 dato0 dato1 v ddd4 v ssd4 dato2 dato3 dato4 dato5 v ddd5 v ddd9 r/w por tc1 tc0 mbclk v ssd7 v ddd8 min0 min1 min2 min3 v ssd6
1996 oct 09 8 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 7 functional description a block diagram of the internal structure of the descrambler (dvb compliant) is illustrated in fig.1. the block diagram illustrates the main functional modules in the descrambler. the modules are as follows: the mpeg-2 syntax parser, which parses transport streams that comply with the mpeg-2 systems specification the descrambler module consisting of: C a packet identification (pid) bank containing 6 pid values of the streams selected for descrambling. all bits of pid5 (address 0x0205) can be masked individually with pid5_mask (address 0x0209), to enable multiple pid selection. C a control word (cw) bank containing 6 cw pairs and a default cw. a cw pair consists of 2 descrambler control words (odd and even), each word with a length of 64 bits. C the descrambler core containing the actual descrambler with the stream cipher and the block cipher module. a microcontroller interface providing protocol handling for the memory mapped i/o control bus (philips 90ce201 compatible). this module contains an interrupt request handler and data filters for the retrieval of conditional access (ca) information: the ca filters select data on the basis of pids, and a combination of mpeg-2 section addressing fields. selected ca data is stored in eighteen 256 byte (constrained random access) buffers which can be read by the microcontroller. the ca message section has a maximum length of 256 bytes. it consists of a 3 bytes long header with table_id and section_length data. the remaining part of the ca message are the ca_data_bytes (see fig.4). if a section is longer than 256 bytes, the data capture is stopped (with an interrupt to the microcontroller) after 256 bytes are in the buffer and the section_to_long bit is set. the filters are capable of monitoring 18 ca streams (containing emm and ecm data) simultaneously. two different lengths are used for address filtering: C 16 filters where the first 7 bytes of the ca_data_bytes field are used for address filtering C 2 (dvb compliant) filters where the first 17 bytes of the ca_data_bytes field are used for address filtering C a chip identification byte (value 0x02) can be read by the software from address 0x0003 (see table 10). fig.3 demultiplexer system configuration. handbook, full pagewidth mgg314 conditional access system demodulator and forward error corrector dvb descrambler (SAA7206h) demultiplexer (saa7205) micro- controller
1996 oct 09 9 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h table 1 explanation of fig.4 syntax description table_id 8-bit ?eld for identi?cation reserved 4-bit ?eld with section_syntax_indicator (1 bit), dvb_reserved (1 bit) and iso_reserved (2 bits) section_length 12-bit ?eld that speci?es the number of bytes that follow the section_length ?eld up to the end of the section ca_data_byte 8-bit ?eld that carries private ca information. up to the ?rst 17 ca_data_bytes may be used for address ?ltering fig.4 syntax of the conditional access message. handbook, full pagewidth mgg316 table_id reserved section length byte 0 byte 1 ca_data_bytes [253 bytes (max.)] section header (3 bytes) section payload [253 bytes (max.)] 7 or 17 bytes of filtering
1996 oct 09 10 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 7.1 mpeg-2 systems parsing the descrambler receives data from a forward error correction (fec) decoder (see fig.5) in a digital tv receiver, in the following input data format: 8 data bits via min7 to min0. a valid input data indicator signal (mdv), which is high for consecutive valid bytes and output by either a fec decoder or a descrambler. consequently the descrambler input data is allowed to have a bursty nature. a transport packet error indicator ( mb/mb) which is high for the duration of each 188 byte transport packet in which the fec decoder found more errors than it could correct. the polarity (active high or low) of the error indicator is programmable [bit bad_polarity (see table 10, address 0x0100)]. a packet sync signal (msync) which goes high at the start of the first byte of a transport packet. only the rising edge of msync is used for synchronization, the exact high time of the signal is therefore irrelevant. a byte strobe signal (mbclk; < 9 mhz) which indicates consecutive data bytes in the input stream, in the non 9 mhz mode only [bit 9 mhz_interface = 0 (see table 10, address 0x0100)]. mbclk is used as an enable signal, and transport stream input bytes are sampled on its rising edges. if the input interface is programmed to the 9 mhz mode (9 mhz_interface = 1), the mbclk signal is ignored and bytes are latched on rising edges of the dclk. a descrambler clock signal (dclk; 9 mhz; duty cycle range 30 to 55%) which is the processing clock for the descrambler ic. if rising edges of this signal are used to input data to the descrambler, the 9 mhz mode must be programmed (bit 9 mhz_interface = 1, see table 10, address 0x0100). the parser module in the descrambler parses transport streams compliant to the mpeg-2 systems syntax. mpeg-2 systems specifies a hierarchical two-level multiplex (see fig.6). the top hierarchical level is the transport stream, consisting of relatively short (188 byte) transport packets. each transport packet consists of a 4 byte transport header, an optional adaptation field and a payload. the transport header contains a 13-bit pid field. the adaptation field may contain program clock reference (pcr) data and transport private data, among others. both transport header and optional adaptation fields are parsed by the ts parser module. the hierarchical multiplex level below the mpeg-2 transport stream is the packetized elementary stream. the pes header is only parsed partially by the dvb descrambler to locate its scrambling control bits. parsing is performed for all incoming transport packets, and the parser is synchronized to a rising edge on its msync input. a microcontroller can compose a set of 6 pids by programming the appropriate registers in the pid filter bank within the descrambler. these pids identify the packets of the streams that are to be descrambled. all 13 bits of pid5 (see table 10, address 0x0205) can be individually enabled/disabled with a mask of 13 bits (see table 10, address 0x0209) to enable multiple pid selection. the pids of pes scrambled packets must be indicated by programming a logic 1 to the corresponding bit of the pidi_is_pes word (see table 10, address 0x0206). mpeg-2 multiplex fields which are related to ca information, in so called sections, are parsed only partly. ca sections containing for instance entitlement management messages (emm) and entitlement control messages (ecm) etc. are retrieved from the stream and stored in 256 byte buffers in the ca filter module. for the selection of ca data, 18 additional pids and section header information (table_id, address field, both with bit masks) can be programmed. all 13 bits of pid filters 16 and 17 can be individually enabled/disabled with a mask of 13 bits (see table 10, addresses 0x03a6 and 0x03ba) to enable multiple pid selection for ca messages. a microcontroller may access data in the 256 byte ca buffers (each filter has its own buffer thus 18 in total) for software based parsing and processing.
1996 oct 09 11 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.5 signal constellation fec decoder - descrambler interfacing. handbook, full pagewidth descrambler fec mbclk min7 to min0 msync mdv mb/mb mb/mb 8 min7 to min0 mbclk mdv mb/mb msync message invalid data message invalid data error-free transport packet (programmable polarity) erroneous transport packet mgg317 dclk fig.6 mpeg-2 two level hierarchical demultiplexing. handbook, full pagewidth transport stream packetized elementary stream elementary stream = transport_header = pes_header = stuffing mgg318
1996 oct 09 12 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 7.2 pes level descrambling pes level descrambling is possible in accordance with the recommendations of the dvb standard with the dvb descrambler ic. the actual restrictions however, required by the dvb descrambler ic, are less strict than to the recommendations in the dvb standard. the restrictions for pes level descrambling imposed by the ic are as follows: scrambling shall only occur at one level (ts or pes) and is not allowed to occur at both levels simultaneously the complete pes header must be present in exactly one ts packet. consequently, the size of a pes packet header shall not exceed 184 bytes only the pes packet data bytes (pes payload) are descrambled ts packets resulting from scrambling at pes level are not chained and thus are independent. consequently, the internal descrambler algorithms (stream decipher and block decipher) are initialized at the start of each (pes scrambled) ts packet payload. in order to be able to distinguish between sections and pes packets, a pid for a pes scrambled packet is indicated by programming the according pidi_is_pes bit (see table 10, address 0x0206) to logic 1. if the payload_unit_start_indicator bit is set in the ts packet header and the pidi_is_pes bit is set for a particular pid, the pes scrambling control bits, which are present in the pes header, are stored in the accessible pes_sc_pidi register (see table 10, address 0x0208). descrambling at ts level always has priority over descrambling at pes level. consequently, pes level descrambling is only possible when the transport_scrambling_control bits in the ts header are 00. in that situation the payload of the pes packets is descrambled using the scrambling control bits of the pes_sc_pidi register. remark: pid masking (for pid5) should not be combined with pes level descrambling. only one pair of pes scrambling control bits per pid is stored in an internal register. thus interleaving of pes messages, which can occur in the situation of multiple pid selection, can give the wrong descrambling result. as a consequence the microcontroller must program the pid5_is_pes bit (see table 10, address 0x0206) to logic 0 when multiple pid selection is used. 7.3 descrambler core the descrambler core consists of three modules: a pid filter which selects packets for descrambling a control word bank containing 6 sets (odd and even) of control words and a default control word (dcw) the super descrambler core with the implementation of the stream decipherment and the block decipherment algorithms. the pid filter contains 6 registers which hold data in the format indicated in fig.7. six individual pids are stored to identify 6 packet streams. all bits of pid5 (see table 10, address 0x0205) can be masked with the pid5_mask (see table 10, address 0x209), to enable descrambling on multiple pids. to disable a bit of pid5 with the pid5_mask a logic 0 must be programmed. after a power-on reset pulse all mask bits are preset to logic 1. to each pid a 3-bit control word pair index pointer (cwpi) is attached. a cwpi prescribes which control word pair, consisting of odd and even control words, has to be used to initialize the dvb descrambler for payloads of packets with the associated pid. after a power-on reset all cwpis are set to 111 to enable a correct initialization of the conditional access system. if two or more programmed pids match the pid of the ts packet at the same time (while the cwpi value of the programmed pids is not equal to 110 or 111), the programmed pid with the lower index number has a higher priority. however, the default control word, when enabled, has the highest priority. thus, the built-in priority (high-to-low transition) for the programmed pids is; dcw, pid0, pid1, pid2, pid3, pid4 and pid5. a 2-bit scrambling_control field is present in the ts packet header and in the pes header (ts_sc1 and ts_sc0 and pes_sc1 and pes_sc0 respectively). the bits in this header field indicate whether the ts packet or pes payload is scrambled or not. in addition, these bits also indicate which control word (odd or even) of a control word pair was used to initialize the dvb descrambler, as indicated in tables 2 and 3.
1996 oct 09 13 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h if the payload of a packet is descrambled, the descrambler subsequently resets the scrambling_control bits in the ts or pes header (to 00). for each of the 6 pids in the pid filter bank the values of the ts scrambling_control bits are stored in a microcontroller accessible register, prior to descrambling [bits: ts_sc_pidi1 and ts_sc_pidi0; (see table 10, address 0x0208), i is in the range 5 to 0]. for each of the 6 pids in the pid filter bank, of which the corresponding pidi_is_pes bit (see table 10, address 0x0206) is also set to logic 1, the values of the pes scrambling_control bits are stored in a microcontroller accessible register, prior to descrambling [bits:pes_sc_pidi1 and pes_sc_pidi0 (see table 10, address 0x0208) i is in the range 5 to 0]. ts and pes scrambling_control retrieval is independent of the value of the cwpi. table 2 de?nition of the bits in the pes scrambling_control ?eld table 3 de?nition of the bits in the ts scrambling_control ?eld value description 00 data is not scrambled 01 data is not scrambled 10 data is scrambled with the even control word 11 data is scrambled with the odd control word value description 00 data is not scrambled 01 data is scrambled with the default control word 10 data is scrambled with the even control word 11 data is scrambled with the odd control word remark: the payloads of packets with ts scrambling_control bits equal to 01 are descrambled using the default control word, regardless of their pid and/or cwpi values. thus, even pids which are not programmed in the pid filter bank are descrambled with the dcw should transport_scrambling_control = 01. for pids in the pid filter bank, if transport_scrambling_control = 01, the payload is descrambled with the default control word, regardless of the value of the associated cwpi. if the default cw is invalid however [dcw_valid = 0 (see table 10, address 0x0206)], dcw based descrambling is disabled. descrambling using the dcw is only possible on ts packet level. the control word bank contains storage space for 6 control word pairs and a default control word. a control word pair consists of 2 cws and an odd and even cw, as indicated in table 4. a control word contains 64 bits. in conjunction with the control word selection mechanism given in table 4, the cw bank allows any cw pair to be used with any pid. all pids may, therefore, use their own specific cw pair, but all of them may also share one cw pair. the super descrambler algorithm is implemented in the core of the descrambler. descrambling is performed on the payload of a transport packet or a pes. the transport header, the (optional) adaptation field and the pes header are excepted.
1996 oct 09 14 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h table 4 descrambler control word storage; see table 10 table 5 cwpi values; see fig.7 control word (128 bits) address control word 0 odd control word 0 even 0x1000 to 0x1007 control word 1 odd control word 1 even 0x1008 to 0x100f control word 2 odd control word 2 even 0x1010 to 0x1017 control word 3 odd control word 3 even 0x1018 to 0x101f control word 4 odd control word 4 even 0x1020 to 0x1027 control word 5 odd control word 5 even 0x1028 to 0x102f default control word - 0x1030 to 0x1033 cwpi value description 0 0 0 select control word pair 0 0 0 1 select control word pair 1 0 1 0 select control word pair 2 0 1 1 select control word pair 3 1 0 0 select control word pair 4 1 0 1 select control word pair 5 1 1 0 do not descramble 1 1 1 do not descramble fig.7 syntax and definition of pid and control word pair index. handbook, full pagewidth 15 15 15 15 15 0 0 3 2 6 721 12 12 11 12 11 13 pid_0 pid_5 cwpi_0 cwpi_5 pid5_is_pes to pid0_is_pes dcw_valid ts_sc_pid5[1..0] to ts_sc_pid0[1..0] pes_sc_pid5[1..0] to pes_sc_pid0[1..0] pid5_mask 0x0200 - w 0x0205 - w 0x0206 - w 0x0207 - r 0x0208 - r 0x0209 - w mgg319 see table 10 for details.
1996 oct 09 15 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 7.4 microcontroller interface the microcontroller interface provides a means of communication between a system controller (for instance philips 90ce201 ) in a digital tv receiver and the descrambler internal registers and buffers. the physical interface consists of: dat7 to dat0; an 8-bit wide bidirectional data bus. data and address information are multiplexed on this bus. dcs; an active low chip select signal. the descrambler only responds to microcontroller communication if this signal is driven low. r/ w; an active high read signal, indicating that the microcontroller is attempting to read data from registers or buffers inside the descrambler. if this signal is low, data is being written to registers or buffers inside the descrambler. a1 and a0; a 2-bit address bus. if the least significant address bit (0) is logic 0, the most significant byte of a 16-bit register is addressed, otherwise the least significant byte is selected. if the most significant address bit (1) is logic 1 dat7 to dat0 carries the address information, otherwise it will carry control data. irq; an active low (open-drain output) interrupt request signal. an interrupt is set if one of the15 bits in the descramblers internal interrupt register is set. the interrupt mechanism consists of three 15-bit registers and one 4-bit register, as illustrated in fig.8. the interrupt status register enables the microcontroller to monitor the momentary status of the interrupts. this is particularly useful during read operations in the descramblers ca buffers, as the interrupt status bits in question [flt0_stat, flt1_stat, etc. (see table 10, addresses 0x0002 and 0x0004)] are reset when the buffers have been emptied or released. the interrupt mask register (see table 10, address 0x0001) prevents individual interrupts from resetting irq (to logic 0). the interrupt status bits are logically anded with the mask. if a rising edge occurs on one of the resulting signals, it is latched into the interrupt register, thus resetting irq. table 6 de?nition of interrupt mechanism; see fig.8 bit number meaning of interrupt 0 ?lter 0 retrieved ca data 1 ?lter 1 retrieved ca data 2 ?lter 2 retrieved ca data 3 ?lter 3 retrieved ca data 4 ?lter 4 retrieved ca data 5 ?lter 5 retrieved ca data 6 ?lter 6 retrieved ca data 7 ?lter 7 retrieved ca data 8 ?lter 8 retrieved ca data 9 ?lter 9 retrieved ca data 10 ?lter 10 retrieved ca data 11 ?lter 11 retrieved ca data 12 ?lter 12 retrieved ca data 13 ?lter 13 retrieved ca data 14 ?lter 14, 15, 16 or 17 retrieved ca data 15 empty fig.8 descrambler version 3, microcontroller interrupt mechanism. the interrupt register is reset when addressed. handbook, halfpage mgg320 0x0002/0x0004 (read only) 19-bit status 0x0001 (write only) 15-bit mask 0x0000 (read/write) 15-bit interrupt momentary status of the individual interrupt bits enables/disables individual interrupts latched interrupts, indicating which interrupt(s) set irq irq
1996 oct 09 16 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h the interrupt register itself is reset (to 0000000000000000) as soon as it is addressed (0x0000) by the microcontroller. a typical example of communication between microcontroller and descrambler is illustrated in fig.9. the descrambler contains an auto increment address counter which can be loaded by performing a write address operation. the present operation, whether read or write, is now performed on the current address. the next operation, whether read or write, is performed on the current address plus 1. remark: avoid resetting the auto increment address counter to 0x0000, when not handling interrupts, as addressing it causes the interrupt register to be reset. consequently, interrupt information might be lost. the descrambler internal register and buffer addresses are organized as illustrated in fig.10. the first 4 address bits (15 to 12) are used to select either the descrambler registers (equals 0) or one of the descrambler buffers (ranges 1 and 2). in the buffer mode, the remaining address bits (11 to 0) are part of the word address (range depending on the buffer, see table 10). in the register mode, bits 11 to 8 specify the register unit number (see fig.10). the remaining 8 bits of the address (7 to 0) indicate specific register addresses within a selected unit. the address range in a specific register unit depends on the number of registers present and is different for each unit. for details refer to table 10. the ca filter module in the microcontroller interface unit is capable of accessing general ca messages (ecm and emm, etc.) in the transport stream. the ca filter module consists of 18 filters and 18 buffers of 256 bytes each, thus each filter has its own data buffer. the 18 filters are divided into two types of filters, which are specified in table 9. for each filter the table_id of the section (the first byte of the section see fig.9), can be masked. the architecture of the 9 ca filter pairs is shown in fig.11. fig.9 microcontroller descrambler communication (example). the descrambler internal register address is incremented automatically. handbook, full pagewidth mgg321 a1 a0 r/w dcs dat7 to dat0 > 666 ns > 666 ns msbyte lsbyte msbyte lsbyte msbyte lsbyte > 24 ns write address n read data @ n write data @ n + 1
1996 oct 09 17 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.10 descrambler, register organization (see table 10). (1) see table 7. (2) see table 8. handbook, halfpage mgg322 if 0, registers are addressed, if >0, buffers are addressed register unit number, range 0 to 3 individual register addresses, range depending on the unit number 0 x h h h h (1) (2) table 7 buffer contents table 8 unit contents buffer number buffer contents 1 cw bank 2 ca data buffers for ?lters 0 to 15 3 ca data buffers for ?lters 16 and 17 register unit number unit contents 0 interrupt request handling control 1 parser input control 2 pid ?lter bank control 3 ca ?ltering control table 9 speci?cation of the number of ca_data_bytes which can be used for address ?ltering in the three types of ?lters in the ca ?lter module (all bits in the ?lter can be masked individually) filter number number of filters filter length (bytes) pid maskable filters 0 to 15 16 7 no filters 16 and 17 (dvb compliant) 2 17 yes the filter consists of 18 section detectors. each section detector selects and retrieves section data for ca_messages on the basis of: pid; which is maskable only for filters 16 and 17 table_id; which is maskable for all filters for filters 0 to 15; the first 7 bytes in the section payload, which are maskable for all filters (see fig.4) for filters 16 and 17; the first 17 bytes in the section payload, which are maskable for all filters (see fig.4). the ca data detected by a certain filter is stored in the 256 byte buffer, only if its buffer is empty. as soon as an entire section of ca data is stored, an interrupt is generated (see table 10, address 0x0000). the 18 section detectors can be separately enabled, to avoid unnecessary interrupts. the filter fired registers enable the microcontroller to track which filter caused a buffer to be loaded (see table 10, addresses 0x0300 and 0x0301). the maximum section length of a conditional access message is 256 bytes. if the section length of a message is higher, data acquisition into the buffer is stopped after 256 bytes and an interrupt signal (plus filter fired signal) is generated as normal. in this (erroneous) situation the section_to_long bit of the filter is also set, which can be read by the microcontroller (see table 10). the ca filters allow retrieval of multiple consecutive ca messages, even if these messages have identical selection criteria. for this purpose the 18 filters are grouped in 9 filter pairs (0 and 1, 2 and 3 to 16 and 17). each of the ca filters in a pair can be programmed equivalently. to prevent two filters from firing at the same time the equal conditions bits of the appropriate filter pair can be programmed to logic 1. as a result, the filter with the even (equals lowest) index number (for instance filter_8 of filter pair 8 and 9) fires at the first occurrence of a matching section. if, at the time of the second occurrence of a matching section, the buffer of the filter with the even index number is still occupied, the other filter (with odd index number) of a filter pair fires, thus storing the section data in its buffer.
1996 oct 09 18 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h if the microcontroller decides to read data from one of the ca buffers (see table 10, address range filter_0: 0x2000 to 0x207f to filter_17: 0x2880 to 0x28ff) it can determine when to stop reading in two ways. it can periodically poll the flt0_stat to flt17_stat bits in the interrupt status register (see table 10, address 0x0002 and 0x0004). each of these bits goes low as soon as the last valid section data is read from the associated ca buffer. another possibility is to read the high_flt_address word (haddr7 to 0, table 10, addresses 0x0302 to 0x0313). the high address indicates the number of valid section words (1 word = 2 bytes) that were written into the buffer. this number equals the number of read cycles that has to be performed to retrieve all valid data from the buffer. if the buffer contents have to be removed without being read, the microcontroller can write a logic 1 to the rst_bf17-0 bit (see table 10, address 0x0314 and 0x0315) thus releasing the buffer. another possibility is to perform a write address operation with a value of haddr7 to haddr0 plus buffer base address. the internal auto increment address counter is thus set to the last word in the buffer, causing the interrupt status bit to be reset and the filters to be reactivated, after having been idle during buffer emptying. if, during the acquisition of a ca message, one of the ts packets composing a message contains an error (transport_error_indicator = 1) the erroneous ts packet is removed and ca message acquisition is restarted. thus the complete ca message is lost when at least one of the ts packets which composes this message contains an error. duplicate ts packets containing ca messages are also removed. 7.5 output interfacing the output data stream consists of a sequence of bytes. a new byte is present at the data output pins dato7 to dato0 at each rising edge of the descrambler chip clock dclk. the control signals synco and dvo are a delayed (9 mhz) version of the input interface signals msync and mdv respectively. by this form of delay correction the relationship between the data and control signals is maintained. the mb/mb and mbclk signals are not output to the demultiplexer. the descrambler converts the mb/mb signal to the transport_error_indicator bit in the ts packets. at the descrambler output all information is consequently contained in the stream. mbclk is only used to clock data into the descrambler, interfacing to the demultiplexer is performed using the 9 mhz dclk, which is generated by the demultiplexer. 7.6 boundary scan test the dvb compliant descrambler is equipped with a 5-pins test port interface for boundary scan test (bst). the implementation is in accordance with the bst standard.
1996 oct 09 19 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h handbook, full pagewidth mgg323 filter 0 filter 1 equal conditions 256b buffer_0 256b buffer_1 filter 16 filter 17 equal conditions 256b buffer_16 256b buffer_17 identical filter (pairs) 2 to15 input stream ca module structure pid r table_id y address c pid s table_id z address d ca buffer (256 bytes) ca buffer (256 bytes) equal conditions interrupt to microcontroller interrupt to microcontroller ca filter pair architecture = filter fired indicator = filter enable fig.11 ca two filter architecture.
1996 oct 09 20 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 7.7 programming the descrambler table 10 descrambler programming. register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 irpt 0x0000- r/ w ?t14-17_irp ?t13_irp ?t12_irp ?t11_irp ?t10_irp ?t9_irp ?t8_irp ?t7_irp ?t6_irp ?t5_irp ?t4_irp ?t3_irp ?t2_irp ?t1_irpt ?t0_irpt irpt_ mask 0x0001- r/ w - msk14 msk13 msk12 msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 irpt_ status 0x0002- r - ?t14-17_stat ?t13_stat ?t12_stat ?t11_stat ?t10_stat ?t9_stat ?t8_stat ?t7_stat ?t6_stat ?t5_stat ?t4_stat ?t3_stat ?t2_stat ?t1_stat ?t0_stat chip_ identification 0x0003- r - - ------ 0 0 000011 irpt_ status_ flt14-17 0x0004- r - - ------ ---- ?t17_stat ?t16_stat ?t15_stat ?t14_stat empty 0x0005 to 0x00ff - - ------ - - ------ prs_inp ctrl 0x0100- w - - ------ - - ---- bad_ polarity 9 mhz_ interface empty 0x0101 to 0x01ff - - ------ - - ------ pid0, cwpi0 0x0200- w pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 cwpi2 cwpi1 cwpi0 pid1, cwpi1 0x0201- w pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 cwpi2 cwpi1 cwpi0 pid2, cwpi2 0x0202- w pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 cwpi2 cwpi1 cwpi0 pid3, cwpi3 0x0203- w pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 cwpi2 cwpi1 cwpi0 pid4, cwpi4 0x0204- w pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 cwpi2 cwpi1 cwpi0 pid5, cwpi5 0x0205- w pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 cwpi2 cwpi1 cwpi0
1996 oct 09 21 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h dcw_ valid 0x0206- w - - ------ - pid5_ is_pes pid4_ is_pes pid3_ is_pes pid2_ is_pes pid1_ is_pes pid0_ is_pes dcw_valid ts_scr_ ctrl 0x0207- r ---- ts_sc_ pid5_1 ts_sc_ pid5_0 ts_sc_ pid4_1 ts_sc_ pid4_0 ts_sc_ pid3_1 ts_sc_ pid3_0 ts_sc_ pid2_1 ts_sc_ pid2_0 ts_sc_ pid1_1 ts_sc_ pid1_0 ts_sc_ pid0_1 ts_sc_ pid0_0 pes_scr_ctrl 0x0208- r ---- pes_sc_ pid5_1 pes_sc_ pid5_0 pes_sc_ pid4_1 pes_sc_ pid4_0 pes_sc_ pid3_1 pes_sc_ pid3_0 pes_sc_ pid2_1 pes_sc_ pid2_0 pes_sc_ pid1_1 pes_sc_ pid1_0 pes_sc_ pid0_1 pes_sc_ pid0_0 pid5_mask 0x0209- w --- pid5_ msk12 pid5_ msk11 pid5_ msk10 pid5_ msk9 pid5_ msk8 pid5_ msk7 pid5_ msk6 pid5_ msk5 pid5_ msk4 pid5_ msk3 pid5_ msk2 pid5_ msk1 pid5_ msk0 empty 0x0210 to 0x02ff - - ------ - - ------ flt17-16 fired status 0x0300- r - - ------ - - ---- ?t17_frd ?t16_frd flt15-0 fired status 0x0301- r ?t15_frd ?t14_frd ?t13_frd ?t12_frd ?t11_frd ?t10_frd ?t9_frd ?t8_frd ?t7_frd ?t6_frd ?t5_frd ?t4_frd ?t3_frd ?t2_frd ?t1_frd ?t0_frd flt0 status 0x0302- r section to_long - ------ hadr0_7 hadr0_6 hadr0_5 hadr0_4 hadr0_3 hadr0_2 hadr0_1 hadr0_0 flt1 status 0x0303- r section to_long - ------ hadr1_7 hadr1_6 hadr1_5 hadr1_4 hadr1_3 hadr1_2 hadr1_1 hadr1_0 flt2 status 0x0304- r section to_long - ------ hadr2_7 hadr2_6 hadr2_5 hadr2_4 hadr2_3 hadr2_2 hadr2_1 hadr2_0 flt3 status 0x0305- r section to_long - ------ hadr3_7 hadr3_6 hadr3_5 hadr3_4 hadr3_3 hadr3_2 hadr3_1 hadr3_0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 22 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt4 status 0x0306- r section to_long - ------ hadr4_7 hadr4_6 hadr4_5 hadr4_4 hadr4_3 hadr4_2 hadr4_1 hadr4_0 flt5 status 0x0307- r section to_long - ------ hadr5_7 hadr5_6 hadr5_5 hadr5_4 hadr5_3 hadr5_2 hadr5_1 hadr5_0 flt6 status 0x0308- r section to_long - ------ hadr6_7 hadr6_6 hadr6_5 hadr6_4 hadr6_3 hadr6_2 hadr6_1 hadr6_0 flt7 status 0x0309- r section to_long - ------ hadr7_7 hadr7_6 hadr7_5 hadr7_4 hadr7_3 hadr7_2 hadr7_1 hadr7_0 flt8 status 0x030a- r section to_long - ------ hadr8_7 hadr8_6 hadr8_5 hadr8_4 hadr8_3 hadr8_2 hadr8_1 hadr8_0 flt9 status 0x030b- r section to_long - ------ hadr9_7 hadr9_6 hadr9_5 hadr9_4 hadr9_3 hadr9_2 hadr9_1 hadr9_0 flt10 status 0x030c- r section to_long - ------ hadr10_7 hadr10_6 hadr10_5 hadr10_4 hadr10_3 hadr10_2 hadr10_1 hadr10_0 flt11 status 0x030d- r section to_long - ------ hadr11 _7 hadr11 _6 hadr11 _5 hadr11 _4 hadr11 _3 hadr11 _2 hadr11 _1 hadr11 _0 flt12 status 0x030e- r section to_long - ------ hadr12_7 hadr12_6 hadr12_5 hadr12_4 hadr12_3 hadr12_2 hadr12_1 hadr12_0 flt13 status 0x030f- r section to_long - ------ hadr13_7 hadr13_6 hadr13_5 hadr13_4 hadr13_3 hadr13_2 hadr13_1 hadr13_0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 23 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt14 status 0x0310- r section to_long - ------ hadr14_7 hadr14_6 hadr14_5 hadr14_4 hadr14_3 hadr14_2 hadr14_1 hadr14_0 flt15 status 0x0311- r section to_long - ------ hadr15_7 hadr15_6 hadr15_5 hadr15_4 hadr15_3 hadr15_2 hadr15_1 hadr15_0 flt16 status 0x0312- r section to_long - ------ hadr16_7 hadr16_6 hadr16_5 hadr16_4 hadr16_3 hadr16_2 hadr16_1 hadr16_0 flt17 status 0x0313- r section to_long - ------ hadr17_7 hadr17_6 hadr17_5 hadr17_4 hadr17_3 hadr17_2 hadr17_1 hadr17_0 reset buffer 16 and 17 0x0314- w - - ------ - - ---- rst_bf17 rst_bf16 reset buffer 0to15 0x0315- w rst_bf15 rst_bf14 rst_bf13 rst_bf12 rst_bf11 rst_bf10 rst_bf9 rst_bf8 rst_bf7 rst_bf6 rst_bf5 rst_bf4 rst_bf3 rst_bf2 rst_bf1 rst_bf0 flt0 cntrl 0x0316- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt0 tbl_id 0x0317- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt0 adr byte0 0x0318- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt0 adr byte1 0x0319- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt0 adr byte2 0x031a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt0 adr byte3 0x031b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt0 adr byte4 0x031c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 24 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt0 adr byte5 0x031d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt0 adr byte6 0x031e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 cntrl 0x031f- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt1 tbl_id 0x0320- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt1 adr byte0 0x0321- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 adr byte1 0x0322- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 adr byte2 0x0323- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 adr byte3 0x0324- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 adr byte4 0x0325- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 adr byte5 0x0326- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt1 adr byte6 0x0327- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt2 cntrl 0x0328- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt2 tbl_id 0x0329- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt2 adr byte0 0x032a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt2 adr byte1 0x032b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 25 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt2 adr byte2 0x032c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt2 adr byte3 0x032d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt2 adr byte4 0x032e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt2 adr byte5 0x032f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt2 adr byte6 0x0330- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 cntrl 0x0331- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt3 tbl_id 0x0332- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt3 adr byte0 0x0333- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 adr byte1 0x0334- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 adr byte2 0x0335- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 adr byte3 0x0336- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 adr byte4 0x0337- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 adr byte5 0x0338- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt3 dr byte6 0x0339- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 cntrl 0x033a- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 26 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt4 tbl_id 0x033b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt4 adr byte0 0x033c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 adr byte1 0x033d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 adr byte2 0x033e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 adr byte3 0x033f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 adr byte4 0x0340- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 adr byte5 0x0341- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt4 adr byte6 0x0342- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt5 cntrl 0x0343- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt5 tbl_id 0x0344- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt5 adr byte0 0x0345- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt5 adr byte1 0x0346- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt5 adr byte2 0x0347- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt5 adr byte3 0x0348- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt5 adr byte4 0x0349- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 27 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt5 adr byte5 0x034a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt5 adr byte6 0x034b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 cntrl 0x034c- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt6 tbl_id 0x034d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt6 adr byte0 0x034e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 adr byte1 0x034f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 adr byte2 0x0350- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 adr byte3 0x0351- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 adr byte4 0x0352- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 adr byte5 0x0353- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt6 adr byte6 0x0354- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt7 cntrl 0x0355- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt7 tbl_id 0x0356- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt7 adr byte0 0x0357- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt7 adr byte1 0x0358- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 28 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt7 adr byte2 0x0359- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt7 adr byte3 0x035a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt7 adr byte4 0x035b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt7 adr byte5 0x035c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt7 adr byte6 0x035d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 cntrl 0x035e- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt8 tbl_id 0x031f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt8 adr byte0 0x0360- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 adr byte1 0x0361- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 adr byte2 0x0362- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 adr byte3 0x0363- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 adr byte4 0x0364- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 adr byte5 0x0365- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt8 adr byte6 0x0366- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 cntrl 0x0367- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 29 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt9 tbl_id 0x0368- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt9 adr byte0 0x0369- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 adr byte1 0x036a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 adr byte2 0x036b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 adr byte3 0x036c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 adr byte4 0x036d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 adr byte5 0x036e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt9 adr byte6 0x0363f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt10 cntrl 0x0370- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt10 tbl_id 0x0371- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt10 adr byte0 0x0372- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt10 adr byte1 0x0373- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt10 adr byte2 0x0374- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt10 adr byte3 0x0375- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt10 adr byte4 0x0376- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 30 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt10 adr byte5 0x0377- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt10 adr byte6 0x0378- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 cntrl 0x0379- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt11 tbl_id 0x037a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt11 adr byte0 0x037b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 adr byte1 0x037c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 adr byte2 0x037d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 adr byte3 0x037e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 adr byte4 0x037f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 adr byte5 0x0380- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt11 adr byte6 0x0381- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt12 cntrl 0x0382- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt12 tbl_id 0x0383- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt12 adr byte0 0x0384- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt12 adr byte1 0x0385- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 31 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt12 adr byte2 0x0386- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt12 adr byte3 0x0387- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt12 adr byte4 0x0388- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt12 adr byte5 0x0389- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt12 adr byte6 0x038a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 cntrl 0x038b- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt13 tbl_id 0x038c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt13 adr byte0 0x038d- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 adr byte1 0x038e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 adr byte2 0x038f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 adr byte3 0x0390- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 adr byte4 0x0391- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 adr byte5 0x0392- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt13 adr byte6 0x0393- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 cntrl 0x0394- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 32 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt14 tbl_id 0x0395- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt14 adr byte0 0x0396- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 adr byte1 0x0397- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 adr byte2 0x0398- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 adr byte3 0x0399- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 adr byte4 0x039a- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 adr byte5 0x039b- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt14 adr byte6 0x039c- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt15 cntrl 0x039d- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt15 tbl_id 0x039e- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt15 adr byte0 0x039f- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt15 adr byte1 0x03a0- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt15 adr byte2 0x03a1- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt15 adr byte3 0x03a2- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt15 adr byte4 0x03a3- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 33 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt15 adr byte5 0x03a4- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt15 adr byte6 0x03a5- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 pid mask 0x03a6- w --- msk12 msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 flt16 cntrl 0x03a7- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt16 tbl_id 0x03a8- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt16 adr byte0 0x03a9- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte1 0x03aa- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte2 0x03ab- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte3 0x03ac- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte4 0x03ad- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte5 0x03ae- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte6 0x03af- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte7 0x03b0- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte8 0x03b1- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte9 0x03b2- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 34 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt16 adr byte10 0x03b3- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte11 0x03b4- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte12 0x03b5- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte13 0x03b6- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte14 0x03b7- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte15 0x03b8- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt16 adr byte16 0x03b9- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 pid mask 0x03ba- w --- msk12 msk11 msk10 msk9 msk8 msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 flt17 cntrl 0x03bb- w - equal_cond enable pid12 pid11 pid10 pid9 pid8 pid7 pid6 pid5 pid4 pid3 pid2 pid1 pid0 flt17 tbl_id 0x03bc- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 tblid_7 tblid_6 tblid_5 tblid_4 tblid_3 tblid_2 tblid_1 tblid_0 flt17 adr byte0 0x03bd- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte1 0x03be- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte2 0x03bf- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte3 0x03c0- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte4 0x03c1- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 35 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt17 adr byte5 0x03c2- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte6 0x03c3- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte7 0x03c4- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte8 0x03c5- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte9 0x03c6- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte10 0x03c7- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte11 0x03c8- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte12 0x03c9- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte13 0x03ca- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte14 0x03cb- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte15 0x03cc- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 flt17 adr byte16 0x03cd- w msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 adr7 adr6 adr5 adr4 adr3 adr2 adr1 adr0 empty 0x03ce to 0x0fff - - ------ - - ------ ctrl wrd0_ even3 0x1000- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd0_ even2 0x1001- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 36 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h ctrl wrd0_ even1 0x1002- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd0_ even0 0x1003- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd0_ odd3 0x1004- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd0_ odd2 0x1005- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd0_ odd1 0x1006- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd0_ odd0 0x1007- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd1_ even3 0x1008- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd1_ even2 0x1009- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd1_ even1 0x100a- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd1_ even0 0x100b- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd1_ odd3 0x100c- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd1_ odd2 0x100d- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd1_ odd1 0x100e- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd1_ odd0 0x100f- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd2_ even3 0x1010- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 37 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h ctrl_ wrd2_ even2 0x1011- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd2_ even1 0x1012- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd2_ even0 0x1013- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd2_ odd3 0x1014- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd2_ odd2 0x1015- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd2_ odd1 0x1016- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd2_ odd0 0x1017- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd3_ even3 0x1018- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd3_ even2 0x1019- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd3_ even1 0x101a- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd3_ even0 0x101b- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd3_ odd3 0x101c- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd3_ odd2 0x101d- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd3_ odd1 0x101e- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 scw18 cw17 cw16 ctrl_ wrd3_ odd0 0x101f- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 38 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h ctrl wrd4_ even3 0x1020- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd4_ even2 0x1021- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd4_ even1 0x1022- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd4_ even0 0x1023- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd4_ odd3 0x1024- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd4_ odd2 0x1025- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd4_ odd1 0x1026- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd4_ odd0 0x1027- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd5_ even3 0x1028- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd5_ even2 0x1029- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd5_ even1 0x102a- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 ctrl_ wrd5_ even0 0x102b- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 ctrl wrd5_ odd3 0x102c- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 ctrl_ wrd5_ odd2 0x102d- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 ctrl wrd5_ odd1 0x102e- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 39 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h ctrl_ wrd5_ odd0 0x102f- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 dflt_ ctrl_ wrd3 0x1030- w cw63 cw62 cw61 cw60 cw59 cw58 cw57 cw56 cw55 cw54 cw53 cw52 cw51 cw50 cw49 cw48 dflt_ ctrl_ wrd2 0x1031- w cw47 cw46 cw45 cw44 cw43 cw42 cw41 cw40 cw39 cw38 cw37 cw36 cw35 cw34 cw33 cw32 dflt_ ctrl_ wrd1 0x1032- w cw31 cw30 cw29 cw28 cw27 cw26 cw25 cw24 cw23 cw22 cw21 cw20 cw19 cw18 cw17 cw16 dflt_ ctrl_ wrd0 0x1033- w cw15 cw14 cw13 cw12 cw11 cw10 cw9 cw8 cw7 cw6 cw5 cw4 cw3 cw2 cw1 cw0 empty 0x1034 to 0x1fff - - ------ - - ------ flt0_ buffer 0x2000 to 0x207f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2080 to 0x20ff - - ------ - - ------ flt1_ buffer 0x2100 to 0x217f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2180 to 0x21ff - - ------ - - ------ flt2_ buffer 0x2200 to 0x227f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2280 to 0x22ff - - ------ - - ------ flt3_ buffer 0x2300 to 0x237f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2380 to 0x23ff - - ------ - - ------ flt4_ buffer 0x2400 to 0x247f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 40 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h empty 0x2480 to 0x24ff - - ------ - - ------ flt5_ buffer 0x2500 to 0x257f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2580 to 0x25ff - - ------ - - ------ flt6_ buffer 0x2600 to 0x267f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2680 to 0x26ff - - ------ - - ------ flt7_ buffer 0x2700 to 0x277f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2780 to 0x27ff - - ------ - - ------ flt8_ buffer 0x2800 to 0x287f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2880 to 0x28ff - - ------ - - ------ flt9_ buffer 0x2900 to 0x297f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2980 to 0x29ff - - ------ - - ------ flt10_ buffer 0x2a00 - 0x2a7f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2a80 to 0x2aff - - ------ - - ------ flt11_ buffer 0x2b00 to 0x2b7f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2b80 to 0x2bff - - ------ - - ------ register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 41 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h flt12_ buffer 0x2c00 to 0x2c7f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2c80 to 0x2cff - - ------ - - ------ flt13_ buffer 0x2d00 to 0x2d7f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2d80 to 0x2dff - - ------ - - ------ flt14_ buffer 0x2e00 to 0x2e7f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2e80 to 0x2eff - - ------ - - ------ flt15_ buffer 0x2f00 to 0x2f7f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x2f80 to 0x2fff - - ------ - - ------ flt16_ buffer 0x3000 to 0x307f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x3080 to 0x30ff - - ------ - - ------ flt17_ buffer 0x3100 to 0x317f- r data15 data14 data13 data12 data11 data10 data9 data8 data7 data6 data5 data4 data3 data2 data1 data0 empty 0x3180 to 0xffff - - ------ - - ------ register function address (hex) bits 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0
1996 oct 09 42 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 8 limiting values in accordance with the absolute maximum rating system (iec 134). 9 handling inputs and outputs are protected against electrostatic discharges in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. every pin withstands the esd test in accordance with uzw-bo/fq-b3020 ; 0 w , 200 pf machine model (300 v). 10 thermal characteristics 11 dc characteristics v ddd(core) = 3.3 v 0.3 v; v ddd =5v 0.5 v; t amb = 0 to 70 c; unless otherwise speci?ed. notes 1. all inputs at v ssd or v ddd . 2. operating inputs, unloaded outputs. symbol parameter min. max. unit v ddd(pads) digital supply voltage for pads (+5 v) - 0.5 +6.5 v v ddd(core) digital supply voltage for core (+3.3 v) - 0.5 +5.0 v v i dc input voltage - 0.5 v ddd + 0.5 v v o dc output voltage; - 0.5 v ddd + 0.5 v i ddd , i ssd dc current; v dd or v ss - 52 ma i i(max) maximum input current - 10 +10 ma i o(max) maximum output current - 20 +20 ma p tot total power dissipation - 250 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature 0 70 c symbol parameter conditions value unit r th j-a thermal resistance from junction to ambient in free air 56 k/w symbol parameter conditions min. max. unit i ddd(q) quiescent supply current v ddd = 5.5 v; note 1 - 100 m a i ddd(core) digital operating current for core v ddd = 5.5 v; v ddd(core) = 3.6 v; note 2 - 42 ma i ddd(pads) digital operating current for pads v ddd = 5.5 v; v ddd(core) = 3.6 v; note 2 - 10 ma v il low level input voltage 0 0.8 v v ih high level input voltage 2.0 v ddd v i li input leakage current v i = 0 v; t amb =25 c - 10 m a v i = 5.5 v; t amb =25 c - 10 m a v ol low level output voltage i o = 4 ma 0 0.1v ddd v v oh high level output voltage i o = 4 ma 0.9v ddd v ddd v
1996 oct 09 43 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 12 ac characteristics v ddd(core) = 3.3 v 0.3 v; v ddd =5v 0.5 v; t amb = 0 to 70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit input interface; (see fig.12) c i input capacitance - 5pf t cy byte strobe input cycle time (asynchronous mode) note 1 111 - ns t i(r)(clk) input clock rise time - 10 ns t i(f)(clk) input clock fall time - 10 ns t clkh input clock high time 20 - ns t clkl input clock low time 20 - ns t i(r) input rise time - 10 ns t i(f) input fall time - 10 ns t su(i) input set-up time 15 - ns t h(i) input hold time 5 - ns microcontroller interface c i input capacitance - 5pf t cy(cs) chip select cycle time see also fig.9 111 - ns t r(cs) chip select rise time - 10 ns t f(cs) chip select fall time - 10 ns t csh chip select high time 20 - ns t csl chip select low time 20 - ns w rite cycle ; (see figs 14 and 15) t i(r) input rise time - 10 ns t i(f) input fall time - 10 ns t su(i) input set-up time 15 - ns t h(i) input hold time 5 - ns r ead cycle ; (see fig.16) t cslr chip select low time in read mode 240 - ns t o(r) output rise time - 10 ns t o(f) output fall time - 10 ns t o(d) output delay time - 30 ns t o(h) output hold time 5 - ns t ol(z) output low z time note 2 3 30 ns t oh(z) output high z time note 2 3 30 ns
1996 oct 09 44 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h notes 1. in the synchronous mode all input signals are referenced to the descrambler clock which is specified in the output interface part. in the asynchronous mode all input signals are referenced to the mbclk. 2. data output is low impedance when both ( dcs = 0) and (r/ w = 1). t ol(z) is defined after the last change of both signals which makes the data output low impedance. t oh(z) is defined after the first change of both signals which makes the data output high impedance. output interface; (see fig.13) c o output capacitance - 10 pf c l output load capacitance - 50 pf t cy(dclk) output clock cycle time (dclk) 111 - ns t o(r)(dclk) output clock rise time - 10 ns t o(f)(dclk) output clock fall time - 10 ns t dclkh output clock high time 20 - ns t dclkl output clock low time 20 - ns t o(r) output rise time - 10 ns t o(f) output fall time - 10 ns t o(h) output hold time c l = 5 pf 3 - ns t o(d) output delay time c l =30pf - 40 ns symbol parameter conditions min. max. unit
1996 oct 09 45 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.12 timing definition of the input interface signals. handbook, full pagewidth mgg324 t i(r) t i(f) t su(i) t h(i) t cy(clk) t i(r)(clk) t i(f)(clk) t clkh t clkl min 7 to min0 mdv mb/mb msync dcs (synchronous mode) mbclk (asynchronous mode) or fig.13 timing definition of the output interface signals. handbook, full pagewidth mgg325 t o(r)(dclk) t o(f)(dclk) t dclkh t dclkl t cy(dclk) t o(d) t o(h) t o(r) t o(f) dcs dato7 to dato0 dvo synco
1996 oct 09 46 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.14 timing definition of the microcontroller interface signals (address write cycle). handbook, full pagewidth mgg326 t r(cs) t f(cs) t csl t csh t cy(cs) t su(i) t su(i) t su(i) t h(i) t h(i) t h(i) t su(i) t su(i) t su(i) t h(i) t h(i) t h(i) t i(r) t i(f) t i(r) t i(f) dcs a1 a0 r/w dat0 to dat7 msbyte lsbyte
1996 oct 09 47 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.15 timing definition of the microcontroller interface signals (data write cycle). handbook, full pagewidth mgg327 t r(cs) t f(cs) t csl t csh t cy(cs) t su(i) t su(i) t su(i) t h(i) t h(i) t h(i) t su(i) t h(i) t su(i) t h(i) t su(i) t h(i) t i(f) t i(r) t i(r) t i(f) dcs a1 a0 r/w dat0 to dat7 msbyte lsbyte
1996 oct 09 48 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h fig.16 timing definition of the microcontroller interface signals (read cycle). handbook, full pagewidth mgg328 t f(cs) t r(cs) t cslr t su(i) t h(i) t o(d) t o(h) t o(d) t o(h) lsbyte msbyte t ol(z) t o(r) t o(f) t oh(z) dcs a1 a0 r/w data
1996 oct 09 49 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 13 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 14.1 13.9 1 18.2 17.6 1.4 1.2 1.2 0.8 7 0 o o 0.2 0.1 0.2 1.95 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot319-2 92-11-17 95-02-04 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 1.2 0.8 d e q e a 1 a l p q detail x l (a ) 3 b 19 y c e h a 2 d z d a z e e v m a 1 64 52 51 33 32 20 x pin 1 index b p d h b p v m b w m w m 0 5 10 mm scale qfp64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm sot319-2 a max. 3.20
1996 oct 09 50 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 14 soldering 14.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 14.2 re?ow soldering reflow soldering techniques are suitable for all qfp and so packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference manual (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 14.3 wave soldering 14.3.1 qfp wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). 14.3.2 so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. 14.3.3 m ethod (qfp and so) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 oct 09 51 philips semiconductors product speci?cation dvb compliant descrambler SAA7206h 15 definitions 16 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca52 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 247 9145, fax. +7 095 247 9144 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580/xxx france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 537021/1200/02/pp52 date of release: 1996 oct 09 document order number: 9397 750 01331

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