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x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 1 of 24 x-mgc part number: FCU-010M002 features compliant with ieee802.3ak (10gbase-cx4) xenpak msa rev 3.0 type compatible module industry standard electrica l connector, microgigacn tm (i/o interface) xaui four channel electrical in terface (host side card edge) xaui standard 70 pin connector for host connection front panel hot swap ability. xenpak msa rev 3.0 compliant mdio link alarm status interrupt (lasi) support total power consumption under 3.0 watt 20 meters over standard infiniband copper cable (24awg) with media detect converter (o-mgc), up to 100 meters over standard multi mode fiber. no external clocks requirement ? oscillator on board description the x-mgc is a 10gigabit ethernet cx4 module that designed to ease xenpak msa 3.0 and it is an electrical module that incorporates the complete phy sical layer functionality from xaui compliant 4 lanes x 3.125 gb/s four differential electrical interface to th e microgigacn? cx4 compliant electrical interface. the x-mgc is plugged into a xenpak hosting system and connects to a 4x infiniband cable. the control interface (mdio)is also integrated. the x-mgc modul e includes 10gb/s ethernet transmitter and receiver ports. the host may control the x-mgc registers usi ng xaui interface as defined in the xenpak msa. the mux/demux, xaui interface and mdio management functi ons are all integrated into the module, as is a precision oscillator that removes any need for an external reference clock.
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 2 of 24 x-mgc block diagram 7 figure 1: functional brock diagram of x-mgc module (*1) in case of infiniband cable is connected, the power does not supply to cable, and if o-mgc is connected, a ground contact is changed vcc for power supply to o-mgc by media detect function. absolute maximum ratings parameter min typ max units notes storage temperature -20 60 ?? storage humidity 0 80 % wet bulb 38 ?? supply voltage(3.3v) 3.135 3.3 3.465 v adaptable power supply(1.5v) 1.425 1.5 1.575 v voltage on lvcmos pins 1.2 v recommended operating conditions parameter min typ max units notes operating temperature 0 50 ?? operating humidity 0 80 % wet bulb 38 ?? general electrical specification interface: xaui side; 70 pin smt connector (see xenpak msa rev3.0, chapter 8.3 and 10.7) cx4 side; infiniband 4x connector ( microgigacn? , fujitsu component ltd. patented) differential signal rate: tx and rx each 3.125 gb/s x 4 pair impedance: 100 ohms differential, ac-coupled i/o transceiver management media detect re-timer xaui in xaui out xgxs rx tx xaui in xaui out infiniband cable (< 20m) o-mgc + optical fiber (< 100m (*1) ) cx4 interface (microgigacn ? connector) power ( *1 ) reference clock vcc hot swap control normalization mdio, mdc, other signal xaui interface (70pin connector)
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 3 of 24 adaptable cable and link length: infiniband 4x cable 20m over environmental specification operating case temperature: 0 - 70 degree (in an uniform air flow of 0.5 m/s.) power consumption: 3 watt max mechanical forces maximum insertion force = 80 n (includes connector, interposer and connector shield ground spring) maximum extraction force = 50 n minimum retention force (with screws engaged) = 130 n fastener torque: 0.1 nm (3mm captive screw) transceiver and connector durability minimum mate/de-mate cycles for transceiver = 50 cycles minimum mate/de-mate cycles for 70-pin connector = 200 cycles minimum mate/de-mate cycles for cx4 connector = 250 cycles
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 4 of 24 figure 2: top level brock diagram of x-mgc driver
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 5 of 24 technical specification table 1: transmitter characteristics parameter typical units notes signal data rate 3.125 gb/s +/-100ppm unit interval (ui) nominal 320 ps differential peak to peak output voltage maximum minimum 1200 800 mvp-p mvp-p differential peak to peak output voltage difference 150 mvp-p maximum differential output template see figure 3 v transition time (20-80%) maximum minimum 130 60 ps ps figure 3: normalized transmit template 0.000 5.000 10.000 0.000 time (ui) normalized amplitude (v) -1.000 -1.500 1.000 0.500 -1.500 1.500
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 6 of 24 0 table 2: receiver characteristics parameter typical units notes bit error ratio 10 -12 signal data rate 3.125 gb/s +/-100ppm unit interval (ui) nominal 320 ps differential input amplitude 1200 mvp-p maximum return loss differential (minimum) see figure 4 db 100ohm figure 4: return loss differential (minimum) 15 10 1,000 5 10,000 100 frequency (mhz) loss (db)
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 7 of 24 x-mgc xaui pin out top of transceiver pcb bottom of transceiver pcb (as viewed through top) figure 6: x-mgc transcei ver electrical pad layout toward bezel
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 8 of 24 lower row upper row figure 7: 10gb host board pad layout toward bezel
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 9 of 24 pin function definitions table 6: xaui pin function 1 pin no name dir function notes 1 gnd electrical ground 1 2 gnd electrical ground 1 3 gnd electrical ground 1 4 5.0v power 2 5 3.3v power 2 6 3.3v power 2 7 aps (1.5v) adaptive power supply 2 8 aps (1.5v) adaptive power supply 2 9 lasi lvcmos 1.2v open drain 3 10 reset i lvcmos 1.2v open drain 3 11 vend specific-signal detect passive 12 tx on/off 13 reserved reserved 4 14 mod detect o passive 15 vend specific-spare passive 16 vend specific-spare passive 17 mdio i/o management data io lvcmos 1.2v open drain 3,4 18 mdc i management data clock 3,4 19 prtad4 i port address bit 4 (low = 0) 3 20 prtad3 i port address bit 3 (low = 0) 3 21 prtad2 i port address bit 2 (low = 0) 3 22 prtad1 i port address bit 1 (low = 0) 3 23 prtad0 i port address bit 0 (low = 0) 3 24 vend specific-not connected passive 25 aps set (1.5v) passive 26 reserved reserved 4 27 aps sense passive connector to a 348 ohm resistor 28 aps (1.5v) adaptive power supply 2 29 aps (1.5v) adaptive power supply 2 30 3.3v power 2 31 3.3v power 2 32 5.0v power 2 33 gnd electrical ground 1 34 gnd electrical ground 1 35 gnd electrical ground 1
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 10 of 24 table 7: xaui pin function 2 pin no name dir function notes 36 gnd electrical ground 1 37 gnd electrical ground 1 38 reserved reserved 39 reserved reserved 40 gnd electrical ground 1 41 rx lane0+ module xaui output lane 0+ 5 42 rx lane0- module xaui output lane 0- 5 43 gnd electrical ground 1 44 rx lane1+ module xaui output lane 1+ 5 45 rx lane1- module xaui output lane 1- 5 46 gnd electrical ground 1 47 rx lane2+ module xaui output lane 2+ 5 48 rx lane2- module xaui output lane 2- 5 49 gnd electrical ground 1 50 rx lane3+ module xaui output lane 3+ 5 51 rx lane3- module xaui output lane 3- 5 52 gnd electrical ground 1 53 gnd electrical ground 1 54 gnd electrical ground 1 55 tx lane0+ module xaui input lane 0+ 5 56 tx lane0- module xaui input lane 0- 5 57 gnd electrical ground 1 58 tx lane1+ module xaui input lane 1+ 5 59 tx lane1- module xaui input lane 1- 5 60 gnd electrical ground 1 61 tx lane2+ module xaui input lane 2+ 5 62 tx lane2- module xaui input lane 2- 5 63 gnd electrical ground 1 64 tx lane3+ module xaui input lane 3+ 5 65 tx lane3- module xaui input lane 3- 5 66 gnd electrical ground 1 67 reserved reserved 68 reserved reserved 69 gnd electrical ground 1 70 gnd electrical ground 1 notes: 1) ground connections are common for tx and rx. 2) all contacts of xaui 70 pin conn ector are rated at 0.5a nominal. 3) 1.2v cmos compatible. 4) mdio and mdc timing must comply with ieee802.3ae, clause 45.3 5) xaui output characteristics should comply with ieee802.3ae clause 47.
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 11 of 24 package design mechanical design of x-mgc is shown as in following figure8. (part number: fcu-010m001) figure 8: mechanical design n ote4) this module is unable to withstand aqueous wash. n ote3) lot code, the product part number, serial number and fujitsu component limited logo are indicated. n ote2) unless otherwise specified, tolerance shall be +/-0.5mm. n ote1) this module is xenpak ?] cx4 transceiver. (part number: FCU-010M002) datum e is transceiver top surface of slot. datum h is leading edge of transceiver's pcb.
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 12 of 24 appendix a : programmable logic implementation 1 scope this document scopes to x-mgc (xenpak/x2-cx4), p/n :FCU-010M002-** (xenpak), fcu-02*m101-** (x2) 2 introduction this document describes management block implementation when x-mgc is used as 10g-cx4 phy transceiver in xenpak/x2-type application. figure 1 describes the generic x-mgc design block diagram using retimer ic. ? high speed block includes a retimer ic 10g cx4-compliant device which ensures full-duplex xaui-to-cx4 communication link ? power block that includes adaptive power supply support and power filtering ? the management block includes a register file that host can access. a non volatile memory (nvr) stores the default value of this register file. the host reads the register file for system capabilities, vendor information and link status information. the host may read or write from the register file, stor e its content in the nvr or load the default value from the nvr. retime r cx4 connecto r xenpak / x2 host interface mana g ment block nvr nvr interface powe r su pp l y
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 13 of 24 the host may indirectly access the link and host transceivers to change setting or to read status information. following reset or power up the management block initializes the host and link transceiver by a pre defined initialization sequence. after the initialization the management reads a defined link of link status registers and stores them in the register file. in case of a link status event the management generates an interrupt signal name link alarm status interrupt (lasi). 3. functional description the management block in the retimer ic xenpak/x2-rd is implemented in a fpga. the the fpga is updated over jtag. the code is written to be ported to any other technology with minimal usage of technology specific macro. any macro that can not be avoided is set to a specific verilog file. features ? compliant with xenpak msa 3.0 / x2 msa 2.0 ? smi (mdio/mdc) ? 802.3ae compliant ? i2c i/o ? to upload eprom content (vendor specific info) ? link alarm status interrupt (lasi) support. ? non volatile memory that contains xenpak/x2 registers default value. ? in circuit programming for fpga over jtag ? xenpak/x2 registers file mapped to host md io space with configurable port address. ? retimer ic initialization ? retimer ic performance optimization routine (optional) ? signal detect indication
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 14 of 24 internal architecture the following figure describes internal fpga functionality: xenpack registers nvr acess fsm smi target xen reg wr xen reg rd nvr commands nvr command status nvr write nvr read nvr wr data nvr add lasi lasi control lasi status smi master smi master fsm phy ini data (rom) phy reg.add phyreg.wrdata phy address phyreg.wr phyreg.rd phyini.address phyin.data phyreg.rddata lasi status registers update lasi block mdc mdi mdo mdooe mdc mdooe mdi mdo eeprom interface external serial eeporm nvr rd data eeclk eedo eedi eecs smi control by host xm_smi phy reg.add phyreg.wrdata phy address phyreg.wr phyreg.rd phyreg.rddata host smi figure 1 fpga block diagram the management block is comprised of several sub blocks. a xenpak/x2 register file is a volatile memory th at is mapped to the host mdio address space. the xenpak/x2 register file is defined by the xenpak/x2 msa. it makes use of the lower eight bit of the mdio data register. (except from the host indirect smi access registers) the host may read or write each register from the xenp ak/x2 register file. it can load or save the whole register file in a non volatile memory. the xenpak/x2 register file is mapped into device number 2, at the port address set by the host. the non volatile ram (nvr) fsm, manages nvr access. the following nvr commands are supported: write all read all in case of read/write all the state machine manages addr ess incrementing and data transfer from register file to nvr. nvr master, performs a 2 wire nvr commands as described by the eeprom vendor, this is a separate module support of other nvr devices is done by replacing this module. link alarm status interrupt (lasi) circuit. generates an interrupt if one of the events in the following table occurs (set). the user may mask each one of the events. the lasi block implementation follows figure 21 in
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 15 of 24 the msa. with the following exceptions: global pmd signal pk is not applicable pcs block lock 1 is not applicable. wis local fault not applicable laser fault not applicable initialization rom data is a rom that stores the initialization date. smi master together read writes the transceivers register files. in initialize the transceivers after power up and reset and reads the status registers used by the lasi block. the following state machine describes the smi master state machine. fetch data from ini data rom state 0 romferch finished ini sequence (rid_last =1) smi initalization write state 1 read reg 1.10.0 state 2 read reg 3.32.0 state 3 read reg 4.24.12 state 4 read reg 1.8.10 state 5 read reg 3.8.10 state 6 read reg 4.8.10 state 7 pol reg 1.8.11 state 9 pol reg 3.8.11 state 10 pol reg 4.8.11 state 11 reset/power up data is transfered from rid to smim, generate start pulse, latch rom data on exist from state increase rom address wait till smi tranaction finsh wait for ready from smi master data from rom is being trasfered via a trasparent latch that is open duriong this state set the address/data generate start pulse wait to ready set the address/data generate start pulse wait to ready host control state 12 to indirect mdio access fsm
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 16 of 24 interface host interface signal name type direction description mdc hstl i host management clock mdi hstl i host management data input mdo lvcmos od o host management data output xenp_prtad [4:0] hstl i xenpak/x2 registers port address tx_on_off hstl i transmit on off (only apply for optical module) lasi_out lvcmos od o link alarm status interrupt output vspec[3:1] lvcmos o vendor specific [3:1] phy interface signal name type direction description xm_mdc hstl o xenpak/x2 module management clock output, toggling at xm_clk /8 xm_mdo lvcmos od o xenpak/x2 module management data output xm_mdi hstl i xenpak/x2 module management input xm_rst_n lvcmos od o xenpak/x2 module active low reset output d1_led_tx0 hstl i signal detect from port1 d2_led_tx0 hstl i signal detect from port2 rmtctrl hstl o remote control eeprom interface signal name type direction description sda lvcmos io eeprom data scl lvcmos o eeprom clock wp lvcmos o eeprom write protect global signal name type direction description xm_clk lvcoms i clock input 20mhz hrst_n lvcmos i hardware active low reset input
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 17 of 24 programming interface port and device mapping the xenpak/x2 module is mapped to the host mdio address space. the host accesses the module using smi transactions. smi frame description appeared in table 45-64 in the ieee 802.3ea standard. ? the host sets the xenpak/x2 module port address. the xenpak/x2 register file is mapped to device 2 at that port address. ? the xenpak/x2 module as an internal smi bus that enable the management block to access the retimer registers this bus is s_smi. in this bus the line transceiver is at port address 1 and the host transceiver is at port address 2. the registers in the retimer are mapped to devices 4. ? the host has indirect access to th e retimer via registers mapped to the xenpak/x2 vendor specific space. the xenpak/x2 module has an internal smi secondary bus. on that bus, port one is mapped to smi port address ?2? while port two is mapped to smi port address ?3?. register map register address register name default value 32768 nvr control/status refer to page 23 32775 version 1e 32776 nvr_size 0 1 32777 nvr_size 1 0 32778 mem_used 1 32779 mem_used 0 32780 basic addr b 32781 cust adde 77 32782 vend addr a7 32783 ext vend addr 0 0 32784 ext vend addr 1 0 32785 reserved 0 32786 tcvr type 1: xenpak, 2: x2 32787 connector 0 32788 encoding 1 32789 bit rate h 27 32790 bit rate l 10 32791 protocol 1 32792 std comp code 0 0 32793 std comp code 1 0 32794 std comp code 2 0 32795 std comp code 3 0 32796 std comp code 4 0 32797 std comp code 5 0 32798 std comp code 6 0 32799 std comp code 7 0 32800 std comp code 8 0
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 18 of 24 register address register name default value 32801 std comp code 9 0 32802 range 0 0 32803 range 1 2 32804 fiber type 0 0 32805 fiber type 1 0 32806 wave length ch. 00 0 32807 wave length ch. 01 0 32808 wave length ch. 02 0 32809 wave length ch. 10 0 32810 wave length ch. 11 0 32811 wave length ch. 12 0 32812 wave length ch. 20 0 32813 wave length ch. 21 0 32814 wave length ch. 22 0 32815 wave length ch. 30 0 32816 wave length ch. 31 0 32817 wave length ch. 32 0 32818 package oui 0 0 32819 package oui 1 41:xenpak, c0:x2 32820 package oui 2 f4:xenpak, 98:x2 32821 package oui 3 0 32822 vendor oui 0 0 32823 vendor oui 1 9 32824 vendor oui 2 2 32825 vendor oui 3 2 32826 vendor name 0 46 32827 vendor name 1 75 32828 vendor name 2 6a 32829 vendor name 3 69 32830 vendor name 4 74 32831 vendor name 5 73 32832 vendor name 6 75 32833 vendor name 7 43 32834 vendor name 8 6f 32835 vendor name 9 6d 32836 vendor name 10 70 32837 vendor name 11 6f 32838 vendor name 12 6e 32839 vendor name 13 65 32840 vendor name 14 6e 32841 vendor name 15 74 32842 vendor p/n 0 46 32843 vendor p/n 1 43 32844 vendor p/n 2 55 32845 vendor p/n 3 2d 32846 vendor p/n 4 30 32847 vendor p/n 5 31:xenpak, 32:x2 32848 vendor p/n 6 30:xenpak, 32:x2 32849 vendor p/n 7 4d 32850 vendor p/n 8 30:xenpak, 31:x2 32851 vendor p/n 9 30
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 19 of 24 register address register name default value 32852 vendor p/n 10 32:xenpak, 31:x2 32853 vendor p/n 11 20 32854 vendor p/n 12 20 32855 vendor p/n 13 20 32856 vendor p/n 14 20 32857 vendor p/n 15 20 32858 vendor rev 0 vender information 32859 vendor rev 1 vender information 32860 vendor sn 0 0 32861 vendor sn 1 0 32862 vendor sn 2 0 32863 vendor sn 3 0 32864 vendor sn 4 0 32865 vendor sn 5 0 32866 vendor sn 6 0 32867 vendor sn 7 0 32868 vendor sn 8 0 32869 vendor sn 9 0 32870 vendor sn 10 0 32871 vendor sn 11 0 32872 vendor sn 12 0 32873 vendor sn 13 0 32874 vendor sn 14 0 32875 vendor sn 15 0 32876 data code year 0 vender information 32877 data code year 1 vender information 32878 data code year 2 vender information 32879 data code year 3 vender information 32880 date code month 0 vender information 32881 date code month 1 vender information 32882 date code day 0 vender information 32883 date code day 1 vender information 32884 date code lot 0 vender information 32885 date code lot 1 vender information 32886 current ref 5v 0 32887 current ref 3.3v 4 32888 current ref aps stress 4 32889 aps voltage 10 32890 dom cap 0 32891 optional cap 0 32892 reserved 0 32893 basic check sum 0 32894 customer area 0 0 32895 customer area 1 0 32896 customer area 2 0 32897 customer area 3 0 32898 customer area 4 0 32899 customer area 5 0 32900 customer area 6 0 32901 customer area 7 0 32902 customer area 8 0
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 20 of 24 register address register name default value 32903 customer area 9 0 32904 customer area 10 0 32905 customer area 11 0 32906 customer area 12 0 32907 customer area 13 0 32908 customer area 14 0 32909 customer area 15 0 32910 customer area 16 0 32911 customer area 17 0 32912 customer area 18 0 32913 customer area 19 0 32914 customer area 20 0 32915 customer area 21 0 32916 customer area 22 0 32917 customer area 23 0 32918 customer area 24 0 32919 customer area 25 0 32920 customer area 26 0 32921 customer area 27 0 32922 customer area 28 0 32923 customer area 29 0 32924 customer area 30 0 32925 customer area 31 0 32926 customer area 32 0 32927 customer area 33 0 32928 customer area 34 0 32929 customer area 35 0 32930 customer area 36 0 32931 customer area 37 0 32932 customer area 38 0 32933 customer area 39 0 32934 customer area 40 0 32935 customer area 41 0 32936 customer area 42 0 32937 customer area 43 0 32938 customer area 44 0 32939 customer area 45 0 32940 customer area 46 0 32941 customer area 47 0 32942 xm_smi register address refer to page 23 32943 xm_smi register data refer to page 23 32944 xm_smi command refer to page 23 32945 aggregate_mod_ctrl refer to page 24 32946 - 33030 vender specific 0 36864 rx_alarm_ctrl refer to page 24 36865 tx_alarm_ctrl refer to page 24 36866 lasi_ctrl refer to page 25 36867 rx_alarm_stat refer to page 25 36868 tx_alarm_stat refer to page 25 36869 lasi_stat refer to page 26
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 21 of 24 register detailed description register 0x8000 -- nvr_ctrl_stat address name description mode default 0.15:6 reserved no 0.5 comm command 0 = read nvr 1 = write nvr the set this bit to perform write operation or clear it for read operation rw 0 0.4 reserved no 0.3:2 comm_stat command status 00 = idle 01 = command completed successfully 10 = command in progress 11 = command failed ro 00 0.1:0 ext_comm extended command 00 = reserved 01 = reserved 10 = reserved 11 = read/write all nvr writing 11 to this filed performs write or read operation to/from all registers depends on the value of command field. rw 11 register 0x80ae -- xm_smi_addr address name description mode default 174.15:0 xm_smi_addr address register for host indirect smi transactions rw 0h register 0x80af -- xm_smi_data address name description mode default 175.15:0 xm_smi_data data register for host indirect smi transactions rw 0h register 0x80b0 -- xm_smi_command address name description mode default 176.15:3 reserved no 176.2 wr_command specifies the host initiate smi write transaction. this register is cleared at the end of the write operation 0 = idle 1 = write command rw 0 176.1 rd_command specifies the host initiate smi read transaction this register is cleared at the end of the write operation 0 = idle 1 = read operation notice: a write operation has priority over read operation. rw 0 176.0 host_line specifies to which phy the host turns 0 = host turns to line phy 1 = host turns to host phy rw 0
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 22 of 24 register 0x80b1 -- aggregate_mod_ctrl address name description mode default 7:4 reserved no 3 xmreset the content of this register drives xmreset 0 ? normal operation 1 ? retimer is held at reset rw 0 2 write_protect this register write protecting the basic region and vendor specific register 0 = vendor specific register area is not write protected 1 = vendor specific is write protected rw 1 1 d2_int_agg the content of this re gister drives int/agg input of the retimer port 2 rw 1 0 d1_int_agg the content of this re gister drives int/agg input of the retimer port 1 rw 1 register 0x9000 -- rx_alarm_ctrl address name description mode default 0.15:5 reserved no 0.4 pma_pmd_rec_ loc_fault_ct rl pma/pmd local receiver fault control, setting this bit enables lasi indication for pm a/pmd local receiver fault. 0 ? disable 1 - enable rw 1 0.3 pcs_rec_loc_f ault_ctrl pcs local receiver fault control, setting this bit enables lasi indication for pcs local receiver fault. 0 ? disable 1 - enable rw 1 0.2:1 reserved no 0.0 phy_xs_rec_l oc_fault_ctr l phy xs local receiver fault control, setting this bit enables lasi indication for phy xs local receiver fault. 0 ? disable 1 - enable rw 1 register 0x9001 -- tx_alarm_ctrl address name description mode default 15:5 reserved no 4 pma_pmd_tar_ loc_fault_ct rl pma/pmd local transmitter fault control, setting this bit enables lasi indication for pma/pmd local transmitter fault. 0 ? disable 1 - enable rw 1 3 pcs_tar_loc_f ault_ctrl pcs local transmitter fault control, setting this bit enables lasi indication for pcs local transmitter fault. 0 ? disable 1 - enable rw 1 2:1 reserved no
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 23 of 24 address name description mode default 0 phy_xs_tar_l oc_fault_ctr l phy xs local transmitter fault control, setting this bit enables lasi indication for ph y xs local transmitter fault. 0 ? disable 1 - enable rw 1 register 0x9002 -- lasi_ctrl address name description mode default 15:3 reserved no 2 rx_alarm_en receive alarm enable 0 ? disable 1 - enable rw 0 1 tx_alarm_en transmit alarm enable 0 ? disable 1 ? enable rw 0 0 ls_alarm_en lasi alarm enable 0 ? disable 1 - enable rw 0 register 0x9003 -- rx_alarm_stat address name description mode default 15:5 reserved no 4 pma_pmd_rec_ loc_fault_sta t pma/pmd local receiver fault status, 0 ? normal 1 ? fault indication ro 0 3 pcs_rec_loc_f ault_stat pcs local receiver fault status, 0 ? normal 1 ? fault indication ro 0 2:1 reserved no 0 phy_xs_rec_l oc_fault_stat phy xs local receiver fault status, 0 ? normal 1 ? fault indication ro 0 register 0x9004 -- tx_alarm_stat address name description mode default 15:5 reserved no 4 pma_pmd_tar_ loc_fault_sta t pma/pmd local transmitter fault status, 0 ? normal 1 ? fault indication ro 0 3 pcs_tar_loc_f ault_stat pcs local transmitter fault status, 0 ? normal 1 ? fault indication ro 0 2:1 reserved no 0 phy_xs_tar_l oc_fault_stat phy xs local transmitter fault status, 0 ? normal 1 ? fault indication ro 0
x x - - m m g g c c , , e e l l e e c c t t r r i i c c a a l l t t r r a a n n s s c c e e i i v v e e r r f f o o r r 1 1 0 0 g g b b a a s s e e - - c c x x 4 4 fujitsu component limited page 24 of 24 register 0x9005 -- lasi_stat address name description mode default 15:4 reserved no 3 smi_mfsm_hos t_control_gr ant ro 0 2 rx_alarm receive alarm status ro 0 1 tx_alarm transmit alarm status ro 0 0 ls_alarm lasi alarm status ro 0 references ? xenpak 10 gigabit ethernet msa rev 3.0, x2 10 gigabit ethernet msa rev 2.0 ? ieee 802.3ae clause 45

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