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description the cat1026 and cat1027 are complete memory and supervisory solutions for microcontroller-based systems. a 2kbit serial eeprom memory and a system power supervisor with brown-out protection are integrated together in low power cmos technology. memory interface is via a 400khz i 2 c bus. the cat1026 and cat1027 provide a precision v cc sense circuit with five reset threshold voltage options that support 5v, 3.3v and 3v systems. the power supply monitor and reset circuit protects memory and systems controllers during power up/down and against brownout conditions. if power supply voltages are out of tolerance reset signals become active preventing the system microcontroller, asic, or peripherals from operating. the cat1026 features two open drain reset outputs: one (reset) drives high and the other ( reset ) drives low whenever v cc falls below the threshold. reset outputs become inactive typically 200 ms after the supply voltage exceeds the reset threshold value. with both active high and low reset signals, interface to microcontrollers and other ics is simple. cat1027 has only a reset output. in addition, the reset pin can be cat1026, cat1027 dual voltage supervisory circuits with i 2 c serial 2k cmos eeprom features precision v cc power supply voltage monitor ?5v, 3.3v and 3v systems ?five threshold voltage options additional voltage monitoring ?externally adjustable down to 1.25v watchdog timer (cat1027 only) active high or low reset ?valid reset guaranteed to v cc =1v 400khz i 2 c bus 2.7v to 5.5v operation low power cmos technology 16-byte page write buffer built-in inadvertent write protection 1,000,000 program/erase cycles manual reset capability 100 year data retention 8-pin dip, soic, tssop, tdfn (msop (3x4.9mm) & 3x3mm foot prints) or msop packages ?tdfn max height is 0.8mm automotive, extended automotive and industrial temperature ranges ?2003 by catalyst semiconductor, inc. characteristics subject to change without notice doc no. 3010, rev. e used as an input for push-button manual reset capability. the cat1026 and cat1027 provide an auxiliary voltage sensor input, v sense , which is used to monitor a second system supply. the auxiliary high impedance comparator drives the open drain output, v low , whenever the sense voltage is below 1.25v threshold. the cat1027 is designed with a 1.6 second watchdog timer circuit that resets a system to a known state if software or a hardware glitch halts or ?angs?the system. the cat1027 features a watchdog timer interrupt input, wdi. eeprom memory features a 16-byte page. in addition, hardware data protection is provided by a v cc sense circuit that prevents writes to memory whenever v cc falls below the reset threshold or until v cc reaches the reset threshold during power up. available packages include 8-pin dip and surface mount, 8-pin so, 8-pin tssop, 8-pin tdfn and 8-pin msop packages. the tdfn package thickness is 0.8mm maximum. tdfn footprint options are 3x3mm or 3x4.9mm (msop pad layout). preliminary information
2 cat1026, cat1027 preliminary information doc. no. 3010, rev. e part dash minimum maximum number threshold threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 reset threshold options block diagram pin configuration (bottom view) tdfn package: 3mm x 4.9mm 0.8mm maximum height - (rd2) (bottom view) tdfn package: 3mm x 3mm 0.8mm maximum height - (rd4) v low v cc rese t scl sda reset v sense v ss cat1026 1 2 3 4 8 7 6 5 v cc wdi scl sda cat1027 1 2 3 4 8 7 6 5 v low reset v sense v ss 1 2 3 4 8 7 6 5 v cc reset scl sda cat1026 v low reset v sense v ss 1 2 3 4 8 7 6 5 v cc wdi scl sda cat1027 v low reset v sense v ss 1 2 3 4 8 7 6 5 v cc reset scl sda v low reset v sense v ss cat1026 1 2 3 4 8 7 6 5 v cc wdi scl sda cat1027 v low reset v sense v ss 2kbit d out ack sense amps shift registers control logic word address buffers start/stop logic eeprom v cc external load column decoders xdec data in storage high voltage/ timing control v ss sda reset controller state counters slave address comparators sc l reset reset (cat1026) wdi (cat1027) - + v cc v sense - + v ref v low v ref auxiliary voltage monitor v cc monitor
3 preliminary information cat1026, cat1027 doc no. 3010, rev. e pin description reset/ reset reset reset reset reset : reset outputs (reset cat1026 only) these are open drain pins and reset can be used as a manual reset trigger input. by forcing a reset condition on the pin the device will initiate and maintain a reset condition. the reset pin must be connected through a pull-down resistor, and the reset pin must be connected through a pull-up resistor. sda: serial data address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. scl: serial clock serial clock input. v sense : auxiliary voltage monitor input the v sense input is a second voltage monitor which is compared against cat1026 and cat1027 internal reference voltage of 1.25v typically. whenever the input voltage is lower than 1.25v, the open drain vlow output will be driven low. an external resistor divider is used to set the voltage level to be sensed. connect v sense to v cc if unused. v low : auxiliary voltage monitor output this open drain output goes low when v sense is less than 1.25v and goes high when v sense exceeds the reference voltage. wdi (cat1027 only): watchdog timer interrupt watchdog timer interrupt input is used to reset the watchdog timer. if a transition from high to low or low to high does not occur every 1.6 seconds, the reset outputs will be driven active. cat10xx family overview e c i v e d l a u n a m t e s e r n i p t u p n i g o d h c t a w g o d h c t a w r o t i n o m n i p e t i r w n o i t c e t o r p n i p t n e d n e p e d n i y r a i l i x u a e s n e s e g a t l o v e v i t c a : t e s e r w o l d n a h g i h m o r p e e 1 2 0 1 t a c a d s k 2 2 2 0 1 t a c a d s k 2 3 2 0 1 t a c i d w k 2 4 2 0 1 t a c k 2 5 2 0 1 t a c k 2 6 2 0 1 t a c k 2 7 2 0 1 t a c i d w k 2 operating temperature range industrial -40 ? c to 85 ? c automotive -40 ? c to 105 ? c extended -40 ? c to 125 ? c pin functions pin name function reset active low reset input/output v ss ground sda serial data/address scl clock input reset active high reset output (cat1026 only) v cc power supply v sense auxiliary voltage monitor input v low auxiliary voltage monitor output wdi watchdog timer interrupt (cat1027 only) for supervisory circuits with embedded 16k eeprom, please refer to the cat1161, cat1162 and cat1163 data sheets.
4 cat1026, cat1027 preliminary information doc. no. 3010, rev. e absolute maximum ratings temperature under bias ................. 55 c to +125 c storage temperature ....................... 65 c to +150 c voltage on any pin with respect to ground (1) ............ 2.0v to +v cc +2.0v v cc with respect to ground ............... 2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w d.c. operating characteristics v cc = +2.7v to +5.5v and over the recommended temperature conditions unless otherwise specified. notes: 1. this parameter is tested initially and after a design or process change that affects the parameter. not 100% tested. 2. latch-up protection is provided for stresses up to 100ma on input and output pins from -1v to v cc + 1v. 3. v il min and v ih max are reference values only and are not tested. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a ms t i n u i i l t n e r r u c e g a k a e l t u p n iv n i c c v o t d n g =2 -0 1a i o l t n e r r u c e g a k a e l t u p t u ov n i c c v o t d n g =0 1 -0 1a i 1 c c t n e r r u c y l p p u s r e w o p ) e t i r w ( f l c s z h k 0 0 4 = v c c v 5 . 5 = 3a m i 2 c c t n e r r u c y l p p u s r e w o p ) d a e r ( f l c s z h k 0 0 4 = v c c v 5 . 5 = 1a m i b s t n e r r u c y b d n a t s 6 2 0 1 t a c v 5 . 5 = c c v v n i 7 2 0 1 t a c c c v r o d n g = 0 5 a 0 6 v l i 3 e g a t l o v w o l t u p n i5 . 0 -c c v x 3 . 0v v h i 3 e g a t l o v h g i h t u p n ic c v x 7 . 05 . 0 + c c vv v l o e g a t l o v w o l t u p t u o , a d s ( , t e s e r v w o l ) i l o a m 3 = v c c v 7 . 2 = 4 . 0v v h o e g a t l o v h g i h t u p t u o ) t e s e r ( i h o a m 4 . 0 - = v c c v 7 . 2 = - c c v 5 7 . 0 v v h t d l o h s e r h t t e s e r v ( c c ) r o t i n o m 5 4 - x 2 0 1 t a c v ( c c ) v 5 = 0 5 . 45 7 . 4 v 2 4 - x 2 0 1 t a c v ( c c ) v 5 = 5 2 . 40 5 . 4 0 3 - x 2 0 1 t a c v ( c c ) v 3 . 3 = 0 0 . 35 1 . 3 8 2 - x 2 0 1 t a c v ( c c ) v 3 . 3 = 5 8 . 20 0 . 3 5 2 - x 2 0 1 t a c v ( c c ) v 3 = 5 5 . 20 7 . 2 v d i l a v r v d i l a v t u p t u o t e s e r c c e g a t l o v 0 0 . 1v v t r 1 s i s e r e t s y h d l o h s e r h t t e s e r5 1v m v f e r r o t i n o m e g a t l o v y r a i l i x u a d l o h s e r h t 2 . 15 2 . 13 . 1v lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. note: (1) the minimum dc input voltage is 0.5v. during transitions, inputs may undershoot to -2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time.
5 preliminary information cat1026, cat1027 doc no. 3010, rev. e capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test test conditions max units c out (1) output capacitance v out = 0v 8 pf c in (1) input capacitance v in = 0v 6 pf a.c. characteristics v cc = 2.7v to 5.5v and over the recommended temperature conditions, unless otherwise specified. notes: 1. this parameter is characterized initially and after a design or process change that affects the parameter. not 100% tested. 2. test conditions according to ac test conditions table. 3. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high and the device does not respond to its slave address. e l c y c e t i r w & d a e r y r o m e m 2 l o b m y sr e t e m a r a pn i mx a ms t i n u f l c s y c n e u q e r f k c o l c0 0 4z h k t p s e k i p s r e t l i f t u p n i ) l c s , a d s ( n o i s s e r p p u s 0 0 1s n t w o l d o i r e p w o l k c o l c3 . 1s t h g i h d o i r e p h g i h k c o l c6 . 0s t r 1 e m i t e s i r l c s d n a a d s0 0 3s n t f 1 e m i t l l a f l c s d n a a d s0 0 3s n t a t s ; d h e m i t d l o h n o i t i d n o c t r a t s6 . 0s t a t s ; u s e m i t p u t e s n o i t i d n o c t r a t s ) t r a t s d e t a e p e r a r o f ( 6 . 0s t t a d ; d h e m i t d l o h t u p n i a t a d0s n t t a d ; u s e m i t p u t e s t u p n i a t a d0 0 1s n t o t s ; u s e m i t p u t e s n o i t i d n o c p o t s6 . 0s t a a d i l a v t u o a t a d o t w o l l c s0 0 9s n t h d e m i t d l o h t u o a t a d0 5s n t f u b 1 a e r o f e b e e r f e b t s u m s u b e h t e m i t t r a t s n a c n o i s s i m s n a r t w e n 3 . 1s t c w 3 ) e g a p r o e t y b ( e m i t e l c y c e t i r w5s m
6 cat1026, cat1027 preliminary information doc. no. 3010, rev. e voltage monitor and reset circuit a.c. characteristics notes: 1. test conditions according to ac test conditions table. 2. power-up, input reference voltage v cc = v th , reset output reference voltage and load according to ac test conditions table. 3. power-down, input reference voltage v cc = v th , reset output reference voltage and load according to ac test conditions table. 4. v cc glitch reference voltage = v thmin ; based on characterization data. 5. 0 7 preliminary information cat1026, cat1027 doc no. 3010, rev. e data protection the cat1026 and cat1027 devices have been designed to solve many of the data corruption issues that have long been associated with serial eeproms. data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. whenever the device is in a reset condition, the embedded eeprom is disabled for all operations, including write operations. if the reset output(s) are active, in progress communications to the eeprom are aborted and no new communications are allowed. in this condition an internal write cycle to the memory can not be started, but an in progress internal non-volatile memory write cycle can not be aborted. an internal write cycle initiated before the reset condition can be successfully finished if there is enough time (5ms) before vcc reaches the minimum value of 2v. in addition, to avoid data corruption due to the loss of power supply voltage during the memory internal write operation, the system controller should monitor the unregulated dc power. using the second voltage sensor, v sense , to monitor an unregulated power supply, the cat1026 and cat1027 signals an impending power failure by setting v low low. watchdog timer the watchdog timer provides an independent protection for microcontrollers. during a system failure, the cat1027 device will provide a reset signal after a time-out interval of 1.6 seconds for a lack of activity. cat1027 is designed with the watchdog timer feature on the wdi pin. if wdi does not toggle within 1.6 second intervals, the reset condition will be generated on reset output. the watchdog timer is cleared by any transition on monitored line. as long as reset signal is asserted, the watchdog timer will not count and will stay cleared. device operation reset controller description the cat1026 and cat1027 precision reset controllers ensure correct system operation during brownout and power up/down conditions. they are configured with open drain reset outputs. during power-up, the reset outputs remain active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200ms (t purst ) after reaching v th . after the t purst timeout interval, the device will cease to drive the reset outputs. at this point the reset outputs will be pulled up or down by their respective pull up/down resistors. during power-down, the reset outputs will be active when v cc falls below v th . the reset output will be valid so long as v cc is >1.0v (v rvalid ). the device is designed to ignore the fast negative going v cc transient pulses (glitches). reset output timing is shown in figure 1. manual reset capability the reset pin can operate as reset output and manual reset input. the input is edge triggered; that is, the reset input will initiate a reset timeout after detecting a high to low transition. when reset i/o is driven to the active state, the 200 msec timer will begin to time the reset interval. if external reset is shorter than 200 ms, reset outputs will remain active at least 200 ms. monitoring two voltages the cat1026 and cat1027 feature a second voltage sensor, v sense , which drives the open drain v low output low whenever the input voltage is below 1.25v. the auxiliary voltage monitor timing is shown in figure 2. by using an external resistor divider the sense circuitry can be set to monitor a second supply in the system. the circuit shown in figure 3 provides an externally adjustable threshold voltage, v th_adj to monitor the auxiliary voltage. the low leakage current at v sense allows the use of large value resistors, to reduce the system power consumption. the v low output can be externally connected to the reset output to generate a reset condition when either of the supplies is invalid. in other applications, v low signal can be used to interrupt the system controller for an impending power failure notification.
8 cat1026, cat1027 preliminary information doc. no. 3010, rev. e figure 2. auxiliary voltage monitor timing t rpd2 v low t rpd2 t rpd2 t rpd 2 v sense v ref v low v sense v aux r 1 r 2 externally adjustable threshold v th-adj v th-adj = v ref r 1 + r 2 r 2 = 1.25v r 1 + r 2 r 2 cat1026/27 v cc power fail interrupt figure 3. auxiliary voltage monitor figure 1. reset output timing glitch t v cc purst t purst t rpd1 t rvalid v v th reset reset rpd1 t
9 preliminary information cat1026, cat1027 doc no. 3010, rev. e embedded eeprom operation the cat1026 and cat1027 feature a 2kbit embedded serial eeprom that supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat1026 and cat1027 monitor the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat1026 and cat1027 monitor the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat1026 and cat1027 then perform a read or write operation depending on the r/ w bit. t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 4. bus timing figure 5. write cycle timing t wr stop condition start condition address ack 8th bit byte n scl sda
10 cat1026, cat1027 preliminary information doc. no. 3010, rev. e acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat1026 and cat1027 respond with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat1026 and cat1027 begin a read mode it transmits 8 bits of data, releases the sda line and monitors the line for an acknowledge. once it receives this acknowledge, the cat1026 and cat1027 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends a 8-bit address that is to be written into the address pointers of the device. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the cat1026 and cat1027 acknowledge once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to non-volatile memory. while the cycle is in progress, the device will not respond to any request from the master device. figure 8. slave address bits cat default configuration 1 0100 00r/w start bit sda stop bit scl figure 6. start/stop timing acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 7. acknowledge timing
11 preliminary information cat1026, cat1027 doc no. 3010, rev. e page write the cat1026 and cat1027 write up to 16 bytes of data in a single write cycle, by using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been transmitted, the cat1026 and cat1027 will respond with an acknowledge and internally increment the lower order address bits by one. the high order bits remain unchanged. if the master transmits more than 16 bytes before sending the stop condition, the address counter wraps around, and previously transmitted data will be overwritten. when all 16 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the cat1026 and cat1027 in a single write cycle. byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t figure 9. byte write timing bus activity: master sda line data n+15 byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address figure 10. page write timing
12 cat1026, cat1027 preliminary information doc. no. 3010, rev. e acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write opration, the cat1026 and cat1027 initiate the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the device is still busy with the write operation, no ack will be returned. if a write operation has completed, an ack will be returned and the host can then proceed with the next read or write operation. read operations the read operation for the cat1026 and cat1027 is initiated in the same manner as the write operation with one exception, the r/ w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. scl sda 8th bit stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t figure 11. immediate address read timing
13 preliminary information cat1026, cat1027 doc no. 3010, rev. e immediate/current address read the cat1026 and cat1027 address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. for all devices, n=e=255. the counter will wrap around to zero and continue to clock out valid data for the 2k devices. after the cat1026 and cat1027 receive a slave address (with the r/ w bit set t o one), an acknowledge is issued, and the requested 8-bit byte is transmitted. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after the cat1026 and cat1027 acknowledge, the master device sends the start condition and the slave address again, this time with the r/ w bit set to one. the cat1026 and cat1027 then respond with an acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat1026 and cat1027 send the inital 8-bit byte requested, the master responds with an acknowledge which tells the device it requires more data. the cat1026 and cat1027 will continue to output an 8-bit byte for each acknowledge, thus sending the stop condition. the data being transmitted from the cat1026 and cat1027 is sent sequentially with the data from address n followed by data from address n+1. the read operation address counter increments all of the cat1026 and cat1027 address bits so that the entire memory array can be read during one operation. slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address figure 12. selective read timing figure 13. sequential read timing
14 cat1026, cat1027 preliminary information doc. no. 3010, rev. e d 0.08 c f 0.10 c 0.10m c a b 0.15 8 5 a 5 b 8 3.00 + 0.15 2.00 + 0.15 0.10 0.15 0.20 0.25 pin 1 id 0.60 + 0.10 (8x) d 0.15 c 2x 4.90 + 0.10 (5) 1 pin 1 index area 3.00 + 0.10 (s) 4 2x d c 4 0.30 + 0.05 (8x) 8x j 1.95 ref. (2x) 1 0.65 typ. (6x) 0.75 + 0.05 0.0-0.05 8x 0.20 ref. c note: 1. all dimension are in mm. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. coplanarity shall not exceed 0.08mm. 3. warpage shall not exceed 0.10mm. 4. package length / package width are considered as special characteristic(s). 5. refer to jedec mo-229, footprints are compatible to 8 msop. tdfn 3x4.9 package (rd2) package outlines
15 preliminary information cat1026, cat1027 doc no. 3010, rev. e 3.00 + 0.10 (s) 85 1 4 3.00 + 0.10 (s) pin 1 index area c 0.75 + 0.05 0.0 - 0.05 0.30 + 0.07 (8x) 0.25 min. 0.75 + 0.05 a b 58 2.30 + 0.10 c0.35 pin 1 id 1.50 + 0.10 1.95 ref. (2x) 0.65 typ. (6x) 0.30 + 0.10 (8x) 1 2x 2x 0.15 0.15 c c note: 1. all dimension are in mm. angles in degrees. 2. coplanarity shall not exceed 0.08 mm. 3. warpage shall not exceed 0.10 mm. 4. package length / package width are considered as special characteristic(s) 5. refer jedec mo-229 / weec tdfn 3x3 package (rd4)
16 cat1026, cat1027 preliminary information doc. no. 3010, rev. e ordering information note: (1) the device used in the above example is a cat1026si-30te13 (supervisory circuit with i 2 c serial 2k cmos eeprom, soic, industrial temperature, 3.0-3.15v reset threshold voltage, tape and reel). 1026 temperature range i = industrial (-40 ? c to 85 ? c) a = automotive (-40 ? c to +105 ? c) prefix device # suffix s i te13 product number 1026: 2k tape & reel te13: 2000/reel package p: pdip s: soic r: msop u: tssop rd2: 8-pad tdfn (3x4.9mm, msop footprint) rd4: 8-pad tdfn (3x3mm) -30 cat reset threshold voltage 45: 4.5-4.75v 42: 4.25-4.5v 30: 3.0-3.15v 28: 2.85-3.0v 25: 2.55-2.7v optional company id 1027: 2k e = extended automotive (-40 ? c to +125 ? c)
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 3010 revison: e issue date: 4/11/03 type: preliminary

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