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| rev. a a ad5582/ad5583 quad, parallel input, voltage output, 12-/10-bit digital-to-analog converters information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. features 12-bit linearity and monotonic ad5582 10-bit linearity and monotonic ad5583 wide operating range: single 5 v to 15 v or dual 5 v supply unipolar or bipolar operation double buffered registers enable independent or simultaneous multichannel update 4 independent rail-to-rail reference inputs 20 ma high current output drive parallel interface data readback capability 5 s settling time built-in matching resistor simplifies negative reference unconditionally stable under any capacitive loading compact footprint: tssop-48 extended temperature range: 40 c to 125 c applications process control equipment closed-loop servo control data acquisition systems digitally controlled calibration optical network control loops 4 m to 20 ma current transmitter general description the ad5582/ad5583 family of quad, 12-/10-bit, voltage output digital-to-analog converters is designed to operate from a single 5 v to 15 v or dual 5 v supply. it offers the user ease of use in single- or dual-supply systems. built using an advance bicmos process, this high performance dac is dynamically stable, ca pable of high current drive, and in small form factor. the applied external reference v ref determines the full-scale out- put voltage ranges from v ss to v dd , resulting in a wide selection of full-scale outputs. for multiplying and w ide dynamic appli- cations, ac reference inputs can be as high as |v dd ?v ss |. two built-in precision trimmed resis tors are avail able and can be configured easily to provide four- quadrant multiplications. a doubled-buffered parallel interface offers a fast settling time. a common level sensitive load dac strobe ( ldac ) input allows additional simultaneous update of all dac outputs. an external asynchronous reset ( rs ) forces all registers to the zero code state when the msb = 0 or to midscale when the msb = 1. both parts are offered in the same pinout and package to allow users to select the appropriate resolution for a given application without pcb layout changes. the ad5582 is well suited for dac8412 replacement in me dium voltage applications in new designs, as well as any other general purpose multichannel 10- to 12-bit applications. the ad5582/ad5583 are specified over the extended industrial (?0 c to +125 c) temperature range and offered in a thin and compact 1.1 mm tssop-48 package. ad5582 functional block diagram 44 vod + 33 a1 32 a0 31 db11 30 db10 29 db9 28 db8 26 db7 25 db6 24 db5 23 db4 21 db3 20 db2 19 db1 18 db0 34 cs 35 r/ w 14 dv dd 17 msb 16 rs 15 ldac i n t e r f a c e oe control logic 22 dgnd1 27 dgnd2 36 dgnd3 40 v refhd 39 v refld 41 v refhc 42 v reflc 45 v ss2 46 v dd2 d o in reg d i 47 voc 3 v dd1 4 v ss1 5 voa 2 vob 11 r1 12 rct 13 r2 20k 20k 1 a gnd1 48 a gnd2 dac reg addr decode 38 v dd3 37 v ss3 4 4 ad5582 + 10 v refla 9 v refha 7 v reflb 8 v refhb adr421 ref dac a 2.5v dac b 2.5v dac c 2.5v dac d 2.5v ad5582/ad5583 v refha v refhb v refhc v refhd v refla v reflb v reflc v refld 2.5v r1 r2 + 2.5v rct digital circuitry omitted for clarity figure 1. using built-in matching resistors to generate a negative voltage reference
rev. a C C rev. a ad5582/ad5583 C C rev. a C C rev. a ad5582/ad5583 C C rev. a C C rev. a ad5582/ad5583 C C rev. a C C rev. a ad5582/ad5583 C C rev. a C C rev. a t ypical performance characteristicsead5582/ad5583 C C code (decimal) 1.0 05 12 1024 2048 3072 4096 inl (lsb) 0.6 0.2 ?0.2 ?0.6 ?1.0 1536 2560 3584 0.8 0.4 0 ?0.4 ?0.8 tpc 1. ad5582 integral nonlinearity error code (decimal) 1.0 0 512 1024 2048 3072 4096 dnl ( lsb) 0.6 0.2 ?0.2 ?0.6 ?1.0 1536 2560 3584 0.8 0.4 0 ?0.4 ?0.8 tpc 2. ad5582 differential nonlinearity error code (decimal) 1.0 01 28 256 512 768 1024 inl (lsb) 0.6 0.2 ?0.2 ?0.6 ?1.0 384 640 896 0.8 0.4 0 ?0.4 ?0.8 dac-a dac-b dac-d dac-c tpc 3. ad5583 integral nonlinearity error code (decimal) 1.0 012825 651276 8 1024 dnl (lsb) 0.6 0.2 ?0.2 ?0.6 ?1.0 384 640 896 0.8 0.4 0 ?0.4 ?0.8 tpc 4. ad5583 differential nonlinearity error v dd ? v refh (mv) 6 0510 20 30 error (lsb) 2 ?2 ?6 15 25 4 0 ?4 zse dnl v dd = 5v v ss = 0v v refl = 0v no load inl ge tpc 5. ad5582 inl, dnl, zse, and ge at positive rail-to-rail operation v refl ? v ss (mv) 4 0510 20 35 error (lsb) 1 ?1 ?4 15 25 2 0 ?2 zse dnl v dd = +5v v ss = ?5v v refh = +4v no load inl ge 30 3 ?3 tpc 6. ad5582 inl, dnl, ge, and zse at negative rail-to-rail operation rev. a C C v refh ? v refl (v) 5.0 02 12 linearity error (lsb) 2.5 0 1.5 6 0.5 3.0 4.0 3.5 4.5 10 inl 8 4 2.0 1.0 dnl tpc 11. ad5582 linearity errors vs. differential reference ranges v dd (v) 2.00 02 16 i dd (ma) 1.75 1.50 1.65 6 1.55 1.80 1.90 1.85 1.95 12 8 4 1.70 1.60 14 10 v ss = 0v v refh = +4v v refl = 0v v dd = +5v v ss = ?5v v refh = +4v tpc 12. ad5582 supply current vs. supply voltage rev. a ad5582/ad5583 C C v refh (v) 3.5 ?10 ?5 20 i dd (ma) 2.5 0 1.5 5 0.5 3.0 10 0 2.0 1.0 15 v dd = +5v v ss = ?5v v refl = ?5v v dd = +5v v ss = 0v v refl = 0v v dd = +15v v ss = 0v v refl = 0v tpc 13. ad5582 supply current vs. reference voltage temperature ( c) 4.0 e60 e40 140 i dd (ma) 2.5 0 1.5 20 0.5 3.0 60 e20 2.0 1.0 100 120 04080 3.5 v dd = 15v v ss = 0v v refh = 10v v refl = 0v v dd = 5v v ss = 5v v refh = 4v v refl = 0v tpc 14. ad5582 supply current vs. temperature v ih (v) 20 01 5 i dd (ma) 10 0 6 4 2 12 2 8 4 3 16 v dd = 5v or 15v dv dd = 3v v ss = 0v 18 14 v dd = 5v or 15v dv dd = 5v v ss = 0v tpc 15. ad5582 supply current vs. logic input voltage code (decimal) 300 0 512 4096 reference current ( a) 250 0 150 3584 50 1536 200 100 2560 v dd = 5v v ss = 0v v refh = 4v v refl = 0v 3072 1024 2048 tpc 16. ad5582 reference current code (decimal) 140 0 512 4096 r ref (k ) 100 0 60 3584 20 1536 80 40 2560 3072 1024 2048 120 tpc 17. ad5582 referenced input resistance clock frequency (hz) 6 10k 100k 100m supply current (ma) 5 0 3 10m 1 4 2 1m v dd = 5v 0.5v v ss = 0v v ref = 4v data = 800 h tpc 18. ad5582 supply current vs. clock frequency rev. a C C rev. a ad5582/ad5583 C C v refh and v refl , and the output is obtained from the rightmost ladder node. as the code is sequenced through all possible states, the voltage of this node changes in steps of (2/3 v refh ?v refl )/(2 n ?1) starting from the lowest v refl and going to the highest v refh ?dutlsb. buffering it with an amplifier with a gain of 1.5 brings the output to: v d vv v out n refh refl refl = () + () 21 (1) where d is the decimal equivalent of the data bits and n is the numbers of bits. if ? refl is equal to v refh as v ref , v out is simplified to: v d v out ref = ? ? 2 4095 1 (for ad5582) (2) v d v out ref = ? ? 2 1023 1 (for ad5583) (3) the advantage of this scheme is that it allows the dac to inter- polate between two voltages for differential references or single-ended reference. these dacs feature double buffers, which allow both synchro- nous and asynchronous channels update with additional data readback capability. these parts can be reset to zero scale or mid- scale controlled by the rs and msb pins. when rs is activated, the msb of 0 resets the dacs to zero scale and the msb of 1 resets the dacs to midscale. the ability to operate from wide supply voltages, +5 v to +15 v or 5 v, with multiplying bipolar references is another key feature of these dacs. + v o r 2r 2r sw0 b0 2r sw1 b1 2r sw2 b2 2r swn? bn? 2r swn? bn? 2r r r r v refl + v refh + figure 3. simplified r-2r architecture (segmentation not shown) power supplies there are three separate power supplies needed for the opera- tion of the dacs. for dual supply, v ss can be set from ?.5 v to ?.7 v and v dd can be set from +2.7 v to +6.5 v. for single supply, v ss should be set at 0 v while v dd is set from 3 v to 16.5 v. however, setting the single supply of v dd below 4.5 v can impact the overall accuracy of the device. rev. a C C rev. a ad5582/ad5583 C C i rrr r v l dac = + () 231 3 / (4) r 3 in theory can be made small to achieve the current needed within the u4 output current driving capability. in this circuit, the ad8510 can deliver 20 ma in both directions and the voltage compliance approaches 15 v. this circuit is versatile, but users must pay attention to the compensation. without c1, it can be shown that the output impedance becomes: z rr r r rr r r r r o = + () + () + () 131 2 12 3 1 2 3 ' ''?' (5) if the resistors are perfectly matched, z o is infinite, which is highly desirable. on the other hand, if they are not matched, z o can either be positive or negative. the latter, because of the pole in the right s-plane, can cause oscillation. as a result, c1 in the range of a few pf is needed to prevent the oscillation. for critical applications, c1 should be found empirically without overcompensating. boosted programmable voltage source for users who need higher than 20 ma current driving capabil- ity, they can add an external op amp and power transistors. the capacitive loading capability will change, but it can still drive 100 nf capacitive load without oscillation in this circuit. figure 7 shows a programmable power supply with 200 ma capability. u3 op1177 + u1 ref198 v dd c1 1 f +4.096v +5v u2 ad5582 v refh v refl v dd v ss +15v fdv30in n1 load v o decoupling caps are omitted for clarity figure 7. boosted programmable voltage source table i. ad5582/ad5583 logic table input dac operation selected a1 a0 r/ wc s ldac rs rsr rsr d dac w a w w c w d w w a w w w w c w w d r rdd a r rdd r rdd c r rdd d ar ar a a a a a a ssdc rev. a C C rev. a ad5582/ad5583 C C rev. a c03040 C C C C |
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