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CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 synchronous buck nexfet ? power block 1 features description the CSD87350Q5D nexfet ? power block is an 2 ? half-bridge power block optimized design for synchronous buck applications ? 90% system efficiency at 25a offering high current, high efficiency, and high ? up to 40a operation frequency capability in a small 5-mm 6-mm outline. optimized for 5v gate drive applications, this product ? high frequency operation (up to 1.5mhz) offers a flexible solution capable of offering a high ? high density C son 5-mm 6-mm footprint density power supply when paired with any 5v gate ? optimized for 5v gate drive drive from an external controller/driver. ? low switching losses text added for spacing ? ultra low inductance package top view ? rohs compliant ? halogen free ? pb-free terminal plating applications ? synchronous buck converters C high frequency applications C high current, low duty cycle applications text added for spacing ordering information ? multiphase synchronous buck converters device package media qty ship ? pol dc-dc converters son 5-mm 6-mm 13-inch tape and CSD87350Q5D 2500 plastic package reel reel ? imvp, vrm, and vrd applications text added for spacing text added for spacing text added for spacing typical power block efficiency typical circuit and power loss 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 nexfet is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. p0116-01 1 2 3 v sw v sw v sw 4 b g 5 t gr 6 t g p gnd (pin 9) 7 v in 8 v in 0 5 10 15 20 25 30 35 40 75 77 79 81 83 85 87 89 91 93 95 0 1.2 2.4 3.6 4.8 6 7.2 8.4 9.6 10.8 12 output current (a) efficiency (%) power loss (w) v gs = 5v v in = 12v v out = 1.3v l out = 0.3h f sw = 500khz t a = 25oc
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings t a = 25 c (unless otherwise noted) (1) parameter conditions value unit v in to p gnd -0.8 to 30 v voltage range t g to t gr -8 to 10 v b g to p gnd -8 to 10 v pulsed current rating, i dm 120 a power dissipation, p d 12 w sync fet, i d = 105a, l = 0.1mh 551 avalanche energy e as mj control fet, i d = 60a, l = 0.1mh 180 operating junction and storage temperature range, t j , t stg -55 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions t a = 25 (unless otherwise noted) parameter conditions min max unit gate drive voltage, v gs 4.5 8 v input supply voltage, v in 27 v switching frequency, f sw c bst = 0.1 f (min) 200 1500 khz operating current 40 a operating temperature, t j 125 c power block performance t a = 25 (unless otherwise noted) parameter conditions min typ max unit v in = 12v, v gs = 5v, v out = 1.3v, i out = 25a, power loss, p loss (1) 3.0 w f sw = 500khz, l out = 0.3 h, t j = 25 o c t g to t gr = 0v v in quiescent current, i qvin 10 a b g to p gnd = 0v (1) measurement made with six 10 f (tdk c3216x5r1c106kt or equivalent) ceramic capacitors placed across v in to p gnd pins and using a high current 5v driver ic. thermal information t a = 25 c (unless otherwise stated) thermal metric min typ max unit junction to ambient thermal resistance (min cu) (1) (2) 102 r ja junction to ambient thermal resistance (max cu) (1) (2) 50 c/w junction to case thermal resistance (top of package) (2) 20 r jc junction to case thermal resistance (p gnd pin) (2) 2 (1) device mounted on fr4 material with 1-inch 2 (6.45-cm 2 ) cu. (2) r jc is determined with the device mounted on a 1-inch 2 (6.45-cm 2 ), 2 oz. (0.071-mm thick) cu pad on a 1.5-inch 1.5-inch (3.81-cm 3.81-cm), 0.06-inch (1.52-mm) thick fr4 board. r jc is specified by design while r ja is determined by the user s board design. 2 submit documentation feedback copyright ? 2011, texas instruments incorporated
CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 electrical characteristics t a = 25 c (unless otherwise stated) q1 control fet q2 sync fet parameter test conditions min typ max min typ max unit static characteristics bv dss drain to source voltage v gs = 0v, i ds = 250 a 30 30 v drain to source leakage i dss v gs = 0v, v ds = 20v 1 1 a current gate to source leakage i gss v ds = 0v, v gs = +10 / -8 100 100 na current gate to source threshold v gs(th) v ds = v gs , i ds = 250 a 1 2.1 0.75 1.4 v voltage v gs = 4.5v, i ds = 20a 5 6.8 2.1 2.8 m ? drain to source on r ds(on) resistance v gs = 8v, i ds = 20a 4.3 5.9 1.9 2.5 m ? g fs transconductance v ds = 15v, i ds = 20a 97 157 s dynamic characteristics c iss input capacitance 1360 1770 2950 3835 pf c oss output capacitance v gs = 0v, v ds = 15v, 565 735 1300 1690 pf f = 1mhz reverse transfer c rss 19 25 50 65 pf capacitance r g series gate resistance 1.3 3.0 0.8 2.0 q g gate charge total (4.5v) 8.4 10.9 20 26 nc gate charge - gate to q gd 1.6 3.6 nc drain v ds = 15v, i ds = 20a gate charge - gate to q gs 2.6 4.3 nc source q g(th) gate charge at vth 1.6 2.3 nc q oss output charge v ds = 17v, v gs = 0v 9.7 28 nc t d(on) turn on delay time 7 8 ns t r rise time 17 10 ns v ds = 15v, v gs = 4.5v, i ds = 20a, r g = 2 ? t d(off) turn off delay time 13 33 ns t f fall time 2.3 4.7 ns diode characteristics v sd diode forward voltage i ds = 20a, v gs = 0v 0.85 1 0.77 1 v q rr reverse recovery charge 12.5 32 nc v dd = 17v, i f = 20a, di/dt = 300a/ s t rr reverse recovery time 22 28 ns max r ja = 50 c/w max r ja = 102 c/w when mounted on when mounted on 1 inch 2 (6.45 cm 2 ) of minimum pad area of 2-oz. (0.071-mm thick) 2-oz. (0.071-mm thick) cu. cu. copyright ? 2011, texas instruments incorporated submit documentation feedback 3 hd hg lg ld m0189-01 5x6 qfn tta min rev1 ls hs hd hg lg ld m0190-01 5x6 qfn tta min rev1 ls hs
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com typical power block device characteristics t j = 125 c, unless stated otherwise. figure 1. power loss vs output current figure 2. normalized power loss vs temperature figure 3. safe operating area C pcb vertical mount (1) figure 4. safe operating area C pcb horizontal mount (1) figure 5. typical safe operating area (1) (1) the typical power block system characteristic curves are based on measurements made on a pcb design with dimensions of 4.0 (w) 3.5 (l) x 0.062 (h) and 6 copper layers of 1 oz. copper thickness. see application section for detailed explanation. 4 submit documentation feedback copyright ? 2011, texas instruments incorporated 0 5 10 15 20 25 30 35 40 45 50 0 20 40 60 80 100 120 140 board temperature (oc) output current (a) v in = 12v v gs = 5v v out = 1.3v f sw = 500khz l out = 0.3h 0 5 10 15 20 25 30 35 40 45 50 0 10 20 30 40 50 60 70 80 90 ambient temperature (oc) output current (a) 400lfm200lfm 100lfm nat conv v in = 12v v gs = 5v v out = 1.3v f sw = 500khz l out = 0.3h 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 40 output current (a) power loss (w) v in = 12v v gs = 5v v out = 1.3v f sw = 500khz l out = 0.3h 0 5 10 15 20 25 30 35 40 45 50 0 10 20 30 40 50 60 70 80 90 ambient temperature (oc) output current (a) 400lfm200lfm 100lfm nat conv v in = 12v v gs = 5v v out = 1.3v f sw = 500khz l out = 0.3h 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 ?50 ?25 0 25 50 75 100 125 150 t c ? junction temperature ? oc power loss, normalized v in = 12v v gs = 5v v out = 1.3v f sw = 500khz l out = 0.3h
CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 typical power block device characteristics (continued) t j = 125 c, unless stated otherwise. text added for spacing text added for spacing figure 6. normalized power loss vs switching frequency figure 7. normalized power loss vs input voltage text added for spacing text added for spacing figure 8. normalized power loss vs. output voltage figure 9. normalized power loss vs. output inductance copyright ? 2011, texas instruments incorporated submit documentation feedback 5 3 5 7 9 11 13 15 17 19 21 23 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?11.7 ?8.8 ?5.9 ?2.9 0.0 2.9 5.9 8.8 11.7 14.6 17.6 input voltage (v) power loss, normalized soa temperature adj (oc) v gs = 5v v out = 1.3v l out = 0.3h f sw = 500khz i out = 40a 200 350 500 650 800 950 1100 1250 1400 1550 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?11.7 ?8.8 ?5.9 ?2.9 0.0 3.0 5.9 8.8 11.8 14.7 17.6 switching frequency (khz) power loss, normalized soa temperature adj (oc) v in = 12v v gs = 5v v out = 1.3v l out = 0.3h i out = 40a 0.5 1 1.5 2 2.5 3 3.5 4 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?11.7 ?8.8 ?5.9 ?2.9 0 2.9 5.9 8.8 11.7 14.7 17.6 output voltage (v) power loss, normalized soa temperature adj (oc) v in = 12v v gs = 5v f sw = 500khz l out = 0.3h i out = 40a 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?11.7 ?8.8 ?5.9 ?2.9 0 3 5.9 8.8 11.8 14.7 17.6 output inductance (h) power loss, normalized soa temperature adj (oc) v in = 12v v gs = 5v v out = 1.3v f sw = 500khz i out = 40a
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com typical power block mosfet characteristics t a = 25 c, unless stated otherwise. text added for spacing text added for spacing figure 10. control mosfet saturation figure 11. sync mosfet saturation text added for spacing text added for spacing figure 12. control mosfet transfer figure 13. sync mosfet transfer text added for spacing text added for spacing figure 14. control mosfet gate charge figure 15. sync mosfet gate charge 6 submit documentation feedback copyright ? 2011, texas instruments incorporated 0.001 0.01 0.1 1 10 100 0 0.5 1 1.5 2 2.5 3 3.5 4 v gs - gate-to-source voltage - v i ds - drain-to-source current - a t c = 125c t c = 25c t c = ?55c v ds = 5v 0 10 20 30 40 50 60 70 80 0 0.05 0.1 0.15 0.2 0.25 0.3 v ds - drain-to-source voltage - v i ds - drain-to-source current - a v gs = 8.0v v gs = 4.5v v gs = 4.0v 0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 q g - gate charge - nc (nc) v gs - gate-to-source voltage (v) i d = 20a v dd = 15v 0 10 20 30 40 50 60 70 80 0 0.1 0.2 0.3 0.4 0.5 0.6 v ds - drain-to-source voltage - v i ds - drain-to-source current - a v gs = 8.0v v gs = 4.5v v gs = 4.0v 0.001 0.01 0.1 1 10 100 0 0.5 1 1.5 2 2.5 3 v gs - gate-to-source voltage - v i ds - drain-to-source current - a t c = 125c t c = 25c t c = ?55c v ds = 5v 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 30 35 q g - gate charge - nc (nc) v gs - gate-to-source voltage (v) i d = 20a v dd = 15v
CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 typical power block mosfet characteristics (continued) t a = 25 c, unless stated otherwise. text added for spacing text added for spacing figure 16. control mosfet capacitance figure 17. sync mosfet capacitance text added for spacing text added for spacing figure 18. control mosfet v gs(th) figure 19. sync mosfet v gs(th) text added for spacing text added for spacing figure 20. control mosfet r ds(on) vs v gs figure 21. sync mosfet r ds(on) vs v gs copyright ? 2011, texas instruments incorporated submit documentation feedback 7 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 v ds - drain-to-source voltage - v c ? capacitance ? nf c iss = c gd + c gs c oss = c ds + c gd c rss = c gd f = 1mhzv gs = 0v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 ?75 ?25 25 75 125 175 t c - case temperature - oc v gs ( th ) - threshold voltage - v i d = 250a 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 v gs - gate-to- source voltage - v r ds ( on ) - on-state resistance - m w t c = 25c t c = 125oc i d = 20a 0 2 4 6 8 10 12 14 16 0 1 2 3 4 5 6 7 8 9 10 v gs - gate-to- source voltage - v r ds ( on ) - on-state resistance - m w t c = 25c t c = 125oc i d = 20a 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 ?75 ?25 25 75 125 175 t c - case temperature - oc v gs ( th ) - threshold voltage - v i d = 250a 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 v ds - drain-to-source voltage - v c ? capacitance ? nf c iss = c gd + c gs c oss = c ds + c gd c rss = c gd f = 1mhzv gs = 0v
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com typical power block mosfet characteristics (continued) t a = 25 c, unless stated otherwise. text added for spacing text added for spacing figure 22. control mosfet normalized r ds(on) figure 23. sync mosfet normalized r ds(on) text added for spacing text added for spacing figure 24. control mosfet body diode figure 25. sync mosfet body diode text added for spacing text added for spacing figure 26. control mosfet unclamped inductive figure 27. sync mosfet unclamped inductive switching switching 8 submit documentation feedback copyright ? 2011, texas instruments incorporated 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?75 ?25 25 75 125 175 t c - case temperature - oc normalized on-state resistance i d = 20a v gs = 8v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?75 ?25 25 75 125 175 t c - case temperature - oc normalized on-state resistance i d = 20a v gs = 8v 1 10 100 0.01 0.1 1 10 t ( av ) - time in avalanche - ms i ( av ) - peak avalanche current - a t c = 25c t c = 125c 1 10 100 1000 0.01 0.1 1 10 t ( av ) - time in avalanche - ms i ( av ) - peak avalanche current - a t c = 25c t c = 125c 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 v sd ? source-to-drain voltage - v i sd ? source-to-drain current - a t c = 25c t c = 125c 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 v sd ? source-to-drain voltage - v i sd ? source-to-drain current - a t c = 25c t c = 125c
CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 application information the CSD87350Q5D nexfet ? power block is an optimized design for synchronous buck applications using 5v gate drive. the control fet and sync fet silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. as a result, a new rating method is needed which is tailored towards a more systems centric environment. system level performance curves such as power loss, safe operating area, and normalized graphs allow engineers to predict the product performance in the actual application. power loss curves mosfet centric parameters such as r ds(on) and q gd are needed to estimate the loss generated by the devices. in an effort to simplify the design process for engineers, texas instruments has provided measured power loss performance curves. figure 1 plots the power loss of the CSD87350Q5D as a function of load current. this curve is measured by configuring and running the CSD87350Q5D as it would be in the final application (see figure 28 ).the measured power loss is the CSD87350Q5D loss and consists of both input conversion loss and gate drive loss. equation 1 is used to generate the power loss curve. (v in x i in ) + (v dd x i dd ) C (v sw_avg x i out ) = power loss (1) the power loss curve in figure 1 is measured at the maximum recommended junction temperatures of 125 c under isothermal test conditions. safe operating curves (soa) the soa curves in the CSD87350Q5D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. figure 3 to figure 5 outline the temperature and airflow conditions required for a given load current. the area under the curve dictates the safe operating area. all the curves are based on measurements made on a pcb design with dimensions of 4 (w) x 3.5 (l) x 0.062 (t) and 6 copper layers of 1 oz. copper thickness normalized curves the normalized curves in the CSD87350Q5D data sheet provides guidance on the power loss and soa adjustments based on their application specific needs. these curves show how the power loss and soa boundaries will adjust for a given set of systems conditions. the primary y-axis is the normalized change in power loss and the secondary y-axis is the change is system temperature required in order to comply with the soa curve. the change in power loss is a multiplier for the power loss curve and the change in temperature is subtracted from the soa curve. figure 28. typical application copyright ? 2011, texas instruments incorporated submit documentation feedback 9
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com calculating power loss and soa the user can estimate product loss and soa boundaries by arithmetic means (see design example). though the power loss and soa curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions. design example operating conditions: ? output current = 25a ? input voltage = 7v ? output voltage = 1v ? switching frequency = 800khz ? inductor = 0.2 h calculating power loss ? power loss at 25a = 3.5w ( figure 1 ) ? normalized power loss for input voltage 1.07 ( figure 7 ) ? normalized power loss for output voltage 0.95 ( figure 8 ) ? normalized power loss for switching frequency 1.11 ( figure 6 ) ? normalized power loss for output inductor 1.07 ( figure 9 ) ? final calculated power loss = 3.5w x 1.07 x 0.95 x 1.11 x 1.07 4.23w calculating soa adjustments ? soa adjustment for input voltage 2 o c ( figure 7 ) ? soa adjustment for output voltage -1.3 o c ( figure 8 ) ? soa adjustment for switching frequency 2.8 o c ( figure 6 ) ? soa adjustment for output inductor 1.6 o c ( figure 9 ) ? final calculated soa adjustment = 2 + (-1.3) + 2.8 + 1.6 5.1 o c in the design example above, the estimated power loss of the CSD87350Q5D would increase to 4.23w. in addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1 o c. figure 29 graphically shows how the soa curve would be adjusted accordingly. 1. start by drawing a horizontal line from the application current to the soa curve. 2. draw a vertical line from the soa curve intercept down to the board/ambient temperature. 3. adjust the soa board/ambient temperature by subtracting the temperature adjustment value. in the design example, the soa temperature adjustment yields a reduction in allowable board/ambient temperature of 5.1 o c. in the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature. figure 29. power block soa 10 submit documentation feedback copyright ? 2011, texas instruments incorporated board temperature ( c) 0 20 40 60 80 100 120 140 0 5 10 15 20 25 30 35 40 45 50 g028 v = 12v in v = 5v gs v = 1.3v out f = 500khz sw l = 0.3 h out output current (a) 1 2 3
CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 recommended pcb design overview there are two key system-level parameters that can be addressed with a proper pcb design: electrical and thermal performance. properly optimizing the pcb layout will yield maximum performance in both areas. a brief description on how to address each parameter is provided. electrical performance the power block has the ability to switch voltages at rates greater than 10kv/ s. special care must be then taken with the pcb layout design and placement of the input capacitors, driver ic, and output inductor. ? the placement of the input capacitors relative to the power block s vin and pgnd pins should have the highest priority during the component placement routine. it is critical to minimize these node lengths. as such, ceramic input capacitors need to be placed as close as possible to the vin and pgnd pins (see figure 30 ). the example in figure 30 uses 6x10 f ceramic capacitors (tdk part # c3216x5r1c106kt or equivalent). notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. in terms of priority of placement next to the power block, c5, c7, c19, and c8 should follow in order. ? the driver ic should be placed relatively close to the power block gate pins. t g and b g should connect to the outputs of the driver ic. the t gr pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the ic (sometimes called lx, ll, sw, ph, etc.). the bootstrap capacitor for the driver ic will also connect to this pin. ? the switching node of the output inductor should be placed relatively close to the power block vsw pins. minimizing the node length between these two components will reduce the pcb conduction losses and actually reduce the switching noise level. (1) thermal performance the power block has the ability to utilize the gnd planes as the primary thermal path. as such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel: ? intentionally space out the vias from each other to avoid a cluster of holes in a given area. ? use the smallest drill size allowed in your design. the example in figure 30 uses vias with a 10 mil drill hole and a 16 mil capture pad. ? tent the opposite side of the via with solder-mask. in the end, the number and drill size of the thermal vias should align with the end user s pcb design rules and manufacturing capabilities. figure 30. recommended pcb layout (top down view) (1) keong w. kam, david pommerenke, emi analysis methods for synchronous buck converter emi root cause analysis , university of missouri C rolla copyright ? 2011, texas instruments incorporated submit documentation feedback 11 v in v sw p gnd b g t g t gr v sw v sw output inductor input capacitors power block input capacitors output capacitors driver ic bottom layer top layer rc snubber power block location on top layer
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com mechanical data q5d package dimensions millimeters inches dim min max min max a 1.40 1.55 0.055 0.061 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 1.630 1.730 0.064 0.068 d1 0.280 0.380 0.011 0.015 d2 0.200 0.300 0.008 0.012 d3 0.291 0.391 0.012 0.015 d1 4.900 5.100 0.193 0.201 d2 4.269 4.369 0.168 0.172 e 4.900 5.100 0.193 0.201 e1 5.900 6.100 0.232 0.240 e2 3.106 3.206 0.122 0.126 e 1.27 typ 0.050 f 0.396 0.496 0.016 0.020 l 0.510 0.710 0.020 0.028 0.00 C C C k 0.812 0.032 12 submit documentation feedback copyright ? 2011, texas instruments incorporated m0187-01 e1 e q c 5 6 7 8 1 2 3 4 l d1 f k b d3 l e1 e a e2 d2 top view bottom view front view side view 5 9 6 7 8 1 2 3 4 q c1 d1 d2 d pinout position designation pin 1 v in pin 2 v in pin 3 t g pin 4 t gr pin 5 b g pin 6 v sw pin 7 v sw pin 8 v sw pin 9 p gnd exposed tie bar may vary
CSD87350Q5D www.ti.com slps288a C march 2011 C revised march 2011 land pattern recommendation note: dimensions are in mm (inches). text for spacing stencil recommendation note: dimensions are in mm (inches). text for spacing for recommended circuit layout for pcb designs, see application note slpa005 C reducing ringing through pcb layout techniques . copyright ? 2011, texas instruments incorporated submit documentation feedback 13 m0188-01 0.650 (0.026) 0.650 (0.026) 0.620 (0.024) 0.620 (0.024) 0.415 (0.016) 1 4 5 8 0.345 (0.014) 3.480 (0.137) 0.850 (0.033) 0.850 (0.033) 0.530 (0.021) 0.400 (0.016) 6.240 (0.246) 1.920 (0.076) 4.460 (0.176) 4.460 (0.176) 1.270 (0.050) m0208-01 0.341 (0.013) 0.410 (0.016) 1 4 5 8 0.250 (0.010) 0.300 (0.012) 0.300 (0.012) stencil opening 0.300 (0.012) 0.950 (0.037) pcb pattern 1.290 (0.051) 0.610 (0.024) 1.680 (0.066) 1.710 (0.067)
CSD87350Q5D slps288a C march 2011 C revised march 2011 www.ti.com q5d tape and reel information notes: 1. 10-sprocket hole-pitch cumulative tolerance 0.2 2. camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. material: black static-dissipative polystyrene 4. all dimensions are in mm, unless otherwise specified. 5. thickness: 0.30 0.05mm 6. msl1 260 c (ir and convection) pbf reflow compatible spacer revision history changes from original (march 2011) to revision a page ? changed power dissipation, p d in the absolute maximum ratings table from; 13 w to 12 w ............................... 2 14 submit documentation feedback copyright ? 2011, texas instruments incorporated ? 1.50 +0.10 C0.00 4.00 0.10 (see note 1) 1.75 0.10 r 0.30 typ ? 1.50 min a0 k0 0.30 0.05 r 0.20 max a0 = 5.30 0.10b0 = 6.50 0.10 k0 = 1.90 0.10 m0191-01 2.00 0.05 8.00 0.10 b0 5.50 0.05 12.00 0.30
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant CSD87350Q5D son dqy 8 2500 330.0 12.4 5.3 6.3 1.8 8.0 12.0 q2 package materials information www.ti.com 27-may-2011 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) CSD87350Q5D son dqy 8 2500 346.0 346.0 29.0 package materials information www.ti.com 27-may-2011 pack materials-page 2
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