pin definition 512k x 8 sram module 512k x 8 sram module 512k x 8 sram module 512k x 8 sram module 512k x 8 sram module issue 5.0: november 1999 sys8512fkx-70/85/10/12 sys8512fkx-70/85/10/12 sys8512fkx-70/85/10/12 sys8512fkx-70/85/10/12 sys8512fkx-70/85/10/12 block diagram block diagram block diagram block diagram block diagram description features pin functions pin functions pin functions pin functions pin functions ao - a 16 oe cs 128k x 8 sram d0 - d7 we 128k x 8 sram 128k x 8 sram 128k x 8 sram decoder a17 a18 cs cs cs cs address inputs a0 - a18 a0 - a18 a0 - a18 a0 - a18 a0 - a18 data input/output d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 chip select input cs cs cs cs cs read/write input we we we we we output enable input oe oe oe oe oe power (+5v) v v v v v cc cc cc cc cc ground gnd gnd gnd gnd gnd ? access times of 70/85/100/120 ns. low seated height 32 pin 0.6" dual-in-line package with jedec compatible pinout. 5 volt supply 10%. low power dissipation: average (min cycle) 605mw (maximum). standby (cmos) 44mw (maximum). completely static operation. equal access and cycle times. all inputs and outputs directly ttl compatible. on-board supply decoupling capacitors. the sys8512fkx is plastic 4m static ram module housed in a standard 32 pin dual-in-line package organised as 512k x 8. the module utilises fast srams housed in tsop packages, and uses double sided surface mount techniques, buried decoder and dual board construction to achieve a very high density module. the module has chip select, write enable and output enable control inputs; the output enable pin allows faster access times than address access during a read cycle. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 d0 d1 d2 gnd vcc a15 a17 we a13 a8 a9 a11 oe a10 cs d7 d6 d5 d4 d3 package top view
issue 5.0 november 1999 sys8512fkx-70/85/10/12 2 dc operating conditions dc operating conditions dc operating conditions dc operating conditions dc operating conditions absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings absolute maximum ratings (1) dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics dc electrical characteristics (v cc =5v10%) t a 0 to 70 o c recommended operating conditions recommended operating conditions recommended operating conditions recommended operating conditions recommended operating conditions parameter symbol min typ max unit voltage on any pin relative to v ss v t -0.3v - +7 v power dissipation p t - 1- w storage temperature t stg -55 - +150 o c notes : (1) stresses above those listed may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specificatio n is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) v t can be -3.5v pulse of less than 20ns. parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v input high voltage v ih 2.2 - vcc + 0.3 v input low voltage v il -0.3 - 0.8 v operating temperature t a 0 - 70 o c t ai -40 - 85 o c (i) pa rameter symbol test condition min typ (2) max unit i/p leakage current a0~a16, oe i li1 0v - v in - v cc --8a output leakage current d0~d7 i lo cs = v ih, v i/o = gnd to v cc - - 8 a operating supply current i cc cs = v il ,i i/o = 0ma, v il - v in - v cc -2.1v -1645ma average supply current ttl levels i cc1 min. cycle, cs = v il , v in = v il /v cc -2.1v - 70 110 ma cmos levels i cc2 min. cycle, cs - 0.2v, v in = 0.2v/v cc -0.2v -2440ma standby supply current ttl levels i sb cs,a17-a18 = v cc -2.1v, v il - v in - v cc -2.1v -512ma cmos levels i sb1 cs,a17-a18 = v cc -0.2v, 0.2 - v in - v cc -0.2v - 0.2 8 ma -l part i sb2 as above - 10 500 a output voltage v ol i ol = 2.1ma - - 0.4 v v oh i oh = -1.0ma 2.4 - - v typical values are at v cc =5.0v,t a =25 o c and specified loading.
sys8512fkx-70/85/10/12 issue 5.0 november 1999 3 capacitance capacitance capacitance capacitance capacitance (v cc =5v10%,t a =25 o c) note: capacitance calculated, not measured. operation truth table operation truth table operation truth table operation truth table operation truth table low v low v low v low v low v cc cc cc cc cc data retention characteristics - l version only data retention characteristics - l version only data retention characteristics - l version only data retention characteristics - l version only data retention characteristics - l version only parameter symbol test condition max unit input capacitance (cs, a17, a18) c in1 v in = 0v 10 pf i/p capacitance (other) c in2 v in = 0v 40 pf i/o capacitance c i/o v i/o = 0v 40 pf cs oe we data pins supply current mode h x x high impedance i sb1 , i sb2 standby l l h data out i cc1 , i cc2 read l l l data in i cc1 , i cc2 write l h l data in i cc1 , i cc2 write notes : h = v ih : l =v il : x = v ih or v il -l part parameter symbol test condition min typ (1) max v cc for data retention v dr cs - v cc -0.2v 2.0 - - data retention current v cc = 3.0v, cs = v cc -0.2v i ccdr2 t op = 0c to 70c - 9 230 a i ccdr3 t op = t ai - - 310 a chip deselect to data retention time t cdr see retention waveform 0- - 0- -ns operation recovery time t r see retention waveform 5- - 0- -ms notes (1) typical figures are measured at 25c. (2) this parameter is guaranteed not tested. * input pulse levels: 0v to 3.0v * input rise and fall times: 5ns * input and output timing reference levels: 1.5v * output load: see diagram * v cc =5v10% ac test conditions ac test conditions ac test conditions ac test conditions ac test conditions output load output load output load output load output load
issue 5.0 november 1999 sys8512fkx-70/85/10/12 4 read cycle read cycle read cycle read cycle read cycle ac operating conditions -70 -85 -10 -12 parameter symbol min max min max min max min max unit read cycle time t rc 70 - 85 - 100 - 120 - ns address access time t aa - 70 - 85 - 100 - 120 ns chip select access time t acs - 70 - 85 - 100 - 120 ns output enable to output valid t oe -50-55 -60-70ns output hold from address change t oh 10 - 10 - 10 - 10 - ns chip selection to output in low z t clz 10 - 10 - 10 - 10 - ns output enable to output in low z t olz 5-5-5-5-ns chip deselection to o/p in high z t chz 025030 035045ns output disable to output in high z t ohz 025030 035045ns notes. (1) t hz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.these parameters are sampled and not 100% tested. -70 -85 -10 -12 parameter sym min max min max min max min max unit write cycle time t wc 70 - 85 - 100 - 120 - ns chip selection to end of write t cw 60 - 80 - 90 - 100 - ns address valid to end of write t aw 60 - 80 - 90 - 100 - ns address setup time t as 0-0-0-0-ns write pulse width t wp 55 - 65 - 75 - 85 - ns write recovery time t wr 5-5-10-10-ns write to output in high z t whz (11) 025030 035040ns data to write time overlap t dw 30 - 35 - 40 - 45 - ns data hold from write time t dh 0-0-0-0-ns output active from end of write t ow (10) 5-5-5-5-ns write cycle
sys8512fkx-70/85/10/12 issue 5.0 november 1999 5 read cycle timing waveform read cycle timing waveform read cycle timing waveform read cycle timing waveform read cycle timing waveform (1,2) ohz olz aa acs clz oe oh chz data valid t t t t t t t t t rc address cs dout oe don't care. notes (1) we is high for read cycle. (2) t hz and t ohz are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels.these parameters are sampled and not 100% tested. write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform write cycle no.1 timing waveform dw dh wp ( 1 ) as ( 3 ) aw cw ( 2 ) don't care t t t t t t t t t wc wr ( 4 ) ohz ( 5 ) address oe cs we dout din ( 6 ) hi g h-z hi g h-z ow t
issue 5.0 november 1999 sys8512fkx-70/85/10/12 6 write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform write cycle no.2 timing waveform ac characteristics notes ac characteristics notes ac characteristics notes ac characteristics notes ac characteristics notes (1) a write occurs during the overlap (t wp ) of a low cs and a low we. (2) t cw is measured from the earlier of cs or we going high to the end of write cycle. (3) t as is measured from the address valid to the beginning of write. (4) t wr is measured from the earliest of cs or we going high to the end of write. (5) during this period, i/o pins are in the output state. input signals out of phase must not be applied. (6) if cs goes low simultaneously with we going low or after we going low , outputs remain in a high impedance state. (7) d out is in the same phase as written data of this write cycle. (8) d out is the read data of next address. (9) if cs is low during this period, i/o pins are in the output state, and inputs out of phase must not be applied to i/o pins. (10) this parameter is sampled and not 100% tested. (11) t whz is defined as the time at which the outputs achieve open circuit conditions and is not referenced to output voltage levels. this parameter is sampled and not 100% tested. cw ( 2 ) wr ( 4 ) wc as ( 3 ) dw dh oh ow whz ( 5 ) aw wp ( 1 ) don't t t t t t t address cs we dout din t t t t t care hi g h-z hi g h-z (7) (8) data retention waveform data retention waveform data retention waveform data retention waveform data retention waveform t r t cdr 4.5v 2.2v 4.5v 2.2v 0v data retention mode vcc cs v dr cs > vcc -0.2v
sys8512fkx-70/85/10/12 issue 5.0 november 1999 7 package information dimensions in mm ordering information speed 70 = 70 ns 85 = 85 ns 10 = 100 ns 12 = 120 ns temperature range blank = commercial temperature i = industrial temperature power consumption blank = s tandard part l = low power part package fkx = plastic 32 pin dil organization 8512 = 512k x 8 memory type sys = static ram although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantability or fitness for a particular purpose. our products are subject to a constant process of development. data may be changed at any time without notice. products are not authorised for use as critical components in life support devices without the express approval of a company director. sys8512fkxli-10 sys8512fkxli-10 sys8512fkxli-10 sys8512fkxli-10 sys8512fkxli-10 15.24 t y p. 2.54 t y p. 3.50 +/-0.50 42.50 max. 15.92 max. min. 6.0 max.
|
