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single-channel, 1024-position, digital rheostat with i 2 c interface and 50-tp memory ad5175 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features single-channel, 1024-position resolution 10 k nominal resistance 50-times programmable (50-tp) wiper memory rheostat mode temperature coefficient: 35 ppm/c 2.7 v to 5.5 v single-supply operation 2.5 v to 2.75 v dual-supply operation for ac or bipolar operations i 2 c-compatible interface wiper setting and memory readback power on refreshed from memory resistor tolerance stored in memory thin lfcsp, 10-lead, 3 mm 3 mm 0.8 mm package compact msop, 10-lead 3 mm 4.9 mm 1.1 mm package applications mechanical rheostat replacements op-amp: variable gain control instrumentation: gain, offset adjustment programmable voltage to current conversions programmable filters, delays, time constants programmable power supply sensor calibration functional block diagram 10 v dd a w ad5175 scl addr sda i 2 c serial interface power-on reset rdac register 50-tp memory block reset v ss ext_cap gnd 08719-001 figure 1. general description the ad5175 is a single-channel, 1024-position digital rheostat that combines industry leading variable resistor performance with nonvolatile memory (nvm) in a compact package. this device supports both dual-supply operation at 2.5 v to 2.75 v and single-supply operation at 2.7 v to 5.5 v, and offers 50-times programmable (50-tp) memory. the ad5175 device wiper settings are controllable through the i 2 cCcompatible digital interface. unlimited adjustments are allowed before programming the resistance value into the 50-tp memory. the ad5175 does not require any external voltage supply to facilitate fuse blow and there are 50 oppor- tunities for permanent programming. during 50-tp activation, a permanent blow fuse command freezes the resistance position (analogous to placing epoxy on a mechanical rheostat). the ad5175 is available in a 3 mm 3mm 10-lead lfcsp package and in a 10-lead msop package. the part is guaranteed to operate over the extended industrial temperature range of ?40c to +125c.
ad5175 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 interface timing specifications .................................................. 4 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 test circuits ..................................................................................... 11 theory of operation ...................................................................... 12 serial data interface ................................................................... 12 shift register ............................................................................... 12 write operation.......................................................................... 13 read operation........................................................................... 15 rdac register ............................................................................ 16 50-tp memory block ................................................................ 16 write protection ......................................................................... 16 50-tp memory write-acknowledge polling .......................... 18 reset ............................................................................................. 18 shutdown mode ......................................................................... 18 rdac architecture .................................................................... 18 programming the variable resistor ......................................... 18 ext_cap capacitor .................................................................. 19 terminal voltage operating range ......................................... 19 power-up sequence ................................................................... 19 outline dimensions ....................................................................... 20 ordering guide .......................................................................... 20 revision history 7/10rev. 0 to rev. a changes to ordering guide .......................................................... 20 3/10revision 0: initial version
ad5175 rev. a | page 3 of 20 specifications electrical characteristics v dd = 2.7 v to 5.5 v, v ss = 0 v; v dd = 2.5 v to 2.75 v, v ss = ?2.5 v to ?2.75 v; ?40c < t a < +125c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ 1 max unit dc characteristicsrheostat mode resolution 10 bits resistor integral nonlinearity 2 , 3 r-inl |v dd ? v ss | = 3.6 v to 5.5 v ?1 +1 lsb |v dd ? v ss | = 3.3 v to 3.6 v ?1 +1.5 lsb |v dd ? v ss | = 2.7 v to 3.3 v ?2.5 +2.5 lsb resistor differential nonlinearity 2 r-dnl ?1 +1 lsb nominal resistor tolerance 15 % resistance temperature coefficient 4 , 5 code = full scale 35 ppm/c wiper resistance code = zero scale 35 70 resistor terminals terminal voltage range 4 , 6 v term v ss v dd v capacitance a 4 f = 1 mhz, measured to gnd, code = half scale 90 pf capacitance w 4 f = 1 mhz, measured to gnd, code = half scale 40 pf common-mode leakage current 4 v a = v w 50 na digital inputs input logic 4 high v inh 2.0 v low v inl 0.8 v input current i in 1 a input capacitance 4 c in 5 pf digital output output voltage 4 high v oh r pull_up = 2.2 k to v dd v dd ? 0.1 v low v ol r pull_up = 2.2 k to v dd v dd = 2.7 v to 5.5 v, v ss = 0 v 0.4 v v dd = 2.5 v to 2.75 v, v ss = ?2.5 v to ?2.75 v 0.6 v tristate leakage current ?1 +1 a output capacitance 4 5 pf power supplies single-supply power range v ss = 0 v 2.7 5.5 v dual-supply power range 2.5 2.75 v supply current positive i dd 1 a negative i ss ?1 a 50-tp store current 4 , 7 positive i dd_otp_store 4 ma negative i ss_otp_store ?4 ma 50-tp read current 4 , 8 positive i dd_otp_read 500 a negative i ss_otp_read ?500 a power dissipation 9 p diss v ih = v dd or v il = gnd 5.5 w power supply rejection ratio 4 psrr v dd /v ss = 5 v 10% ?50 ?55 db
ad5175 rev. a | page 4 of 20 parameter symbol test conditions/comments min typ 1 max unit dynamic characteristics 4 , 10 bandwidth ?3 db, r aw = 5 k, terminal w, see figure 23 700 khz total harmonic distortion v a = 1 v rms, f = 1 khz, r aw = 5 k ?90 db resistor noise density r wb = 5 k, t a = 25c, f = 10 khz 13 nv/hz 1 typical specifications represe nt average readings at 25c, v dd = 5 v, and v ss = 0 v. 2 resistor position nonlinearity error (r-inl) is the deviatio n from the ideal value measured be tween the maximum resistance and the minimum resistance wiper positions. r-dnl measures the relative step change from ideal between successive tap positions. 3 the maximum current in each code is defined by i aw = (v dd ? 1)/r aw . 4 guaranteed by design and not subject to production test. 5 see figure 8 for more details. 6 resistor terminal a and resistor terminal w have no limitations on polarity with re spect to each other. dual-supply operation enables ground referenced bipolar signal adjustment. 7 different from operating current; the supply curre nt for the fuse program lasts approximately 55 ms. 8 different from operating current; the supply curr ent for the fuse read lasts approximately 500 ns. 9 p diss is calculated from (i dd v dd ) + (i ss v ss ). 10 all dynamic characteristics use v dd = +2.5 v, v ss = ?2.5 v. interface timing specifications v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 2. limit at t min , t max parameter conditions 1 min max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz serial clock frequency t 1 standard mode 4 s t high , scl high time fast mode 0.6 s t high , scl high time t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s t low , scl low time t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns t su;dat , data setup time t 4 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s t hd;dat , data hold time t 5 standard mode 4.7 s t su;sta , set-up time for a repeated start condition fast mode 0.6 s t su;sta, set-up time for a repeated start condition t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s t hd;sta , hold time (repeated) start condition high speed mode 160 ns t hd;sta , hold time (repeated) start condition t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t buf , bus free time between a stop and a start condition t 8 standard mode 4 s t su;sto , setup time for a stop condition fast mode 0.6 s t su;sto , setup time for a stop condition t 9 standard mode 1000 ns t rda , rise time of the sda signal fast mode 300 ns t rda , rise time of the sda signal t 10 standard mode 300 ns t fda , fall time of the sda signal fast mode 300 ns t fda , fall time of the sda signal t 11 standard mode 1000 ns t rcl , rise time of the scl signal fast mode 300 ns t rcl , rise time of the scl signal t 11a standard mode 1000 ns t rcl1 , rise time of the scl signal after a repeated start condition and after an acknowledge bit fast mode 300 ns t rcl1 , rise time of the scl signal after a repeated start condition and after an acknowledge bit t 12 standard mode 300 ns t fcl , fall time of the scl signal fast mode 300 ns t fcl , fall time of the scl signal t 13 reset pulse time 20 ns minimum reset low time t sp 3 fast mode 0 50 ns pulse width of the spike is suppressed t exec 4 , 5 500 ns command execute time
ad5175 rev. a | page 5 of 20 limit at t min , t max parameter conditions 1 min max unit description t rdac_r-perf 2 s rdac register write command execute time (r-perf mode) t rdac_normal 600 ns rdac register write command execute time (normal mode) t memory_read 6 s memory readback execute time t memory_program 350 ms memory program time t reset 600 s reset 50-tp restore time t power-up 6 2 ms power-on 50-tp restore time 1 maximum bus capacitance is limited to 400 pf. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate but has a negative effect on emc behavior of the part. 3 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns for fast mode. 4 refer to t rdac_r-perf and t rdac_normal for rdac register write operations. 5 refer to t memory_read and t memory_program for memory comma nds operations. 6 maximum time after v dd ? v ss is equal to 2.5 v. shift register and timing diagrams data bits db9 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 control bits c0 c1 c2 d9 d8 c3 0 0 0 8719-003 figure 2. shift register content reset t 7 t 6 t 2 t 4 t 11 t 12 t 6 t 5 t 10 t 1 scl sda ps s p t 3 t 8 t 9 t 1 3 0 8719-002 figure 3. 2-wire i 2 c timing diagram
ad5175 rev. a | page 6 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to gnd C0.3 v to +7.0 v v ss to gnd +0.3 v to ?7.0 v v dd to v ss 7 v v a , v w to gnd v ss ? 0.3 v, v dd + 0.3 v digital input and output voltage to gnd ?0.3 v to v dd + 0.3 v ext_cap to v ss 7 v i a , i w pulsed 1 frequency > 10 khz 6 ma/d 2 frequency 10 khz 6 ma/d 2 continuous 6 ma operating temperature range 3 ?40c to +125c maximum junction temperature (t j maximum) 150c storage temperature range ?65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounde d by the maximum current handling of the switches, maximum power dissip ation of the package, and maximum applied voltage across any two of the a and w terminals at a given resistance. 2 pulse duty factor. 3 includes programmin g of 50-tp memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by jedec specification jesd-51 and the value is dependent on the test board and test environment. table 4. thermal resistance package type ja jc unit 10-lead lfcsp 50 3 c/w 10-lead msop 135 1 n/a c/w 1 jedec 2s2p test board, st ill air (0 m/sec airflow). esd caution
ad5175 rev. a | page 7 of 20 pin configuration and fu nction descriptions v dd 1 1 v ss 2 2 a 3 3 w 4 4 reset 10 9 8 scl 7 5 ext_cap sda 6 gnd ad5175 top view (not to scale) addr 08719-004 *leave floating or connected to v ss . addr v dd 1 v ss 2 a 3 w 4 reset 10 9 8 scl 7 5 ext_cap sda 6 gnd ad5175 (exposed pad)* 08719-103 figure 4. msop pin co nfiguration figure 5. lfcsp pin configuration table 5. pin function descriptions pin o. mnemonic description 1 v dd positive power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 2 a terminal a of rdac. v ss v a v dd . 3 w wiper terminal of rdac. v ss v w v dd . 4 v ss negative supply. connect to 0 v for single-supply applicat ions. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 5 ext_cap external capacitor. connect a 1 f capacitor between ext_cap and v ss . this capacitor must have a voltage rating of 7 v. 6 gnd ground pin, logic ground reference. 7 reset hardware reset pin. refreshes the rdac register with the contents of the 50-tp memory register. factory default loads midscale until the first 50-tp wiper memory location is programmed. reset is active low. tie reset to v dd if not used. 8 sda serial data line. this pin is used in conjunction with the scl line to clock data into or out of the 16-bit input registers. it is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 scl serial clock line. this pin is used in conjunction with the sda line to clock data into or out of the 16-bit input registers. 10 addr tristate address input. sets th e two least significant bits (bit a1, bit a0) of the 7-bit slave address (see table 6 ). epad exposed pad leave floating or connected to v ss
ad5175 rev. a | page 8 of 20 typical performance characteristics 0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0 128 256 384 512 640 768 896 1023 inl (lsb) code (decimal) +25c ?40c +125c 08719-014 figure 6. r-inl in normal mode vs. code vs. temperature 0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0 128 256 384 512 640 768 896 1023 dnl (lsb) code (decimal) +25c ?40c +125c 08719-015 figure 7. r-dnl in normal mode vs. code vs. temperature 700 600 500 400 300 200 100 0 0 128 256 384 512 640 768 896 1023 rheostat mode tempco (ppm/c) code (decimal) v dd /v ss = 5v/0v 08719-019 figure 8. tempco r wa /t vs. code 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 current (ma) voltage (v) 0 8719-038 v dd /v ss = 5v/0v figure 9. supply current (i dd ) vs. digital input voltage ?500 ?400 ?300 ?200 ?100 0 100 200 300 400 500 current (na) temperature (c) ?40 ?30 ?20 ?10 0 20 30 40 50 60 70 80 90 100 110 10 i dd = 5v i ss = 5v i dd = 3v i ss = 3v 0 8719-018 figure 10. supply current (i dd , i ss ) vs. temperature 7 0 1 2 3 4 5 6 0 1023 850765 935 680 510 595 340 425 170 255 85 theoretical l wa_max (ma) code (decimal) 08719-028 v dd /v ss = 5v/0v figure 11. theoretical maximum current vs. code
ad5175 rev. a | page 9 of 20 08719-031 v dd /v ss = 5v/0v ?50 ?45 ?35 ?40 ?30 ?25 ?20 ?15 ?10 ?5 0 1 10m 1m 100k 10k 1k 100 10 gain (db) frequency (hz) 0x040 0x020 0x010 0x008 0x004 0x002 0x001 0x200 0x100 0x080 figure 12. bandwidth vs. frequency vs. code thd + n (db) 08719-039 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k frequency (hz) 1m v dd /v ss = 2.5v code = half scale f in = 1v rms noise bw = 22khz figure 13. thd + n vs. frequency 08719-026 0 ?100 ?80 ?60 ?40 ?20 0.001 0.01 0.1 1 thd + n (db) amplitude (v rms) 10k? v dd /v ss = 2.5v code = half scale f in = 1khz noise bw = 22khz figure 14. thd + n vs. amplitude ? 20 ?25 ?30 ?35 ?40 ?45 ?50 ?55 ?60 10 100 1m 100k 10k 1k psrr (db) frequency (hz) v dd /v ss = 5v/0v code = half scale 08719-024 figure 15. psrr vs. frequency 4 5 6 7 8 voltage (v) time (seconds) 0.07 0.09 0.11 0.13 0.15 0.17 08719-029 figure 16. v ext_cap waveform while writing fuse 20 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 ?2 4 2 0 glitch amplitude (mv) time (s) 08719-102 v dd /v ss = 2.5v i aw = 200a figure 17. maximum glitch energy
ad5175 rev. a | page 10 of 20 1.0 ?1.5 ?1.0 ?0.5 0 0.5 ?10 60 50 40 30 20 10 0 voltage (mv) time (s) 08719-100 v dd /v ss = 2.5v i aw = 200a 0.006 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 0.005 0 1000900800700 600500400 300200100 r aw resistance (%) operation at 150c (hours) 08719-101 v dd /v ss = 5v/0v i aw = 10a code = half scale figure 18. digital feedthrough figure 19. long-term drift accelerated average by burn-in
ad5175 rev. a | page 11 of 20 test circuits figure 20 to figure 24 define the test conditions used in the specifications section. v ms i w a w dut 08719-033 figure 20. resistor position nonlinearity error (rheostat operation; r-inl, r-dnl) r wa = v ms i w r w = r wa 2 a w i w dut v ms code = 0x00 08719-034 figure 21. wiper resistance v dd i w v ms a w v+ v ms % v dd % v ms v dd v + = v dd 10 % psrr (db) = 20 log pss (%/%) = 08719-035 figure 22. power supply sensitivity (pss, psrr) v ms a w dut v 1g ? 08719-036 figure 23. gain vs. frequency i cm dut w a nc = no connect gnd +2.75v nc +2.75v ?2.75v ?2.75v gnd gnd 08719-037 figure 24. common leakage current
ad5175 rev. a | page 12 of 20 theory of operation the ad5175 is designed to operate as a true variable resistor for analog signals within the terminal voltage range of v ss < v term < v dd . the rdac register contents determine the resistor wiper position. the rdac register acts as a scratchpad register, which allows unlimited changes of resistance settings. the rdac register can be programmed with any position setting using the i 2 c interface. when a desirable wiper position is found, this value can be stored in a 50-tp memory register. thereafter, the wiper position is always restored to that position for subsequent power-up. the storing of 50-tp data takes approximately 350 ms; during this time, the ad5175 is locked and does not acknowl- edge any new command thereby preventing any changes from taking place. the acknowledge bit can be polled to verify that the fuse program command is complete. serial data interface the ad5175 has a 2-wire i 2 c-compatible serial interface. it can be connected to an i 2 c bus as a slave device under the control of a master device; see figure 3 for a timing diagram of a typical write sequence. the ad5175 supports standard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10-bit addressing and general call addressing. the ad5175 has a 7-bit slave address. the five msbs are 01011 and the two lsbs are determined by the state of the addr pin. the facility to make hardwired changes to addr allows the user to incorporate up to three of these devices on one bus, as outlined in tabl e 6 . the 2-wire serial bus protocol operates as follows: the master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the next byte is the address byte, which consists of the 7-bit slave address and a r/ w bit. the slave device corresponding to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowl- edge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse, that is, the sda line remains high. the master then brings the sda line low before the 10 th clock pulse, and then high during the 10 th clock pulse to establish a stop condition. shift register for the ad5175, the shift register is 16 bits wide, as shown in figure 2 . the 16-bit word consists of two unused bits, which should be set to 0, followed by four control bits and 10 rdac data bits, and data is loaded msb first (bit d9). the four control bits determine the function of the software command ( tabl e 7 ). figure 25 shows a timing diagram of a typical ad5175 write sequence. the command bits (cx) control the operation of the digital potentiometer and the internal 50-tp memory. the data bits (dx) are the values that are loaded into the decoded register. table 6. device address selection addr pin a1 a0 7-bit i 2 c device address gnd 1 1 0101111 v dd 0 0 0101100 nc (no connection) 1 1 0 0101110 1 not available in bipolar mode. v ss < 0 v.
ad5175 rev. a | page 13 of 20 write operation it is possible to write data for the rdac register or the control register. when writing to the ad5175, the user must begin with a start command followed by an address byte (r/ w = 0), after which the ad5175 acknowledges that it is prepared to receive data by pulling sda low. two bytes of data are then written to the rdac, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the ad5175. a stop condition follows. the write operations for the ad5175 are shown in figure 25 . a repeated write function gives the user flexibility to update the device a number of times after addressing the part only once, as shown in figure 26 . scl sda start by master ack. by ad5175 frame 1 serial bus address byte frame 2 most significant data byte frame 3 least significant data byte scl (continued) sda (continued) ack. by ad5175 ack. by ad5175 stop by master 0 19 1 99 9 1 1 011a1a0 00c3c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r/w 0 8719-005 figure 25. write command
ad5175 rev. a | page 14 of 20 scl s d a 0 19 1 99 9 1 1 0 1 1 a1 a0 r/w 0 0 c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 scl (continued) sda (continued) scl (continued) sda (continued) scl (continued) sda (continued) 1 99 d7 d6 d5 d4 d3 d2 d1 d0 1 99 0 0 c3 c2 c1 c0 d9 d8 frame 4 most significant data byte frame 5 least significant data byte start by master ack. by ad5175 ack. by ad5175 ack. by ad5175 ack. by ad5175 ack. by ad5175 stop by master frame 1 serial bus address byte frame 2 most significant data byte frame 3 least significant data byte 08719-006 figure 26. multiple write
ad5175 rev. a | page 15 of 20 read operation when reading data back from the ad5175, the user must first issue a readback command to the device, this begins with a start command followed by an address byte (r/ w = 0), after which the ad5175 acknowledges that it is prepared to receive data by pulling sda low. two bytes of data are then written to the ad5175, the most significant byte followed by the least significant byte; both of these data bytes are acknowledged by the ad5175. a stop condition follows. these bytes contain the read instruction, which enables readback of the rdac register, 50-tp memory, or the control register. the user can then read back the data beginning with a start command followed by an address byte (r/ w = 1), after which the device acknowledges that it is prepared to transmit data by pulling sda low. two bytes of data are then read from the device, as shown in . a stop condition follows. if the master does not acknowledge the first byte, the second byte is not transmitted by the ad5175. figure 27 0 19 1 99 9 1 1 0 1 1 a1 a0 r/w 0 0 c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 19 1 99 9 1 1 0 1 1 a1 a0 r/w 0 0 x x x x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ack. by ad5175 ack. by ad5175 ack. by ad5175 ack. by ad5175 ack. by master no ack. by master scl sd a scl (continued) sda (continued) scl (continued) sda (continued) start by master scl sd a start by master stop by master stop by master frame 1 serial bus address byte frame 1 serial bus address byte frame 2 most significant data byte frame 2 most significant data byte frame 3 least significant data byte frame 3 least significant data byte 08719-007 figure 27. read command
ad5175 rev. a | page 16 of 20 rdac register the rdac register directly controls the position of the digital rheostat wiper. for example, when the rdac register is loaded with all 0s, the wiper is connected to terminal a of the variable resistor. it is possible to both write to and read from the rdac register using the i 2 c interface. the rdac register is a standard logic register; there is no restriction on the number of changes allowed. 50-tp memory block the ad5175 contains an array of 50-tp programmable memory registers, which allow the wiper position to be pro- grammed up to 50 times. table 11 shows the memory map. command 3 in table 7 programs the contents of the rdac register to memory. the first address to be programmed is location 0x01, see tabl e 11 , and the ad5175 increments the 50-tp memory address for each subsequent program until the memory is full. programming data to 50-tp consumes approximately 4 ma for 55 ms, and takes approximately 350 ms to complete, during which time the shift register is locked preventing any changes from taking place. bit c2 of the control register in table 10 can be polled to verify that the fuse program command was successful. no change in supply voltage is required to program the 50-tp memory; however, a 1 f capacitor on the ext_cap pin is required as shown in figure 29 . prior to 50-tp activation, the ad5175 presets to midscale on power-up. it is possible to read back the contents of any of the 50-tp memory registers through the i 2 c interface by using command 5 in table 7 . the lower six lsb bits, d0 to d5 of the data byte, select which memory location is to be read back. a binary encoded version address of the most recently pro- grammed wiper memory location can be read back using command 6 in table 7 . this can be used to monitor the spare memory status of the 50-tp memory block. write protection on power-up, serial data input register write commands for both the rdac register and the 50-tp memory registers are disabled. the rdac write protect bit (bit c1) of the control register (see table 9 and table 10 ), is set to 0 by default. this disables any change of the rdac register content regardless of the software commands, except that the rdac register can be refreshed from the 50-tp memory using the software reset, command 4, or through the hardware by the reset pin. to enable programming of the variable resistor wiper position (programming the rdac register), the write protect bit (bit c1) of the control register must first be programmed. this is accomplished by loading the serial data input register with command 7 (see ). to enable programming of the 50-tp memory block, bit c0 of the control register, which is set to 0 by default, must first be set to 1. table 7 table 7. command operation truth table command number command[db13:db10] data[db9:db0] 1 c3 c2 c1 c0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x nop: do nothing. 1 0 0 0 1 d9 d8 d7 d6 d5 d4 d3 d2 d1 d write contents of serial register data to rdac. 2 0 0 1 0 x x x x x x x x x x read contents of rdac wiper register. 3 0 0 1 1 x x x x x x x x x x store wiper setting: store rdac setting to 50-tp. 4 0 1 0 0 x x x x x x x x x x software reset: refresh rdac with the last 50-tp memory stored value. 5 2 0 1 0 1 x x x x d5 d4 d3 d2 d1 d0 read contents of 50-tp from the sdo output in the next frame. 6 0 1 1 0 x x x x x x x x x x read address of the last 50-tp programmed memory location. 7 3 0 1 1 1 x x x x x x x x d1 d0 write contents of the serial register data to the control register. 8 1 0 0 0 x x x x x x x x x x read contents of the control register. 9 1 0 0 1 x x x x x x x x x d0 software shutdown. d0 = 0; normal mode. d0 = 1; shutdown mode. 1 x is dont care. 2 see table 11 for the 50-tp memory map. 3 see table 10 fo r bit details.
ad5175 rev. a | page 17 of 20 table 8. write and read to rdac and 50-tp memory din sdo 1 action 0x1c03 0xxxxx enable update of wiper position and 50-tp memory contents through digital interface. 0x0500 0x1c03 write 0x100 to the rdac register, wiper moves to ? full-scale position. 0x0800 0x0500 prepare data read from rdac register. 0x0c00 0x100 stores rdac register content into 50-tp memory. 16-bit word appears out of sdo, where the last 10-bits contain the contents of the rdac register 0x100. 0x1800 0x0c00 prepare data read of the last programmed 50-tp memory monitor location. 0x0000 0xxx19 nop instruction 0 sends a 16-bit word out of sdo, where the si x lsbs (that is, the last 6 bits) contain the binary address of the last programmed 50-tp memory location, for example, 0x19 (see table 11 ). 0x1419 0x0000 prepares data read from memory location 0x19. 0x2000 0x0100 prepare data read from the control register. sends a 16-bit word out of sdo, where the last 10-bits contain the contents of memory location 0x19. 0x0000 0xxxxx nop instruction 0 sends a 16-bit word out of sdo, where the la st four bits contain the contents of the control register. if bit c2 = 1, fuse program command successful. 1 x is dont care. table 9. control register bit map db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 c2 0 c1 c0 table 10. control register description bit name description c0 50-tp program enable 0 = 50-tp program disabled (default) 1 = enable device for 50-tp program c1 rdac register write protect 0 = wiper position frozen to value in otp memory (default) 1 1 = allow update of wiper position through a digital interface c2 50-tp memory program success bit 0 = fuse program command unsuccessful (default) 1 = fuse program command successful 1 wiper position is frozen to the last va lue programmed in the 50-tp me mory. wiper freezes to midscal e if 50-tp memory has not b een previously programmed. table 11. memory map command number data byte[db9:db0] 1 register contents d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 5 x x x 0 0 0 0 0 0 0 reserved x x x 0 0 0 0 0 0 1 1 st programmed wiper location (0x01) x x x 0 0 0 0 0 1 0 2 nd programmed wiper location (0x02) x x x 0 0 0 0 0 1 1 3 rd programmed wiper location (0x03) x x x 0 0 0 0 1 0 0 4 th programmed wiper location (0x04) x x x 0 0 0 1 0 1 0 10 th programmed wiper location (0xa) x x x 0 0 1 0 1 0 0 20 th programmed wiper location (0x14) x x x 0 0 1 1 1 1 0 30 th programmed wiper location (0x1e) x x x 0 1 0 1 0 0 0 40 th programmed wiper location (0x28) x x x 0 1 1 0 0 1 0 50 th programmed wiper location (0x32) x x x 0 1 1 1 0 0 1 msb resistance tolerance (0x39) x x x 0 1 1 1 0 1 0 lsb resistance tolerance (0x3a) 1 x is dont care.
ad5175 rev. a | page 18 of 20 50-tp memory write-acknowledge polling after each write operation to the 50-tp registers, an internal write cycle begins. the i 2 c interface of the device is disabled. to determine if the internal write cycle is complete and the i 2 c interface is enabled, interface polling can be executed. i 2 c interface polling can be conducted by sending a start condition followed by the slave address and the write bit. if the i 2 c inter- face responds with an acknowledge (ack), the write cycle is complete and the interface is ready to proceed with further operations. otherwise, i 2 c interface polling can be repeated until it completes. reset the ad5175 can be reset through software by executing command 4 (see table 7 ) or through hardware on the low pulse of the reset pin. the reset command loads the rdac register with the contents of the most recently programmed 50-tp memory location. the rdac register loads with midscale if no 50-tp memory location has been previously programmed. tie reset to v dd if the reset pin is not used. shutdown mode the ad5175 can be shut down by executing the software shutdown command, command 9 (see table 7 ), and setting the lsb to 1. this feature places the rdac in a zero-power- consumption state where terminal a is disconnected from the wiper terminal. it is possible to execute any command from table 7 while the ad5175 is in shutdown mode. the part can be taken out of shutdown mode by executing command 9 and setting the lsb to 0, or by issuing a software or hardware reset. rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac segmentation architecture for all the digital potentiometers. in particular, the ad5175 employs a three-stage segmentation approach, as shown in figure 28 . the ad5175 wiper switch is designed with the transmission gate cmos topology. a w 10-bit address decoder r l r l r m r m r w s w r w 08719-008 figure 28. simplified rdac circuit programming the variable resistor rheostat operation the nominal resistance between terminal w and terminal a, r wa , is available in 10 k and has 1024-tap points accessed by the wiper terminal. the 10-bit data in the rdac latch is decoded to select one of the 1024 possible wiper settings. as a result, the general equation for determining the digitally programmed output resistance between the w terminal and a terminal is wa wa r d dr = 1024 )( (1) where: d is the decimal equivalent of the binary code loaded in the 10-bit rdac register. r wa is the end-to-end resistance. in the zero-scale condition, a finite total wiper resistance of 120 is present. regardless of which setting the part is oper- ating in, take care to limit the current between the a terminal to w terminal, and w terminal to b terminal, to the maximum continuous current of 6 ma, or the pulse current specified in table 3 . otherwise, degradation or possible destruction of the internal switch contact can occur.
ad5175 rev. a | page 19 of 20 calculate the actual end-to-end resistance terminal voltage operating range the resistance tolerance is stored in the internal memory during factory testing. the actual end-to-end resistance can, therefore, be calculated (which is valuable for calibration, tolerance matching, and precision applications). the positive v dd and negative v ss power supplies of the ad5175 define the boundary conditions for proper 2-terminal digital resistor operation. supply signals present on terminal a and terminal w that exceed v dd or v ss are clamped by the internal forward-biased diodes (see figure 30 ). the resistance tolerance in percentage is stored in fixed-point format, using a 16-bit sign magnitude binary. the sign bit(0 = negative and 1 = positive) and the integer part is located in address 0x39, as shown in tabl e 11 . address 0x3a contains the fractional part, as shown in table 12 . v ss v dd a w 0 8719-109 that is, if the data readback from address 0x39 is 0000001010 and data from address 0x3a is 0010110000, then the end-to-end resistance can be calculated as follows. for memory location 0x39, db[9:8]: xx = dont care ? db[7]: 0 = negative figure 30. maximum terminal voltages set by v dd and v ss db[6:0]: 0001010 = 10 the ground pin of the ad5175 is primarily used as a digital ground reference. to minimize the digital ground bounce, join the ad5175 ground terminal remotely to the common ground. the digital input control signals to the ad5175 must be refe- renced to the device ground pin (gnd) and satisfy the logic level defined in the specifications section. an internal level shift circuit ensures that the common-mode voltage range of the three terminals extends from v ss to v dd , regardless of the digital input level. for memory location 0x3a, db[9:8]: xx = dont care db[7:0]: 10110000 = 176 2 ?8 = 0.6875 therefore, tolerance = ?10.6875% and r wa (1023)= 8.931 k. ext_cap capacitor a 1 f capacitor to v ss must be connected to the ext_cap pin (see figure 29 ) on power-up and throughout the operation of the ad5175. power-up sequence because there are diodes to limit the voltage compliance at te r m i n a l a a nd te r m i n a l w ( s e e figure 30 ), it is important to power v dd /v ss first before applying any voltage to terminal a and terminal w; otherwise, the diode is forward-biased such that v dd /v ss are powered unintentionally. the ideal power-up sequence is v ss , gnd, v dd , digital inputs, v a , and v w . the order of powering v a , v w , and digital inputs is not important as long as they are powered after v dd /v ss . ad5175 50-tp memory block ext_cap c1 1f v ss v ss 0 8719-009 as soon as v dd is powered, the power-on preset activates, which first sets the rdac to midscale and then restores the last programmed 50-tp value to the rdac register. figure 29. ext_cap hardware setup table 12. end-to-end resistance tolerance bytes data byte 1 memory map address db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0x39 x x sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0x3a x x 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 2 ?8 1 x is dont care.
ad5175 rev. a | page 20 of 20 outline dimensions 2.48 2.38 2.23 0.50 0.40 0.30 121009-a top view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 31. 10-lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very thin, dual lead (cp-10-9) dimensions shown in millimeters compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 32. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model 1 r ab (k) resolution temperature range packag e description package option branding ad5175brmz-10 10 1,024 ?40c to +125c 10-lead msop rm-10 ddr ad5175brmz-10-rl7 10 1,024 ?40c to +125c 10-lead msop rm-10 ddr AD5175BCPZ-10-RL7 10 1,024 ?40c to +125c 10-lead lfcsp_wd cp-10-9 deg 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08719-0-7/10(a)

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