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3 a, 1.2 mhz/600 khz high efficiency synchronous step-down dc-to-dc regulator adp2118 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features 3 a continuous output current 75 m and 40 m integrated fet 1.5% output accuracy input voltage range from 2.3 v to 5.5 v output voltage from 0.6 v to v in 600 khz or 1.2 mhz fixed switching frequency synchronizable between 600 khz and 1.4 mhz selectable synchronize phase shift: 0 o or 180 o selectable pwm or pfm mode operation current mode architecture precision enable input power good output voltage tracking input integrated soft start internal compensation starts up into a precharged output uvlo, ovp, ocp, and thermal shutdown available in 16-lead 4mm 4mm lfcsp_wq package applications point of load conversion communications and networking equipments industrial and instrumentation consumer electronics medical appliances general description the adp2118 is a low quiescent current, synchronous, step-down, dc-to-dc regulator in a compact 4mm 4mm lfcsp_wq package. it uses a current mode, constant frequency pulse-width modulation (pwm) control scheme for excellent stability and transient response. under light loads, the adp2118 can be configured to operate in pulse frequency modulation (pfm) mode that reduces switching frequency to save power. the adp2118 runs from input voltages of 2.3 v to 5.5 v. the output voltage of the adp2118acpz-r7 is adjustable from 0.6 v to input voltage (v in ), and the adp2118acpz-x.x-r7 are available in preset output voltage options of 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, and 1.0 v. the adp2118 requires minimal external parts and provides a high efficiency solution with its integrated power switch, synchronous rectifier, and internal compensation. the ic draws less than 3 a from the input source when it is disabled. other key features include undervoltage lockout (uvlo), integrated soft start to limit inrush current at startup, overvoltage protection (ovp), overcurrent protection (ocp), and thermal shutdown (tsd). r top 10k? r bot 2.21k ? r2 10k ? r1 10? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 100f x5r, 6.3v c1 0.1f v in 5v v out 3.3v 3a 08301-001 l 1h 16 15 14 13 5 6 7 8 pgnd g nd pgnd pgnd pgood en vin p vin figure 1. typical applications circuit 08301-050 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficiency (%) output current (a) v in = 5v v out = 3.3v f s = 1.2mhz pfm operation fpwm operation figure 2. efficiency vs. output current
adp2118 rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 functional block diagram ............................................................ 13 theory of operation ...................................................................... 14 control scheme .......................................................................... 14 pwm mode operation .............................................................. 14 pfm mode operation ................................................................ 14 slope compensation .................................................................. 14 enable/shutdown ....................................................................... 14 integrated soft start ................................................................... 14 tracking ....................................................................................... 14 oscillator and synchronization ................................................ 15 current limit and short-circuit protection .......................... 15 overvoltage protection (ovp) ................................................. 15 undervoltage lockout (uvlo) ............................................... 15 thermal shutdown .................................................................... 15 power good ................................................................................ 15 applications information .............................................................. 16 output voltage selection ........................................................... 16 inductor selection ...................................................................... 16 output capacitor selection ....................................................... 16 input capacitor selection .......................................................... 17 voltage tracking ......................................................................... 17 typical application circuits ......................................................... 18 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 10/09rev. 0 to rev. a changed converter to regulator (throughout) .......................... 1 changes to applications section .................................................... 1 7/09revision 0: initial version
adp2118 rev. a | page 3 of 24 specifications vin = pvin = 3.3 v, en = vin, sync/mode = high @ t j = ?40c to +125c, unless otherwise noted. typical values are at t j = 25 o c. table 1. parameter symbol test conditions/comments min typ max unit vin and pvin vin voltage range vin 2.3 5.5 v pvin voltage range pvin 2.3 5.5 v quiescent current i vin no switching, sync/mode = gnd 100 150 a switching, no load, sync/mode = high 680 900 a shutdown current i shdn vin = pvin = 5.5 v, en = gnd 0.3 3 a vin undervoltage lockout threshol d uvlo vin rising 2.2 2.3 v vin falling 2 2.1 v output characteristics load regulation 1 i o = 0 a to 3 a 0.08 %/a line regulation 1 i o = 1.5 a 0.05 %/v fb fb regulation voltage v fb vin = 2.3 v to 5.5 v 0.591 0.6 0.609 v fb bias current i fb 0.01 0.1 a sw high-side on resistance 2 vin = pvin = 3.3 v, i sw = 500 ma 75 110 m low-side on resistance 2 vin = pvin = 3.3 v, i sw = 500 ma 40 60 m sw peak current limit high-side switch, vin = pvin = 3.3 v 4 5.2 6.4 a sw maximum duty cycle vin = pvin = 5.5 v, full frequency 100 % sw minimum on time 3 vin = pvin = 5.5 v, full frequency 100 ns trk trk input voltage range 0 600 mv trk to fb offset voltage trk = 0 mv to 500 mv ?10 +10 mv trk input bias current 100 na frequency oscillator frequency freq = vin 1.0 1.2 1.4 mhz freq = gnd 500 600 700 khz freq input high voltage 1.2 v freq input low voltage 0.4 v sync/mode synchronization range 0.6 1.4 mhz sync minimum pulse width 100 ns sync minimum off time 100 ns sync input high voltage 1.2 v sync input low voltage 0.4 v integrated soft start soft start time all switching frequency 2048 clock cycles pgood power good range fb rising threshold 105 110 115 % fb rising hysteresis 2.5 % fb falling threshold 85 90 94 % fb falling hysteresis 2.5 % power good deglitch time from fb to pgood 16 clock cycles pgood leakage current v pgood = 5 v 0.1 1 a pgood output low voltage i pgood = 1 ma 140 200 mv
adp2118 rev. a | page 4 of 24 parameter symbol test conditions/comments min typ max unit en en input rising threshold vin = 2.3 v to 5.5 v 1.12 1.2 1.28 v en input hysteresis vin = 2.3 v to 5.5 v 100 mv en pull-down resistor 1 m thermal thermal shutdown threshold 140 c thermal shutdown hysteresis 15 c 1 specified by the circuit in . figure 45 2 pin-to-pin measurements. 3 guaranteed by design.
adp2118 rev. a | page 5 of 24 absolute maximum ratings table 2. parameter rating vin, pvin ?0.3 v to +6 v sw ?0.3 v to +6 v fb, sync/mode, en, trk, freq, pgood ?0.3 v to +6 v pgnd to gnd ?0.3 v to +0.3 v operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 16-lead lfcsp_wq 38.3 c/w boundary conditions ja is measured using natural convection on a jedec 4-layer board, and the exposed pad is soldered to the printed circuit board with thermal vias. esd caution
adp2118 rev. a | page 6 of 24 pin configuration and fu nction descriptions notes 1. the exposed pad should be soldered to an external ground plane underneath the ic for thermal dissipation. 12 11 10 1 3 4 pvin sw sw 9 sw sync/mode trk 2 freq fb 6 pgnd 5 gnd 7 pgnd 8 pgnd 16 pgoo d 15 en 14 vin 13 pvin top view adp2118 08301-002 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 sync/mode synchronization input (sync). connect this pin to an external clock between 600 khz and 1.4 mhz to synchronize the switching frequency to the external clock (see the oscillator and synchronization section for details). ccm/pfm selection (mode). when this pin is connected to vin, pfm mode is disabled and the adp2118 only works in continuous conduction mode (ccm). when this pin is connected to ground, pfm mode is enabled and becomes active at light loads. 2 freq frequency selection. connect to gnd to select 600 khz and vin for 1.2 mhz. 3 trk tracking input. to track a master voltage, drive trk from a voltage divider from the master voltage. if the tracking function is not used, connect trk to vin. 4 fb feedback voltage sense input. connect to a resistor divider from v out . for the fixed output version, connect to v out directly. 5 gnd analog ground. connect to the ground plane. 6, 7, 8 pgnd power ground. connect to the ground plane and to the output return side of the output capacitor. 9, 10, 11 sw switch node output. connect to the output inductor. 12, 13 pvin power input pin. connect this pin to the input power source. connect a bypass capacitor between this pin and pgnd. 14 vin bias voltage input pin. connect a bypass capacitor between this pin and gnd and a small (10 ) resistor between this pin and pvin. 15 en precision enable pin. the external resistor divider can be used to set the turn-on threshold. to enable the part automatically, connect the en pin to vin. this pin has a 1 m pull-down resistor to gnd. 16 pgood power-good output (open drain). connect to a resistor to any pull-up voltage <5.5 v. 17 (epad) exposed pad the exposed pad should be soldered to an external ground plane underneath the ic for thermal dissipation.
adp2118 rev. a | page 7 of 24 typical performance characteristics t a = 25c, v in = 5 v, v out = 1.2 v, l = 1 h, c in = 100 f, c out = 100 f, unless otherwise noted. 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor coilcraft mss1038-102nl 08301-014 figure 4. efficiency (1.2 mhz, v in = 3.3 v, fpwm) vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency (%) output current (a) inductor coilcraft mss1038-102nl v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 08301-015 figure 5. efficiency (1.2 mhz, v in = 5 v, fpwm) vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor sumida cdrh105r2r2nc 08301-016 figure 6. efficiency (600 khz, v in = 3.3 v, fpwm) vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor coilcraft mss1038-102nl 08301-017 figure 7. efficiency (1.2 mhz, v in = 3.3 v, pfm) vs. output current 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency (%) output current (a) inductor coilcraft mss1038-102nl v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 0 8301-018 figure 8. efficiency (1.2 mhz, v in = 5 v, pfm) vs. output current 0 0.5 1.0 1.5 2.0 2.5 3.0 0 10 20 30 40 50 60 70 80 90 100 efficien c y (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor sumida cdrh105r2r2nc 0 8301-019 figure 9. efficiency (600 khz, v in = 3.3 v, pfm) vs. output current
adp2118 rev. a | page 8 of 24 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficien c y (%) output current(a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor sumida cdrh105r2r2nc 08301-020 figure 10. efficiency (600 khz, v in = 5 v, fpwm) vs. output current 80 85 90 95 100 105 110 115 120 2.32.73.13.53.94.34.75.15.5 quiescent current (a) v in (v) t j = ?40c t j = +25c t j = +125c 08301-021 figure 11. quiescent current vs. v in (no switching) 40 50 60 70 80 90 100 110 120 130 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 pfet resistor (m ? ) t j = ?40c t j = +25c t j = +125c v in (v) 08301-022 figure 12. pfet resistor vs. v in (pin-to-pin measurements) 0 10 20 30 40 50 60 70 80 90 100 0 0.5 1.0 1.5 2.0 2.5 3.0 efficien c y (%) output current (a) inductor sumida cdrh105r2r2nc v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v 08301-023 figure 13. efficiency (600 khz, v in = 5 v, pfm) vs. output current 594 595 596 597 598 599 600 601 602 603 604 605 606 ?40 ?20 0 20 40 60 80 100 120 feedback voltage (mv) temperature (c) 0 8301-024 figure 14. feedback voltage vs. temperature (v in = 3.3 v) 10 20 30 40 50 60 70 80 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 nfet resistor (m ? ) v in (v) t j = ?40c t j = +25c t j = +125c 08301-025 figure 15. nfet resistor vs. v in (pin-to-pin measurements)
adp2118 rev. a | page 9 of 24 1000 1050 1100 1150 1200 1250 1300 1350 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 switching frequency (khz) t j = ?40c t j = +25c t j = +125c v in (v) 08301-026 figure 16. switching frequency vs. v in at 1.2 mhz 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 ?40 ?20 0 20 40 60 80 100 120 enable threshold (v) temperature (c) rising falling 0 8301-027 figure 17. en threshold vs. temperature 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 ?40 ?20 0 20 40 60 80 100 120 peak current limit (a) temperature (c) 08301-028 figure 18. peak current limit vs. temperature (v in = 3.3 v) 500 520 540 560 580 600 620 640 660 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 switching frequency (khz) t j = ?40c t j = +25c t j = +125c v in (v) 08301-029 figure 19. switching frequency vs. v in at 600 khz ?40 ?20 0 20 40 60 80 100 120 temperature (c) 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 uvlo threshold (v) rising 08301-030 falling figure 20. uvlo threshold vs. temperature (v in = 3.3 v) 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 peak current limit (a) v in (v) 08301-031 figure 21. peak current limit vs. v in (t j = 25c)
adp2118 rev. a | page 10 of 24 08301-032 ch1 500mv ch2 5v ch3 5v ch4 2a ? m1ms a ch3 3.10v 3 1 2 4 t 20.40% v out en pgood i l figure 22. soft start with full load (1.2 mhz, v in = 5 v) t 30.40% 08301-033 ch1 50mv ch4 2a ? m200s a ch4 1.36a 1 4 v o u t ( a c ) i o figure 23. load transient (1.2 mhz, pfm, v in = 5 v) 08301-034 ch2 2v ch3 2v m 400ns a ch2 2.88v 3 2 t ?8ns sw sync figure 24. synchronized to 1 mhz in phase 08301-035 ch1 500mv ch2 5v ch3 5v ch4 2a ? m1ms a ch3 3.10v 3 1 2 4 t 30.2% v out en pgood i l figure 25. soft start with precharge (1.2 mhz, v in = 5 v) 08301-036 ch1 50mv ch4 2a ? m200s a ch4 1.36a 1 4 t 30.40% v out (ac) i o figure 26. load transient (1.2 mhz, fpwm, v in = 5 v) 08301-037 ch2 2v ch3 2v m400ns a ch2 2.88v 3 2 t ?8ns sw sync figure 27. synchronized to 1 mhz 180 out of phase
adp2118 rev. a | page 11 of 24 08301-038 ch1 500mv ch2 5v ch4 5a ? m2ms a ch1 670mv 1 2 4 t 29.60% v out sw i l figure 28. output short t 59% 08301-039 ch1 500mv ch2 500mv m4ms a ch2 640mv 1 fb trk figure 29. tracking function 08301-040 ch2 5v ch4 1a ? ch1 10mv m 400ns a ch2 3.90v 1 2 4 t 57.80% v out (ac) sw i l figure 30. discontinuous conduction mode (dcm) 08301-041 ch1 500mv ch2 5v ch4 5a ? m2ms a ch1 670mv 1 2 4 t 59.60% v out sw i l figure 31. output short recovery 08301-042 ch1 50mv ch2 5v ch4 1a ? m4s a ch4 1.72a 1 2 4 t 64.60% sw i l v out (ac) figure 32. pfm mode 08301-043 m400ns a ch2 3.1v 1 2 4 t 57.8% ch1 10mv ch2 5v ch4 2a ? v out (ac) i l sw figure 33. continuous conduction mode (ccm)
adp2118 rev. a | page 12 of 24 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 magnitude (db) phase (degrees) frequency (hz) 100 1k 10k 100k 1m 0 8301-044 cross frequency: 102khz phase margin: 50 12 figure 34. bode plot at v in = 5 v, v out = 1.0 v, i o = 3 a, f s = 1.2 mhz 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 magnitude (db) phase (degrees) frequency (hz) 100 1k 10k 100k 1m 0 8301-045 cross frequency: 81khz phase margin: 63 12 figure 35. bode plot at v in = 5 v, v out = 1.5 v, i o = 3 a, f s = 1.2 mhz 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 magnitude (db) phase (degrees) frequency (hz) 100 1k 10k 100k 1m 0 8301-046 cross frequency: 52khz phase margin: 76 12 figure 36. bode plot at v in = 5 v, v out = 2.5 v, i o = 3 a, f s = 1.2 mhz 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 magnitude (db) phase (degrees) frequency (hz) 100 1k 10k 100k 1m 0 8301-047 cross frequency: 93khz phase margin: 56 12 figure 37. bode plot at v in = 5 v, v out = 1.2 v, i o = 3 a, f s = 1.2 mhz 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 magnitude (db) phase (degrees) frequency (hz) 100 1k 10k 100k 1m 0 8301-048 cross frequency: 69khz phase margin: 69 12 figure 38. bode plot at v in = 5 v, v out = 1.8 v, i o = 3 a, f s = 1.2 mhz 60 48 36 24 12 0 ?12 ?24 ?36 ?48 ?60 200 160 120 80 40 0 ?40 ?80 ?120 ?160 ?200 magnitude (db) phase (degrees) frequency (hz) 100 1k 10k 100k 1m 0 8301-049 cross frequency: 46khz phase margin: 79 12 figure 39. bode plot at v in = 5 v, v out = 3.3 v, i o = 3 a, f s = 1.2 mhz
adp2118 rev. a | page 13 of 24 functional block diagram 0 8301-003 nmos current sense amp zero current cmp pgnd pvin pmos current sense amp 0.6v erro amp 0.54v freq fb slope compensation oscillator skip mode threshold skip cmp sync/mode logic control clk sw en uvlo v in pfet nfet gnd trk z comp 0.66v pgood soft start gm adp2118 figure 40. functional block diagram
adp2118 rev. a | page 14 of 24 theory of operation the adp2118 is a step-down, dc-to-dc regulator that uses fixed frequency, peak current-mode architecture with an integrated high-side switch and low-side synchronous rectifier. the high switching frequency and tiny 16-lead, 4 mm 4 mm lfcsp_wq package allow for a small step-down dc-to-dc regulator solu- tion. the integrated high-side switch (p-channel mosfet) and synchronous rectifier (n-channel mosfet) yield high efficiency at medium-to-full loads, and light load efficiency is improved by pfm mode. the adp2118 operates with an input voltage from 2.3 v to 5.5 v and regulates the output voltage down to 0.6 v. the adp2118 is also available with preset output voltage options of 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v, and 1.0 v. control scheme the adp2118 uses the fixed frequency, peak current mode pwm control architecture and operates in pwm mode for medium-to-full loads but shifts to pfm mode (if enabled) at light loads to maintain high efficiency. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage. when operating in pfm mode at light loads, the switching frequency is adjusted to regulate the output voltage. the adp2118 operates in pwm mode when the load current is greater than the pulse-skipping threshold current. at load currents below this value, the regulator smoothly transitions to the pfm mode of operation. pwm mode operation in pwm mode, the adp2118 operates at a fixed frequency set by the freq pin. at the start of each oscillator cycle, the p- channel mosfet switch is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current level, turns off the p-channel mosfet switch, and turns on the n-channel mosfet synchronous rectifier. this puts a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on for the rest of the cycle or until the inductor current reaches zero, which causes the zero- crossing comparator to turn off the n-channel mosfet as well. the peak inductor current level is set by v comp . the v comp is the output of a transconductance error amplifier that compares the feedback voltage with an internal 0.6 v reference. pfm mode operation when pfm mode is enabled, the adp2118 smoothly transi- tions to the variable frequency pfm mode of operation when the load current decreases below the pulse-skipping threshold current, switching only as necessary to maintain the output voltage within regulation. when the output voltage drops below regulation, the adp2118 enters pwm mode for a few oscillator cycles to increase the output voltage back to regulation. during the wait time between bursts, both power switches are off, and the output capacitor supplies all the load current. because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger than the ripple in the pwm mode of operation. slope compensation slope compensation stabilizes the internal current control loop of the adp2118 when operating close to and beyond 50% duty cycle to prevent subharmonic oscillations. it is implemented by summing an artificial voltage ramp to the current sense signal during the on-time of the p-channel mosfet switch. this voltage ramp depends on the output voltage. when operating at high output voltages, there is more slope compensation. the slope compensation ramp value determines the minimum inductor that can be used to prevent subharmonic oscillations. enable/shutdown the en pin is a precision analog input that enables the device when the voltage exceeds 1.2 v (typical) and has 100 mv hysteresis. when the enable voltage falls below 1.1 v (typical) the part turns off. to force the adp2118 to automatically start when input power is applied, connect en to vin. when the adp2118 is shut down, the soft start capacitor is discharged. this causes a new soft start cycle to begin when the part is reenabled. an internal pull-down resistor (1 m) prevents an accidental enable if en is left floating. integrated soft start the adp2118 has integrated soft start circuitry to limit the output voltage rise time and reduce inrush current at startup. the soft start time is fixed at 2048 clock cycles. if the output voltage is precharged prior to turn-on, the adp2118 prevents a reverse inductor current (that would discharge the output capacity) until the soft start voltage exceeds the voltage on the fb pin. tracking the adp2118 has a tracking input, trk, that allows the output voltage to track another voltage (m aster voltage). it is especially useful in core and i/o voltage tracking for fpgas, dsps, and asics. the internal error amplifier includes three positive inputs: the internal reference voltage, the soft start voltage, and the trk voltage. the error amplifier regulates the fb voltage to the lowest of the three voltages. to track a master voltage, tie the trk pin to a resistor divider from the master voltage. if the trk function is not used, connect the trk pin to vin.
adp2118 rev. a | page 15 of 24 oscillator and synchronization the internal oscillator of adp2118 can be set to 600 khz or 1.2 mhz. drive the freq pin low for 600 khz; drive freq pin high for 1.2 mhz. to synchronize the adp2118, drive an external clock at the sync/mode pin. the frequency of the external clock can be in the range of 600 khz to 1.4 mhz. during synchronization, the regulator operates in ccm mode only. if the freq pin is low, the switching frequency is in phase with the external clock; if the freq pin is high, the switching frequency is 180 o out of phase with the external clock. current limit and short-circuit protection the adp2118 has a peak current limit protection circuit to prevent current runaway. the peak current is limited at 5.2 a. when the inductor peak current reaches the current limit value, the high-side mosfet turns off and the low-side mosfet turns on until the next cycle while the overcurrent counter increments. if the overcurrent counter count exceeds 10, the part enters hiccup mode. the high-side fet and low-side fet are both turned off. the part remains in this mode for 4096 clock cycles and then attempts to restart from soft start. if the current limit fault has cleared, the part resumes normal operation. otherwise, it reenters hiccup mode again after counting 10 current-limit violations. overvoltage protection (ovp) the output voltage is continuously monitored by a comparator through the fb pin, which is at 0.6 v (typical) under normal operation. this comparator is set to activate when the fb voltage exceeds 0.66 v (typical), thus indicating an output overvoltage condition. if the voltage remains above this threshold for 16 clock cycles, the high-side mosfet turns off and the low-side mosfet turns on until the current through it reaches the limit (?0.9 a for forced continuous mode and 0 a for pfm mode). thereafter, both the mosfets are held in the off state until fb falls below 0.54 v (typical), and then the part restarts. the behavior of pgood under this condition is described in the power good section. undervoltage lockout (uvlo) undervoltage lockout circuitry is integrated on the adp2118. if the input voltage drops below 2.1 v, the adp2118 shuts down, and both the power switch and the synchronous rectifier turn off. when the voltage rises again above 2.2 v, the soft start period is initiated, and the part is enabled. thermal shutdown in the event that the adp2118 junction temperature rises above 140c, the thermal shutdown circuit turns off the regulator. extreme junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. a 15c hysteresis is included so that when thermal shutdown occurs, the adp2118 does not return to operation until the on-chip temperature drops below 125c. when coming out of thermal shutdown, soft start is initiated. power good pgood is an active high, open-drain output and requires a resistor to pull it up to a voltage. a high indicates that the voltage on the fb pin (and therefore the output voltage) is within 10% of the desired value. a low on this pin indicates that the voltage on the fb pin is not within 10% of the desired value. there is a 16 cycle waiting period after fb is detected as being out of bounds. if fb returns to within the 10% range, it is ignored by pgood circuitry.
adp2118 rev. a | page 16 of 24 applications information this section describes the external components selection for the adp2118. the typical application circuit is shown in figure 41 . 0 8301-004 r top 10k ? r bot 10k ? r2 10k? r1 10 ? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 100f x5r, 6.3v c1 0.1f v in 5v v out 1.2v 3a l 1h 16 15 14 13 5 6 7 8 pgnd gnd pgnd pgn d pgo od en vin pvin figure 41. application circuit output voltage selection the output voltage of the adjustable version of the adp2118 can be set by an external resistive voltage divider by using the following equation to set the voltage: u bot top out r r v 16.0 to limit output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximum), ensure that r bot is less than 30 k. inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage, and ripple current. using a small inductor leads to larger inductor current ripple and provides fast transient response but degrades efficiency, whereas a large inductor value leads to small current ripple and good efficiency but slow transient response. as a guideline, the inductor current ripple, i l , is typically set to 1/3 of the maximum load current trade-off between the transient response and efficiency. the inductor can be calculated using the following equation: s l out in fi dvv l where: v in is the input voltage. v out is the output voltage. i l is the inductor current ripple. d is the duty cyle. in out v v d the adp2118 uses slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value. the negative current limit (?0.9 a) also limits the minimum inductor value. the inductor current ripple (i l ) calculated by the selected inductor should not exceed 1.8 a. the peak inductor current should be kept below the peak current limit threshold value and can be calculated as 2 l o peak i ii ensure that the rms current of the selected inductor is greater than the maximum load current and that its saturation current is greater than the peak current limit of the regulator. output capacitor selection the output voltage ripple, load step transient, and loop stability determine the output capacitor selection. the output ripple is determined by the esr and the capacitance. uu u s out l out fc esriv 8 1 the load transient response depends on the inductor, output capacitor, and the control loop. the adp2118 has integrated loop compensation for simple power design. table 5 and table 6 show the typical recom- mended inductors and capacitors for the adp2118. x5r or x7r ceramic capacitors are highly recommended. table 5. recommended l and c out value at f s = 1.2 mhz v in (v) v out (v) l (h ) c out (f) 3.3 1.0 1 100 + 47 3.3 1.2 1 100 3.3 1.5 1 100 3.3 1.8 1 100 3.3 2.5 1 100 5 1.0 1 100 + 47 5 1.2 1 100 5 1.5 1 100 5 1.8 1 100 5 2.5 1 100 5 3.3 1 100
adp2118 rev. a | page 17 of 24 table 6. recommended l and c out value at f s = 600 khz v in (v) v out (v) l (h ) c out (f) 3.3 1.0 1.5 100 + 47 3.3 1.2 1.5 100 3.3 1.5 1.5 100 3.3 1.8 1.5 100 3.3 2.5 1.5 100 5 1.0 1.5 100 + 47 5 1.2 1.5 100 5 1.5 2.2 100 5 1.8 2.2 100 5 2.5 2.2 100 5 3.3 2.2 100 higher or lower inductors and output capacitors can be used in the regulator, but the system stability and load transient performance need to be checked. the minimum output capacitor can be 47 f. if f s = 1.2 mhz, the inductor range is 0.8 h to 3.3 h. if f s = 600 khz, the inductor range is 1.5 h to 3.3 h. table 7. recommended inductors manufacturer part number coilcraft mss1038, mss1048, mss1260 sumida cdrh103r, cdrh104r, cdrh105r table 8. recommended capacitors manufacturer part number description murata grm32er60j107me20 100 f, 6.3 v, x5r, 1210 murata grm32er60j476me20 47 f, 6.3 v, x5r, 1210 tdk c3225x5r0j107m 100 f, 6.3 v, x5r, 1210 tdk c3225x5r0j476m 47 f, 6.3 v, x5r, 1210 input capacitor selection the input capacitor reduces the input voltage ripple caused by the switch current on pvin. place the input capacitor as close as possible to the pvin pin. a 22 f or 47 f ceramic capacitor is recommended. the rms current rating of the input capacitor should be larger than the following equation: () ddii o rms ?= 1 voltage tracking the adp2118 includes a tracking feature that allows the adp2118 output (slave voltage) to be configured to track an external voltage (master voltage), as shown in figure 42 . a common application is coincident tracking, shown in figure 43 . coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. connect the trk pin to a resistor divider from the master voltage. for coincident tracking, set r trkt = r top and r trkb = r bot . ratiometric tracking is shown in figure 44 . the slave output is limited to a fraction of the master voltage. in this application, the slave and master voltages reach the final value at the same time. the ratio of the slave output voltage to the master voltage is a function of the two dividers. trkb trkt bot top master slave r r r r v v + + = 1 1 08301-005 v master v slave r top r bot r trkt r trkb trk fb adp2118 figure 42. voltage tracking 08301-006 voltage time v master v slave figure 43. coincident tracking 08301-007 time v master v slave voltage figure 44. ratiometric tracking
adp2118 rev. a | page 18 of 24 typical application circuits r top 10k? r bot 10k ? r2 10k ? r1 10? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 100f x5r, 6.3v c1 0.1f v in 3.3v v out 1.2v 3a l 1h 16 15 14 13 5 6 7 8 pgnd gnd pgnd pgnd pgood en vin pvin l: mss1038-102nl coilcraft c in , c out : c3225x5r0j107m tdk 08301-008 figure 45. 1.2 v, 3 a, 1.2 mhz step-down regulator, force continuous conduction mode r top 47.5k ? r bot 15k ? r2 10k? r1 10? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 47f x5r, 10v c1 0.1f v in 5v v out 2.5v 3a l 1h 16 15 14 13 5 6 7 8 pgnd gnd pgnd pgnd pgood en vin pvin l: mss1038-102nl coilcraft c in : c3225x5r0j107m tdk c out : grm32er61a476ke20 murata 0 8301-009 figure 46. 2.5 v, 3 a, 1.2 mhz step-down regulator, enable pfm mode
adp2118 rev. a | page 19 of 24 r top 20k? r bot 10k? r2 10k? r1 10? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 100f x5r, 6.3v c1 0.1f v in 5v v out 1.8v 3a l 1h 16 15 14 13 5 6 7 8 pgnd gnd pgnd pgnd pgood en vin pvin l: mss1038-102nl coilcraft c in , c out : c3225x5r0j107m tdk 1mhz ext clock 08301-010 figure 47. 1.8 v, 3 a step-down regulator, synchronized to 1 mhz in phase with the external clock r top 15k? r bot 10k? r2 10k? r1 10 ? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 100f x5r, 6.3v c1 0.1f v in 5v v out 1.5v 3a l 1h 16 15 14 13 5 6 7 8 pgnd gnd pgnd pgnd pgood en vin pvin l: mss1038-102nl coilcraft c in , c out : c3225x5r0j107m tdk 1mhz ext clock 08301-011 figure 48. 1.5 v, 3 a step-down regulator, synchronized to 1 mhz, 180 out of phase with the external clock
adp2118 rev. a | page 20 of 24 r top 10k? r trkt 10k ? r bot 2.21k ? r2 10k ? r1 10? sync/mode freq trk fb pvin adp2118 sw sw sw 1 2 3 4 12 11 10 9 c in 100f x5r, 6.3v c out 100f x5r, 6.3v c1 0.1f v in 5v v out 3.3v 3a l 1h 16 15 14 13 5 6 7 8 pgnd g nd pgnd pgnd pgood en vin pvin l: mss1038-102nl coilcraft c in , c out : c3225x5r0j107m tdk v master r trkb 2.21k ? 08301-012 figure 49. 3.3 v, 3 a, 1.2 mhz step-down regulator, tracking mode
adp2118 rev. a | page 21 of 24 outline dimensions compliant to jedec standards mo-220-wggc. 042709-a 1 0.65 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 0.50 0.40 0.30 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indicator 0.35 0.30 0.25 2.60 2.50 sq 2.40 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 50. 16-lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-16-26) dimensions shown in millimeters ordering guide model temperature range output voltage package description package option adp2118acpz-r7 1 ?40c to +125c adjustable 16-lead lfcsp_wq cp-16-26 adp2118acpz-1.0-r7 1 ?40c to +125c 1.0 v 16-lead lfcsp_wq cp-16-26 adp2118acpz-1.2-r7 1 ?40c to +125c 1.2 v 16-lead lfcsp_wq cp-16-26 adp2118acpz-1.5-r7 1 ?40c to +125c 1.5 v 16-lead lfcsp_wq cp-16-26 adp2118acpz-1.8-r7 1 ?40c to +125c 1.8 v 16-lead lfcsp_wq cp-16-26 adp2118acpz-2.5-r7 1 ?40c to +125c 2.5 v 16-lead lfcsp_wq cp-16-26 adp2118acpz-3.3-r7 1 ?40c to +125c 3.3 v 16-lead lfcsp_wq cp-16-26 adp2118-evalz evaluation board 1 z = rohs compliant part.
adp2118 rev. a | page 22 of 24 notes
adp2118 rev. a | page 23 of 24 notes
adp2118 rev. a | page 24 of 24 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08301-0-10/09(a)

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