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imsh1g[u/e]03a1f1c(t) imsh2g[u/e]13a1f1c(t) 240-pin ddr3 unbuffered memory modules 1-gbyte and 2-gbyte eu rohs compliant advance internet data sheet rev. 0.63 august 2008
advance internet data sheet imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm qag_techdoc_a4, 4.20, 2008-01-25 2 03052008-r2g5-2fn2 we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com imsh1g[u/e]03a1f1c(t), imsh2g[u/e]13a1f1c(t) revision history: 2008-08, rev. 0.63 page subjects (major chang es since last revision) 21 - 41 updated spd codes and adapted to internet edition. previous revision: rev. 0.62, 2008-06 all added product type imsh[1/2]gu[0/1]3a1f1c-16j. previous revision: rev. 0.61, 2008-05 19 - 34 updated spd codes. previous revision: rev. 0.60, 2008-04 all editorial change. previous revision: rev. 0.51, 2008-03 all added 1gb and 2gb ecc-unbuffer ed dimm with thermal sensor product types and related information. previous revision: rev. 0.51, 2008-03 all added 1gb and 2gb ecc-unbuffer ed dimm with thermal sensor product types and related information. previous revision: rev. 0.5, 2007-12 all data sheet for 1gbyte and 2gbyte unbuffered dimm product family.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 3 03052008-r2g5-2fn2 1overview this chapter gives an overview of the 240?pin unbuffered ddr3 dual-in-line memory modules product family and describes its main characteristics. 1.1 features ? 240-pin 8-byte ddr3 sdram unbuffered dual-in-line memory modules. ? module organization: 128m 64, 256m 64, 128m 72, 256m 72 chip organization: 128m 8 ? pc3-12800, pc3-10600, pc3-8500 and pc3-6400 module speed grades. ? 2gb, 1gb, 512mb modules built with 1gb ddr3 sdrams in packages pg-tfbga-78. ? ddr3 sdrams with a single 1.5 v ( 0.075 v) power supply. ? asynchronous reset. ? programmable cas latency, cas write latency, additive latency, burst length and burst type. ? on-die-termination (odt) and dynamic odt for improved signal integrity. ? refresh. self refresh and power down modes. ? zq calibration for output driver and odt. ? system level timing calibration support via write leveling and multi purpose register (mpr) read pattern. ? serial presence detect with eeprom. ? thermal sensor functionality supported. ? udimm dimensions: 133.35 mm x 30 mm. ? based on standard reference raw cards: 'a', 'b', 'd', and 'e'. ? rohs compliant products 1) . table 1 performance table for ddr3?1600 and ddr3?1333 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, pol ybrominated biphenyls and polybro minated biphenyl ethers. for more information please vi sit www.qimonda.com/green_products . qag speed code ?16j ?13g ?13h unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setti ng and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?12800j ?10600g ?10600h device speed bin ddr3 ?1600j ?1333g ?1333h cl- n rcd - n rp 10-10-10 8-8-8 9-9-9 cl and cwl settings for maximum clock frequency cl = 10 cwl = 8 cl = 8 cwl = 7 cl = 9 cwl = 7 mhz maximum clock frequency and data rate with above cl and cwl settings 800 1600 667 1333 667 1333 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 667 1333 533 1066 533 1066 mhz mb/s
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 4 03052008-r2g5-2fn2 table 2 performance table for ddr3?1066 and ddr3?800 qag speed code ?10f ?10g ?08d ?08e unit note 1) 1) the available cl and cwl settings depend on t he sdram device speed bin. the cl setti ng and cwl setting result in maximum but also minimum clock frequency re quirements. when making a selecti on of operating clock frequency, bot h need to be fulfilled: requirem ents from cl setting as well as requirements from cwl setting. for details, refer to chapter 4.1 speed bins. module speed bin pc3 ?8500f ?8500g ?6400d ?6400e device speed bin ddr3 ?1066f ?1066g ?800d ?800e cl- n rcd - n rp 7-7-7 8-8-8 5-5-5 6-6-6 cl and cwl settings for maximum clock frequency cl = 7 cwl = 6 cl = 8 cwl = 6 cl = 5 cwl = 5 cl = 6 cwl = 5 mhz maximum clock frequency and data rate with above cl and cwl settings 533 1066 533 1066 400 800 400 800 mhz mb/s minimum clock frequency and data rate with above cl and cwl settings 400 800 400 800 300 600 300 600 mhz mb/s
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 5 03052008-r2g5-2fn2 1.2 description qimonda imsh[1g/2g][u/e]x3 a1f1c(t) are unbuffered dimm family with 30 mm height based on ddr3 sdram technology. dimms are available non-ecc modules in 128m 64 (1gb), 256m 64 (2gb), and as ecc modules in 128m 72 (1gb), 256m 72 (2gb) organization and density, intended for mounting into 240 pin connector sockets. the memory array is designed with 1gb double data rate (ddr3) synchronous drams. de-coupling capacitors, stub resistors, calibration resistor s and termination resistors are mounted on the pcb board. the dimms feature serial presence detect based on a 2 56 byte serial eeprom device using the 2-pin i 2 c protocol. the first 176 bytes are programmed with module specific spd data. table 3 ordering information table for modules without thermal sensor qag part number compliance code description 1024 mbyte non-ecc unbuffered dimm imsh1gu03a1f1c IMSH1GU03A1F1C-08D 1gb 1r8 pc3?6400u?5-10?a0 240 -pin 1024 mbyte ddr3 unbuffered dimm with one rank for non-ecc applications. the memory rank consists of eight ddr3 components in x8 organization. standard reference card a is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh1gu03a1f1c-08e 1gb 1r8 pc3?6400u?6-10?a0 imsh1gu03a1f1c-10f 1gb 1r8 pc3?8500u?7-10?a0 imsh1gu03a1f1c-10g 1gb 1r8 pc3?8500u?8-10?a0 imsh1gu03a1f1c-13g 1gb 1r8 pc3?10600u?8-10?a0 imsh1gu03a1f1c-13h 1gb 1r8 pc3?10600u?9-10?a0 imsh1gu03a1f1c-16j 1gb 1r8 pc3?12800u-10-10?a0 2048 mbyte non-ecc unbuffered dimm imsh2gu13a1f1c imsh2gu13a1f1c-08d 2gb 2r8 pc3?6400u?5-10?b0 240 -pin 2048 mbyte ddr3 unbuffered dimm with two ranks for non-ecc applications. each memory rank consists of eight ddr3 components in x8 organization. standard reference card b is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh2gu13a1f1c-08e 2gb 2r8 pc3?6400u?6-10?b0 imsh2gu13a1f1c-10f 2gb 2r8 pc3?8500u?7-10?b0 imsh2gu13a1f1c-10g 2gb 2r8 pc3?8500u?8-10?b0 imsh2gu13a1f1c-13g 2gb 2r8 pc3?10600u?8-10?b0 imsh2gu13a1f1c-13h 2gb 2r8 pc3?10600u?9-10?b0 imsh2gu13a1f1c-16j 2gb 2r8 pc3?12800u?10-10?b0
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 6 03052008-r2g5-2fn2 table 4 ordering information table for modules with thermal sensor qag part number compliance code description 1024 mbyte ecc unbuffered dimm imsh1ge03a1f1ct imsh1ge03a1f1ct08d 1g 1r8 pc3?6400e?5-10?d0 240-pin 1024 mbyte ddr3 unbuffered dimm with one rank and on-dimm thermal sensor for ecc applications. the memory rank consists of nine ddr3 components in x8 organization. standard reference card d is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh1ge03a1f1ct08e 1g 1r8 pc3?6400e?6-10?d0 imsh1ge03a1f1ct10f 1g 1r8 pc3?8500e?7-10?d0 imsh1ge03a1f1ct10g 1g 1r8 pc3?8500e?8-10?d0 imsh1ge03a1f1ct13g 1g 1r8 pc3?10600e?8-10?d0 imsh1ge03a1f1ct13h 1g 1r8 pc3?10600e?9-10?d0 2048 mbyte ecc unbuffered dimm imsh2ge13a1f1ct imsh2ge13a1f1ct08d 2gb 2r8 pc3?6400e?5-10?e0 240-p in 2048 mbyte ddr3 unbuffered dimm with two ranks and on-dimm thermal sensor for ecc applications. each memory rank consists of nine ddr3 components in x8 organization. standard reference card e is used on this assembly used ddr3 sdram component part number: idsh1g-03a1f1c density: 1gbit organization: 128mbit 8 address bits (row/column/bank): 14/10/3 imsh2ge13a1f1ct08e 2gb 2r8 pc3?6400e?6-10?e0 imsh2ge13a1f1ct10f 2gb 2r8 pc3?8500e?7-10?e0 imsh2ge13a1f1ct10g 2gb 2r8 pc3?8500e?8-10?e0 imsh2ge13a1f1ct13g 2gb 2r8 pc3?10600e?8-10?e0 imsh2ge13a1f1ct13h 2gb 2r8 pc3?10600e?9-10?e0
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 7 03052008-r2g5-2fn2 2 configuration 2.1 pin configuration table 5 pin configuration of ddr3 udimm - 240 pins pin name eda signal name 1) pin no. pin type buffer type function clock signals ck0 ck0_t 184 i sstl clock inputs [1:0] and diff ernetial clock inputs [1:0] ck0 ck0_c 185 i sstl ck1 ck1_t 63 i sstl ck1 ck1_c 64 i sstl control signals cke0 cke0 50 i sstl clock enable [1:0] cke1/nc cke1 169 i sstl odt0 odt0 195 i sstl on-die termina tion [1:0] odt1/nc odt1 77 i s0 s0_n 193 i sstl chip select [1:0] s1 /nc s1_n 76 i sstl command signals ras ras_n 192 i sstl row address strobe cas cas_n 74 i sstl column address strobe we we_n 73 i sstl write enable bank address signals ba0 ba0 71 i sstl bank address bus[2:0] ba1 ba1 190 i sstl ba2 ba2 52 i sstl address signals a0 a0 188 i sstl address bus [15:0] a1 a1 181 i sstl a2 a2 61 i sstl a3 a3 180 i sstl a4 a4 59 i sstl a5 a5 58 i sstl
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 8 03052008-r2g5-2fn2 a6 a6 178 i sstl address bus [15:0] a7 a7 56 i sstl a8 a8 177 i sstl a9 a9 175 i sstl a10/ap a10 70 i sstl a11 a11 55 i sstl a12/bc a12 174 i sstl a13 a13 196 i sstl a14 a14 172 i sstl a15/nc a15 171 i sstl data signals dq0 dq0 3 i/o sstl data bus [63:0] dq1 dq1 4 i/o sstl dq2 dq2 9 i/o sstl dq3 dq3 10 i/o sstl dq4 dq4 122 i/o sstl dq5 dq5 123 i/o sstl dq6 dq6 128 i/o sstl dq7 dq7 129 i/o sstl dq8 dq8 12 i/o sstl dq9 dq9 13 i/o sstl dq10 dq10 18 i/o sstl dq11 dq11 19 i/o sstl dq12 dq12 131 i/o sstl dq13 dq13 132 i/o sstl dq14 dq14 137 i/o sstl dq15 dq15 138 i/o sstl dq16 dq16 21 i/o sstl dq17 dq17 22 i/o sstl dq18 dq18 27 i/o sstl dq19 dq19 28 i/o sstl dq20 dq20 140 i/o sstl dq21 dq21 141 i/o sstl dq22 dq22 146 i/o sstl dq23 dq23 147 i/o sstl dq24 dq24 30 i/o sstl dq25 dq25 31 i/o sstl dq26 dq26 36 i/o sstl dq27 dq27 37 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 9 03052008-r2g5-2fn2 dq28 dq28 149 i/o sstl data bus [63:0] dq29 dq29 150 i/o sstl dq30 dq30 155 i/o sstl dq31 dq31 156 i/o sstl dq32 dq32 81 i/o sstl dq33 dq33 82 i/o sstl dq34 dq34 87 i/o sstl dq35 dq35 88 i/o sstl dq36 dq36 200 i/o sstl dq37 dq37 201 i/o sstl dq38 dq38 206 i/o sstl dq39 dq39 207 i/o sstl dq40 dq40 90 i/o sstl dq41 dq41 91 i/o sstl dq42 dq42 96 i/o sstl dq43 dq43 97 i/o sstl dq44 dq44 209 i/o sstl dq45 dq45 210 i/o sstl dq46 dq46 215 i/o sstl dq47 dq47 216 i/o sstl dq48 dq48 99 i/o sstl dq49 dq49 100 i/o sstl dq50 dq50 105 i/o sstl dq51 dq51 106 i/o sstl dq52 dq52 218 i/o sstl dq53 dq53 219 i/o sstl dq54 dq54 224 i/o sstl dq55 dq55 225 i/o sstl dq56 dq56 108 i/o sstl dq57 dq57 109 i/o sstl dq58 dq58 114 i/o sstl dq59 dq59 115 i/o sstl dq60 dq60 227 i/o sstl dq61 dq61 228 i/o sstl dq62 dq62 233 i/o sstl dq63 dq63 234 i/o sstl cb0/nc cb0 39 i/o sstl check bit [7:0] cb1/nc cb1 40 i/o sstl cb2/nc cb2 45 i/o sstl pin name eda signal name 1) pin no. pin type buffer type function
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 10 03052008-r2g5-2fn2 cb3/nc cb3 46 i/o sstl check bit [7:0] cb4/nc cb4 158 i/o sstl cb5/nc cb5 159 i/o sstl cb6/nc cb6 164 i/o sstl cb7/nc cb7 165 i/o sstl dqs0 dqs0_t 7 i/o sstl data strobe signal s [8:0] and complementary data strobe signals[8:0] dqs0 dqs0_c 6 i/o sstl dqs1 dqs1_t 16 i/o sstl dqs1 dqs1_c 15 i/o sstl dqs2 dqs2_t 25 i/o sstl dqs2 dqs2_c 24 i/o sstl dqs3 dqs3_t 34 i/o sstl dqs3 dqs3_c 33 i/o sstl dqs4 dqs4_t 85 i/o sstl dqs4 dqs4_c 84 i/o sstl dqs5 dqs5_t 94 i/o sstl dqs5 dqs5_c 93 i/o sstl dqs6 dqs6_t 103 i/o sstl dqs6 dqs6_c 102 i/o sstl dqs7 dqs7_t 112 i/o sstl dqs7 dqs7_c 111 i/o sstl dqs8/nc dqs8_t 43 i/o sstl dqs8 /nc dqs8_c 42 i/o sstl dm0 dm0 125 i sstl data mask signals [8:0] dm1 dm1 134 i sstl dm2 dm2 143 i sstl dm3 dm3 152 i sstl dm4 dm4 203 i sstl dm5 dm5 212 i sstl dm6 dm6 221 i sstl dm7 dm7 230 i sstl dm8/nc dm8 161 i sstl eeprom scl scl 118 i cmos serial bus clock sda sda 238 i/o od serial data bus sa0 sa0 117 i cmos serial address select bus [2:0] sa1 sa1 237 i cmos sa2 sa2 119 i cmos power supply pin name eda signal name 1) pin no. pin type buffer type function
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 11 03052008-r2g5-2fn2 v dd vdd 51, 54, 57, 60, 62, 65, 66, 69, 72, 75, 78, 170, 173, 176, 179, 182, 183,186, pwr - power supply v dd vdd 189, 191, 194, 197 pwr - power supply v ss vss 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 80, 83, 86, 89,92, 95, 98, 101, 104, 107, 110, 113, 116, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 199, 202, 205, 208, 211, 214, 217, 220, 223, 226, 229, 232, 235, 239 gnd - ground v ref.dq vrefdq 1 ai - reference voltage v ref.ca vrefca 67 ai - reference voltage v tt vtt 120 , 240 pwr - termination voltage v ddspd vddspd 236 - eeprom and thermal sensor power supply other pins test/nc -167 i/o- test event / nc event_n 187 o - event reset reset_n 168 i cmos asynchronous reset nc nc 48, 49, 53, 68, 79, 126,135, 144, 153, 162, 198, 204, 213, 222, 231 not connected 1) the eda (electronic design automation) signal name is used in qimonda simulation models such as ebd (electronic board descrip tion). pin name eda signal name 1) pin no. pin type buffer type function
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 12 03052008-r2g5-2fn2 table 6 abbreviations for pin type table 7 abbreviations for buffer type abbreviation description i standard input pin only. digital levels. o standard output pin only - digital levels. i/o i/o is a bidirectional input/output signal. ai input - analog levels. pwr power gnd ground nc not connected abbreviation description sstl serial stub terminated logic cmos cmos levels od open drain. the corresponding pin has 2 oper ational states, active low and tri-state, and allows multiple devices to share as a wire-or.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 13 03052008-r2g5-2fn2 figure 1 pin configuration udimm - 240 pin 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 5()'4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 &%1& '461& 9 66 &%1& 1& &.( %$ 9 '' $ $ 9 '' 9 '' &. 9 '' 1& $$3 9 '' &$6 61& 9 '' 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 6&/ 9 77 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 &%1& 9 66 '461& &%1& 9 66 1& 9 '' 1& $ 9 '' $ $ &. 9 '' 9 5()&$ 9 '' %$ :( 9 '' 2'71& 1& '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 '4 9 66 '46 '4 9 66 '4 '46 9 66 '4 6$ 6$ 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 '4 9 66 1& '4 9 66 '4 '0 9 66 '4 '4 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 9 66 1& '4 9 66 '4 '0 9 66 '4 &%1& 9 66 1& &%1& 9 66 5(6(7 9 '' $ $%& 9 '' $ $ 9 '' &. 9 '' $ %$ 5$6 9 ''4 $ 1& '4 9 66 1& '4 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 '4 '0 9 66 '4 9 ''63' 6'$ 9 77 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq 3lq '4 '0 9 66 '4 '4 9 66 1& '4 9 66 &%1& '01& 9 66 &%1& 7(671& &.(1& $1& 9 '' $ $ 9 '' $ 9 '' &. (9(171& 9 '' 9 '' 6 2'7 9 '' 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 '4 '0 9 66 '4 '4 9 66 1& '4 9 66 6$ 9 66 ) 5 2 1 7 6 , ' ( % $ & . 6 , ' ( 033+
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 14 03052008-r2g5-2fn2 3 operating conditions 3.1 absolute maximum ratings table 8 absolute maximum ratings table 9 environmental parameters attention: stresses greater than those listed under ?abs olute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the device at these or any other conditions above those indicated in the operational sect ions of this specification is not implied. exposure to absolute maximum rating conditions fo r extended periods may affect reliability. parameter symbol rating unit note min. max. voltage on v dd pin relative to v ss v dd ?0.4 +1.975 v 1) 1) v dd and v ddq must be within 300mv of each other at all times. v refdq and v refca must not be greater than 0.6 x v ddq . when v dd and v ddq are less than 500 mv, v refdq and v refca may be equal or less than 300 mv. voltage on v ddq pin relative to v ss v ddq ?0.4 +1.975 v voltage on any pin relative to v ss v in , v out ?0.4 +1.975 v parameter symbol rating unit note min. max. operating temperature t opr 055 c 1) 1) the component maximum case temperature ( t case ) shall not exceed the value specified in the ddr3 dra m component specification.. operating humidity (relative) h opr 10 90 % storage temperature t stg ?50 +100 c 2) 2) storage temperature is the case surface temperature on the c enter/top side of the sdram mentioned in qimonda component datash eet. storage humidity (without condensation) h stg 595 % barometric pressure (operating and storage) p bar 69 105 kpascal 3) 3) up to 9850 ft.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 15 03052008-r2g5-2fn2 table 10 dram component operating temperature range 3.2 recommended dc operating conditions table 11 dc operating conditions parameter symbol rating unit note min. max. normal operating temperature range t oper 085 c 1)2) 1) operating temperature t oper is the case surface temperature on the center / top side of the sdram mentioned.. 2) the normal temperature range specifies the temperat ures where all sdram spec ification will be supported. extended temperature range 85 95 c 1)3) 3) some application require operation of the dram in the extended temperature range between 85 c and 95 c operating temperature. for more details please refer to qimonda component datasheet. parameter symbol min. typ. max. unit note supply voltage v dd 1.425 1.5 1.575 v 1)2) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together 2) under all conditions v ddq must be less than or equal to v dd . supply voltage for eeprom and thermal sensor v dd.spd 3.0 3.3 3.6 v 1)2) supply voltage for output v ddq 1.425 1.5 1.575 v 1)2) reference voltage for dq, dm inputs v refdq.dc 0.49 x v dd 0.5 x v dd 0.51 x v dd v 3)4) 3) the ac peak noise on v ref may not allow v ref to deviate from v ref.dc by more than 1% v dd (for reference: approx. 15 mv). 4) for reference: approx. v dd /2 15 mv. reference voltage for add, cmd inputs v refca.dc 0.49 x v dd 0.5 x v dd 0.51 x v dd v 3)4) terminal voltage v tt 0.49 x v dd 0.5 x v dd 0.51 x v dd v external calibration resistor connected from zq pin to ground r zq 237.6 240.0 242.4 5) 5) the external calibration resistor r zq can be time-shared among drams in multi-rank dimms.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 16 03052008-r2g5-2fn2 4 speed bins and timing parameters ac timings are provided with ck/ck and dqs/dqs differential slew rate of 2.0 v/ns. timings are further provided for calibrated ocd driv e strength. the ck/ck input reference level (for timing referenced to ck / ck ) is the point at which ck and ck cross.the dqs/dqs reference level (for timing referenced to dqs/dqs ) is the point at which dqs and dqs cross.inputs are not re cognized as valid until v ref stabilizes. during the period before v ref.ca and v refdq stabilizes, cke = 0.2 x v ddq is recognized as low. the output timing reference voltage level is v tt .for details of all relevant ac timing parameters see the qimonda ddr3 component datasheet. 4.1 speed bins the following tables show ddr3 speed bins and relevant timing parameters. other timi ng parameters are provided in the following chapter. the absolute specification for all speed bins is t oper and v dd = v ddq = 1.5 v +/-0.075 v. in addition the following general notes apply. general notes for speed bins: ? the cl setting and cwl setting result in t ck.avg.min and t ck.avg.max requirements. when making a selection of t ck.avg , both need to be fulfiled: requirements from cl setting as well as requirements from cwl setting ? t ck.avg.min limits: since cas latency is not purely analog - data and strobe output are syn chronized by the dll - all possible intermediate frequencies may not be provided. an application should use the next smaller standard t ck.avg value (2.5, 1.875, 1.5, or 1. 25 ns) when calculating cl [nck] = t aa [ns] / t ck.avg [ns], rounding up to the next ?supported cl? ? t ck.avg.max limits: calculate t ck.avg = t aa.max / clselected and round the resulting t ck.avg down to the next valid speed bin limit (i.e. 3.3 ns or 2.5 ns or 1.875 ns or 1.25 ns). this result is t ck.avg.max corresponding to clselected ? ?reserved? settings are not a llowed. user must program a different value ? any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization ? any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization ? any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the tables which are not subject to production tests but verified by design/characterization table 12 ddr3-800 speed bins an d operating conditions speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qag partnumber extension -08d -08e parameter symbol min. max. min. max. internal read command to first data t aa 12.5 20.0 15.0 20.0 ns 1) act to internal read or write delay time t rcd 12.5 ? 15.0 ? ns 1) pre command period t rp 12.5 ? 15.0 ? ns 1) act to act or ref command period t rc 50.0 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6 6 n ck 1) supported cwl settings sup_cwl 5 5 n ck 1)
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 17 03052008-r2g5-2fn2 table 13 ddr3-1066 speed bins and operating conditions average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) 1) please refer to "general notes for speed bins" at beginning of this chapter. 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. speed bin ddr3-1066e ddr3- 1066f ddr3-1066g unit note cl- n rcd - n rp 6-6-6 7-7-7 8-8-8 qag partnumber extension -10e -10f -10g parameter symbol min. max. min. max. min. max. internal read command to first data t aa 11.25 20.0 13.125 20.0 15.0 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 11.25 ? 13.125 ? 15.0 ? ns 1) pre command period t rp 11.25 ? 13.125 ? 15.0 ? ns 1) act to act or ref command period t rc 48.75 ? 50.625 ? 52.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8 6, 7, 8 6, 8 n ck 1) supported cwl settings sup_cwl 5, 6 5, 6 5, 6 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) speed bin ddr3-800d ddr3-800e unit note cl- n rcd - n rp 5-5-5 6-6-6 qag partnumber extension -08d -08e parameter symbol min. max. min. max.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 18 03052008-r2g5-2fn2 table 14 ddr3-1333 speed bins and operating conditions speed bin ddr3-1333g ddr3-1333h unit note cl-nrcd-nrp 8-8-8 9-9-9 qag partnumber extension -13g -13h parameter symbol min. max. min. max. internal read command to first data t aa 12.0 20.0 13.5 20.0 ns 1) 1) please refer to "general notes for speed bins" at beginning of this chapter. act to internal read or write delay time t rcd 12.0 ? 13.5 ? ns 1) pre command period t rp 12.0 ? 13.5 ? ns 1) act to act or ref command period t rc 48.0 ? 49.5 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8, 9, 10 6, 8, 9, 10 n ck 1) supported cwl settings sup_cwl 5, 6, 7 5, 6, 7 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 reserved ns 1)2) 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 reserved ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.875 ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 ns 1)2)
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 19 03052008-r2g5-2fn2 table 15 ddr3-1600 speed bins and operating conditions speed bin ddr3-1600g ddr3-1600h ddr3-1600j ddr3-1600k unit note cl-nrcd-nrp 8-8-8 9-9-9 10-10-10 11-11-11 qag partnumber exte nsion -16g -16h -16j -16k parameter symbol min. max. mi n. max. min. max. min. max. internal read command to first data t aa 10.0 20.0 11.25 20.0 12.5 20.0 13.75 20.0 ns 1) act to internal read or write delay time t rcd 10.0 ? 11.25 ? 12.5 ? 13.75 ? ns 1) pre command period t rp 10.0 ? 11.25 ? 12.5 ? 13.75 ? ns 1) act to act or ref command period t rc 45.0 ? 46.25 ? 47.5 ? 48.75 ? ns 1) supported cl settings sup_cl 5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11 5, 6, 7, 8, 9, 10, 11 6, 8, 10, 11 n ck 1) supported cwl settings sup_cwl 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 5, 6, 7, 8 n ck 1) average clock period with cl = 5; cwl = 5 t ck.avg.cl05.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 reserved ns 1)2) average clock period with cl = 5; cwl = 6 t ck.avg.cl05.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 5; cwl = 7 t ck.avg.cl05.cwl07 reserved reserved reserved reserved ns 1)2) average clock period with cl = 5; cwl = 8 t ck.avg.cl05.cwl08 reserved reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 5 t ck.avg.cl06.cwl05 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 ns 1)2) average clock period with cl = 6; cwl = 6 t ck.avg.cl06.cwl06 1.875 2.5 1.875 2.5 reserved reserved ns 1)2) average clock period with cl = 6; cwl = 7 t ck.avg.cl06.cwl07 reserved reserved reserved reserved ns 1)2) average clock period with cl = 6; cwl = 8 t ck.avg.cl06.cwl08 reserved reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 5 t ck.avg.cl07.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 6 t ck.avg.cl07.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 reserved ns 1)2) average clock period with cl = 7; cwl = 7 t ck.avg.cl07.cwl07 1.5 1.875 reserved reserved reserved ns 1)2) average clock period with cl = 7; cwl = 8 t ck.avg.cl07.cwl08 reserved reserved reserved reserved ns 1)2) average clock period with cl = 8; cwl = 5 t ck.avg.cl08.cwl05 reserved reserved reserved reserved ns 1)2)
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 20 03052008-r2g5-2fn2 average clock period with cl = 8; cwl = 6 t ck.avg.cl08.cwl06 1.875 2.5 1.875 2.5 1.875 2.5 1.875 2.5 ns 1)2) average clock period with cl = 8; cwl = 7 t ck.avg.cl08.cwl07 1.5 1.875 1.5 1.875 reserved reserved ns 1)2) average clock period with cl = 8; cwl = 8 t ck.avg.cl08.cwl08 1.25 1.5 reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 5 t ck.avg.cl09.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 6 t ck.avg.cl09.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 9; cwl = 7 t ck.avg.cl09.cwl07 1.5 1.875 1.5 1.87 5 1.5 1.875 reserved ns 1)2) average clock period with cl = 9; cwl = 8 t ck.avg.cl09.cwl08 1.25 1.5 1.25 1.5 reserved reserved ns 1)2) average clock period with cl = 10; cwl = 5 t ck.avg.cl10.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 6 t ck.avg.cl10.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 10; cwl = 7 t ck.avg.cl10.cwl07 1.5 1.875 1.5 1.875 1.5 1.875 1.5 1.875 ns 1)2) average clock period with cl = 10; cwl = 8 t ck.avg.cl10.cwl08 1.25 1.5 1.25 1.5 1.25 1.5 reserved ns 1)2) average clock period with cl = 11; cwl = 5 t ck.avg.cl11.cwl05 reserved reserved reserved reserved ns 1)2) average clock period with cl = 11; cwl = 6 t ck.avg.cl11.cwl06 reserved reserved reserved reserved ns 1)2) average clock period with cl = 11; cwl = 7 t ck.avg.cl11.cwl07 reserved reserved reserved reserved ns 1)2) average clock period with cl = 11; cwl = 8 t ck.avg.cl11.cwl08 1.25 1.5 1.25 1.5 1.25 1.5 1.25 1.5 ns 1)2) 1) please refer to "general notes for speed bins" at beginning of this chapter. 2) max. limits are exclusive. e.g. if t ck.avg.max value is 2.5 ns, t ck.avg needs to be < 2.5 ns. speed bin ddr3-1600g ddr3-1600h ddr3-1600j ddr3-1600k unit note cl-nrcd-nrp 8-8-8 9-9-9 10-10-10 11-11-11 qag partnumber exte nsion -16g -16h -16j -16k parameter symbol min. max. mi n. max. min. max. min. max.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 21 03052008-r2g5-2fn2 5 spd codes this chapter lists all hexadecimal byte values stored in the eeprom of the products described in this data sheet. spd stands for serial presence detect. all values with xx in the table are module specific bytes which are defined during production. list of spd code tables ? table 16 ?spd codes for imsh1gu03a1f1c? on page 21 ? table 17 ?spd codes for imsh1gu03a1f1c? on page 25 ? table 18 ?spd codes for imsh2gu13a1f1c? on page 28 ? table 19 ?spd codes for imsh2gu13a1f1c? on page 31 ? table 20 ?spd codes for imsh1ge03a1f1ct? on page 34 ? table 21 ?spd codes for imsh2ge13a1f1ct? on page 38 table 16 spd codes for imsh1gu03a1f1c product type imsh1gu03a1f1c?08d imsh1gu03a1f1c?08e imsh1gu03a1f1c?10f imsh1gu03a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 1 spd revision 10 10 10 10 2 sdram technology key byte 0b 0b 0b 0b 3 dimm module type 02 02 02 02 4 sdram density and banks 02 02 02 02 5 sdram addressing 11 11 11 11 6 module physical attributes 00 00 00 00 7 module organization 01 01 01 01 8 module memory bus width 03 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 22 03052008-r2g5-2fn2 11 medium time base (mtb) divisor 08 08 08 08 12 minimum sdram cycle time ( t ck.min )14140f0f 13 reserved 00 00 00 00 14 cas latencies supported - lsb 06 04 1c 14 15 cas latencies supported - msb 00 00 00 00 16 minimum cas latency time (t ck.min )64786978 17 minimum write recovery time (t wr.min )78787878 18 minimum ras# tocas# delay time (t rcd.min )64 78 69 78 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 20 minimum row prechargetime (t rp.min )64786978 21 upper nibbles fo r t ras and t rc 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb 2c 2c 2c 2c 23 minimum active to active/refresh time (t rc.min ), lsb 90 a4 95 a4 24 minimum refresh recovery time (t rfc.min ), lsb 70 70 70 70 25 minimum refresh recovery time (t rfc.min ), msb 03 03 03 03 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 29 minimum four activate window delay time (t faw.min )40 40 2c 2c 30 sdram output drivers supported 02 02 02 02 31 sdram refresh options 81 81 81 81 32 - 59 reserved 00 00 00 00 60 module nominal height 10 10 10 10 product type imsh1gu03a1f1c?08d imsh1gu03a1f1c?08e imsh1gu03a1f1c?10f imsh1gu03a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 23 03052008-r2g5-2fn2 61 module maximum thickness 01 01 01 01 62 raw card used 00 00 00 00 63 address mapping from edge connector to dram 00 00 00 00 64 - 116 reserved 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 119 module manufacturing location xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx 122 - 125 module serial number xx xx xx xx 126 cyclical redundancy code lsb 9a 95 0d 6e 127 cyclical redundancy code msb 76 87 de 2b 128 product type, char 1 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 131 product type, char 4 48 48 48 48 132 product type, char 5 31 31 31 31 133 product type, char 6 47 47 47 47 134 product type, char 7 55 55 55 55 135 product type, char 8 30 30 30 30 136 product type, char 9 33 33 33 33 137 product type, char 10 41 41 41 41 138 product type, char 11 31 31 31 31 139 product type, char 12 46 46 46 46 140 product type, char 13 31 31 31 31 product type imsh1gu03a1f1c?08d imsh1gu03a1f1c?08e imsh1gu03a1f1c?10f imsh1gu03a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 24 03052008-r2g5-2fn2 141 product type, char 14 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 143 product type, char 16 30 30 31 31 144 product type, char 17 38 38 30 30 145 product type, char 18 44 45 46 47 146 module revision code, lsb 2x 2x 2x 2x 147 module revision code, msb xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 176 - 255 blank for customer use 00 00 00 00 product type imsh1gu03a1f1c?08d imsh1gu03a1f1c?08e imsh1gu03a1f1c?10f imsh1gu03a1f1c?10g organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 64 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 25 03052008-r2g5-2fn2 table 17 spd codes for imsh1gu03a1f1c product type imsh1gu03a1f1c?13g imsh1gu03a1f1c?13h imsh1gu03a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3?10600u?8 pc3?10600u?9 pc3?12800u?11 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 1 spd revision 10 10 10 2 sdram technology key byte 0b 0b 0b 3 dimm module type 02 02 02 4 sdram density and banks 02 02 02 5 sdram addressing 11 11 11 6 module physical attributes 00 00 00 7 module organization 01 01 01 8 module memory bus width 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 10 medium time base (mtb) dividend 01 01 01 11 medium time base (mtb) divisor 08 08 08 12 minimum sdram cycle time ( t ck.min )0c0c0a 13 reserved 00 00 00 14 cas latencies supported - lsb 7e 7c 7e 15 cas latencies supported - msb 00 00 00 16 minimum cas latency time (t ck.min )606964 17 minimum write recovery time (t wr.min )78 78 78 18 minimum ras# tocas# delay time (t rcd.min )60 69 64 19 minimum row active to row active delay time (t rrd.min ) 30 30 30 20 minimum row prechargetime (t rp.min )60 69 64 21 upper nibbles fo r t ras and t rc 11 11 11 22 minimum active to precharge time (t ras.min ), lsb 20 20 18
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 26 03052008-r2g5-2fn2 23 minimum active to active/refresh time (t rc.min ), lsb 80 8c 7c 24 minimum refresh recovery time (t rfc.min ), lsb 70 70 70 25 minimum refresh recovery time (t rfc.min ), msb 03 03 03 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 28 upper nibble for t faw 00 00 00 29 minimum four activate window delay time (t faw.min )f0f0f0 30 sdram output drivers supported 02 02 02 31 sdram refresh options 81 81 81 32 - 59 reserved 00 00 00 60 module nominal height 10 10 10 61 module maximum thickness 01 01 01 62 raw card used 00 00 00 63 address mapping from edge connector to dram 00 00 00 64 - 116 reserved 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 119 module manufacturing location xx xx xx 120 - 121 module manufacturing date xx xx xx 122 - 125 module serial number xx xx xx 126 cyclical redundancy code lsb c9 d9 cc 127 cyclical redundancy code msb 51 ce a8 128 product type, char 1 49 49 49 product type imsh1gu03a1f1c?13g imsh1gu03a1f1c?13h imsh1gu03a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3?10600u?8 pc3?10600u?9 pc3?12800u?11 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 27 03052008-r2g5-2fn2 129 product type, char 2 4d 4d 4d 130 product type, char 3 53 53 53 131 product type, char 4 48 48 48 132 product type, char 5 31 31 31 133 product type, char 6 47 47 47 134 product type, char 7 55 55 55 135 product type, char 8 30 30 30 136 product type, char 9 33 33 33 137 product type, char 10 41 41 41 138 product type, char 11 31 31 31 139 product type, char 12 46 46 46 140 product type, char 13 31 31 31 141 product type, char 14 43 43 43 142 product type, char 15 2d 2d 2d 143 product type, char 16 31 31 31 144 product type, char 17 33 33 36 145 product type, char 18 47 48 4a 146 module revision code, lsb 3x 3x 0x 147 module revision code, msb xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 150 - 175 manufactures?s specific data 00 00 00 176 - 255 blank for customer use 00 00 00 product type imsh1gu03a1f1c?13g imsh1gu03a1f1c?13h imsh1gu03a1f1c?16j organization 1 gbyte 1 gbyte 1 gbyte 64 64 64 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3?10600u?8 pc3?10600u?9 pc3?12800u?11 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 28 03052008-r2g5-2fn2 table 18 spd codes for imsh2gu13a1f1c product type imsh2gu13a1f1c?08d imsh2gu13a1f1c?08e imsh2gu13a1f1c?10f imsh2gu13a1f1c?10g organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 1 spd revision 10 10 10 10 2 sdram technology key byte 0b 0b 0b 0b 3 dimm module type 02 02 02 02 4 sdram density and banks 02 02 02 02 5 sdram addressing 11 11 11 11 6 module physical attributes 00 00 00 00 7 module organization 09 09 09 09 8 module memory bus width 03 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 11 medium time base (mtb) divisor 08 08 08 08 12 minimum sdram cycle time ( t ck.min )14140f0f 13 reserved 00 00 00 00 14 cas latencies supported - lsb 06 04 1c 14 15 cas latencies supported - msb 00 00 00 00 16 minimum cas latency time (t ck.min )64786978 17 minimum write recovery time (t wr.min )78787878 18 minimum ras# tocas# delay time (t rcd.min )64 78 69 78 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 20 minimum row prechargetime (t rp.min )64786978 21 upper nibbles fo r t ras and t rc 11 11 11 11
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 29 03052008-r2g5-2fn2 22 minimum active to precharge time (t ras.min ), lsb 2c 2c 2c 2c 23 minimum active to active/refresh time (t rc.min ), lsb 90 a4 95 a4 24 minimum refresh recovery time (t rfc.min ), lsb 70 70 70 70 25 minimum refresh recovery time (t rfc.min ), msb 03 03 03 03 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 29 minimum four activate window delay time (t faw.min )40 40 2c 2c 30 sdram output drivers supported 02 02 02 02 31 sdram refresh options 81 81 81 81 32 - 59 reserved 00 00 00 00 60 module nominal height 10 10 10 10 61 module maximum thickness 11 11 11 11 62 raw card used 01 01 01 01 63 address mapping from edge connector to dram 01 01 01 01 64 - 116 reserved 00 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 51 119 module manufacturing location xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx 122 - 125 module serial number xx xx xx xx 126 cyclical redundancy code lsb e7 e8 70 13 127 cyclical redundancy code msb bf 4e 17 e2 product type imsh2gu13a1f1c?08d imsh2gu13a1f1c?08e imsh2gu13a1f1c?10f imsh2gu13a1f1c?10g organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 30 03052008-r2g5-2fn2 128 product type, char 1 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 131 product type, char 4 48 48 48 48 132 product type, char 5 32 32 32 32 133 product type, char 6 47 47 47 47 134 product type, char 7 55 55 55 55 135 product type, char 8 31 31 31 31 136 product type, char 9 33 33 33 33 137 product type, char 10 41 41 41 41 138 product type, char 11 31 31 31 31 139 product type, char 12 46 46 46 46 140 product type, char 13 31 31 31 31 141 product type, char 14 43 43 43 43 142 product type, char 15 2d 2d 2d 2d 143 product type, char 16 30 30 31 31 144 product type, char 17 38 38 30 30 145 product type, char 18 44 45 46 47 146 module revision code, lsb 2x 2x 2x 2x 147 module revision code, msb xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 176 - 255 blank for customer use 00 00 00 00 product type imsh2gu13a1f1c?08d imsh2gu13a1f1c?08e imsh2gu13a1f1c?10f imsh2gu13a1f1c?10g organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 64 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400u?5 pc3? 6400u?6 pc3? 8500u?7 pc3? 8500u?8 jedec spd revision rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 31 03052008-r2g5-2fn2 table 19 spd codes for imsh2gu13a1f1c product type imsh2gu13a1f1c?13g imsh2gu13a1f1c?13h imsh2gu13a1f1c?16j organization 2 gbyte 2 gbyte 2 gbyte 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3?10600u?8 pc3?10600u?9 pc3?12800u?11 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 1 spd revision 10 10 10 2 sdram technology key byte 0b 0b 0b 3 dimm module type 02 02 02 4 sdram density and banks 02 02 02 5 sdram addressing 11 11 11 6 module physical attributes 00 00 00 7 module organization 09 09 09 8 module memory bus width 03 03 03 9 fine time base (ftb) dividend and divisor 52 52 52 10 medium time base (mtb) dividend 01 01 01 11 medium time base (mtb) divisor 08 08 08 12 minimum sdram cycle time ( t ck.min )0c0c0a 13 reserved 00 00 00 14 cas latencies supported - lsb 7e 7c 7e 15 cas latencies supported - msb 00 00 00 16 minimum cas latency time (t ck.min )606964 17 minimum write recovery time (t wr.min )78 78 78 18 minimum ras# tocas# delay time (t rcd.min )60 69 64 19 minimum row active to row active delay time (t rrd.min ) 30 30 30 20 minimum row prechargetime (t rp.min )60 69 64 21 upper nibbles fo r t ras and t rc 11 11 11 22 minimum active to precharge time (t ras.min ), lsb 20 20 18
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 32 03052008-r2g5-2fn2 23 minimum active to active/refresh time (t rc.min ), lsb 80 8c 7c 24 minimum refresh recovery time (t rfc.min ), lsb 70 70 70 25 minimum refresh recovery time (t rfc.min ), msb 03 03 03 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 28 upper nibble for t faw 00 00 00 29 minimum four activate window delay time (t faw.min )f0f0f0 30 sdram output drivers supported 02 02 02 31 sdram refresh options 81 81 81 32 - 59 reserved 00 00 00 60 module nominal height 10 10 10 61 module maximum thickness 11 11 11 62 raw card used 01 01 01 63 address mapping from edge connector to dram 01 01 01 64 - 116 reserved 00 00 00 117 dimm manufacturer?s id code lsb 85 85 85 118 dimm manufacturer?s id code msb 51 51 51 119 module manufacturing location xx xx xx 120 - 121 module manufacturing date xx xx xx 122 - 125 module serial number xx xx xx 126 cyclical redundancy code lsb b4 a4 b1 127 cyclical redundancy code msb 98 07 61 128 product type, char 1 49 49 49 product type imsh2gu13a1f1c?13g imsh2gu13a1f1c?13h imsh2gu13a1f1c?16j organization 2 gbyte 2 gbyte 2 gbyte 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3?10600u?8 pc3?10600u?9 pc3?12800u?11 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 33 03052008-r2g5-2fn2 129 product type, char 2 4d 4d 4d 130 product type, char 3 53 53 53 131 product type, char 4 48 48 48 132 product type, char 5 32 32 32 133 product type, char 6 47 47 47 134 product type, char 7 55 55 55 135 product type, char 8 31 31 31 136 product type, char 9 33 33 33 137 product type, char 10 41 41 41 138 product type, char 11 31 31 31 139 product type, char 12 46 46 46 140 product type, char 13 31 31 31 141 product type, char 14 43 43 43 142 product type, char 15 2d 2d 2d 143 product type, char 16 31 31 31 144 product type, char 17 33 33 36 145 product type, char 18 47 48 4a 146 module revision code, lsb 3x 3x 0x 147 module revision code, msb xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 150 - 175 manufactures?s specific data 00 00 00 176 - 255 blank for customer use 00 00 00 product type imsh2gu13a1f1c?13g imsh2gu13a1f1c?13h imsh2gu13a1f1c?16j organization 2 gbyte 2 gbyte 2 gbyte 64 64 64 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3?10600u?8 pc3?10600u?9 pc3?12800u?11 jedec spd revision rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 34 03052008-r2g5-2fn2 table 20 spd codes for imsh1ge03a1f1ct product type imsh1ge03a1f1ct08d imsh1ge03a1f1ct08e imsh1ge03a1f1ct10f imsh1ge03a1f1ct10g imsh1ge03a1f1ct13g imsh1ge03a1f1ct13h organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 92 1 spd revision 10 10 10 10 10 10 2 sdram technology key byte 0b 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 02 4 sdram density and banks 02 02 02 02 02 02 5 sdram addressing 11 11 11 11 11 11 6 module physical attributes 00 00 00 00 00 00 7 module organization 01 01 01 01 01 01 8 module memory bus width 0b 0b 0b 0b 0b 0b 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 01 11medium time base (mtb) divisor 080808080808 12 minimum sdram cycle time ( t ck.min ) 14140f0f0c0c 13 reserved 00 00 00 00 00 00 14 cas latencies supported - lsb 06 04 1c 14 7e 7c 15 cas latencies supported - msb 00 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 647869786069 17 minimum write recovery time (t wr.min ) 787878787878 18 minimum ras# tocas# delay time (t rcd.min ) 647869786069 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 30 30 20 minimum row prechargetime (t rp.min ) 647869786069
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 35 03052008-r2g5-2fn2 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2c2c2c2c20 20 23 minimum active to active/refresh time (t rc.min ), lsb90a495a4808c 24 minimum refresh recovery time (t rfc.min ), lsb707070707070 25 minimum refresh recovery time (t rfc.min ), msb030303030303 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 00 00 29 minimum four activate window delay time (t faw.min )40402c2cf0f0 30sdram output drivers supported 020202020202 31 sdram refresh options 81 81 81 81 81 81 32 - 59 reserved 00 00 00 00 00 00 60 module nominal height 10 10 10 10 10 10 61 module maximum thickness 01 01 01 01 01 01 62 raw card used 03 03 03 03 03 03 63 address mapping from edge connector to dram 00 00 00 00 00 00 64 - 116reserved 000000000000 117dimm manufacturer?s id code lsb 858585858585 118dimm manufacturer?s id code msb 515151515151 119 module manufacturing location xx xx xx xx xx xx 120 - 121 module manufacturing date xx xx xx xx xx xx product type imsh1ge03a1f1ct08d imsh1ge03a1f1ct08e imsh1ge03a1f1ct10f imsh1ge03a1f1ct10g imsh1ge03a1f1ct13g imsh1ge03a1f1ct13h organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 36 03052008-r2g5-2fn2 122 - 125 module serial number xx xx xx xx xx xx 126 cyclical redundancy code lsb 08 07 9f fc 5b 4b 127 cyclical redundancy code msb 4e bf e6 13 69 f6 128 product type, char 1 49 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 48 132 product type, char 5 31 31 31 31 31 31 133 product type, char 6 47 47 47 47 47 47 134 product type, char 7 45 45 45 45 45 45 135 product type, char 8 30 30 30 30 30 30 136 product type, char 9 33 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 43 142 product type, char 15 54 54 54 54 54 54 143 product type, char 16 30 30 31 31 31 31 144 product type, char 17 38 38 30 30 33 33 145 product type, char 18 44 45 46 47 47 48 146 module revision code, lsb 2x 2x 2x 2x 2x 2x 147 module revision code, msb xx xx xx xx xx xx product type imsh1ge03a1f1ct08d imsh1ge03a1f1ct08e imsh1ge03a1f1ct10f imsh1ge03a1f1ct10g imsh1ge03a1f1ct13g imsh1ge03a1f1ct13h organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 37 03052008-r2g5-2fn2 148 dram manufacturer?s id code, lsb 85 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 00 176 - 255 blank for customer use 000000000000 product type imsh1ge03a1f1ct08d imsh1ge03a1f1ct08e imsh1ge03a1f1ct10f imsh1ge03a1f1ct10g imsh1ge03a1f1ct13g imsh1ge03a1f1ct13h organization 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 1 gbyte 72 72 72 72 72 72 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) 1 rank ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 38 03052008-r2g5-2fn2 table 21 spd codes for imsh2ge13a1f1ct product type imsh2ge13a1f1ct08d imsh2ge13a1f1ct08e imsh2ge13a1f1ct10f imsh2ge13a1f1ct10g imsh2ge13a1f1ct13g imsh2ge13a1f1ct13h organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex 0 # of spd bytes utilized / # of bytes in spd / crc 92 92 92 92 92 92 1 spd revision 10 10 10 10 10 10 2 sdram technology key byte 0b 0b 0b 0b 0b 0b 3 dimm module type 02 02 02 02 02 02 4 sdram density and banks 02 02 02 02 02 02 5 sdram addressing 11 11 11 11 11 11 6 module physical attributes 00 00 00 00 00 00 7 module organization 09 09 09 09 09 09 8 module memory bus width 0b 0b 0b 0b 0b 0b 9 fine time base (ftb) dividend and divisor 52 52 52 52 52 52 10 medium time base (mtb) dividend 01 01 01 01 01 01 11medium time base (mtb) divisor 080808080808 12 minimum sdram cycle time ( t ck.min ) 14140f0f0c0c 13 reserved 00 00 00 00 00 00 14 cas latencies supported - lsb 06 04 1c 14 7e 7c 15 cas latencies supported - msb 00 00 00 00 00 00 16 minimum cas latency time (t ck.min ) 647869786069 17 minimum write recovery time (t wr.min ) 787878787878 18 minimum ras# tocas# delay time (t rcd.min ) 647869786069 19 minimum row active to row active delay time (t rrd.min ) 50 50 3c 3c 30 30
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 39 03052008-r2g5-2fn2 20 minimum row prechargetime (t rp.min ) 647869786069 21 upper nibbles fo r t ras and t rc 11 11 11 11 11 11 22 minimum active to precharge time (t ras.min ), lsb2c2c2c2c20 20 23 minimum active to active/refresh time (t rc.min ), lsb90a495a4808c 24 minimum refresh recovery time (t rfc.min ), lsb707070707070 25 minimum refresh recovery time (t rfc.min ), msb030303030303 26 minimum internal write to read command delay time (t wtr.min ) 3c 3c 3c 3c 3c 3c 27 minimum internal read to precharge command delay time (t rtp.min ), msb 3c 3c 3c 3c 3c 3c 28 upper nibble for t faw 01 01 01 01 00 00 29 minimum four activate window delay time (t faw.min )40402c2cf0f0 30sdram output drivers supported 020202020202 31 sdram refresh options 81 81 81 81 81 81 32 - 59 reserved 00 00 00 00 00 00 60 module nominal height 10 10 10 10 10 10 61 module maximum thickness 11 11 11 11 11 11 62 raw card used 04 04 04 04 04 04 63 address mapping from edge connector to dram 01 01 01 01 01 01 64 - 116reserved 000000000000 117dimm manufacturer?s id code lsb 858585858585 118dimm manufacturer?s id code msb 515151515151 119 module manufacturing location xx xx xx xx xx xx product type imsh2ge13a1f1ct08d imsh2ge13a1f1ct08e imsh2ge13a1f1ct10f imsh2ge13a1f1ct10g imsh2ge13a1f1ct13g imsh2ge13a1f1ct13h organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 40 03052008-r2g5-2fn2 120 - 121 module manufacturing date xx xx xx xx xx xx 122 - 125 module serial number xx xx xx xx xx xx 126 cyclical redundancy code lsb cb c4 5c 3f 98 88 127 cyclical redundancy code msb 59 a8 f1 04 7e e1 128 product type, char 1 49 49 49 49 49 49 129 product type, char 2 4d 4d 4d 4d 4d 4d 130 product type, char 3 53 53 53 53 53 53 131 product type, char 4 48 48 48 48 48 48 132 product type, char 5 32 32 32 32 32 32 133 product type, char 6 47 47 47 47 47 47 134 product type, char 7 45 45 45 45 45 45 135 product type, char 8 31 31 31 31 31 31 136 product type, char 9 33 33 33 33 33 33 137 product type, char 10 41 41 41 41 41 41 138 product type, char 11 31 31 31 31 31 31 139 product type, char 12 46 46 46 46 46 46 140 product type, char 13 31 31 31 31 31 31 141 product type, char 14 43 43 43 43 43 43 142 product type, char 15 54 54 54 54 54 54 143 product type, char 16 30 30 31 31 31 31 144 product type, char 17 38 38 30 30 33 33 145 product type, char 18 44 45 46 47 47 48 product type imsh2ge13a1f1ct08d imsh2ge13a1f1ct08e imsh2ge13a1f1ct10f imsh2ge13a1f1ct10g imsh2ge13a1f1ct13g imsh2ge13a1f1ct13h organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 41 03052008-r2g5-2fn2 146 module revision code, lsb 2x 2x 2x 2x 2x 2x 147 module revision code, msb xx xx xx xx xx xx 148 dram manufacturer?s id code, lsb 85 85 85 85 85 85 149 dram manufacturer?s id code, msb 51 51 51 51 51 51 150 - 175 manufactures?s specific data 00 00 00 00 00 00 176 - 255 blank for customer use 000000000000 product type imsh2ge13a1f1ct08d imsh2ge13a1f1ct08e imsh2ge13a1f1ct10f imsh2ge13a1f1ct10g imsh2ge13a1f1ct13g imsh2ge13a1f1ct13h organization 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 2 gbyte 72 72 72 72 72 72 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) 2 ranks ( 8) label code pc3? 6400e? 5 pc3? 6400e? 6 pc3? 8500e? 7 pc3? 8500e? 8 pc3? 10600e ?8 pc3? 10600e ?9 jedec spd revision rev. 1.0 rev. 1. 0 rev. 1.0 rev. 1.0 rev. 1.0 rev. 1.0 byte# description hex hex hex hex hex hex
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 42 03052008-r2g5-2fn2 6 package outline diagrams figure 2 package outline lg-dim-240-061 r/c a note: sdram component outlines are symbolic representation of the device placement. for actual sdram outline details please refer to sdram component data sheet. %xuu pd[ doorzhg )32b/*',0bbbb 0$; ? ? ? 0,1 'hwdlo ri frqwdfwv ? ? ? ? ? ? ? ? ? 'udzlqj dffruglqj wr ,62 *hqhudo wrohudqfhv ? 'lphqvlrqv lq pp ? ?
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 43 03052008-r2g5-2fn2 figure 3 package outline lg-dim-240-062 r/c b note: sdram component outlines are symbolic representation of the device placement. for actual sdram outline details please refer to sdram component data sheet. )32b/*',0bbbb 0$; ? ? ? 0,1 'hwdlo ri frqwdfwv ? ? ? ? ? ? ? ? ? 'udzlqj dffruglqj wr ,62 *hqhudo wrohudqfhv ? 'lphqvlrqv lq pp ? ?
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 44 03052008-r2g5-2fn2 figure 4 package outline lg-dim-240-064 r/c d notes 1. option to place either combi device (spd with integrated thermal sensor) or only spd. 2. sdram component outlines are symbolic representation of t he device placement. for act ual sdram outline details please refer to sdram component data sheet. )32b/*',0bbbb 0$; ? ? ? 0,1 'hwdlo ri frqwdfwv ? ? ? ? ? ? ? ? ? 'udzlqj dffruglqj wr ,62 *hqhudo wrohudqfhv ? 'lphqvlrqv lq pp ? ?
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 45 03052008-r2g5-2fn2 figure 5 package outline lg-dim-240-065 r/c e notes 1. option to place either combi device (spd with integrated thermal sensor) or only spd. 2. sdram component outlines are symbolic representation of t he device placement. for act ual sdram outline details please refer to sdram component data sheet. )32b/*',0bbbb ? ? ? ? ? ? ? ? 0,1 'hwdlo ri frqwdfwv 'udzlqj dffruglqj wr ,62 *hqhudo wrohudqfhv ? 'lphqvlrqv lq pp ? ? ? ? ? ?
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 46 03052008-r2g5-2fn2 7 product type nomenclature for reference the applicable qimonda ddr3 dimm module nomenclature is listed in this chapter. table 22 example: ddr3 1gbyte unbuffered module table 23 ddr3 dimm nomenclature field number 1+2 3 4 5+6 7 8 9 10+11 12+13 14 15 16+17 18 qag part number im s h 1g u 0 3 a1 f1 c ?/t 08 e field description value coding 1+2 qimonda identifier im qimonda dimm modules 3 power or application s standard llow power 4 product family h ddr3 5+6 density 51 512 mbytes 1g 1024 mbytes 2g 2048 mbytes 4g 4096 mbytes 7 module type / ecc support u 240 pin unbuffered dimms - non-ecc e 240 pin unbuffered dimms - ecc s 204 pin small outline dimms - non-ecc r 240 pin registered dimms - ecc p 240 pin registered dimms with parity bit - ecc 8 number of ranks 0 one rank of sdrams 1 two ranks of sdrams 2 four ranks of sdrams 9 dram device number of ios 2 4 components (2 2 ) 3 8 components (2 3 ) 4 16 components (2 4 ) 10+11 die revision a1 first 12+13 package f1 planar fbga, lead- and halogen-free f2 dual die fbga, lead- and halogen-free 14 temperature range c commercial (0 c - 95 c) 15 rfu/thermal sensor ?/t reserved for future use/ modules with thermal sensor.
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 47 03052008-r2g5-2fn2 16+17 band width 08 pc3?6400, 6.4 gb/s, t ck = 2.5 ns, f ck =400 mhz 10 pc3?8500, 8.5 gb/s, t ck = 1.875 ns, f ck =533 mhz 13 pc3?10600, 10,66 gb/s, t ck = 1.5 ns, f ck =667 mhz 16 pc3?12800, 12,8 gb/s, t ck = 1.25 ns, f ck =800 mhz 18 latencies d cl?rcd?rp = 5?5?5 e cl?rcd?rp = 6?6?6 f cl?rcd?rp = 7?7?7 g cl?rcd?rp = 8?8?8 h cl?rcd?rp = 9?9?9 j cl?rcd?rp = 10?10?10 field description value coding
imsh[1g/2g][u/e]x3a1f1c(t) ddr3 unbuffered dimm advance internet data sheet rev. 0.63, 2008-08 48 03052008-r2g5-2fn2 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 speed bins and timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 speed bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 package outline diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7 product type nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
edition 2008-08 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein an d/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any ki nd, including without limitation warranties of non-infringement of in tellectual property righ ts of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com advance internet data sheet

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