revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 1 may 1999 document title 64k x16 bit super low power and low voltage full cmos static ram revision history revision no. 0.0 0.1 1.0 2.0 3.0 remark advance preliminary final final final history initial draft revise - erase 100ns part from km616fs1000 family - add 150ns part on km616fs1000 family - add 32-stsop1 new package - add high power version i sb1 =5.0 m a(max) - change v dr (min) 1.0 to 1.5v finalize - concept change high power version to low low power version i sb1 =5 .0m a(max) - change super low power version with special handling i sb1 =1.0 m a(max) - reduce icc & icc1 read : 15ma to 10ma write : 25ma to 20ma revise - change datasheet format - erase reverse type package revise - add 48- m bga type package draft date march 15, 1996 june 3, 1996 december 1, 1996 february 26, 1998 may 3, 1999 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices.
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 2 may 1999 64kx16 bit super low power and low voltage full cmos static ram general description the k6f1016v3m, k6f1016s3m and k6f1016r3m fami- lies are fabricated by samsung s advanced full cmos process technology. the families support various operating temperature ranges for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology: full cmos organization: 64kx16 bit power supply voltage k6f1016v3m family: 3.0v~3.6v k6f1016s3m family: 2.3v~3.3v k6f1016r3m family: 1.8v~2.7v low data retention voltage: 1.5v(min) three state output status and ttl compatible package type: 44-tsop2-400f, 48- m bga-6.00x8.00 pin description name function name function cs chip select input lb lower byte(i/o 1 ~ 8 ) oe output enable input ub upper byte(i/o 9 ~ 16 ) we write enable input vcc power a 0 ~a 15 address inputs vss ground i/o 1 ~i/o 16 data inputs/outputs n.c. no connection product family 1. the parameter is measured with 30pf test load. 2. super low power product=1 m a with special handling. 3. availiable parts are 100ns@v cc =3.0 0.3v, 150ns@v cc =2.5 0.2v and 300ns@v cc =2.0 0.2v with 30pf test load. product family operating temperature vcc range speed(ns) power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6f1016v3m-c commercial(0~70 c) 3.0~3.6v 70 1) /85@v cc =3.3 0.3v 5 m a 2) 80ma 44-tsop2 forward k6f1016s3m-c 2.3~3.3v 70 1) /85@v cc =3.0 0.3v 80ma 120 1) /150@v cc =2.5 0.2v 50ma k6f1016r3m-c 1.8~2.7v 300 1) @v cc =2.0 0.2v 20ma k6f1016v3m-i industrial(-40~85 c) 3.0~3.6v 70 1) /85@v cc =3.3 0.3v 80ma k6f1016s3m-i 2.3~3.3v 70 1) /85@v cc =3.0 0.3v 80ma 44-tsop2 forward 48- m bga 3) 120 1) /150@v cc =2.5 0.2v 50ma k6f1016r3m-i 1.8~2.7v 300 1) @v cc =2.0 0.2v 20ma functional block diagram a4 a3 a2 a1 a0 cs i/oi i/o2 i/o3 i/o4 vcc vss i/o5 i/o6 i/o7 i/o8 we a15 a14 a13 a12 n.c a5 a6 a7 oe ub lb i/o16 i/o15 i/o14 i/o13 vss vcc i/o12 i/o11 i/o10 i/o9 n.c a8 a9 a10 a11 n.c 44-tsop2 forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 samsung electronics co., ltd. reserves the right to change products and specifications without notice. precharge circuit. memory array 1024 rows 64 16 columns i/o circuit column select clk gen. row select a10 a13 a12 a11 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 we oe ub cs i/o 1 ~i/o 8 a15 data cont data cont data cont lb i/o 9 ~i/o 16 vcc vss a14 control logic lb oe a0 a1 a2 n.c i/o9 ub a3 a4 cs i/o1 i/o10 i/o11 a5 a6 i/o2 i/o3 vss i/o12 n.c a7 i/o4 vcc vcc i/o13 n.c n.c i/o5 vss i/o15 i/o14 a14 a15 i/o6 i/o7 i/o16 n.c a12 a13 we i/o8 n.c a8 a9 a10 a11 n.c 1 2 3 4 5 6 a b c d e f g h 48- m bga top view
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 3 may 1999 absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. 2. v in /v out =-0.2 to 3.9v for k6f1016v3m family. 3. v cc =-0.2 to 4.6v for k6f1016v3m family. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.2 to 3.6v 2) v - voltage on vcc supply relative to vss v cc -0.2 to 4.0v 3) v - power dissipation p d 1.0 w - storage temperature t stg -55 to 150 c - operating temperature t a 0 to 70 c k6f1016v3m-c , k6f1016s3m-c , k6f1016r3m-c -40 to 85 c k6f1016v3m- i, k6f1016s3m- i, k6f1016r3m- i soldering temperature and time t solder 260 c, 5sec(lead only) - - product list commercial temperature products(0~70 c) industrial temperature products(-40~85 c) part name function part name function k6f1016v3m-tb70 k6f1016v3m-tb85 k6f1016s3m-tb12 k6f1016s3m-tb15 k6f1016r3m-tb30 44-tsop2 f, 70ns, 3.3v, ll 44-tsop2 f, 85ns, 3.3v, ll 44-tsop2 f, 120/70ns, 2.5/3.0v, ll 44-tsop2 f, 150/85ns, 2.5/3.0v, ll 44-tsop2 f, 300ns, 2.0/2.5v, ll k6f1016v3m-tf70 k6f1016v3m-tf85 k6f1016s3m-tf12 k6f1016s3m-tf15 K6F1016S3M-ZF15 k6f1016r3m-tf30 k6f1016r3m-zf30 44-tsop2 f, 70ns, 3.3v, ll 44-tsop2 f, 85ns, 3.3v, ll 44-tsop2 f, 120/70ns, 2.5/3.0v, ll 44-tsop2 f, 150/85ns, 2.5/3.0v, ll 48- m bga, 2.5v/3.0v, 150/100ns 44-tsop2 f, 300ns, 2.0/2.5v, ll 48- m bga, 1.8v/2.5v, 300ns functional description 1. x means don t care. (must be in low or high state) cs oe we lb ub i/o 1~8 i/o 9~16 mode power h x 1) x 1) x 1) x 1) high-z high-z deselected standby l h h x 1) x 1) high-z high-z output disabled active l x 1) x 1) h h high-z high-z output disabled active l l h l h dout high-z lower byte read active l l h h l high-z dout upper byte read active l l h l l dout dout word read active l x 1) l l h din high-z lower byte write active l x 1) l h l high-z din upper byte write active l x 1) l l l din din word write active
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 4 may 1999 recommended dc operating conditions 1) note 1 commercial product : t a =0 to 70 c, unless otherwise specified industrial product : t a =-40 to 85 c, unless otherwise specified 2. overshoot : vcc + 1.0v in case of pulse width 20ns 3. undershoot : -1.0v in case of pulse width 20ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc k6f1016v3m family 3.0 3.3 3.6 v k6f1016s3m family 2.3 2.5/3.0 3.3 k6f1016r3m family 1.8 2.0/2.5 2.7 ground vss all family 0 0 0 v input high voltage v ih k6f1016v3m family vcc=3.3 0.3v 2.2 - vcc+0.2 2) v k6f1016s3m family vcc=3.0 0.3v 2.2 vcc=2.5 0.2v 2.0 k6f1016r3m family vcc=2.5 0.2v 2.0 vcc=2.0 0.2v 1.6 input low voltage v il all family -0.2 3) - 0.4 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics 1. super low power product=1 m a with special handling. item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs =v il , v in =v il or v ih , read - - 2 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma, cs 0.2v, v in 0.2v or v in 3 v cc -0.2v read - - 5 ma write - - 20 i cc2 cycle time=min, 100% duty, i io =0ma, cs =v il , v in =v il or v ih vcc=3.3v@70ns - - 65 ma vcc=2.7v@120ns - - 55 vcc=2.2v@300ns - - 20 output low voltage v ol i ol 2.1ma at vcc=3.0/3.3v - - 0.4 v 0.5ma at vcc=2.5v 0.33ma at vcc=2.0v output high voltage v oh i oh -1.0ma at vcc=3.0/3.3v 2.4 - - v -0.5ma at vcc=2.5v 2.0 - - -0.44ma at vcc=2.0v 1.6 - - standby current(ttl) i sb cs =v ih , other inputs=v il or v ih - - 0.3 ma standby current(cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc - - 5 1) m a
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 5 may 1999 ac operating conditions test conditions (test load and test input/output reference) input pulse level: 0.4 to 2.2v for vcc=3.3v, 3.0v, 2.5v 0.4 to 1.8v for vcc=2.0v input rising and falling time: 5ns input and output reference voltage: 1.5v for vcc=3.3v, 3.0v 1.1v for vcc=2.5v 0.9v for vcc=2.0v output load (see right):c l =100pf+1ttl c l =30pf+1ttl c l 1) 1. including scope and jig capacitance r 2 2) r 1 2) v tm 3) 2. r 1 =3070 w , r 2 =3150 w 3. v tm =2.8v for v cc =3.0/3.3v =2.3v for v cc =2.5v =1.8v for v cc =2.0v ac characteristics (commercial product:t a =0 to 70 c, industrial product: t a =-40 to 85 c k6f1016v3m family: vcc=3.0~3.6v, k6f1016s3m family: vcc=2.3~3.3v, k6f1016r3m family: vcc=1.8~2.7v) parameter list symbol speed bins units 70ns 85ns 100ns 120ns 150ns 300ns min max min max min max min max min max min max read read cycle time t rc 70 - 85 - 100 - 120 - 150 - 300 - ns address access time t aa - 70 - 85 - 100 - 120 - 150 - 300 ns chip select to output t co - 70 - 85 - 100 - 120 - 150 - 300 ns output enable to valid output t oe - 35 - 45 - 50 - 60 - 75 - 150 ns ub , lb access time t ba - 35 - 45 - 50 - 60 - 75 - 150 ns chip select to low-z output t lz 10 - 10 - 10 - 20 - 20 - 50 - ns output enable to low-z output t olz , t blz 5 - 5 - 5 - 20 - 20 - 30 - ns chip disable to high-z output t hz 0 25 0 25 0 30 0 35 0 40 0 60 ns output disable to high-z output t ohz , t bhz 0 25 0 25 0 30 0 35 0 40 0 60 ns output hold from address change t oh 10 - 15 - 15 - 15 - 15 - 30 - ns write write cycle time t wc 70 - 85 - 100 - 120 - 150 - 300 - ns chip select to end of write t cw 65 - 70 - 80 - 100 - 120 - 300 - ns address set-up time t as 0 - 0 - 0 - 0 - 0 - 0 - ns address valid to end of write t aw 65 - 70 - 80 - 100 - 120 - 300 - ns write pulse width t wp 55 - 60 - 70 - 80 - 100 - 200 - ns ub , lb valid to end of write t bw 65 - 70 - 80 - 100 - 120 - 300 - ns write recovery time t wr 0 - 0 - 0 - 0 - 0 - 0 - ns write to output high-z t whz 0 25 0 25 0 30 0 35 0 40 0 60 ns data to write time overlap t dw 30 - 35 - 40 - 50 - 60 - 120 - ns data hold from write time t dh 0 - 0 - 0 - 0 - 0 - 0 - ns end write to output low-z t ow 5 - 5 - 5 - 5 - 5 - 20 - ns data retention characteristics 1. super low power product=1 m a with special handling. item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 1.5 - 3.6 v data retention current i dr vcc=3.0v - - 5.0 1) m a data retention set-up time t sdr see data retention waveform 0 - - ns recovery time t rdr t rc - -
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 6 may 1999 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih , ub or/and lb =v il ) timing waveform of read cycle(2) ( we =v ih ) data valid high-z t rc cs address ub , lb oe data out t aa t rc t oh t oh t aa t co t ba t oe t olz t blz t lz t ohz t bhz t hz notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection.
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 7 may 1999 timing waveform of write cycle(1) ( we controlled) address cs data undefined ub , lb we data in data out timing waveform of write cycle(2) ( cs controlled) address cs data valid ub , lb we data in data out high-z high-z t wc t cw(2) t wr(4) t aw t bw t wp(1) t as(3) t dh t dw t whz t ow t wc t cw(2) t aw t bw t wp(1) t dh t dw t wr(4) high-z high-z data valid t as(3)
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 8 may 1999 address cs data valid ub , lb we data in data out high-z high-z timing waveform of write cycle(3) ( ub , lb controlled) notes (write cycle) 1. a wri t e occurs during the overlap(t wp ) of low cs and low we . a write begins when cs goes low and we goes low with asserting ub or lb for single byte operation or simultaneously asserting ub and lb for double byte operation. a write ends at the earliest transi- tion when cs goes high and we goes high. the t wp is measured from the beginning of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end or write to the address change. t wr applied in case a write ends as cs or we going high. t wc t cw(2) t bw t wp(1) t dh t dw t wr(4) t aw data retention wave form cs controlled v cc 3.0/2.7/2.3/1.8v 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr t as(3)
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 9 may 1999 44 pin thin small outline package type ii (400f) units: millimeters(inches) package dimensions 0.002 #1 0.05 #22 #44 #23 0.35 0.10 0.014 0.004 0.80 0.0315 min. 0.047 1.20 max. 0.741 18.81 max. 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0 . 1 0 - 0 . 0 5 0.50 + 0 . 0 0 4 - 0 . 0 0 2 0 . 1 5 0 . 0 0 6 0.020 1 0 . 1 6 0 . 4 0 0 0.10 0.004 0~8 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 ( ) 0.805 0.032 ( ) max 1.00 0.10 0.039 0.004
revision 3.0 cmos sram k6f1016v3m, k6f1016s3m, k6f1016r3m family 10 may 1999 units: millimeters package dimensions 6 5 4 3 2 1 a b c d e f g h c / 2 b/2 c b b1 c 1 ball #a1 b b/2 elastomer sram die c ball #a1 c / 2 bottom view top view d e 2 e 1 e c detail a side view 0 . 5 5 / t y p . 0 . 3 2 / t y p . 0 . 2 5 / t y p . a y elastomer 0.42/typ. die detail a notes. 1. bump counts: 48(8row x 6column) 2. bump pitch: (x,y)=(0.75 x 0.75)(typ.) 3. all tolerence are +/-0.050 unless otherwise specified. 4. typ: typical 5. y is coplanarity: 0.08(max) min typ max a - 0.75 - b 5.90 6.00 6.10 b1 - 3.75 - c 7.90 8.00 8010 c1 - 5.25 - d 0.30 0.35 0.40 e - 0.80 0.81 e1 - 0.55 - e2 - 0.25 - y - - 0.08 48 ball micro ball grid array- 0.75mm ball pitch
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