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hyb18h512321bf?11/12/14 hyb18h512321bf?08/10 512-mbit gddr3 graphics ram gddr3 graphics ram rohs compliant internet data sheet rev. 1.3 december 2007
internet data sheet hyb18h512321bf 512-mbit gddr3 qag_techdoc_rev411 / 3.31 qag / 2007-01-22 2 05292007-wau2-uu95 we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com hyb18h512321bf?11/12/14 hyb18h512321bf?08/10 revision history: 2007-12, rev. 1.3 page subjects (major chang es since last revision) 33 table 20, t wr for speed bins -8 and -10 changed from 14 to 13 34 table 20, t xsnr (self refresh exit followed by non-read command) added previous revision: rev. 1.2, 2007-11 all boundary scan deleted 32 table 20 f ck (min) for cl 10 to 7 changed from 400 to 350 mhz and note 1, 2 updated. previous revision: rev. 1.1, 2007-09 32 table 20 max. cl changed from 16 to 13 previous revision: rev. 1.0, 2007-05 32 table 20 - timing parameters for -8 updated
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 3 05292007-wau2-uu95 1overview this chapter lists all main features of the prod uct family hyb18h512321bf and the ordering information. 1.1 features ? 2.0 v v ddq io voltage hyb18h512321bf?08/10 ? 2.0 v v dd core voltage hyb18h512321bf?08/10 ? 1.8 v v ddq io voltage hyb18h512321bf?11/12/14 ? 1.8 v v dd core voltage hyb18h512321bf?11/12/14 ? organization: 2048k 32 8 banks ? 4096 rows and 512 columns (128 burst start locations) per bank ? differential clock inputs (clk and clk ) ? cas latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 ? write latencies of 3, 4, 5, 6, 7 ? burst sequence with length of 4, 8. ? 4n pre fetch ? short ras to cas timing for writes ? t ras lockout support ? t wr programmable for writes with auto-precharge ? data mask for write commands ? single ended read strobe (rdqs) per byte. rdqs edge- aligned with read data ? single ended write strobe (wdqs) per byte. wdqs center-aligned with write data ? dll aligns rdqs and dq transitions with clock ? programmable io interface including on chip termination (odt) ? autoprecharge option with co ncurrent auto precharge support ? 8k refresh (32ms) ? autorefresh and self refresh ? pg?tfbga?136 package (10mm 14mm) ? calibrated output drive. active termination support ? rohs compliant product 1) table 1 ordering information 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. part number 1) 1) hyb: designator for memory components 18h: v ddq = 1.8 v 512: 512-mbit density 32: organization b: product revision f: lead- and halogen-free organisation clock (mhz) package hyb18h512321bf?11/12/14 hyb18h512321bf?08/10 32 1200/1000/900/800 /700 pg?tfbga?136
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 4 05292007-wau2-uu95 1.2 description the qimonda 512-mbit gddr3 graphics ram is a high spe ed memory device, designed for high bandwidth intensive applications like pc graphics systems. the chip?s 8 bank architecture is optimized for high speed. hyb18h512321bf uses a double data rate interface and a 4 n -pre fetch architecture. the gddr3 interface transfers two 32 bit wide data words per clock cycle to/fro m the i/o pins. corresponding to the 4 n -pre fetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal me mory core and four corresponding 32 bit wide, one-half-clock - cycle data transfers at the i/o pins. single-ended unidirectional read and write data strobes are transmitted simultaneously with read and write data respectively in order to capture data properly at the receivers of both the graphics sdram and the controller . data strobes are organized per byte of the 32 bit wide interface. for read commands th e rdqs are edge-aligned with data, and the wdqs are center- aligned with data for write commands. the hyb18h512321bf operates from a differential clock (clk and clk ). commands (addresses and control signals) are registered at every positive edge of clk. input data is registered on both edges of wdqs, and output data is referenced to both edges of rdqs. in this document references to ?the positive edge of clk? impl y the crossing of the positive edge of clk and the negative edge of clk . similarly, the ?negative edge of clk? refers to the crossing of the negative e dge of clk and the positive edge of clk . references to rdqs are to be interpreted as any or all rdqs< 3:0>. wdqs, dm and dq should be interpreted in a similar fashion. read and write accesses to the hyb18h512 321bf are burst oriented. the burst length is fixed to 4 and 8 and the two least significant bits of the burst address are ?don?t care? and inte rnally set to low. accesses begin with the registration of an activate command, which is then followed by a read or write command. the address bits registered coincident with the activate command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the column location for the burst access. each of the 8 banks consists of 4096 row locations and 512 column locations. an auto precharge function can be combined with read and write to provide a self-timed row precha rge that is initiated at the end of the burst access. the pipe lined, multibank architecture of the hyb18h512321bf allows fo r concurrent operation, ther eby providing high effective bandwidth by hiding row precharge and activation time. the ?on die termination? interface (odt) is optimized for high fr equency digital data transfers and is internally controlled. t he termination resistor value can be set using an external zq re sistor or disabled through the extended mode register. the output driver impedance can be set using the extended mode register. it can either be set to zq / 6 (auto calibration) or to 35, 40 or 45 ohms. auto refresh and power down with self refresh operations are supported. an industrial standard pg?tfbga?136 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former ddr graphics sdram products.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 5 05292007-wau2-uu95 2 configuration figure 1 ballout 512-mbit gddr3 graphics ram [top view, mf = low ] cke v dd v ss ba0 ck a9 a11 dm2 dq24 dq25 v ssq dm0 dq4 dq6 dq5 dq17 v ref v ssq v ddq v ssq v ss a1 rfu a10 a7 a2 a5 v ss rdqs0 dq3 dq7 v ss 123 ba1 dq12 dq9 mf v dd 7 dm1 dq0 v ssq v ddq v ss v dd 8 v ddq v ddq dq8 dq11 dq15 dq13 9 456 101112 zq dq1 v ddq dq2 v ddq v ssq wdqs0 v ssq v ddq v ddq v dd v ss v ssq rfu v ddq v dd a0 a4 v dd dq27 a3 v ddq dq26 dm3 v ddq v ssq wdqs3 rdqs3 v ssq v ddq dq28 dq29 v ddq v ssq dq30 dq31 v ssq v ddq v dd v ss sen v ssq v ddq dq10 v ddq v ssq rdqs1 wdqs1 v ssq v ddq v ddq cas ras cs dq14 v dd we v ssq ba2 v ref v ddq ck v ss a6 a8/ap v dd v ssq v ss dq19 dq16 dq18 v ddq v ssq rdqs2 wdqs2 v ssq dq21 dq20 v ddq v ssq dq23 dq22 v ssq reset v ss v dd v ddq a b c d f g h j e l m k n p t v r
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 6 05292007-wau2-uu95 2.1 ball definition and description table 2 ball description ball type detailed function clk, clk input clock: clk and clk are differential clock inputs. address and command inputs are latched on the positive edge of clk. graphics sdram outputs (rdqs, dqs) are referenced to clk. clk and clk are not internally terminated. cke input clock enable: cke high activates and cke low deactivates t he internal clock and input buffers. taking cke low provides power down. if all banks are precha rged, this mode is called precharge power down and self refresh mode is entered if a auto refres h command is issued. if at least one bank is open, active power down mode is entered and no self refr esh is allowed. all input receivers except clk, clk and cke are disabled during power down. in self refresh mode the clock receivers are disabled too. self refresh exit is performed by setting cke asyn chronously high. exit of power down without self refresh is accomplished by setting cke high with a positive edge of clk. the value of cke is latched asynchronously by reset during power on to determine the value of the termination resistor of t he address and command inputs. cke is not allowed to go low duri ng a rd, a wr or a snoop burst. cs input chip select: cs enables the command decoder when low and dis ables it when high. when the command decoder is disabled, new commands with the exception of dterdis are ignored, but internal operations continue. cs is one of the four command balls. ras , cas , we input command inputs: sampled at the positive edge of clk, cas , ras , and we define (together with cs ) the command to be executed. dq<0:31> i/o data input/output: the dq signals form the 32 bit data bus. during reads the balls are outputs and during writes they are inputs. data is tr ansferred at both edges of rdqs. dm<0:3> input input data mask: the dm signals are input mask signals for write data. data is masked when dm is sampled high with the write data. dm is sampled on both edg es of wdqs. dm0 is for dq<0:7>, dm1 is for dq<8:15>, dm2 is for dq<16:23> and dm3 is for dq<24:31>. although dm balls are input-only, their loading is designed to match the dq and wdqs balls. rdqs<0:3> output read data strobes: rdqsx are unidirectional strobe signals. during reads the rdqsx are trans mitted by the graphics sdram and edge-aligned with data. rdqs have pream ble and postamble requirements. rdqs0 is for dq<0:7>, rdqs1 for dq<8:15>, rdqs2 for dq<16:23> and rdqs3 for dq<24:31>. wdqs<0:3> input write data strobes: wdqsx are unidirectional strobe signals. duri ng writes the wdqsx are generated by the controller and center aligned wit h data. wdqs have preamble and postamble requirements. wdqs0 is for dq<0:7>, wdqs1 for dq<8:15>, wdqs2 for dq<16:23> and wdqs3 for dq<24:31>.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 7 05292007-wau2-uu95 2.2 mirror function the gddr3 graphics ram provides a ball mirro ring feature that is enabl ed by applying a logic high on ball mf. this function allows for efficient routing in a clam shell configuration. depending of the logic state applied on mf, the command and address signals will be assigned to different balls. the default ball configuration (see figure 2 ) corresponds to mf = low. the dc level (high or low) must be applied on the mf pi n at power up and is not allowed to change after that. table 3 shows the ball assignment as a function of the logic state applied on mf. ba<0:2> input bank address inputs: ba select to which internal bank an activate, read, write or precharge command is being applied. ba are also used to distinguish between the mode register set and extended mode register set commands. a<0:11> input address inputs: during activate, a0-a11 defines the row addre ss. for read/write, a2-a7 and a9 defines the column address, and a8 defines the auto precha rge bit. if a8 is high, the accessed bank is precharged after execution of the column access. if a8 is low, auto precharge is disabled and the bank remains active. sampled with precharge, a8 determines whether one bank is precharged (selected by ba<0:2>, a8 low) or all 8 banks are precharged (a8 high). during (extended) mode register set the address inputs define the register settings. a<0:11> are sampled with the positive edge of clk. zq - odt impedance reference: the zq ball is used to control the odt impedance. reset input reset pin: the res pin is a v ddq cmos input. res is not internally te rminated. when res is at low state the chip goes into full reset. the chip stays in full reset until res goes to high state. the low to high transition of the res signal is used to latch the c ke value to set the value of the termination resistors of the address and command inputs. after exiting the fu ll reset a complete initialization is required since the full reset sets the internal settings to default. mf input mirror function pin: the mf pin is a v ddq cmos input. this pin must be hardwired on board either to a power or to a ground plane. with mf set to high, the command and address pins are reassigned in order to allow for an easier routing on board for a back to back memory arrangement. sen input enables boundary scan functionality: no boundary scan support. this pin should be connected to gnd. v ref supply voltage reference: v ref is the reference voltage input. v dd , v ss supply power supply: power and ground for the internal logic. v ddq , v ssq supply i/o power supply: isolated power and ground for the output buff ers to provide improved noise immunity. nc, rfu - please do not connect. reserved for future use balls. ball type detailed function
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 8 05292007-wau2-uu95 table 3 ball assignment with mirror mf logic state signal low high h3 h10 ras f4 f9 cas h9 h4 we f9 f4 cs h4 h9 cke k4 k9 a0 h2 h11 a1 k3 k10 a2 m4 m9 a3 k9 k4 a4 h11 h2 a5 k10 k3 a6 l9 l4 a7 k11 k2 a8 m9 m4 a9 k2 k11 a10 l4 l9 a11 g4 g9 ba0 g9 g4 ba1 h10 h3 ba2
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 9 05292007-wau2-uu95 2.3 truth tables 2.3.1 function truth table for more than one activated bank if there is more than one bank activated in the graphics sdram, some commands can be performed in parallel due to the chip?s multibank architecture. the following table defines for which commands such a scheme is possible. all other transitions are illegal. notes 1-11 define the start and end of the action s belonging to a submitted command. this table is based on the assumption that there are no other actions ongoing on bank n or bank m. if there are any actions ongoing on a third bank t rrd , t rtw and t wtr have to be taken always into account. table 4 function truth table i current state ongoing action on bank n possible action in parallel on bank m active activate 1) 1) action activate starts with issuing the command and ends after t rcd . act, pre, write, write/a, read, read/a 2) 2) during action activate an act command on another bank is allowed considering t rrd , a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. write 3) 3) action write starts with issuing the command and ends twr afte r the first pos. edge of clk following the last falling wdqs ed ge. act, pre, write, write/a, read, read/a 4) 4) during action write an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank must be separated by at least one nop from the ongoing write. rd or rd/a are not allowed before t wtr is met. write/a 5) 5) action write/a starts with issuing the command and ends twr afte r the first positive edge of clk following the last falling w dqs edge. act, pre, write, write/a, read 6) 6) during action write/a an act or a pre command on another bank is allowed any time. a new wr or wr/a command on another bank has to be separated by at least one nop from the ongoing command. rd is not allowed before or t wtr is met. rd/a is not allowed during an ongoing write/a action. read 7) 7) action read starts with issuing the command and ends with t he first positive edge of clk following the last falling edge of r dqs. act, pre, write, write/a, read, read/a 8) 8) during action read and read/a an act or a pre command on anot her bank is allowed any time. a new rd or rd/a command on another bank has to be separated by at least one nop from the ongoing command. a wr or wr/a command on another bank has to meet t rtw . read/a 9) 9) action read/a starts with issuing the command and ends with the first positive edge of clk following the last falling edge of rdqs. act, pre, write, wr ite/a, read, read/a 8) precharge 10) 10) action precharge and precharge all start with issuing the command and ends after t rp . act, pre, write, write/a, read, read/a 11) precharge all 10) - power down entry 12) - idle activate 1) act power down entry 12) - auto refresh 13) - self refresh entry 12) - mode register set (mrs) 14) - extended mrs 14) - power down power down exit 15) - self refresh self refresh exit 16) -
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 10 05292007-wau2-uu95 2.4 function truth table for cke table 5 function truth table ii (cke table) notes 1. cken is the logic step at clock edge n; cken-1 was the state of cke at the previous clock edge. 2. current state is the state of the gddr3 graphics ram immediately prior to clock edge n. 3. command is the command registered at clock edge n, and action is a result of command. 4. all states and sequences not shown are illegal or reserved. 5. desel or nop commands should be iss ued on any clock edges occurring during the t xsr period. a minimum of 1000 clock cycles is required before apply ing any other valid command. 11) during action active an act command on another banks is allowed considering t rrd . a pre command on another bank is allowed any time. wr, wr/a, rd and rd/a are always allowed. 12) during power down and self refresh only the exit commands are allowed. 13) auto refresh starts with issuing the command and ends after t rfc . 14) actions mode register set and extended mode register set start with issuing the command and ends after t mrd . 15) action power down exit starts with issuing the command and ends after t xpn . 16) action self refresh exit starts with issuing the command and ends after t xsc . cke n-1 cke n current state command action l l power down x stay in power down self refresh x stay in self refresh l h power down desel or nop exit power down self refresh desel or nop exit self refresh 5 h l all banks idle desel or nop entry precharge power down bank(s) active desel or nop entry active power down all banks idle auto refresh entry self refresh
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 11 05292007-wau2-uu95 3 functional description 3.1 mode register set command (mrs) figure 2 mode register set command the mode register stores the data for controlling the operation modes of the memory. it programs cas latency, test mode, dll reset , the value of the write latency and the burst length. the mode register must be written after power up to operate the sgram. during a moderegister set command the address inputs are sampled and stored in the mode register. the mode register content can only be set or changed when the chip is in idle state. for non-read commands following a mode register set a delay of t mrd must be met. the mode register bitmap is supported in two configurations. the first configuration is intended to support the mid-range- speed application. the second configuration supports higher clock cycles for cas latency and is therefore prepared to support high-speed application. the selected configuration is defined by bit0 of emrs2. clk# clk ras# cke cas# we# a0-a11 ba0 0 don't care cod: code to be loaded into the register cs# cod ba1, ba2 0
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hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 13 05292007-wau2-uu95 figure 4 mode register bitmap for high-speed application figure 5 mode register set timing *$, )* *$,
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hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 14 05292007-wau2-uu95 3.1.1 burst length read and write accesses to the gddr3 graphics ram are burst oriented with burst length of 4 and 8. this value must be programmed using the mode register set comm and (a0 .. a2). the burst length dete rmines the number of column locations that can be accessed for a given read or write command. when a read or write command is issued, a block of columns e qual to the burst length is effectively selected. all accesses for that burst take place within this block if a boundary is reached. the starting locati on within this block is determined by the two least significant bits a0 and a1 which are set internally to the fixed value of ze ro each.reserved states should not be use d, as unknown operation or incompatibility with future versions may result. 3.1.2 burst type accesses within a given bank must be programmed to be seq uential. this is done using the mode register set command (a3). this device does not support the burst interleave mode. table 6 burst definition the value applied at the balls a0 and a1 for the column address is ?don?t care?. 3.1.3 cas latency the cas latency is the delay, in clock cycl es, between the registra tion of a read command and the availability of the first bit of output data. if a read command is registered at clock edge n, and the latency is m clocks, the data will be av ailable nominally coincident with clock edge n+m. the two mode register setups support different cas latencie s in terms of clock cycles. the mid-range-speed mode register supports latencies from 7 to 14. the high-speed mode register supports latencies from 10 to 17. the active mode register setup is selected by bit0 of emrs2. 3.1.4 write latency the write latency, wl, is the delay, in clock cycles, between the registration of a wr ite command and the av ailability of the first bit of input data. burst length starting column address order of accesses within a burst (type = sequential) a2 a1 a0 4 ? x x 0-1-2-3 8 0 x x 0-1-2-3-4-5-6-7 1 x x 4-5-6-7-0-1-2-3
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 15 05292007-wau2-uu95 table 7 on/off mode of dq/dm receivers the on/off state of the dq/dm receivers depends on the write latency. the dependence is given in table 7 . 3.1.5 test mode the normal operating mode is selected by issuing a mode regi ster set command with bit a7 set to zero and bits a0-a6 and a8-a11 set to the desired value. 3.1.6 dll reset the normal operating mode is selected by issuing a mode regi ster set command with bit a8 set to zero and bits a0-a7 and a9-a11 set to the desired values. a dll reset is initiated by i ssuing a mode register set command with bit a8 set to one and bits a0-a7 and a9-a11 set to the desired values. the gddr3 graphics ram returns automatically in the normal mode of operations once the dll reset is completed. wl dq/dm-receivers 3-4 receivers are always on 5-6-7 receivers are off and will be switched on by write command and will be switched off again after wl+bl
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 16 05292007-wau2-uu95 3.2 extended mode register set command (emrs1) figure 6 extended mode register set command the extended mode register is us ed to set the output driver impedance value, the terminatio n impedance value, the write recovery time value for write with autoprecharge. it is used as well to enable/disable the dll, to issue the vendor id and to enable/disable the low power mode. there is no default value for the extended mode register. therefore it must be written after power up to operate the gddr3 graphics ram. the extended mode register can be programmed by performing a normal mode register set operation and setting the ba0 bit to high and ba1,ba2 bits to low. all other bits of the emr register are rese rved and should be set to low. the extended mode register must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation ( figure 9 ). the timing of the emrs command operation is equivalent to the timing of the mrs command operation. clk# clk ras# cke cas# we# a0-a11 ba0 1 don't care cod: code to be loaded into the register cs# cod ba1, ba2 0
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 17 05292007-wau2-uu95 figure 7 extended mode register bitmap for mid-range-speed application there are two bitmaps for the extended mode register. one bitmap shown in figure 7 is supposed to support mid-speed applications. the other bitmap shown in figure 8 is more focused on the high-range-speed application. both bitmaps distinguish different numbers in supported write recovery cl ock cycles. the mid-range bit map provides wr cycles from 4 to 11.the high-speed bitmap supports wr from 7 to 13. figure 8 extended mode register bitmap for high-speed application data z ba1 ba0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 01 a11 a10 dll v rfu wr rtt a2 0 1 a3 0 0 0 1 1 1 odt disabled rfu termination zq / 4 zq / 2 (default) 2) 1 output driver impedance autocal 35 0 40 45 1 a0 a1 1 1 0 0 0 1 wr 11 4 05 6 1 a4 a5 1 1 0 0 0 a10 0 1 vendor id on off a6 0 1 dll enable enable disable a7 0 0 0 0 07 10 0 1 wr ba2 0 18 0 1 09 1 1 1 1 1 0 -
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hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 18 05292007-wau2-uu95 notes 1. these settings are for debugging purposes only. 2. default termination values at power up. 3. the odt disable function disables all terminators on the device. 4. if the user activates bits in the extended mode register in an optional field, either the optional field is activated (if option implemented in the device) or no action is taken by the device (if option not implemented). 5. wr (write recovery time for auto precharge) in clock cycles is calculated by dividing t wr (in ns) and rounding up to the next integer (wr[cycles] = t wr [ns] / t ck [ns]). the mode register must be programmed to this value. figure 9 extended mode register set timing 3.2.1 dll enable the dll must be enabled for normal operation. dll enable is r equired during power-up initialization and upon returning to normal operation after having disabled the dll. (when the device exits self-refresh mode, the dll is enabled automatically). anytime the dll is enabled, 1000 cycles must occur before a read command can be issued. 3.2.2 wr the wr parameter is programmed using the register bits a4, a5 and a7. this integer parameter defines as a number of clock cycles the write recovery time in a write with autoprecharge operation. the following inequality has to be complied with: wr * t ck t wr , where t ck is the clock cycle time. the high-speed bitmap supports wr from 7 to 13. the mid-range bitmap provides wr cycles from 4 to 11. 3.2.3 termination rtt the data termination, rtt, is used to set the value of the inte rnal termination resistors. t he gddr3 dram supports zq / 4 and zq / 2 termination values. the termination may also be disabled for testing and other purposes. 3.2.4 output driver impedance the output driver impedance extended mode register is used to set the value of th e data output driver impedance. when the auto calibration is used, the output driver impedance is set nominally to zq / 6. if the output driver impendanc e is changed to 30, 40 or 45 ohms the user needs to issue 16 aref commands separated by t rfc consecutively to make the change effective. the user must be aware that the command bus needs to be stable for a time of t ko after each aref. clk# clk don't care pa emrs nop a.c. nop t rp t mrd command emrs: extended mrs command pa: preall command a.c.: any command nop
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 19 05292007-wau2-uu95 3.2.5 vendor code and revision identification the manufacturer vendor code is selected by issuing an ex tended mode register set command with bit a10 set to 1 and bits a0-a9 and a11 set to the desired value. when the vendor code function is enabled the gddr3 dram will provide the qimonda vendor code on dq[3:0] and the re vision identification on dq[7:4]. the c ode will be driven onto the dq bus after tridon following the emrs command that sets a10 to 1. the vendor code and revision id will be driven on dq[7:0] until a new emrs command is issued with a10 set back to 0. after t rdoff following the second emrs comm and, the data bus is driven back to high. this second emrs command must be issued before initiating any subsequent operation. violating this requirement will result in unspecified operation. table 8 revision id and vendor code note: please refer to revision release note for revision id value. figure 10 timing of vendor code and revision id generation on dq[7:0] revision identification qimonda vendor code dq[7:4] dq[3:0] 0011 0010 clk# clk n/d n/d com. n/d n/d n/d n/d 01234567 8 add a[9:0], a11 9 10 n/d n/d rdqs dq[7:0] a10 n/d add emrs emrs t ridon vendor code and revision id t ridoff emrs: extended mode register set command add: address don't care n/d: nop or deselect
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 20 05292007-wau2-uu95 3.3 extended mode register 2 set command (emrs2) figure 11 extended mode register 2 set command the extended mode register 2 is used to define the active bitmap of the mode register and the extended mode register. the extended mode register 2 must be written after power up to operate the gddr3 graphics ram. it can be programmed by performing a normal mode register set operation and setting the ba1 bit to high and ba0, ba2 bits to low. all bits defined as rfu in the bitmap are reserved and must be set to low. the extended mode register 2 must be loaded when all banks are idle and no burst are in progress. the controller must wait the specified time t mrd before initiating any subsequent operation. the timing of the emrs2 command operation is equivalent to the timing of the mrs command operation. figure 12 extended mode register 2 bitmap 3.3.1 app mode the gddr3 graphics ram provides two bitmaps for the mode r egister and the extended mode register respectively. the bitmaps are shown in the mrs and emrs chapters. the bit0 of the extended mode regsiter 2 defines which one of the two bitmaps is active. bit0 set to low enables the mid- range bitmap and bit0 set to high enables the high-speed bitmap. clk# clk ras# cke cas# we# a0-a11 ba1 1 don't care cod: code to be loaded into the register cs# cod ba0,2 0

hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 21 05292007-wau2-uu95 4 electrical characteristics 4.1 absolute maximum ratings and operation conditions table 9 absolute maximum ratings attention: stresses above the max. value s listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 4.2 dc operation conditions 4.2.1 recommended power & dc operation conditions table 10 power & dc operation conditions (0 c t c 85 c) parameter symbol rating unit min. max. power supply voltage v dd -0.5 2.5 v power supply voltage for output buffer v ddq -0.5 2.5 v input voltage v in -0.5 2.5 v output voltage v out -0.5 2.5 v storage temperature t stg -55 +150 c junction temperature t j ?+125 c short circuit output current i out ?50ma parameter symbol limit values unit note min. typ. max. power supply voltage v dd , v dda 1.92.02.1v 1)2) power supply voltage for i/o buffer v ddq 1.92.02.1v 1)2)
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 22 05292007-wau2-uu95 4.3 dc & ac logic input levels table 11 dc & ac logic input levels (0 c t c 85 c) power supply voltage v dd , v dda 1.71.81.9v 1)3) power supply voltage for i/o buffer v ddq 1.71.81.9v 1)3) reference voltage v ref 0.69* v ddq ?0.71* v ddq v 4) output low voltage v ol(dc) ??0.8v input leakage current i il ?5.0 ? +5.0 ? 5) clk input leakage current i ilc ?5.0 ? +5.0 ? output leakage current i ol ?5.0 ? +5.0 ? 5) 1) v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. 2) hyb18h512321bf?08/10 3) hyb18h512321bf?11/12/14 4) v ref is expected to equal 70% of v ddq for the transmitting device and to tr ack variations in the dc level of the same. peak-to-peak noise on v ref may not exceed 2% v ref (dc). thus, from 70% of v ddq , v ref is allowed 19mv for dc error and an additional 27mv for ac noise. 5) i il and i ol are measured with odt disabled. parameter symbol limit values unit note min. max. input logic high voltage, dc v ih (dc) v ref + 0.15 ? v 1) 1) the dc values define where the input slew rate requirements ar e imposed, and the input signal mu st not violate these levels i n order to maintain a valid level. input logic low voltage, dc v il (dc) ? v ref -0.15 v 1) input logic high voltage, ac v ih (ac) v ref + 0.25 ? v 2)3) 2) input slew rate = 3 v/ns. if the input slew rate is less than 3 v/ns, input timing may be compromised. all slew rates are measu red between v il (dc) and v ih (dc). 3) v ih overshoot: v ih (max) = v ddq +0.5v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. v il undershoot: v il (min) = 0 v for a pulse width 500ps and the pulse width cannot be greater than 1/3 of the cycle rate. input logic low voltage, ac v il (ac) ? v ref - 0.25 v 2)3) input logic high, dc, reset pin v ihr (dc) 0.65 v ddq v ddq + 0.3 v input logic low, dc, reset pin v ilr (dc) -0.3 0.35 v ddq v input logic high, dc, mf pin v ihmf (dc) v dd v dd + 0.3 v 4) 4) the mf pin must be hard-wired on board to either v dd or v ss . input logic low,dc, mf pin v ilmf (dc) ?0.3 0 v parameter symbol limit values unit note min. typ. max.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 23 05292007-wau2-uu95 4.4 differential clock dc and ac levels table 12 differential clock dc and ac input conditions (0 c t c 85 c) 4.5 output test conditions figure 13 output test circuit parameter symbol limit values unit note min. max. clock input mid-point voltage, clk and clk v mp(dc) 0.7 v ddq ? 0.10 0.7 v ddq + 0.10 v 1) 1) all voltages referenced to v ss. clock input voltage level, clk and clk v in(dc) 0.42 v ddq + 0.3 v 1) clock dc input differential voltage, clk and clk v id(dc) 0.3 v ddq v 1) clock ac input differential voltage, clk and clk v id(ac) 0.5 v ddq + 0.5 v 1)2) 2) v id is the magnitude of the difference between the input level on clk and the input level on clk . ac differential crossing point input voltage v ix(ac) 0.7 v ddq ? 0.15 0.7 v ddq + 0.15 v 1)3) 3) the value of v ix is expected to equal 0.7 v ddq of the transmitting device and must track variations in the dc level of the same. dq 60 ohm test point dqs v ddq
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 24 05292007-wau2-uu95 4.6 pin capacitances table 13 pin capacitances (vddq = 1.8 v, ta = 25c, f = 1 mhz) 4.7 driver current characteristics 4.7.1 driver iv characteristics at 40 ohms figure 14 represents the driver pull-down and pull-up iv charac teristics under process, volt age and temperature best and worst case conditions. the actual driver pull-down and pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal driver output impedance to 40 . figure 14 40 ohm driver pull-down and pull-up characteristics table 14 lists the numerical values of the mi nimum and maximum allowed values of t he output driver pull-down and pull-up iv characteristics. parameter symbol min. max. unit note input capacitance: a0-a11, , ba0-2, cke, cs , cas , ra s, we , cke, res,clk,clk ci,cck 1.0 2.5 pf input capacitance: dq0-dq31, rdqs0-rdqs3, wdqs0-wdqs3, dm0-dm3 cio 2.0 3.0 pf 9rxw9 3xoo'rzq&kdudfwhuvwlfv ,rxwp$ 3xoo8s&kdudfwhuvwlfv 9''49rxw9 ,rxwp$
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 25 05292007-wau2-uu95 table 14 programmed driver iv characteristics at 40 ohm 4.7.2 termination iv characteristic at 60 ohms figure 15 represents the dq termination pull-up iv characteristic u nder process, voltage and temperature best and worst case conditions. the actual dq termination pull-up current must li e between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal dq termination impedance to 60 . (extended mode register programmed to zq/4). voltage (v) pull-down current (ma) pull-up current (ma) minimum maximum m inimum maximum 0.1 2.32 3.04 -2.44 -3.27 0.2 4.56 5.98 -4.79 -6.42 0.3 6.69 8.82 -7.03 -9.45 0.4 8.74 11.56 -9.18 -12.37 0.5 10.70 14.19 -11.23 -15.17 0.6 12.56 16.72 -13.17 -17.83 0.7 14.34 19.14 -15.01 -20.37 0.8 16.01 21.44 -16.74 -22.78 0.9 17.61 23.61 -18.37 -25.04 1.0 19.11 26.10 -19.90 -27.17 1.1 20.53 28.45 .21.34 -29.17 1.2 21.92 30.45 -22.72 -31.25 1.3 23.29 32.73 -24.07 -33.00 1.4 24.65 34.95 -25.40 -35.00 1.5 26.00 37.10 -26.73 -37.00 1.6 27.35 39.15 -28.06 -39.14 1.7 28.70 41.01 -29.37 -41.25 1.8 30.08 42.53 -30.66 -43.29 1.9 ? 43.71 ? -45.23 2.0 ? 44.89 ? -47.07
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 26 05292007-wau2-uu95 figure 15 60 ohm active termination characteristic table 15 lists the numerical values of the minimum and maximum allowed valu es of the output dr iver termination iv characteristic. table 15 programmed terminator char acteristics at 60 ohm voltage (v) terminator pull-u p current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 0.1 -1.63 -2.18 1.1 -14.23 -19.45 0.2 -3.19 -4.28 1.2 -15.14 -20.83 0.3 -4.69 -6.30 1.3 -16.04 -22.00 0.4 -6.12 -8.25 1.4 -16.94 -23.33 0.5 -7.49 -10.11 1.5 -17.82 -24.67 0.6 -8.78 -11.89 1.6 -18.70 -26.09 0.7 -10.01 -13.58 1.7 -19.58 -27.50 0.8 -11.16 -15.19 1.8 -20.44 -28.86 0.9 -12.25 -16.69 1.9 ? -30.15 1.0 -13.27 -18.11 2.0 ? -31.38 2kp7huplqdwlrq&kdudfwhuvwlfv 9''49rxw9 ,rxwp$
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 27 05292007-wau2-uu95 4.8 termination iv characteristic at 120 ohms figure 16 represents the dq or add/cmd termination pull-up iv ch aracteristic under process, voltage and temperature best and worst case conditions. the actual termination pull-up current must lie between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal termination impedance to 120 . (extended mode register programmed to zq/2 for dq terminations or cke = 0 at the r es transition during power-up for add/cmd terminations). figure 16 120 ohm active termination characteristic table 16 lists the numerical values of the minimum and maximum allowed values of the termination iv characteristic. table 16 programmed terminator characteristics of 120 ohm voltage (v) terminator pull-u p current (ma) voltage (v) terminator pull-up current (ma) minimum maximum minimum maximum 0.1 -0.81 -1.09 1.1 -7.11 -9.72 0.2 -1.60 -2.14 1.2 -7.57 -10.42 0.3 -2.34 -3.15 1.3 -8.02 -11.00 0.4 -3.06 -4.12 1.4 -8.47 -11.67 0.5 -3.74 -5.06 1.5 -8.91 -12.33 0.6 -4.39 -5.94 1.6 -9.35 -13.05 0.7 -5.00 -6.79 1.7 -9.79 -13.75 0.8 -5.58 -7.59 1.8 -10.22 -14.43 0.9 -6.12 -8.35 1.9 ? -15.08 1.0 -6.63 -9.06 2.0 ? -15.69 2kp7huplqdwlrq&kdudfwhuvwlfv 9''49rxw9 ,rxwp$
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 28 05292007-wau2-uu95 4.9 termination iv characteristic at 240 ohms figure 17 represents the add/cmd termination pull-up iv characteri stic under process, voltage and temperature best and worst case conditions. the actual add/cmd termination pull- up current must lie between these two bounding curves. the value of the external zq resistor is 240 , setting the nominal termination impedance to 240 . (cke = 1at the res transition during power-up for add/cmd terminations). figure 17 240 ohm active termination characteristic table 17 lists the numerical values of the minimum and ma ximum allowed values of the add/cmd termination iv characteristic. table 17 programmed terminator characteristics at 240 ohm voltage (v) terminator pull-u p current (ma) voltage (v) te rminator pull-up current (ma) minimum maximum minimum maximum 0.1 -0.41 -0.55 1.1 -3.56 -4.86 0.2 -0.80 -1.07 1.2 -3.79 -5.21 0.3 -1.17 -1.58 1.3 -4.01 -5.50 0.4 -1.53 -2.06 1.4 -4.23 -5.83 0.5 -1.87 -2.53 1.5 -4.46 -6.17 0.6 -2.20 -2.97 1.6 -4.68 -6.52 0.7 -2.50 -3.40 1.7 -4.90 -6.88 0.8 -2.79 -3.80 1.8 -5.11 -7.21 0.9 -3.06 -4.17 1.9 ? -7.54 1.0 -3.32 -4.53 2.0 ? -7.85 2kp7huplqdwlrq&kdudfwhuvwlfv 9''49rxw9 ,rxwp$
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 29 05292007-wau2-uu95 4.10 operating currents 4.10.1 operating current ratings for hyb18h512321bf table 18 operating current ratings ( 0 c t c 85 c) parameter symbol values unit note -8 ?10 ?11 ?12 ?14 typ typ. typ. typ. typ. operating current i dd0 630 580 535 500 435 ma 1)2)3) 1) idd specifications are tested afte r the device is properly initialized. 2) input slew rate = 3 v/ns. 3) measured with output open and on die termination off. operating current i dd1 705 650 600 540 415 ma 1)2)3) precharge power-down standby current i dd2p 415 380 350 315 235 ma 1)2)3) precharge floating standby current i dd2f 470 440 410 380 310 ma 1)2)3) precharge quiet standby current i dd2q 505 450 400 350 275 ma 1)2)3) active power-down standy current i dd3p 410 380 350 320 235 ma 1)2)3) active standby current i dd3n 585 540 500 460 395 ma 1)2)3) operating current burst read i dd4r 885 810 740 670 575 ma 1)2)3) operating current burst write i dd4w 890 800 720 660 565 ma 1)2)3) auto-refresh current (t rc =min(t rfc )) i dd5b 740 700 660 620 535 ma 1)2)3) auto-refresh current at t refi i dd5d 520 475 435 400 350 ma 1)2)3) self refresh current i dd6 88888ma 1)2)3)4) 4) enables on-chip refresh and address counter. operating current i dd7 920 860 800 740 680 ma 1)2)3)
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 30 05292007-wau2-uu95 4.11 operating current measurement conditions table 19 operating current measurement conditions symbol parameter/condition i dd0 operating current - one bank, activate - precharge t ck =min( t ck ), t rc =min( t rc ) databus inputs are switchi ng; address and control inputs are switching, cs = high between valid commands. i dd1 operating current - one bank, activate - read - precharge one bank is accessed with t ck =min( t ck ), t rc =min( t rc ), cl = cl(min), address and control inputs are switching; cs = high between valid commands. i out =0 ma i dd2p precharge power-down standby current all banks idle, power-down mode, cke is low, t ck =min( t ck ), data bus inputs are stable (high). i dd2f precharge floating standby current all banks idle; cs is high, cke is high, t ck =min( t ck ); address and control inputs are switching; data bus input are stable (high). i dd2q precharge quiet standby current cs is high, all banks idle, cke is high, t ck =min( t ck ), address and other control inputs stable (high), data bus inputs are stable (high). i dd3p active power-down standby current one bank active, cke is low, address and control inputs are stable (high); data bus inputs are stable (high); standard active power-down mode. i dd3n active standby current one bank active, cs is high, cke is high, t ras = t ras,max , t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd4r operating current - burst read one bank active; continuous read bursts, cl = cl(min); t ck =min( t ck ); t ras = t ras,max ; address and control inputs are switching; iout = 0 ma. i dd4w operating current - burst write one bank active; continuous write bursts; t ck =min( t ck ); address and control inputs are switching; data bus inputs are switching. i dd5b burst auto refresh current refresh command at t rfc =min(t rfc ); t ck =min( t ck ); cke is high, cs is high between all valid commands; other command and address inputs are switchi ng; data bus inputs are switching. i dd5d distributed auto refresh current t ck = t ckmin ; refresh command every t refi ; cke is high, cs is high between valid commands; other command and address inputs are switching; data bus inputs are switching. i dd6 self refresh current cke max( v il ), external clock off, ck and ck low; address and control input s are stable (high); data bus inputs are stable (high). i dd7 operating bank interleave read current all banks interleaving with cl = cl(min); t rcd = t rcdrd (min); t rrd = t rrd (min); i out =0 ma; address and control inputs are stable (high) during deselect; data bus inputs are switching.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 31 05292007-wau2-uu95 notes 1. 0 c tc 85 c 2. data bus consists of dq, dm, wdqs. 3. definitions for idd: low is defined as vin = 0.4 vddq; high is defined as v in = v ddq ; stable is defined as inputs are stable at a high level. switching is defined as inpu ts are changing between high and low ever y clock cycle for address and control signals, and inputs changing 50% of each data transfer for dq signals.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 32 05292007-wau2-uu95 4.12 ac timings for hyb18h512321bf table 20 timing parameters for hyb18h512321bf parameter cas latency symbol limit values unit note -8 ?10 ?11 ?12 ?14 min max min. max. min. max. min. max. min. max. clock and clock enable system frequency cl=13 f ck13 7001200????????mhz 1) cl= 12 f ck12 500 1000 500 1000 ? ? ? ? ? ? mhz 1) cl= 11 f ck11 400 900 400 900 400 900 400 800 400 700 mhz 1) cl =10 f ck10 350 800 350 800 350 800 350 700 350 650 mhz 1)2) cl = 9 f ck9 350 700 350 700 350 700 350 650 350 600 mhz 1)2) cl = 8 f ck8 350 600 350 600 350 600 350 550 350 500 mhz 1)2) cl = 7 f ck7 350 550 350 550 350 550 350 500 350 450 mhz 1)2) clock high level width t ch 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck clock low-level width t cl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 t ck minimum clock half period t hp 0.45 ? 0.45 ? 0.45 ? 0.45 ? 0.45 ? t ck 3) command and address setup and hold timing address/command input setup time t is 0.22 ? 0.24 ? 0.27 ? 0.3 ? 0.35 ? ns address/command input hold time t ih 0.22 ? 0.24 ? 0.27 ? 0.3 ? 0.35 ? ns address/command input pulse width t ipw 0.7 ? 0.7 ? 0.7 ? 0.7 ? 0.7 ? t ck mode register set timing mode register set cycle time t mrd 6 ?6?6?6?6 ? t ck 4)5) mode register set to read timing t mrdr 12?12?12?12?12? t ck row timing row cycle time t rc 40?37?35?34?30? t ck row active time t ras 25?23?22?21?18? t ck 6) act(a) to act(b) command period t rrd 10?9 ?8 ?8 ?7 ? t ck row precharge time t rp 15?14?13?13?12? t ck row to column delay time for reads t rcdrd 14?13?12?12?11? t ck row to column delay time for writes t rcdwr t rcdwr(min) = max( t rcdrd(min) - (wl + 1) t ck ;2 t ck ) t ck 7) four active windows within rank t faw 40?36?32?32?28? t ck
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 33 05292007-wau2-uu95 column timing cas(a) to cas(b) command period t ccd 2 ?2?2?2?2 ? t ck 8) internal write to read command delay t wtr 8 ?7?6?6?5 ? t ck 9) read to write command delay t rtw t rtw(min) = (cl + bl/2 +2 -wl) t ck 10) write cycle timing parameters for data and data strobe write command to first wdqs latching transition t dqss wl? 0.25 wl+ 0.25 wl? 0.25 wl+ 0.25 wl? 0.25 wl+ 0.25 wl? 0.25 wl+ 0.25 wl? 0.25 wl+ 0.25 t ck data-in and data mask to wdqs setup time t ds 0.13 ? 0.14 ? 0.15 ? 0.16 ? 0.18 ? ns data-in and data mask to wdqs hold time t dh 0.13 ? 0.14 ? 0.15 ? 0.16 ? 0.18 ? ns data-in and dm input pulse width (each input) t dipw 0.4 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? t ck dqs input low pulse width t dqsl 0.45 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? t ck dqs input high pulse width t dqsh 0.45 ? 0.40 ? 0.40 ? 0.40 ? 0.40 ? t ck dqs write preamble time t wpre 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck dqs write postamble time t wpst 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck write recovery time t wr 13?13?13?12?10? t ck read cycle timing parameters for data and data strobe data access time from clock t ac -0.20 -0.20 -0.21 0.21 -0.22 0.22 -0.22 0.22 ?0.25 0.25 ns read preamble t rpre 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck read postamble t rpst 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 t ck data-out high impedance time from clk t hz t acmin t acmax t acmin t acmax t acmin t acmax t acmin t acmax t acmin t acmax ns data-out low impedance time from clk t lz t acmin t acmax t acmin t acmax t acmin t acmax t acmin t acmax t acmin t acmax ns dqs edge to clock edge skew t dqsck -0.20 0.20 -0.21 0.21 -0.22 0.22 -0.22 0.22 ?0.25 0.25 ns dqs edge to output data edge skew t dqsq ? 0.110 ? 0.120 ? 0.130 ? 0.140 ? 0.160 ns 11) data hold skew factor t qhs ? 0.110 ? 0.120 ? 0.130 ? 0.140 ? 0.160 ns data output hold time from dqs t qh t hp ? t qhs ns refresh/power down timing refresh period (8192 cycles) t ref ? 32 ? 32 ? 32 ? 32 ? 32 ms average periodic auto refresh interval t refi 3.9 3.9 3.9 3.9 3.9 s parameter cas latency symbol limit values unit note -8 ?10 ?11 ?12 ?14 min max min. max. min. max. min. max. min. max.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 34 05292007-wau2-uu95 delay from aref to next act/ aref t rfc 52.0 ? 52.0 ? 52.0 ? 52.0 ? 52.0 ? ns self refresh exit time t xsc 1000 ? 1000 ? 1000 ? 1000 ? 1000 ? t ck self refresh exit followed by non-read command t xsnr 200 ? 200 ? 200 ? 200 ? 200 ? t ck power down exit time t xpn 7 ?7?7?7?6 ? t ck other timing parameters res to cke setup timing t ats 10?10?10?10?10?ns res to cke hold timing t ath 10?10?10?10?10?ns termination update keep out timing t ko 10?10?10?10?10?ns rev. id emrs to dq on timing t ridon ? 20 ? 20 ? 20 ? 20 ? 20 ns rev. id emrs to dq off timing t ridoff ? 20 ? 20 ? 20 ? 20 ? 20 ns 1) f ck (min), f ck (max) for dll on mode 2) f ck (min) can go down to 200mhz, with t ac and t dqsck shifted up to 1/2 t ck 3) t hp is the lesser of t cl minimum and t ch minimum actually applied to the device clk, clk inputs 4) this value of t mrd applies only to the case where the ?dll reset? bit is not activated 5) t mrd is defined from mrs to any other command then read 6) t rasmax is 8 t ref 7) t rcdwr(min) may not drop below 2 t ck 8) t ccd is either for gapless consecutive reads or gapless consecutive writes. bl =4 9) wtr and t wr start at the first rising edge of clk after the last valid (falling) wdqs edge of the slowest wdqs signal 10) please round up t rtw to the next integer of t ck 11) this parameter is defined per byte parameter cas latency symbol limit values unit note -8 ?10 ?11 ?12 ?14 min max min. max. min. max. min. max. min. max.
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 35 05292007-wau2-uu95 5 package 5.1 package outline figure 18 package outline pg-tfbga-136-054 note: the package is conforming with jedec mo-207i, var dr-z. ' 0 ! x - ! 8 x - ! 8 - ) . # ? - ? ? ? x - # ! " # # 3 % ! 4 ) . ' 0 , ! . % # ! " - i d d l e o f p a c k a g e s e d g e s 0 a c k a g e o r i e n t a t i o n m a r k ! " a d u n i t m a r k i n g " 5 - 3 " ! & i d u c i a l 3 o l d e r " a l l ! t t a c h , e a d f r e e s o l d e r b a l l s ' r e n 3 o l d e r " a l l s - ! 8 - ! 8
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 36 05292007-wau2-uu95 5.2 package thermal characteristics table 21 pg-tfbga-136 package thermal resistances notes 1. theta_ja: junction to ambient thermal resistance. the values have been obtained by simulation using the conditions stated in the jedec jesd-51 standard. 2. theta_jb: junction to board t hermal resistance. the value has been obtained by simulation. 3. theta_jc: junction to case thermal resistance. the value has been obtained by simulation. theta_ja theta_jb theta_jc jedec board 1s0p 2s2p air flow 0 m/s 1 m/s 3 m/s 0 m/s 1 m/s 3 m/s - - k/w 4032272219175 2
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 37 05292007-wau2-uu95 list of illustrations figure 1 ballout 512-mbit gddr3 graphics ram [top view, mf = low ] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2 mode register set command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 mode register bitmap for mid-range-speed application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 mode register bitmap for high-speed application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5 mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 extended mode register set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 7 extended mode register bitmap for mid-range-speed application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8 extended mode register bitmap for high-speed application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9 extended mode register set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10 timing of vendor code and revision id generation on dq[7 :0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11 extended mode register 2 set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12 extended mode register 2 bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13 output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 14 40 ohm driver pull-down and pull-up characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15 60 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16 120 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17 240 ohm active termination characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18 package outline pg-tfbga-136-054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 38 05292007-wau2-uu95 list of tables table 1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table 2 ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3 ball assignment with mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4 function truth table i. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5 function truth table ii (cke table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6 burst definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7 on/off mode of dq/dm receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 8 revision id and vendor code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 9 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10 power & dc operation conditions (0 c t c 85 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11 dc & ac logic input levels (0 c t c 85 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12 differential clock dc and ac input conditions (0 c t c 85 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 13 pin capacitances (vddq = 1.8 v, ta = 25c, f = 1 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14 programmed driver iv characteristics at 40 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15 programmed terminator characteristics at 60 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16 programmed terminator characteristics of 120 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17 programmed terminator characteristics at 240 ohm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 18 operating current ratings ( 0 c t c 85 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20 timing parameters for hyb18h512321bf. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 21 pg-tfbga-136 package thermal resistances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
hyb18h512321bf 512-mbit gddr3 internet data sheet rev. 1.3, 2007-12 39 05292007-wau2-uu95 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 mirror function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 truth tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3.1 function truth table for more than one activated bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 function truth table for cke. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 mode register set command (mrs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.1 burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.2 burst type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.3 cas latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.4 write latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.5 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.6 dll reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 extended mode register set command (emrs1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 dll enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.2 wr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.3 termination rtt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.4 output driver impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2.5 vendor code and revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 extended mode register 2 set command (emrs2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.3.1 app mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 absolute maximum ratings and operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.1 recommended power & dc operation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 dc & ac logic input levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 differential clock dc and ac levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 output test conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7 driver current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7.1 driver iv characteristics at 40 ohms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.7.2 termination iv characteristic at 60 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 termination iv characteristic at 120 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.9 termination iv characteristic at 240 ohms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 operating currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.10.1 operating current ratings for hyb18h512321bf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.11 operating current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.12 ac timings for hyb18h512321bf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2 package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
edition 2007-12 published by qimonda ag gustav-heinemann-ring 212 d-81739 mnchen, germany ? qimonda ag 2008. all rights reserved. legal disclaimer the information given in this internet data sheet shall in no ev ent be regarded as a gua rantee of conditions or characteristics (?beschaffenheitsgarantie?). with respect to any examples or hi nts given herein, any typical values stated herein and/or any information regarding the application of the device, qimonda hereby disclaims any and all warranties and liabilities of any kin d, including without limitation warranties of non-infringem ent of intellectual property rights of any third party. information for further information on technology, delivery terms and conditio ns and prices please contact your nearest qimonda office. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest qimonda office. qimonda components may only be used in life-support devices or systems with the express writte n approval of qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support devi ce or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is re asonable to assume that the he alth of the user or other persons may be endangered. www.qimonda.com internet data sheet

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