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october 2008 rev 13 1/32 1 nandxxxxmx 256/512-mbit or 1-gbit (x8/x16, 1.8/2.6 v, 528-byte page) nand flash and 256/512-mbit (x16/x32 , 1.8 v) lpsdram, mcp or pop features n packages ? mcp (multichip package) ? pop (package on package) n device composition ? 1 die of 256 or 512 mbits or 1 gbit (x8/x16) slc small page nand flash memory ? 1 die of 256 or 512 mbits (x16 or x32) sdr/ddr lpsdram n supply voltages ?v ddf = 1.7 v to 1.95 v or 2.5 v to 3.6 v ?v ddd = v ddqd = 1.7 v to 1.95 v n electronic signature n ecopack ? packages n temperature range: ?30 to 85 c flash memory n nand interface ? x8/x16 bus width ? multiplexed address/data n page size ? x8 device: (512 + 16 spare) bytes ? x16 device: (256 + 8 spare) words n block size ? x8 device: (16k + 512 spare) bytes ? x16 device: (8k + 256 spare) words n page read/program ? random access: 12 s (3 v), 15 s (1.8 v) ? sequential access: 30 ns (3 v), 50 ns (1.8 v) ? page program time: 200 s (typ) n copy back program mode ? fast page copy without external buffering n fast block erase ? block erase time: 2 ms (typ) ? status register n data integrity ? 100 000 program/erase cycles ? 10 years data retention single or double data rate lpsdram n interface: 16 or 32 bus width n deep power-down mode n 1.8 v lvcmos interface n quad internal banks controlled by ba0, ba1 n automatic and controlled precharge n auto refresh and self refresh ? 8 192 refresh cycles/64 ms ? programmable partial array self refresh ? auto temperature compensated self refresh n wrap sequence: sequential/interleave n burst termination by burst stop command and precharge command table 1. device summary nandxxxxmx nand88r3m0 nand99w3m0 nand98r4m2 nand98r3m0 nand99w3m1 nand99r3m1 nand98w3m0 nanda9w3m1 nand99r3m0 nand99r4m2 nand99r3m2 nand98w3m1 nand98r3m1 nand98r3m2 fbga fbga tfbga107 10.5 13 1.2 mm (zbb) tfbga149 10 13.5 1.2 mm (zba) tfbga137 10.5 13 1.2 mm (zbc) lfbga137 10.5 13 1.4 mm (zbc) tfbga152 14 x 14 x 1.1 mm (zpa) www.numonyx.com
contents nandxxxxmx 2/32 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 nand flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 lpsdram component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1 flash memory inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 flash memory inputs/outputs (i/o8-i/o15) . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 flash memory address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 flash memory command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . 16 2.5 flash memory chip enable (e f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 flash memory read enable (r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7 flash memory write enable (w f ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.8 flash memory write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.9 flash memory ready/busy (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.10 flash memory v ddf supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11 flash memory v ssf ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.12 lpsdram address inputs (a0-a12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.13 lpsdram bank select address inputs (ba0-ba1) . . . . . . . . . . . . . . . . . 18 2.14 lpsdram data inputs/outputs (dq0-dq15 and dq16-dq31) . . . . . . . . 18 2.15 lpsdram chip select (e d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.16 lpsdram column address strobe (cas ) . . . . . . . . . . . . . . . . . . . . . . . 18 2.17 lpsdram row address strobe (ras ) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.18 lpsdram write enable (w d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.19 lpsdram clock input (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.20 lpsdram clock input (k ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.21 lpsdram clock enable (ke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.22 lower/upper data read/write strobe input/output (ldqs, udqs) . . . . 19 2.23 lpsdram data input/output mask pins (dqm0, dqm1, dqm2, dqm3) 19 2.24 lpsdram v ddd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.25 lpsdram v ddqd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.26 lpsdram v ssd ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
nandxxxxmx contents 3/32 2.27 v ssqd ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of tables nandxxxxmx 4/32 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. lpsdram details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4. signal names (tfbga107, tfbga137 and tfbga 149 packages) . . . . . . . . . . . . . . . . . 10 table 5. signal names (tfbga152 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. tfbga107 10.5 13 x 1.2 mm - 10 14 active ball array, 0.80 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. tfbga137 10.5 x 13 x 1.2 mm - 10 x 15 active ball array, 0.80 mm pitch, mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. tfbga149 10 13.5 x 1.2 mm - 12 16 active ball array, 0.80 mm pitch, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. tfbga152 14 14 x 1.1 mm - 2r 21 x 21, 0.65 mm pitch, mechanical data . . . . . . . . . . 29 table 11. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
nandxxxxmx list of figures 5/32 list of figures figure 1. logic diagram (tfbga107, tfbga137and tfbga 149 packages). . . . . . . . . . . . . . . . . . . 8 figure 2. logic diagram (tfbga152 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tfbga107 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. tfbga137 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. tfbga149 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6. tfbga152 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. functional block diagram (tfbga107, tfbga137, tfbga149). . . . . . . . . . . . . . . . . . . . 22 figure 8. functional block diagram (tfbga152) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. tfbga107 10.5 13 x 1.2 mm - 10 14 active ball array, 0.80 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. tfbga137 10.5 x 13 x 1.2 mm - 10 x 13 active ball array, 0.80 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 11. tfbga149 10 13.5 x 1.2 mm - 12 16 active ball array, 0.80 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 12. tfbga152 14 14 x 1.1 mm - 2r 21 x 21 , 0.65 mm pitch, package outline . . . . . . . . . . 29
description nandxxxxmx 6/32 1 description the nandxxxxmx devices (see table 1: device summary for the list of devices) combine two memory devices in a multichip package: l 256-mbit, 512-mbit, or 1-gbit slc small page nand flash memory, and either: l 256-mbit or 512-mbit sdr (single data rate) lpsdram or l 256-mbit or 512-mbit ddr (double data rate) lpsdram the nand flash memory and lpsdram components have separate power supplies and grounds. they also have separate control, address and input/output signals; this allows simultaneous access to both devices at any moment. the nand flash memory and lpsdram components are distinguished by a chip enable input, e f , for the nand flash memory and a chip select, e d , for the lpsdram. see figure 1 and figure 2 in conjunction with table 4 and table 5 for an overview of the signal s associated with each component. the nandxxxxmx devices are available with a 1.8 v or 2.6 v voltage supply and are offered in the following packages as shown in table 2: product list : l tfbga107 (10.5 13 1.2 mm) l tfbga149 (10 13.5 1.2 mm) l tfbga137 (10.5 13 1.2 mm) l tfbga152 (14 14 1.1 mm) the memories are supplied with all the nand flash memory bits erased (set to ?1?). this datasheet should be read in conjunction wi th the slc small page nand flash memory and lpsdram datasheets. table 2. product list root part number nand produc t lpsdram product package nand88r3m0 256 mbits (8) - 1.8 v sdr 256 mbits (16) 1.8 v, 133 mhz tfbga107 nand99r3m0 512 mbits (8) - 1.8 v sdr 512 mbits (16) 1.8 v, 133 mhz tfbga149 nand98r3m0 512 mbits (8) - 1.8 v sdr 256 mbits (16) 1.8 v, 133 mhz tfbga107 tfbga149 tfbga152 nand99w3m1 512 mbits (8) - 2.6 v sdr 512 mbits (32) 1.8 v, 133 mhz tfbga137 nand99r3m1 512 mbits (8) - 1.8 v sdr 512 mbits (32) 1.8 v, 133 mhz lfbga137 nand99w3m0 512 mbits (8) - 2.6 v sdr 512 mbits (16) 1.8 v, 133 mhz tfbga107 nand98w3m0 512 mbits (8) - 2.6 v sdr 256 mbits (16) 1.8 v, 133 mhz tfbga107 nanda9w3m1 1 gbit (x8) - 2.6 v sdr 512 mbits (x32) 1.8 v, 133 mhz tfbga 137 nand99r4m2 512 mbits (x16) - 1.8 v ddr 512 mbits (x16) 1.8 v, 133 mhz tfbga 149 nand99r3m2 512 mbits (8) - 1.8 v ddr 51 2 mbits (x16) 1.8 v, 133 mhz tfbga107 nand98w3m1 512 mbits (8) - 2.6 v sdr 256 mbits (x32) 1.8 v, 133 mhz tfbga 137 nand98r3m1 512 mbits (8) - 1.8 v sdr 256 mbits (x32) 1.8 v, 133 mhz tfbga 137
nandxxxxmx description 7/32 1.1 nand flash memory component the nandxxxxmx devices have a 1.8 v or 2.6 v power supply and contain 1 die of nand flash memory with the following features: l 256 mbits, 512 mbits, or 1 gbit l x8/x16 bus width l chip enable ?don?t care? option table 2 specifies the type of nand flash memo ry component contained in each product. for detailed information on how to use the slc small page nand flash memory devices, refer to the respective datasheets, which are available on the internet site http://www.numonyx.com, or from your local numonyx distributor. 1.2 lpsdram component table 3 provides details on the sdr or ddr lpsdram component contained in each device. nand98r3m2 512 mbits (x8) - 1.8 v ddr 256 mbits (x16) 1.8 v, 133 mhz tfbga 107 nand98r4m2 512 mbits (x16) - 1.8 v ddr 256 mbits (x16) 1.8 v, 133 mhz tfbga149 table 2. product list (continued) root part number nand produc t lpsdram product package table 3. lpsdram details root part number lpsdram type lpsdram name nand88r3m0 nand98w3m0 256 mbits (x16) single data rate m65ka256af nand98r3m0 (tfbga152) 256 mbits (x16) single data rate m65ka256af nand99r3m0 nand99w3m0 512 mbits (x16) single data rate m65ka512ab nand99w3m1 nanda9w3m1 512 mbits (x32) single data rate m65kc512ab or m65kc512ac nand99r4m2 512 mbits (x16) double data rate m65kg512ah nand99r3m2 512 mbits (x16) double data rate m65kg512ah nand98w3m1 256 mbits (x32) single data rate m65ka256aj nand98r3m1 256 mbits (x32) single data rate m65ka256aj nand98r3m0 (tfbga107 and tfbga149) 256 mbits (x16) single data rate m65ka256af or m65ka256aj nand98r3m2 256 mbits (x16) double data rate m65kg256aj nand98r4m2 256 mbits (x16) double data rate m65kg256aj
description nandxxxxmx 8/32 for detailed information on how to use the sdr/ddr lpsdram devices, refer to the m65ka256af, m65ka512ab, m65kc5 12ab, m65kc512ac, m65kg512ah, m65kaxxxaj, and m65kgxxxaj datasheets avail able from your local numonyx distributor. figure 1. logic diagram (tfbga1 07, tfbga137and tfbga149 packages) 1. see table 4 for the description of the si gnals related to these packages. 2. k is only available in mcp with ddr, ldqs, and udqs are only available in mcp with ddr x16. 3. dqm2 and dqm3 are only available in mcp with sdr/ddr x32. ni3054 13 a0-a12 dqm0 k v ddf dq0-dq15, x16/x32 nandxxxxmx e f w f al 2 ba0-ba1 ras r v ddqd v ddd rb i/o8-i/o15, x16 v ssd i/o0-i/o7, x8/x16 cl ke e d w d cas dqm2 (3) dqm1 dqm3 (3) wp k (2) dq16-dq31, x32 udqs (2) ldqs (2) v ssf v ssqd 8 8 16 16
nandxxxxmx description 9/32 figure 2. logic diagram (tfbga152 package) 1. see table 5 for the description of the si gnals related to these packages. ni3056 13 a0-a12 dqm0 k v ddf dq0-dq15 nand98r3m0 e f w f al 2 ba0-ba1 ras r v ddqd v ddd rb v ss i/o0-i/o7 cl ke e d w d cas dqm1 wp 8 16
description nandxxxxmx 10/32 table 4. signal names (tfbga107, tfbga137 and tfbga149 packages) nand flash memory signal function direction i/o0-i/o7 data inputs/outputs for x8/x16 devices input/output i/o8-i/o15 data inputs/outputs for x16 devices input/output al address latch enable input cl command latch enable input e f chip enable input r read enable input rb ready/busy (open-drain output) output w f write enable input wp write protect input v ddf supply voltage power supply v ssf ground ground lpsdram a0-a12 row address: a0-a12 column address: ? a0-a8 (256 mbits and 512 mbits x32) ? a0-a9 (512 mbits x16) auto-precharge flag: a10 input ba0-ba1 bank address input dq0-dq15 data inputs/outputs, 16/32 input/output dq16-dq31 data inputs/outputs, 32 input/output k, k clock input ke clock enable input e d chip select input w d write enable input ras row address strobe input cas column address strobe input dqm0 dq mask enable (controls dq 0-dq7, 16/32) input/output dqm1 dq mask enable (controls dq8-dq15, 16/32) input/output dqm2 dq mask enable (controls dq16-dq23, 32) input/output dqm3 dq mask enable (controls dq24-dq31, 32) input/output udqm upper data read strobe (ddr x16) input/output ldqm lower data write strobe (ddr x16) input/output v ssd ground ground v ssqd input/output ground ground nc not connected internally n/a
nandxxxxmx description 11/32 table 5. signal names (tfbga152 package) nand flash memory signal function direction i/o0-i/o7 data input/outputs fo r x8 and x16 devices input/output al address latch enable input cl command latch enable input e f chip enable input r read enable input rb ready/busy (open-drain output) output w f write enable input wp write protect input v ddf supply voltage power supply lpsdram a0-a12 row address: a0-a12 column address: a0-a8 auto-precharge flag: a10 ground ba0-ba1 bank select inputs input dq0-dq15 data inputs/outputs input/output k clock input ke clock enable input e d chip select input w d write enable input ras row address strobe input cas column address strobe input dqm0 dq mask enable (c ontrols dq0-dq7) input dqm1 dq mask enable (controls dq8-dq15) input v ddd supply voltage power supply v ddqd input/output supply voltage power supply v ss common nand flash and lpsdram ground ground nc not connected internally n/a du do not use n/a
description nandxxxxmx 12/32 figure 3. tfbga107 connections (top view through package) 1. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. 2. balls shaded in gray are only used for nand + ddr devices. ai10143c v ddd a8 dqm1 v ssd ke a12 dqm0 h a9 d r c dq4 a1 b a3 a 8 7 6 5 4 3 2 1 v ssd v ddqd g f e v ddqd du wp a0 ba0 dq6 v ssqd cas a11 nc w f ba1 a10 du v ddd v ssd 9 nc a2 e d m l k j du dq15 nc dq11 i/o6 v ddqd v ssqd nc dq9 i/o5 dq13 v ddd v ssf v ddf a7 i/o4 i/o7 a5 du du v ssqd a4 du p n 10 nc rb dq2 nc nc e f i/o3 v ddf i/o2 nc cl al dq0 v ssf i/o1 v ssf i/o0 k dq1 dq3 dq5 dq7 v ddd dq10 dq12 dq14 v ssd dq8 du du du du a6 w d nc ras v ddf nc nc k ldqs udqs i/o9 i/o11 i/o13 i/o15 i/o8 i/o10 i/o12 i/o14 du
nandxxxxmx description 13/32 figure 4. tfbga137 connections (top view through package) 1. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai10134c v ddqd nc dq20 nc v ssqd k dq9 dq15 h nc d r c a7 dq30 b nc v ddd a 8 7 6 5 4 3 2 1 a4 v ssd v ddd a5 g f e a11 du wp dq31 dq29 ke a6 a8 dq26 dqm3 dqm2 dq23 v ssd v ssd w f dq28 v ssqd du cas nc ras 9 nc v ddqd v ddqd a12 v ddd m l k j v ssd i/o2 v ddqd v ddd i/o4 nc ba0 a3 dq4 v ssd dqm0 ba1 w d a1 a2 i/o1 a10 dq6 dq3 nc v ddd v ssd i/o7 nc nc nc v ssqd nc dq5 v ddqd du nc nc e d v ssqd i/o0 du r p n 10 dq12 dqm1 rb dq27 dq22 dq24 e f v ssf dq8 dq2 i/o5 i/o6 dq10 dq13 nc v ssf dq25 nc dq19 v ddf nc dq7 dq1 i/o3 v ddf dq11 dq21 dq16 al a9 dq18 dq17 cl nc a0 dq0 nc nc dq14 v ssqd v ddqd v ddd nc v ddqd du v ssqd v ssqd v ssqd v ddqd v ssqd v ssqd v ddqd v ddqd nc du du
description nandxxxxmx 14/32 figure 5. tfbga149 connections (top view through package) 1. balls shaded in gray are only used for nand + ddr devices. 2. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13235c dqm1 ke a11 dqm0 h a9 d r c dq4 a1 b a3 a 8 7 6 5 4 3 2 1 g f e du wp a0 ba0 dq6 cas w f ba1 du v ddd 9 nc a7 e d m l k j du dq15 nc dq13 v ssf i/o0 i/o7 du du v ssqd du p n 12 nc rb dq2 nc nc e f i/o2 nc cl al dq0 v ssd i/o1 k dq1 dq3 dq5 dq7 v ddd dq10 v ssd dq8 du du du du wd nc ras v ddf nc nc nc a10 du a8 du nc du nc v ddqd nc du du du du du du du du du du du du du du 10 11 t r nc du v ssd v ddd du nc i/o6 i/o5 a6 a12 nc nc a2 a5 i/o4 nc nc a4 nc v ddf v ssf nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc i/o3 nc dq11 dq14 dq12 dq9 v ddqd v ssd k udqs i/o9 i/o8 i/o15 i/o14 i/o13 i/o10 i/o12 i/o11 ldqs
nandxxxxmx description 15/32 figure 6. tfbga152 connections (top view through package) 1. ball b20 is the sdram temperature flag. 2. all voltage balls must be connected to t he power supply (the internal connection is not guaranteed). all ground balls must be connected to the ground. ai13622 h d c b wp a 8 7 6 5 4 3 2 1 v ss dqm0 g f e dq9 v ss dqm1 nc v ss 9 v dd m l k j v dd du dq13 dq0 v ddq dq4 dq5 dq2 v dd dq7 dq3 dq6 dq1 v ddqd nc dq8 ba0 dq10 ba1 dq12 v ss v ddqd du dq14 v ddqd dq11 v ss dq15 14 13 11 10 12 i/o1 nc i/o0 i/o2 v ss nc i/o3 rb du du du i/o4 ke nc al r cl nc i/o5 du nc nc i/o6 i/o7 du du n v ddqd du du du du du du du v ddf v ss du v ss du du du du v ss du v dd ras du e d e f du nc v ss nc nc nc nc nc v ddqd nc 21 20 19 18 17 16 15 r p w v u t aa y du v dd du du du v ss du du du du v ss v dd v ss nc a3 a5 k w d a4 v ss a0 cas a2 a1 v ss nc v ss v dd du du du du temp (1) v ss nc v ddf du v dd du du du du du w f du du v dd v ss a12 a10 a7 a11 a9 a8 a6 v dd
signals description nandxxxxmx 16/32 2 signals description figure 1 and figure 2 , in conjunction with table 4 and table 5 , provide a brief overview of the signals connected to nandxxxxmx devices. th is section provides fu rther information on the signals. for additional details on the signals, refer to the nand flash memory and the lpsdram datasheets. 2.1 flash memory inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 are used by the flash memo ry to input the selected address, output the data during a read operation, or input a command or data during a write operation. the inputs are latched on the rising edge of writ e enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 2.2 flash memory inputs/outputs (i/o8-i/o15) input/outputs 8 to 15 are only available in x1 6 nand flash devices. they are used to output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the device is deselected or the outputs are disabled. 2.3 flash memory addr ess latch enable (al) the address latch enable, al, activates the latc hing of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 2.4 flash memory command latch enable (cl) the command latch enable, cl, activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 2.5 flash memory chip enable (e f ) the chip enable input, e f , activates the memory control logic, input buffers, decoders, and read circuitry. when chip enable is low, v il , the device is selected. if chip enable goes high (v ih ) while the device is busy, the device remains selected and does not go into standby mode.
nandxxxxmx signals description 17/32 2.6 flash memory read enable (r ) the read enable, r , controls the sequential data out put during read operations. data is valid t rlqv after the falling edge of r . the falling edge of r also increments the internal column address counter by one. 2.7 flash memory write enable (w f ) the write enable input, w f , controls writing to the command interface, input address, and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down, a minimum reco very time of 10 s is required before the command interface is ready to accept a command . it is recommended to keep write enable high during the recovery time. 2.8 flash memory write protect (wp ) the write protect pin is an input that prov ides hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 2.9 flash memory ready/busy (rb ) the ready/busy output, rb , is an open-drain output that can be used to identify if the p/e/r controller is currently active. when ready/busy is low, v ol , this signifies that a read, prog ram, or erase operation is in progress. when the operation completes, ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low then indicates that one or more of the memories is busy. 2.10 flash memory v ddf supply voltage v ddf provides the power supply to the internal core of the memory de vice. it is the main power supply for all operations (read, program, and erase). an internal voltage detector disables all functions whenever v ddf is below the v lko threshold to protect the device from any invo luntary program/erase operations during power transitions. each device in a system should have v ddf decoupled with a 0.1 f capacitor, and the pcb track widths should be sufficient to carry the required program and erase currents 2.11 flash memory v ssf ground ground, v ssf, is the reference for the power supply. it must be connected to the system ground.
signals description nandxxxxmx 18/32 2.12 lpsdram address inputs (a0-a12) the a0-a12 address inputs are used to select the row or column to be made active. if a row is selected, all thirteen address inputs, a0-a12 , are used. if a column is selected, only the least significant address inputs, a0-a8 (256-mbit device and 512-mbit x32 device) or a0-a9 (512-mbit x16 device), are used. in this latte r case, a10 determines whether auto precharge is used. if a10 is high (set to ?1?) during r ead or write, the operation includes an auto precharge cycle. if a10 is low (set to ?0?) duri ng read or write, the cycle does not include an auto precharge cycle. 2.13 lpsdram bank select address inputs (ba0-ba1) the select address inputs of the ba0 and ba1 banks are used to select the bank to be made active. the following are the necessary settings when selecting the addresses: l the device must be enabled l row address strobe, ras , must be low, v il l column address strobe, cas , must be high, v ih l w must be high, v ih the address inputs are latched on the rising edge of the clock signal, k. 2.14 lpsdram data inputs/outpu ts (dq0-dq15 and dq16-dq31) the dq16-dq31 data inputs/outputs are available only in the nand99w3m1 and nanda9w3m1, where the bus width is 32.the data inputs/outputs output the data stored at the selected address during a read operation, or are used to input the data during a write operation. 2.15 lpsdram chip select (e d ) the chip select input, e d , activates the memory state machine, address buffers, and decoders when driven low, v il . when high, v ih , the device is not selected. 2.16 lpsdram column address strobe (cas ) the column address strobe, cas , is used in conjunction with address inputs a8-a0 (256- mbit device and 512-mbit x32 device) or a9-a0 (512-mbit x16 device) and ba1-ba0, to select the starting column location prior to a read or write operation. 2.17 lpsdram row address strobe (ras ) the row address strobe, ras , is used in conjunction with address inputs a12-a0 and ba1- ba0 to select the starting address location prior to a read or write operation.
nandxxxxmx signals description 19/32 2.18 lpsdram write enable (w d ) the write enable input, w d , controls writing. 2.19 lpsdram clock input (k) the clock signal, k, is used to clock the read and write cycles. during normal operation, the clock enable pin, ke, is high, v ih . the clock signal k can be suspended to switch the device to the self-refresh, power-down or deep power-down mode by driving ke low, v il . 2.20 lpsdram clock input (k ) the clock signal, k , is only available on the ddr lpsd ram and is used in conjunction with the clock signal, k. all lpsdram input signals except dqm0 /dqm1/dqm2/dqm3, udqs/ldqs and dq0- dq31 are referred to the crosspoint of k rising edge and k falling edge. 2.21 lpsdram clock enable (ke) the clock enable, ke, pin is used to contro l the synchronization of the signals with clock signal k. if ke is high, v ih , the next clock rising edge is valid. when ke is low, v il , the signals are no longer clocked and data read and write cycles are extended. ke is also involved in switching the device to the self-refresh, power-down and deep power-down modes. 2.22 lower/upper data read/write strobe input/output (ldqs, udqs) ldqs and udqs can be either input or output signals, and act as write data strobe and read data strobe respectively. ldqs and udqs are the strobe signals for dq0 to dq7 and dq8 to dq15, respectively. 2.23 lpsdram data input/outp ut mask pins (dqm0, dqm1, dqm2, dqm3) dqm2 and dqm3 are available only in the nand99w3m1 and nanda9w3m1, where the bus width is 32. the data input/output mask pins are input signals used to mask the read or write data. the dqm latency is two clock cycles for read operations and there is no latency for write operations. 2.24 lpsdram v ddd supply voltage v ddd provides the power supply to the internal co re of the memory device. it is the main power supply for all read and write operations.
signals description nandxxxxmx 20/32 2.25 lpsdram v ddqd supply voltage v ddqd provides the power supply to the i/o pi ns and enables all outputs to be powered independently of v ddd . v ddqd can be tied to v ddd or can use a separate supply. it is recommended to power up and power down v ddd and v ddqd together to avoid conditions that would result in data corruption. 2.26 lpsdram v ssd ground v ssd is the reference for the nand flash power supply. it must be connected to the system ground. 2.27 v ssqd ground v ssqd ground is the reference for the input/output circuitry driven by v ddqd . v ssqd must be connected to v ssd . note: each device in a system should have v ddd and v ddq d decoupled with a 0.1 f ceramic capacitor close to the pin (high-frequency, inherently-low inductance capacitors should be as close as possible to the package).
nandxxxxmx functional description 21/32 3 functional description the nand flash memory and lpsdram components have separate power supplies and, according to in which package they are delivered, they either share the same grounds or have separate grounds. they also have separate control signals, addresses, and data input/outputs, which allows simultaneous access to both devices at any moment. figure 7 and figure 8 show the functional block diagrams.
functional description nandxxxxmx 22/32 figure 7. functional block diagram (tfbga107, tfbga137, tfbga149) 1. only available in mcp with ddr. 2. only available in mcp with sdr/ddr x32. 3. only available in mcp with ddr x16. ni3055 ba0-ba1 dqm0 k dq0-dq15, x16/x32 lpsdram v ddqd v ddd 16 a0-a12 ke e d w d cas dqm1 v ddf i/o8-i/o15, x16 256-mbit 512-mbit 1-gbit nand flash memory e f w f al r rb i/o0-i/o7, x8/x16 cl wp ras udqs, ldqs (3) v ssqd 8 8 2 13 v ssf dqm2 (2) dqm3 (2) v ssd dq16-dq31, x32 k (1)
nandxxxxmx functional description 23/32 figure 8. functional block diagram (tfbga152) ni3057 ba0-ba1 dqm0 k dq0-dq15 lpsdram v ddqd v ddd 16 a0-a12 ke e d w d cas dqm1 v ddf 512-mbit nand flash memory e f w f al r rb i/o0-i/o7 cl wp ras v ss 8 2 13
maximum ratings nandxxxxmx 24/32 4 maximum ratings stressing the device ab ove the rating listed in table 6: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only; operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect the reliability of the device. table 6. absolute maximum ratings symbol parameter value unit min max t a ambient operating temperature -30 85 c t stg storage temperature -55 125 c v io (1) 1. minimum voltage may undershoot to -2 v for less t han 20 ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2 v for less than 20 ns during transitions on i/o pins. nand flash input or output voltage 1.8 v -0.6 2.7 v 2.6 v -0.6 4.6 v v ddqd lpsdram input or output voltage -0.3 2.3 v v ddf nand flash supply voltage 1.8 v -0.6 2.7 v 2.6 v -0.6 4.6 v v ddd lpsdram supply voltage -0.3 2.3 v lpsdram short circuit output current i os 50 ma
nandxxxxmx package mechanical 25/32 5 package mechanical to meet environmental requirements, numonyx offers the devices in ecopack ? packages, which are lead-free. in compli ance with jedec standard jesd 97, the category of second- level interconnect is marked on the package and on the inner box label. the maximum ratings related to soldering conditions are also marked on the inner box label. figure 9. tfbga107 10.5 13 x 1.2 mm - 10 14 active ball array, 0.80 mm pitch, package outline 1. drawing is not to scale. a2 a1 a bga-z24 ddd d e e b se fd fe e1 e sd d1 ball "b1"
package mechanical nandxxxxmx 26/32 table 7. tfbga107 10.5 13 x 1.2 mm - 10 14 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a ? ?1.20? ?0.047 a1 ?0.25? ?0.012? a2 0.80 ? ? 0.032 ? ? b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.411 0.415 d1 7.20 ? ? 0.283 ? ? ddd ? ? 0.10 ? ? ? e 13.00 12.90 13.10 0.512 0.510 0.514 e1 10.40 ? ? 0.409 ? ? e0.80? ?0.031? ? fd 1.65 ? ? 0.065 ? ? fe 1.30 ? ? 0.051 ? ? sd 0.40 ? ? 0.016 ? ? se 0.40 ? ? 0.016 ? ?
nandxxxxmx package mechanical 27/32 figure 10. tfbga137 10.5 x 13 x 1.2 mm - 10 x 13 active ball array, 0.80 mm pitch, package outline 1. drawing is not to scale. table 8. tfbga137 10.5 x 13 x 1.2 mm - 10 x 15 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a??1.20??0.047 a1 ?0.25? ?0.011? a2 0.80 ? ? 0.031 ? ? b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.409 0.417 d1 7.20 ? ? 0.283 ? ? e 13.00 12.90 13.10 0.512 0.508 0.516 e1 11.20 ? ? 0.441 ? ? e0.80? ?0.031? ? fd 1.65 ? ? 0.065 ? ? fe 0.90 ? ? 0.035 ? ? sd 0.40 ? ? 0.016 ? ? e d e b sd a1 a2 a bga-z71 ddd fd d1 e1 e fe ball "b1"
package mechanical nandxxxxmx 28/32 figure 11. lfbga137 10.5 x 13 x 1.4 mm - 10 x 13 active ball array, 0.80 mm pitch, package outline 1. drawing is not to scale. table 9. lfbga137 10.5 x 13 x 1.4 mm - 10 x 15 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a??1.40??0.055 a1 ?0.25? ?0.011? a2 0.80 ? ? 0.031 ? ? b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.50 10.40 10.60 0.413 0.409 0.417 d1 7.20 ? ? 0.283 ? ? e 13.00 12.90 13.10 0.512 0.508 0.516 e1 11.20 ? ? 0.441 ? ? e0.80? ?0.031? ? fd 1.65 ? ? 0.065 ? ? fe 0.90 ? ? 0.035 ? ? sd 0.40 ? ? 0.016 ? ? e d e b sd a1 a2 a bga-z71 ddd fd d1 e1 e fe ball "b1"
nandxxxxmx package mechanical 29/32 figure 12. tfbga149 10 13.5 x 1.2 mm - 12 16 active ball array, 0.80 mm pitch, package outline table 10. tfbga149 10 13.5 x 1.2 mm - 12 16 active ball array, 0.80 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a ? ? 1.20 ? ? 0.047 a1 ?0.25? ?0.012? a2 0.80 ? ? 0.031 ? ? b 0.45 0.40 0.50 0.018 0.016 0.020 d 10.00 9.90 10.10 0.394 0.390 0.398 d1 8.80 ? ? 0.346 ? ? ddd ? ? 0.10 ? ? ? e 13.50 13.40 13.60 0.531 0.528 0.535 e112.00? ?0.472? ? e0.80? ?0.031? ? fd 0.60 ? ? 0.024 ? ? fe 0.75 ? ? 0.029 ? ? sd 0.40 ? ? 0.016 ? ? se 0.40 ? ? 0.016 ? ? a2 a1 a bga-z78 ddd d e e b se fd fe e1 e sd d1 ball "a1"
package mechanical nandxxxxmx 30/32 figure 13. tfbga152 14 14 x 1.1 mm - 2r 21 x 21 , 0.65 mm pitch, package outline 1. drawing is not to scale. a2 a1 m3 ddd d e e b fd e1 d1 fe a table 11. tfbga152 14 14 x 1.1 mm - 2r 2 1 x 21, 0.65 mm pitch, mechanical data symbol millimeters inches typ min max typ min max a ? ?1.10? ?0.043 a1 ?0.32? ?0.013? a2 0.63 ? ? 0.025 ? ? b 0.42 0.37 0.47 0.016 0.015 0.018 ddd ? ? 0.10 ? ? 0.004 d 14.00 13.90 14.10 0.551 0.547 0.555 d1 13.00 ? ? 0.512 ? ? e 14.00 13.90 14.10 0.551 0.547 0.555 e1 13.00 ? ? 0.512 ? ? e0.65? ?0.026? ? f0.50? ?0.020? ?
nandxxxxmx ordering information 31/32 6 ordering information note: devices are shipped from the factory with t he flash memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest numonyx sales office. table 12. ordering information scheme example: nand8 8 r 3 m 0 a zbb 5 e device type nand flash memory nand flash density 8 = 256 mbits 9 = 512 mbits a = 1 gbit dram density 8 = 256 mbits 9 = 512 mbits nand flash operating voltage r = 1.7 v to 1.95 v w = 2.5 v to 3.6 v nand bus width 3 = x8 4 = x16 family identifier m = 528-byte page nand flash memory dram options 0 = sdr, x16, 133 mhz 1 = sdr, 32, 133 mhz 2 = ddr, x16, 133 mhz product version a b c package zba = tfbga149, 10 13.5 x 1.2 mm zbb = tfbga107 10.5 13 x 1.2 mm zbc = tfbga137 10.5 x 13 x 1.2 mm zpa = tfbga152, 14 14 x 1.1 mm temperature 5 = ?30 c to 85 c option e = ecopack? package, standard packing f = ecopack? package, tape and reel packing
revision history nandxxxxmx 32/32 7 revision history table 13. document revision history date version changes 29-jun-2006 1 initial release. 20-jul-2006 2 nand99r3m0 root part number added. tfbga137 package added. lpsdram input or output voltage and v ddd , v ddqd updated in table 6: absolute maximum ratings . 12-sep-2006 3 added nand99r3m0 to title; updated table 2: product list to show that nand98r3m0 is also delivered in package tfbga149. 19-sep-2006 4 added ?x32? to title description on page 1 10-oct-2006 5 root part numbers corrected in section 1.2: lpsdram component updated. 18-dec-2006 6 nand99w3m0 and nand99w3m1 root part numbers added. tfbga152 package on package (pop) added. v io and v ddf at 3v added in table 6: absolute maximum ratings . 19-feb-2007 7 dqm0, dqm2, dqm3 and dqm4 definition updated in table 4: signal names (tfbga107, tfbga137 and tfbga149 packages) . 12-jun-2007 8 added nanda9w3m1 root part number and added all respective data in table 2 , figure 1 , figure 2 , figure 7 , and figure 8 . table 3: lpsdram details is a new table that outlines the information on the lpsdam components. 7-aug-2007 9 added nand99r4m2 root part number and added/modified all associated data in table 1 , table 2 , table 3 , figure 1 , table 4 , figure 5 , figure 7 , figure 8 ; added the following new sections: section 2.2 , section 2.22 ; modified values in ta ble 6 , table 7 , table 8 , and table 9 . updated the part ordering information in table 11 . 22-jan-2008 10 added nand99r3m2, nand98w3m1, and nand98r3m1 part numbers and added/modified all associated data in table 1 , table 2 , table 3 , figure 1 , and figure 5 . applied numonyx branding. 24-jul-2008 11 added nand98r3m2 root part number. minor text changes. 26-sep-2008 12 added nand98r4m2 root part number. 03-oct-2008 13 added nand99r3m1 part number
nandxxxxmx 32/32 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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