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d a t a sh eet objective speci?cation file under integrated circuits, ic02 2001 oct 22 integrated circuits saa8103 pulse pattern generator for frame transfer ccd (ppgft)
2001 oct 22 2 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 contents 1 features 2 applications 3 general description 4 quick reference data 5 ordering information 6 block diagrams 7 pinning information 7.1 pinning 7.2 pin description 8 functional description 9 operating modes 9.1 full frame ccd 9.2 frame transfer ccd 9.3 standby control function 9.4 standby mode sequence 10 serial interfaces 10.1 control for v-driver (tda9991) and cds or adc 11 command list 12 timing diagrams 13 limiting values 14 thermal characteristics 15 dc characteristics 16 application information 17 package outline 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 data sheet status 20 definitions 21 disclaimers 22 purchase of philips i 2 c components
2001 oct 22 3 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 1 features sync signal generator supports progressive scan operation supports monitoring function supports electronic shutter function supports frame transfer ccd (fxa, ftf and ftt) 8 8-kbyte pixels (maximum) supports 1, 2 and 4 output functions with full frame ccd type sensor generates the system clock for signal processing base oscillation from 6 to 28 mhz i 2 c-bus control. 2 applications ccd camera digital still camera. 3 general description the saa8103 is a pulse pattern generator for the frame transfer ccd image sensors: fxa1012, fxa1013, fxa1022, fxa1004, ftf2020, ftf3020 and ftt1010 as well as for the front-end analog processing and signal processing circuit. the circuit generates drive pulses for the ccd, sample-hold pulses for correlated double sampling (cds), clamp pulses and sync signals. 4 quick reference data 5 ordering information symbol parameter min. typ. max. unit v dddx digital supply voltages: v ddd1 ,v ddd2 ,v ddd3 , v ddd4 and v dd(osc) 3.0 3.3 3.6 v v ddax analog supply voltages: v dda(buf1) , v dda(buf2) , v dda(buf3) , v dda(dll1) and v dda(dll2) 3.0 3.3 3.6 v i p(tot) total power supply current (f clk = 25 mhz) - 65 - ma v il low-level input voltages -- 0.8 v v ih high-level input voltages 2.3 - v dd v v ol low-level output voltages -- 0.5 v v oh high-level output voltages 2.3 - v dd v t amb operating ambient temperature range - 20 +25 +70 c type number package name description version SAA8103HL lqfp64 plastic low pro?le quad ?at package; 64 leads; body 10 10 1.4 mm sot314-2
2001 oct 22 4 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 6 block diagrams handbook, full pagewidth fce846 high speed pulse generator v-transfer pulse generator process pulse generator sync signal generator saa8103 i 2 c-bus and snert serial interface & mode control hf8 hf7 hf4 hf3 hf6 hf5 hf2 hf1 35 37 38 40 41 43 44 46 v dda(buf1) v ssa(buf1) 39 36 33 v dda(buf2) hf9 34 snen 63 sda_snda 62 a1 a2 a3 scl_sncl 61 sis 64 a4 b1 b2 b3 b4 28 27 26 25 23 22 21 20 cr vtlvl 29 24 tg 19 clp2 15 stb2 clp1 clkdc 58 14 17 reset 13 stb1 57 hd 7 vd 8 54 55 xin xout trg 11 6 test1 lockout tdscl 1 tdsda 2 encds2 3 endrv 5 encds1 4 intego 12 32 test2 v dda(dll1) 49 v ssa(dll1) v dda(dll2) v ssa(dll2) 50 51 52 v dd(osc) 53 v ss(osc) 56 48 v ddd1 v ssd1 10 9 v ddd2 v ssd2 18 16 v ddd3 v ssd3 31 30 v ddd4 v ssd4 60 59 v ssa(buf2) 42 45 v dda(buf3) v ssa(buf3) 47 fig.1 block diagram.
2001 oct 22 5 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 handbook, full pagewidth fce848 hf1 hf2 clp1 encds hf3 hd vd clp2 b4 b3 b2 b1 a4 a3 a2 a1 ccd(fxa, ftf, ftt) fxa1012, 1013, 1022 ftf2020, 3020 fxa1004, ftt1010 cds, agc, adc tda87xx tda99xx (1) v-driver tda9991 ppgft saa8103 dsp hf4 hf5 hf6 a1 a2 a3 a4 b1 b2 b3 b4 hf8 tg cr endrv tdscl, tdsda hf7 ccdout lens cds fig.2 system block diagram. (1) tda87xx = tda8783; tda8784; tda8786 and tda8787a tda99xx = tda9952; tda9956; tda9962; tda9964 and tda9965
2001 oct 22 6 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 7 pinning information 7.1 pinning handbook, full pagewidth saa8103 fce847 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 test1 a4 b3 tdscl encds2 trg a1 xout vd b4 sda_snda hf8 v ssa(buf1) v ssd3 scl_sncl a2 v ssd4 v ddd4 stb2 vtlvl xin tdsda endrv reset intego clp1 encds1 v ssd2 tg v ssa(buf2) hf7 v dda(buf2) hf6 v ssa(dll1) hf2 hf5 hf4 v ssa(buf3) hf3 v dda(dll2) v dd(osc) v ss(osc) hd clp2 clkdc cr b1 v dda(buf1) v ddd2 a3 v dda(buf3 ) test2 hf1 b2 v ddd3 hf9 v dda(dll1) lockout stb1 v ssa(dll2) sis snen v ddd1 v ssd1 fig.3 pin configuration.
2001 oct 22 7 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 7.2 pin description table 1 pin description for lqfp64 package symbol pin i/o description tdscl 1 o serial interface clock output for cds/adc and v-driver tdsda 2 o serial interface data output for cds/adc and v-driver endrv 3 o serial interface enable output for v-driver encds1 4 o serial interface enable output 1 for cds/adc encds2 5 o serial interface enable output 2 for cds/adc test1 6 i test input 1; normally connected to ground hd 7 i/o horizontal drive signal input or output; alternative function href signal output is controlled by the serial interface; see chapter 11, address 12 vd 8 i/o vertical drive signal input or output; alternative function vref signal output is controlled by the serial interface; see chapter 11, address 12 v ddd1 9 supply digital supply voltage 1 for core v ssd1 10 supply digital ground 1 for core trg 11 i trigger signal input intego 12 o integration time signal output reset 13 i power-on reset, normally connected to ground clp1 14 o optical black clamp control pulse output clp2 15 o clamp control pulse output for the analog-to-digital convertor (adc) v ddd2 16 supply digital supply voltage 2 clkdc 17 o clock signal output (for the dc-to-dc convertor of tda9991) v ssd2 18 supply digital ground 2 tg 19 o transfer gate pulse output a1 20 o clock output 1 for ccd vertical register drive a2 21 o clock output 2 for ccd vertical register drive a3 22 o clock output 3 for ccd vertical register drive a4 23 o clock output 4 for ccd vertical register drive cr 24 o charge reset pulse output b1 25 o clock output 1 for ccd vertical register drive b2 26 o clock output 2 for ccd vertical register drive b3 27 o clock output 3 for ccd vertical register drive b4 28 o clock output 4 for ccd vertical register drive vtlvl 29 o vertical transport level pulse output v ddd3 30 supply digital supply voltage 3 v ssd3 31 supply digital ground 3 test2 32 i test input 2; normally connected to ground v dda(buf1) 33 supply analog supply voltage for output buffer 1 hf9 34 o high frequency output 9 hf8 35 o high frequency output 8 v ssa(buf1) 36 supply analog ground for output buffer 1 hf7 37 o high frequency output 7
2001 oct 22 8 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 hf6 38 o high frequency output 6 v dda(buf2) 39 supply analog supply voltage for output buffer 2 hf5 40 o high frequency output 5 hf4 41 o high frequency output 4 v ssa(buf2) 42 supply analog ground for output buffer 2 hf3 43 o high frequency output 3 hf2 44 o high frequency output 2 v dda(buf3) 45 supply analog supply voltage for output buffer 3 hf1 46 o high frequency output 1 v ssa(buf3) 47 supply analog ground for output buffer 3 lockout 48 o lock indication of delayed locked loop (dll) v dda(dll1) 49 supply analog supply voltage for dll1 (core) v ssa(dll1) 50 supply analog ground for dll1 (core) v dda(dll2) 51 supply analog supply voltage for dll2 v ssa(dll2) 52 supply analog ground for dll2 v dd(osc) 53 supply digital supply voltage for crystal oscillator xin 54 i/o inverter input for crystal oscillator xout 55 i/o inverter output for crystal oscillator v ss(osc) 56 supply digital ground for crystal oscillator stb1 57 i standby control function inputs; see section 9.4 stb2 58 i v ddd4 59 supply digital supply voltage 4 v ssd4 60 supply digital ground 4 scl_sncl 61 i i 2 c-bus/snert serial interface clock input sda_snda 62 i/o i 2 c-bus/snert serial interface data input/output; 8 ma and 400 khz snen 63 i snert enable input sis 64 i i 2 c-bus/snert selection symbol pin i/o description
2001 oct 22 9 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 8 functional description the saa8103 is a drive pulse generator for the fxa1004, fxa1012, fxa1013, fxa1022, ftf2020, ftf3020 and the ftt1010. the saa8103 also drives the cds, adc front-end, v-driver and the digital signal processor (dsp). the system block diagram is shown in fig.2. the saa8103 generates horizontal and vertical drive signals, summing and reset gate pulses for each ccd, sample-hold pulses and clamp pulses for the front-end devices tda99xx and tda87xx (1) , and also generates sync signals hd and vd and the reference signals href and vref for the dsp. the saa8103 can also take sync signals hd and vd as external inputs, the drive signals generated will then be synchronized to these signals. the saa8103 is designed to operate with an 8192-line (maximum) 8192-pixel (maximum) rgb bayer ccd (fxa, ftf and ftt). progressive scan and sub-sampling modes for these ccds can be used. the device supports three different modes for the data read-out of each ccd: normal mode, shot mode and preview mode. the saa8103 also supports electronic shutter function and will provide exact settings of shutter speed and exposure time. the drive signals for ccd are generated from the main oscillator and range from 6 to 28 mhz. the drive signals are generated by a programmable generator from the main oscillator. the vertical drive signals are provided for the tda9991, horizontal drive signals are provided for the ccd directly or h-driver, sample-hold pulses and clamp pulses are provided for the tda99xx or tda87xx, sync signals hd, vd and reference signals href and vref are provided for the dsp. the drive pulses are controlled by a microcontroller via one of the serial interfaces (i 2 c-bus or snert). the saa8103 takes address and data from the i 2 c-bus or snert, and decodes these inputs for internal logic. it also decodes these inputs for the snert interface of the tda99xx, tda87xx and tda9991. the basic digital camera system consists of a ccd image sensor, a vertical driver and a pulse pattern generator (ppg) for the ccd, an analog front-end (cds, agc and adc) and digital signal processor. the high resolution digital camera system can be built using the ftf3020, tda9965 and tda9991 devices. (1) tda99xx = tda9952; tda9956; tda9962; tda9964; tda9965. tda87xx = tda8783; tda8784; tda8786; tda8787a
2001 oct 22 10 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 9 operating modes for full frame ccd and frame transfer ccd there are two modes for data read-out: shot mode and preview mode. shot mode is used to take an image using an external trigger signal; e.g. camera shutter. preview mode is used to take an image continuously with a fixed (preset) integration; e.g. to show an image on the lcd display of a digital still camera (dsc). 9.1 full frame ccd in the shot mode, the saa8103 takes the external input signal trg, as the trigger signal. after the rising edge of trg, the charge reset pulses (cr) are generated for the appropriate period. integration time is held until the falling edge of the trg signal. a drive signal is generated in each vd period but is not issued until the next event of the trg signal. in the preview mode, the saa8103 generates a drive signal in every frame. the preview mode it is not influenced by the trg signal. the integration time is controlled using the inttime command; see chapter 11, addresses 1 and 2. the shot mode and preview mode for full frame ccd is shown in fig.4. handbook, full pagewidth fce854 trg cr shot mode preview mode vd vd cr data read-out data read-out integration time integration time fig.4 data read-out of full frame ccd.
2001 oct 22 11 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 9.2 frame transfer ccd in the shot mode, the saa8103 takes the external input signal trg, as the trigger signal. after the rising edge of trg the reset gate pulses (cr) are generated for the appropriate period. integration time is held until the falling edge of trg. a drive signal is generated in each vd period but is not issued until the next event of the trg signal. in the preview mode, the saa8103 generates a drive signal in every frame. the preview mode is not influenced by the trg signal. the integration time is controlled using the inttime and exptime command; see chapter 11, addresses 1, 2, 3 and 4. the shot mode and preview mode for frame transfer ccd is shown in fig.5. handbook, full pagewidth fce855 trg cr shot mode preview mode vd vd cr data read-out data read-out integration time integration time fig.5 data read-out of frame transfer ccd.
2001 oct 22 12 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 9.3 standby control function the saa8103 has two external inputs stb1 and stb2 which are used to select the standby control mode, as shown in table 2. table 2 selection of standby control mode 9.4 standby modes 9.4.1 s tandby mode 1 when standby mode 1 is selected, the internal signal hfen1 is inactive (off-state) and the data for hf1 to hf3 is masked. consequently, the outputs of hf1 to hf3 are held low when standby mode 1 is active. 9.4.2 s tandby mode 2 when standby mode 2 is selected, the internal signal hfen2 is inactive (off-state) and the data for hf4 to hf9 is masked. consequently, the outputs hf4 to hf9 are held low when standby mode 2 is active. 9.4.3 s tandby mode 3 when standby mode 3 is selected, the internal signals hfen1, hfen2 and vfen are inactive (off-state) and the data for hf1 to hf9 is masked. consequently, the outputs hf1 to hf9 are held low when standby mode 3 is active. the effect of vfen being inactive (off-state) is described below. figure 7 shows the effect of standby mode 3 on the preview mode. when the standby mode 3 is applied on preview mode, both the v_counter and h_counter are halted. the output signals hold their last state until standby mode 3 is released. all output signals operate continuously after the release of standby mode 3. this situation also applies when standby mode 3 is selected whilst in shot mode. figure 8 shows the effect of an operation change from preview mode to shot mode during standby mode 3. in this situation, both the v_counter and h_counter are reset by the timing of shot mode detection, and all output signals are reset. the operation is changed to idle state after the release from standby mode 3. the saa8103 is now ready to accept the trig signal for shot mode operation. stb2 stb1 mode conditions 0 0 normal hfen1 = on; hfen2 = on; vfen = on 0 1 standby mode 1 hfen1 = off; hfen2 = on; vfen = on 1 0 standby mode 2 hfen1 = on; hfen2 = off; vfen = on 1 1 standby mode 3 hfen1 = off; hfen2 = off; vfen = off handbook, full pagewidth fce856 stb1 power-down control module analog (dll) module digital module hfen1 hfen2 vfen stb2 fig.6 ccd standby control block diagram.
2001 oct 22 13 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth fce857 a1, a2 hd a3, a4 b1, b2 b3, b4 vd 1 1 1 1 1 315/0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 22 21 314 313 312 311 310 309 299 300 301 302 303 304 305 309 310 311 312 313 314 315/0 1 2 3 4 5 306 307 308 119 120 121 122 123 294 295 296 297 298 109 110 111 112 113 114 115 116 117 118 v_counter cr 112 clp1/clp2 stb1 stb2 mode preview preview standby fig.7 ft ccd v-driver timing in preview mode with standby mode 3.
2001 oct 22 14 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... fce858 handbook, full pagewidth a1, a2 hd a3, a4 b1, b2 b3, b4 vd 1 1 1 1 1 1 315/0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 0 314 313 312 311 310 309 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 v_counter cr stb1 stb2 trig mode preview shot standby idle fig.8 ft ccd v-driver timing during change from preview to shot mode with standby mode 3.
2001 oct 22 15 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 10 serial interfaces the saa8103 has two means by which it can communicate with a microcontroller: the i 2 c-bus serial interface and the snert serial interface. the selection of the serial interface is determined by the state of the signal on the sis pin; see table 3. the cds/adc1, cds/adc2 and the v-driver are programmed by a series of commands sent via one of these interfaces. the command list is given in table 4. address and data decoding for the internal logic is carried out within the serial interface block. the ccd transfer pattern data is sent to the serial interface block and is held in one of two registers: register 0 or register 1. register 0 is used to store data when the device is in the shot mode. register 1 is used to store data when the device is in the preview mode. consequently, before any data can be sent, register 0 or register 1 must be selected by writing the appropriate data to address 200. the transfer pattern signal will be loaded by the data read out mode and the trg signal input. the signal flow between the saa8103 and the front-end ics is shown in fig.9. table 3 serial interface selection sis sda_snda scl_sncl snen interface selected 0i 2 c-bus data i 2 c-bus clock - i 2 c-bus; slave address 4eh 1 snert data snert clock snert enable snert handbook, full pagewidth sis snen sda_snda scl_sncl tdsda tdscl encds1 endrv encds2 fce859 saa8103 cds/adc1 (tda9965) cds/adc2 (tda9965) v-driver (tda9991) fig.9 signal flow between the saa8103 and front-end ics.
2001 oct 22 16 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 10.1 control for v-driver (tda9991) and cds or adc the saa8103 can control the v-driver (tda9991) and the cds/adc (tda99xx and tda87xx) via the i 2 c-bus serial interface. handbook, full pagewidth fce860 tdsda endrv tdscl i 2 c-bus interface address 9 a2 a1 a0 d4 d3 d2 d1 d0 a2 a1 a0 d4 d3 d2 d1 d0 fig.10 serial interface for v-driver (tda9991). handbook, full pagewidth fce861 tdsda (tda9964, tda9962, tda9956, tda9952) encds1 encds2 tdscl a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i 2 c-bus interface address 5 and 7 i 2 c-bus interface address 6 and 8 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 fig.11 serial interface timing for cds or adc (tda9964, 62, 56 and 52).
2001 oct 22 17 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 handbook, full pagewidth fce862 tdsda (tda8783, tda8784, tda8786) tdscl a2 a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 -- - sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 control the length of enable signals encds1 encds2 i 2 c-bus interface address 5 and 7 i 2 c-bus interface address 6 and 8 fig.12 serial interface timing for cds or adc (tda8783, 84 and 86). handbook, full pagewidth fce863 tdsda (tda9965, tda8787a) tdscl a1 a0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 - -- - sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 sd15 sd14 sd13 sd12 sd11 sd10 sd9 sd8 control the length of enable signals encds1 encds2 i 2 c-bus interface address 5 and 7 i 2 c-bus interface address 6 and 8 fig.13 serial interface timing for cds or adc (tda9965 and tda8787a).
2001 oct 22 18 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 11 command list table 4 the command list for the serial interfaces: i 2 c-bus and snert address command bit command description operating settings 0 (1) 0 operational mode selection. 0 = shot mode selected; default state 1 = preview mode selected 1 ccd type selection. 0 = ft type ccd 1 = ff type ccd; default state 2 to 3 these 2 bits are reserved. 4 sub-sampling function enable. 0 = sub-sampling off in ft type ccd; default state 1 = sub-sampling on in ft type ccd 5 electronic shutter setting (inttimeon). 0 = integration time is on; default state 1 = integration time is off 1 (1) 7to0 integration time setting (inttime). the data provided by these two commands is combined to form the 13-bit integration time setting. the integration time setting has a range from 0 to 8191; the default value is 3. it is calculated by the following expression: integration time = setting value hd period 2 (1) 4to0 3 (1) 7to0 exposure time setting for ft ccd (exptime). the data provided by these two commands is combined to form the 13-bit exposure time setting. the exposure time setting has a range from 0 to 8191; the default value is 3. it is calculated by the following expression: exposure time = vd period - (setting value hd period) 4 (1) 4to0
2001 oct 22 19 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 setting address, data and enable for serial i/f of analog preprocessing 5 (1) 7to0 serial data setting for cds1 and adc1. the data provided by these two commands is combined to form the 16-bit serial data setting. the data written to address 5 provides serial data sd7 to sd0. the data written to address 6 provides serial data sd15 to sd8. the default value of both commands is 0. 6 (1) 7to0 7 (1) 7to0 serial data setting for cds2 and adc2. the data provided by these two commands is combined to form the 16-bit serial data setting. the data written to address 7 provides serial data sd7 to sd0. the data written to address 8 provides serial data sd15 to sd8. the default value of both commands is 0. 8 (1) 7to0 9 (1) 4to0 data setting for v-driver. these 5 bits (d4 to d0) provide the data setting for the v-driver. the default value is 0. 7to5 address setting for v-driver. these 3 bits (a2 to a0) provide the address for the v-driver. the default value is 0. 10 (1) 7to0 assign the division value of tdscl generator for tdscl output (divtdscl). these 8 bits determine the division value for the tdscl generator. the default value is 3. 11 (1) 0 control signal of serial interface data output (tdsda) for cds or adc. 0 = enable; default state 1 = disable 1 control signal of serial interface clock output (tdscl) for cds or adc. 0 = enable; default state 1 = disable 4 enable signal for cds1 and adc1 (encds1) enable control (cd1enbon). 0 = enable; default state 1 = disable 5 enable signal for cds2 and adc2 (encds2) enable control (cd2enbon). 0 = enable; default state 1 = disable 6 enable signal for v-driver (endrv) enable control (drvenbon). 0 = enable; default state 1 = disable 7 control signal for 3-wire interface (gate3won). 0 = enable; default state 1 = disable address command bit command description
2001 oct 22 20 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 12 (1) 7to4 control the length of enable signals for encds1, encds2 and endrv. 0000 = 12 bits are generated for cds; default state 0010 = 13 bits are generated for cds 0100 = 14 bits are generated for cds 0110 = 15 bits are generated for cds 1000 = 16 bits are generated for cds 0001 = 8 bits are generated for v-driver; default state 0011 = 9 bits are generated for v-driver 0101 = 10 bits are generated for v-driver 0111 = 11 bits are generated for v-driver 1001 = 12 bits are generated for v-driver 1011 = 13 bits are generated for v-driver 1101 = 14 bits are generated for v-driver 1111 = 15 bits are generated for v-driver 2to0 hd, vd and href and vref polarity (hdvdint). 000 = internal mode; negative hd and vd output 001 = internal mode; negative href and vref output 010 = internal mode; positive hd and vd output; default state 011 = internal mode; positive href and vref output 100 = external mode; negative hd input and negative vd output 101 = external mode; negative hd and vd inputs 110 = external mode; positive hd input and positive vd output 111 = external mode; positive hd and vd inputs setting the start and stop points for process timing 13 7 to 0 horizontal sync period (hs). the data provided by these two commands is combined to form the 13-bit horizontal sync period setting. the data written to address 13 provides data d7 to d0. the data written to address 14 provides data d12 to d8. the horizontal sync period setting has a range from 0 to 8191. the default value is 3487. 14 4 to 0 15 7 to 0 vertical sync period (vs). the data provided by these two commands is combined to form the 13-bit vertical sync period setting. the data written to address 15 provides data d7 to d0. the data written to address 16 provides data d12 to d8. the vertical sync period setting has a range from 0 to 8191. the default value is 2060. 16 4 to 0 17 7 to 0 hd stop (hdstp) . the hd stop setting has a range from 0 to 255. the default value is 4. the hd stop value is calculated as shown below. hd stop point = 2 assigned value 18 7 to 0 vd stop (vdstp). the vd stop setting has a range from 0 to 255. the default value is 4. the vd stop value is calculated as shown below. vd stop point = 2 assigned value address command bit command description
2001 oct 22 21 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 19 7 to 0 href start (hrefstr). the href start setting has a range from 0 to 255. the default value is 4. the href start value is calculated as shown below. href start point = 2 assigned value 20 7 to 0 href stop (hrefstp). the data provided by these two commands is combined to form the 13-bit href stop setting. the data written to address 20 provides data d7 to d0. the data written to address 21 provides data d12 to d8. the href stop setting has a range from 0 to 8191. the default value is 0. 21 4 to 0 22 7 to 0 vref start (vrefstr). the data provided by these two commands is combined to form the 13-bit vref start setting. the data written to address 22 provides data d7 to d0. the data written to address 23 provides data d12 to d8. the vref start setting has a range from 0 to 8191. the default value is 4. 23 4 to 0 24 7 to 0 vref stop (vrefstp). the data provided by these two commands is combined to form the 13-bit vref stop setting. the data written to address 24 provides data d7 to d0. the data written to address 25 provides data d12 to d8. the vref stop setting has a range from 0 to 8191. the default value is 0. 25 4 to 0 setting the start and stop points for internal signal ssc 26 7 to 0 ssc start (sscstr). the ssc start setting has a range from 0 to 255. the default value is 0. the ssc start value is calculated as shown below. ssc start point = 2 assigned value 27 7 to 0 ssc stop (sscstp). the data provided by these two commands is combined to form the 13-bit ssc stop setting. the data written to address 27 provides data d7 to d0. the data written to address 28 provides data d12 to d8. the ssc stop setting has a range from 0 to 8191. the default value is 360. 28 4 to 0 setting the start and stop points for clamp timings 29 7 to 0 horizontal direction at the left clamp pulse 1 start (hlclpstr1). the data provided by these two commands is combined to form the 13-bit hlclpstr1 setting. the data written to address 29 provides data d7 to d0. the data written to address 30 provides data d12 to d8. the hlclpstr1 setting has a range from 0 to 8191. the default value is 371. 30 4 to 0 31 7 to 0 horizontal direction at the left clamp pulse 1 stop (hlclpstp1). the data provided by these two commands is combined to form the 13-bit hlclpstp1 setting. the data written to address 31 provides data d7 to d0. the data written to address 32 provides data d12 to d8. the hlclpstp1 setting has a range from 0 to 8191. the default value is 383. 32 4 to 0 33 7 to 0 horizontal direction at the right clamp pulse 1 start (hrclpstr1). the data provided by these two commands is combined to form the 13-bit hrclpstr1 setting. the data written to address 33 provides data d7 to d0. the data written to address 34 provides data d12 to d8. the hrclpstr1 setting has a range from 0 to 8191. the default value is 3470. 34 4 to 0 address command bit command description
2001 oct 22 22 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 35 7 to 0 horizontal direction at the right clamp pulse 1 stop (hrclpstp1). the data provided by these two commands is combined to form the 13-bit hrclpstp1 setting. the data written to address 35 provides data d7 to d0. the data written to address 36 provides data d12 to d8. the hrclpstp1 setting has a range from 0 to 8191. the default value is 3484. 36 4 to 0 37 7 to 0 horizontal direction at the left clamp pulse 2 start (hlclpstr2). the data provided by these two commands is combined to form the 13-bit hlclpstr2 setting. the data written to address 37 provides data d7 to d0. the data written to address 38 provides data d12 to d8. the hlclpstr2 setting has a range from 0 to 8191. the default value is 371. 38 4 to 0 39 7 to 0 horizontal direction at the left clamp pulse 2 stop (hlclpstp2). the data provided by these two commands is combined to form the 13-bit hlclpstp2 setting. the data written to address 39 provides data d7 to d0. the data written to address 40 provides data d12 to d8. the hlclpstp2 setting has a range from 0 to 8191. the default value is 383. 40 4 to 0 41 7 to 0 horizontal direction at the right clamp pulse 2 start (hrclpstr2). the data provided by these two commands is combined to form the 13-bit hrclpstr2 setting. the data written to address 41 provides data d7 to d0. the data written to address 42 provides data d12 to d8. the hrclpstr2 setting has a range from 0 to 8191. the default value is 3470. 42 4 to 0 43 7 to 0 horizontal direction at the right clamp pulse 2 stop (hrclpstp2). the data provided by these two commands is combined to form the 13-bit hrclpstp2 setting. the data written to address 43 provides data d7 to d0. the data written to address 44 provides data d12 to d8. the hrclpstp2 setting has a range from 0 to 8191. the default value is 3484. 44 4 to 0 45 7 to 0 vertical direction at the top clamp pulse 1 start (vtclpstr1). the vtclpstr1 setting has a range from 0 to 255. the default value is 3. 46 7 to 0 vertical direction at the top clamp pulse 1 stop (vtclpstp1). the vtclpstp1 setting has a range from 0 to 255. the default value is 4. 47 7 to 0 vertical direction at the top clamp pulse 1 horizontal start (vthclpstr1). the data provided by these two commands is combined to form the 13-bit vthclpstr1 setting. the data written to address 47 provides data d7 to d0. the data written to address 48 provides data d12 to d8. the vthclpstr1 setting has a range from 0 to 8191. the default value is 0. 48 4 to 0 49 7 to 0 vertical direction at the top clamp pulse 1 horizontal stop (vthclpstp1). the data provided by these two commands is combined to form the 13-bit vthclpstp1 setting. the data written to address 49 provides data d7 to d0. the data written to address 50 provides data d12 to d8. the vthclpstp1 setting has a range from 0 to 8191. the default value is 0. 50 4 to 0 51 7 to 0 vertical direction at the bottom clamp pulse 1 start (vbclpstr1). the data provided by these two commands is combined to form the 13-bit vbclpstr1 setting. the data written to address 51 provides data d7 to d0. the data written to address 52 provides data d12 to d8. the vthclpstr1 setting has a range from 0 to 8191. the default value is 2060. 52 4 to 0 address command bit command description
2001 oct 22 23 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 53 7 to 0 vertical direction at the bottom clamp pulse 1 stop (vbclpstp1). the data provided by these two commands is combined to form the 13-bit vbclpstp1 setting. the data written to address 53 provides data d7 to d0. the data written to address 54 provides data d12 to d8. the vbclpstp1 setting has a range from 0 to 8191. the default value is 0. 54 4 to 0 55 7 to 0 vertical direction at the bottom clamp pulse 1 horizontal start (vbhclpstr1) . the data provided by these two commands is combined to form the 13-bit vbhclpstr1 setting. the data written to address 55 provides data d7 to d0. the data written to address 56 provides data d12 to d8. the vbhclpstr1 setting has a range from 0 to 8191. the default value is 0. 56 4 to 0 57 7 to 0 vertical direction at the bottom clamp pulse 1 horizontal stop (vbhclpstp1). the data provided by these two commands is combined to form the 13-bit vbhclpstp1 setting. the data written to address 57 provides data d7 to d0. the data written to address 58 provides data d12 to d8. the vbhclpstp1 setting has a range from 0 to 8191. the default value is 0. 58 4 to 0 59 7 to 0 vertical direction at the top clamp pulse 2 start (vtclpstr2). the vtclpstr2 setting has a range from 0 to 255. the default value is 3. 60 7 to 0 vertical direction at the top clamp pulse 2 stop (vtclpstp2). the vtclpstp2 setting has a range from 0 to 255. the default value is 4. 61 7 to 0 vertical direction at the top clamp pulse 2 horizontal start (vthclpstr2). the data provided by these two commands is combined to form the 13-bit vthclpstr2 setting. the data written to address 61 provides data d7 to d0. the data written to address 62 provides data d12 to d8. the vthclpstr2 setting has a range from 0 to 8191. the default value is 0. 62 4 to 0 63 7 to 0 vertical direction at the top clamp pulse 2 horizontal stop (vthclpstp2). the data provided by these two commands is combined to form the 13-bit vthclpstp2 setting. the data written to address 63 provides data d7 to d0. the data written to address 64 provides data d12 to d8. the vthclpstp2 setting has a range from 0 to 8191. the default value is 0. 64 4 to 0 65 7 to 0 vertical direction at the bottom clamp pulse 2 start (vbclpstr2). the data provided by these two commands is combined to form the 13-bit vbclpstr2 setting. the data written to address 65 provides data d7 to d0. the data written to address 66 provides data d12 to d8. the vbclpstr2 setting has a range from 0 to 8191. the default value is 2060. 66 4 to 0 67 7 to 0 vertical direction at the bottom clamp pulse 2 stop (vbclpstp2). the data provided by these two commands is combined to form the 13-bit vbclpstp2 setting. the data written to address 67 provides data d7 to d0. the data written to address 68 provides data d12 to d8. the vbclpstp2 setting has a range from 0 to 8191. the default value is 0. 68 4 to 0 69 7 to 0 vertical direction at the bottom clamp pulse 2 horizontal start (vbhclpstr2). the data provided by these two commands is combined to form the 13-bit vbhclpstr2 setting. the data written to address 69 provides data d7 to d0. the data written to address 70 provides data d12 to d8. the vbhclpstr2 setting has a range from 0 to 8191. the default value is 0. 70 4 to 0 address command bit command description
2001 oct 22 24 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 71 7 to 0 vertical direction at the bottom clamp pulse 2 horizontal stop (vbhclpstp2). the data provided by these two commands is combined to form the 13-bit vbhclpstp2 setting. the data written to address 71 provides data d7 to d0. the data written to address 72 provides data d12 to d8. the vbhclpstp2 setting has a range from 0 to 8191. the default value is 0. 72 4 to 0 setting the start and stop points for charge reset timings 73 7 to 0 horizontal direction charge reset pulse start (hcrstr). the data provided by these two commands is combined to form the 13-bit hcrstr setting. the data written to address 73 provides data d7 to d0. the data written to address 74 provides data d12 to d8. the hcrstr setting has a range from 0 to 8191. the default value is 371. 74 4 to 0 75 7 to 0 horizontal direction charge reset pulse stop (hcrstp). the data provided by these two commands is combined to form the 13-bit hcrstp setting. the data written to address 75 provides data d7 to d0. the data written to address 76 provides data d12 to d8. the hcrstp setting has a range from 0 to 8191. the default value is 383. 76 4 to 0 77 7 to 0 horizontal direction vtlvl pulse start (hvtlstr). the data provided by these two commands is combined to form the 13-bit hvtlstr setting. the data written to address 77 provides data d7 to d0. the data written to address 78 provides data d12 to d8. the hvtlstr setting has a range from 0 to 8191. the default value is 371. 78 4 to 0 79 7 to 0 horizontal direction vtlvl pulse stop (hvtlstp). the data provided by these two commands is combined to form the 13-bit hvtlstp setting. the data written to address 79 provides data d7 to d0. the data written to address 80 provides data d12 to d8. the hvtlstp setting has a range from 0 to 8191. the default value is 383. 80 4 to 0 81 7 to 0 vertical direction at the top charge reset pulse start (vtcrstr). the vtcrstr setting (d7 to d0) has a range from 0 to 255. the default value is 3 82 7 to 0 vertical direction at the top charge reset pulse stop (vtcrstp). the vtcrstp setting (d7 to d0) has a range from 0 to 255. the default value is 4. 83 7 to 0 vertical direction at the bottom charge reset pulse start (vbcrstr). the data provided by these two commands is combined to form the 13-bit vbcrstr setting. the data written to address 83 provides data d7 to d0. the data written to address 84 provides data d12 to d8. the vbcrstr setting has a range from 0 to 8191. the default value is 2060. 84 4 to 0 85 7 to 0 vertical direction at the bottom charge reset pulse stop (vbcrstp). the data provided by these two commands is combined to form the 13-bit vbcrstp setting. the data written to address 85 provides data d7 to d0. the data written to address 86 provides data d12 to d8. the vbcrstp setting has a range from 0 to 8191. the default value is 0. 86 4 to 0 87 7 to 0 vertical direction at the top vtlvl pulse start (vtvtlstr). the vtvtlstr setting (d7 to d0) has a range from 0 to 255. the default value is 3. 88 7 to 0 vertical direction at the top vtlvl pulse stop (vtvtlstp). the vtvtlstp setting (d7 to d0) has a range from 0 to 255. the default value is 4. address command bit command description
2001 oct 22 25 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 89 7 to 0 vertical direction at the bottom vtlvl pulse start (vbvtlstr). the data provided by these two commands is combined to form the 13-bit vbvtlstr setting. the data written to address 89 provides data d7 to d0. the data written to address 90 provides data d12 to d8. the vbvtlstr setting has a range from 0 to 8191. the default value is 2060. 90 4 to 0 91 7 to 0 vertical direction at the bottom vtlvl pulse stop (vbvtlstp). the data provided by these two commands is combined to form the 13-bit vbvtlstp setting. the data written to address 91 provides data d7 to d0. the data written to address 92 provides data d12 to d8. the vbvtlstp setting has a range from 0 to 8191. the default value is 0. 92 4 to 0 setting enable for clamp pulse and charge reset pulse 93 0 vertical direction at the top of clamp pulse 1 enable control (vtclpen1). 0 = enable; default state 1 = disable 1 vertical direction at the bottom of clamp pulse 1 enable control (vbclpen1). 0 = enable; default state 1 = disable 2 vertical direction at the top of clamp pulse 2 enable control (vtclpen2). 0 = enable; default state 1 = disable 3 vertical direction at the bottom of clamp pulse 2 enable control (vbclpen2). 0 = enable; default state 1 = disable 4 vertical direction at the top of charge reset pulse enable control (vtcren). 0 = enable 1 = disable; default state 5 vertical direction at the bottom of charge reset pulse enable control (vbcren). 0 = enable 1 = disable; default state 6 vertical direction at the top of vtlvl pulse enable control (vtvtlen). 0 = enable 1 = disable; default state 7 vertical direction at the bottom of vtlvl pulse enable control (vbvtlen). 0 = enable 1 = disable; default state address command bit command description
2001 oct 22 26 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 setting polarity for clamp pulse and charge reset pulse 94 0 trgcrp enable signal (trgcrpen). 0 = disable 1 = enable; default state 4 clamp pulse 1 polarity (clppola1). 0 = negative 1 = positive; default state 5 clamp pulse 2 polarity (clppola2). 0 = negative 1 = positive; default state 6 charge reset pulse polarity (crpola). 0 = negative 1 = positive; default state 7 vtlvl pulse polarity (vtlvpola). 0 = negative 1 = positive; default state 95 7 to 0 data read-out timing control (rdtimcnt). the data read out delay control setting has a range 0 to 255. the default value is 0. setting for vertical transport signals a[1:4] and b[1:4] a ssign state pattern for l ine shift state machine for a pulses (lutlsa) 96 3 to 0 state 0; default value = 1 7 to 4 state 1; default value = 3 97 3 to 0 state 2; default value = 2 7 to 4 state 3; default value = 6 98 3 to 0 state 4; default value = 4 7 to 4 state 5; default value = 12 99 3 to 0 state 6; default value = 8 7 to 4 state 7; default value = 9 a ssign state pattern for f rame shift state machine for a pulses (lutfsa) 100 3 to 0 state 0; default value = 1 7 to 4 state 1; default value = 3 101 3 to 0 state 2; default value = 2 7 to 4 state 3; default value = 6 102 3 to 0 state 4; default value = 4 7 to 4 state 5; default value = 12 103 3 to 0 state 6; default value = 8 7 to 4 state 7; default value = 9 address command bit command description
2001 oct 22 27 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 a ssign state pattern for l ine shift state machine for b pulses (lutlsb) 104 3 to 0 state 0; default value = 0 7 to 4 state 1; default value = 0 105 3 to 0 state 2; default value = 0 7 to 4 state 3; default value = 0 106 3 to 0 state 4; default value = 0 7 to 4 state 5; default value = 0 107 3 to 0 state 6; default value = 0 7 to 4 state 7; default value = 0 a ssign state pattern for f rame shift state machine for b pulses (lutfsb) 108 3 to 0 state 0; default value = 0 7 to 4 state 1; default value = 0 109 3 to 0 state 2; default value = 0 7 to 4 state 3; default value = 0 110 3 to 0 state 4; default value = 0 7 to 4 state 5; default value = 0 111 3 to 0 state 6; default value = 0 7 to 4 state 7; default value = 0 112 5 to 0 assign the division value of clock divider for ls sequence for a pulses (divlsa). the divlsa setting has a range of 0 to 63. the default value is 2. 113 5 to 0 assign the division value of clock divider for ls sequence for b pulses (divlsb). the divlsb setting has a range of 0 to 63. the default value is 2. 114 5 to 0 assign the division value of clock divider for fs sequence for a and b pulses (divfsab). the divfsab setting has a range of 0 to 63. the default value is 7. 115 7 to 0 assign the up point of start signal for ls sequence for a pulses in horizontal direction (hlsastr). the hlsastr setting has a range of 0 to 255. the default value is 0. 116 7 to 0 assign the up point of start signal for ls sequence for b pulses in horizontal direction (hlsbstr). the hlsbstr setting has a range of 0 to 255. the default value is 0. 117 7 to 0 assign the up point of start signal for fs sequence for a pulses in horizontal direction (hfsastr). the hfsastr setting has a range of 0 to 255. the default value is 0. 118 7 to 0 assign the up point of start signal for fs sequence for b pulses in horizontal direction (hfsbstr). the hfsbstr setting has a range of 0 to 255. the default value is 0. address command bit command description
2001 oct 22 28 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 119 7 to 0 assign the up point of start signal 1 for ls sequence for a pulses in vertical direction (vlsastr1). the data provided by these two commands is combined to form the 13-bit vlsastr1 setting. the data written to address 119 provides data d7 to d0. the data written to address 120 provides data d12 to d8. the vlsastr1 setting has a range from 0 to 8191. the default value is 13. 120 4 to 0 121 7 to 0 assign the down point of stop signal 1 for ls sequence for a pulses in vertical direction (vlsastp1). the data provided by these two commands is combined to form the 13-bit vlsastp1 setting. the data written to address 121 provides data d7 to d0. the data written to address 122 provides data d12 to d8. the vlsastp1 setting has a range from 0 to 8191. the default value is 200. 122 4 to 0 123 7 to 0 assign the up point of start signal 2 for ls sequence for a pulses in vertical direction (vlsastr2). the data provided by these two commands is combined to form the 13-bit vlsastr2 setting. the data written to address 123 provides data d7 to d0. the data written to address 124 provides data d12 to d8. the vlsastr2 setting has a range from 0 to 8191. the default value is 1fffh (disable). 124 4 to 0 125 7 to 0 assign the down point of stop signal 2 for ls sequence for a pulses in vertical direction (vlsastp2). the data provided by these two commands is combined to form the 13-bit vlsastp2 setting. the data written to address 125 provides data d7 to d0. the data written to address 126 provides data d12 to d8. the vlsastp2 setting has a range from 0 to 8191. the default value is 240. 126 4 to 0 127 7 to 0 assign the up point of start signal 3 for ls sequence for a pulses in vertical direction (vlsastr3). the data provided by these two commands is combined to form the 13-bit vlsastr3 setting. the data written to address 127 provides data d7 to d0. the data written to address 128 provides data d12 to d8. the vlsastr3 setting has a range from 0 to 8191. the default value is 1fffh (disable). 128 4 to 0 129 7 to 0 assign the down point of stop signal 3 for ls sequence for a pulses in vertical direction (vlsastp3). the data provided by these two commands is combined to form the 13-bit vlsastp3 setting. the data written to address 129 provides data d7 to d0. the data written to address 130 provides data d12 to d8. the vlsastp3 setting has a range from 0 to 8191. the default value is 260. 130 4 to 0 131 7 to 0 assign the up point of start signal for ls sequence for b pulses in vertical direction (vlsbstr). the data provided by these two commands is combined to form the 13-bit vlsbstr setting. the data written to address 131 provides data d7 to d0. the data written to address 132 provides data d12 to d8. the vlsbstr setting has a range from 0 to 8191. the default value is 13. 132 4 to 0 133 7 to 0 assign the down point of stop signal for ls sequence for b pulses in vertical direction (vlsbstp). the data provided by these two commands is combined to form the 13-bit vlsbstp setting. the data written to address 133 provides data d7 to d0. the data written to address 134 provides data d12 to d8. the vlsbstp setting has a range from 0 to 8191. the default value is 200. 134 4 to 0 address command bit command description
2001 oct 22 29 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 135 7 to 0 assign the up point of start signal for fs sequence for a pulses in vertical direction (vfsastr). the vfsastr setting has a range from 0 to 255. the default value is 1. 136 7 to 0 assign the up point of start signal for fs sequence for b pulses in vertical direction (vfsbstr). the vfsbstr setting has a range from 0 to 255. the default value is 1. 137 3 to 0 assign the count value of ls counter_a1 for image gate waveform generation (cntlsa1). the cntlsa1 setting has a range from 0 to 15. the default value is 1. 138 3 to 0 assign the count value of ls counter_a2 for image gate waveform generation (cntlsa2). the cntlsa2 setting has a range from 0 to 15. the default value is 1. 139 3 to 0 assign the count value of ls counter_a3 for image gate waveform generation (cntlsa3). the cntlsa3 setting has a range from 0 to 15. the default value is 1. 140 7 to 0 assign the count value of fs counter_a for storage gate waveform generation (cntfsa). the data provided by these two commands is combined to form the 13-bit cntfsa setting. the data written to address 140 provides data d7 to d0. the data written to address 141 provides data d12 to d8. the cntfsa setting has a range from 0 to 8191. the default value is 0. 141 4 to 0 142 3 to 0 assign the count value of ls counter_b for storage gate waveform generation (cntlsb). the cntlsb setting has a range of 0 to 15. the default value is 0. 143 7 to 0 assign the count value of fs counter_b for storage gate waveform generation (cntfsb). the data provided by these two commands is combined to form the 13-bit cntfsb setting. the data written to address 143 provides data d7 to d0. the data written to address 141 provides data d12 to d8. the cntfsb setting has a range from 0 to 8191. the default value is 0. 144 4 to 0 145 7 to 0 assign the up point of tg signal for horizontal direction (htgstr). the data provided by these two commands is combined to form the 13-bit htgstr setting. the data written to address 145 provides data d7 to d0. the data written to address 146 provides data d12 to d8. the htgstr setting has a range from 0 to 8191. the default value is 0. 146 4 to 0 147 7 to 0 assign the down point of tg signal for horizontal direction (htgstp). the data provided by these two commands is combined to form the 13-bit htgstp setting. the data written to address 147 provides data d7 to d0. the data written to address 148 provides data d12 to d8. the htgstp setting has a range from 0 to 8191. the default value is 0. 148 4 to 0 149 7 to 0 assign the up point of tg signal for vertical direction (vtgstr). the data provided by these two commands is combined to form the 13-bit vtgstr setting. the data written to address 149 provides data d7 to d0. the data written to address 150 provides data d12 to d8. the vtgstr setting has a range from 0 to 8191. the default value is 6. 150 4 to 0 address command bit command description
2001 oct 22 30 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 151 7 to 0 assign the down point of tg signal for vertical direction (vtgstp). the data provided by these two commands is combined to form the 13-bit vtgstp setting. the data written to address 151 provides data d7 to d0. the data written to address 152 provides data d12 to d8. the vtgstp setting has a range from 0 to 8191. the default value is 2054. 152 4 to 0 153 7 to 0 assign the up point of start_sp1 signal for sub-sampling waveform generation sequence for b pulse (spstr1). the data provided by these two commands is combined to form the 13-bit spstr1 setting. the data written to address 153 provides data d7 to d0. the data written to address 154 provides data d12 to d8. the spstr1 setting has a range from 0 to 8191. the default value is 0. 154 4 to 0 155 7 to 0 assign the down point of start_sp1 signal for sub-sampling waveform generation sequence for b pulse (spstp1). the data provided by these two commands is combined to form the 13-bit spstp1 setting. the data written to address 155 provides data d7 to d0. the data written to address 156 provides data d12 to d8. the spstp1 setting has a range from 0 to 8191. the default value is 0. 156 4 to 0 157 7 to 0 assign the up point of start_sp2 signal for sub-sampling waveform generation sequence for b pulse (spstr2). the data provided by these two commands is combined to form the 13-bit spstr2 setting. the data written to address 157 provides data d7 to d0. the data written to address 158 provides data d12 to d8. the spstr2 setting has a range from 0 to 8191. the default value is 0. 158 4 to 0 159 7 to 0 assign the down point of start_sp2 signal for sub-sampling waveform generation sequence for b pulse (spstp2). the data provided by these two commands is combined to form the 13-bit spstp2 setting. the data written to address 159 provides data d7 to d0. the data written to address 160 provides data d12 to d8. the spstp2 setting has a range from 0 to 8191. the default value is 0. 160 4 to 0 161 7 to 0 assign the up point of start_sp3 signal for sub-sampling waveform generation sequence for b pulse (spstr3). the data provided by these two commands is combined to form the 13-bit spstr3 setting. the data written to address 161 provides data d7 to d0. the data written to address 162 provides data d12 to d8. the spstr3 setting has a range from 0 to 8191. the default value is 0. 162 4 to 0 163 7 to 0 assign the down point of start_sp3 signal for sub-sampling waveform generation sequence for b pulse (spstp3). the data provided by these two commands is combined to form the 13-bit spstp3 setting. the data written to address 163 provides data d7 to d0. the data written to address 164 provides data d12 to d8. the spstp3 setting has a range from 0 to 8191. the default value is 0. 164 4 to 0 de?ne the sub-sampling pattern for sppatx waveform generation sequence for b pulse (lutspx) d efine the sub - sampling pattern for sppat1 waveform generation sequence for b pulse (lutsp1) 165 7 to 0 the data written to address 165 provides data d7 to d0 of the sppat1 setting. the default value is 0. 166 7 to 0 the data written to address 166 provides data d15 to d8 of the sppat1 setting. the default value is 0. address command bit command description
2001 oct 22 31 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 167 7 to 0 the data written to address 167 provides data d23 to d16 of the sppat1 setting. the default value is 0. 168 7 to 0 the data written to address 168 provides data d31 to d24 for a clock of the sppat1 setting. the default value is 0. d efine the sub - sampling pattern for sppat2 waveform generation sequence for b pulse (lutsp2) 169 7 to 0 the data written to address 169 provides data d7 to d0 of the sppat2 setting. the default value is 0. 170 7 to 0 the data written to address 170 provides data d15 to d8 of the sppat2 setting. the default value is 0. 171 7 to 0 the data written to address 171 provides data d23 to d16 of the sppat2 setting. the default value is 0. 172 7 to 0 the data written to address 172 provides data d31 to d24 for a clock of the sppat2 setting. the default value is 0. d efine the sub - sampling pattern for sppat3 waveform generation sequence for b pulse (lutsp3) 173 7 to 0 the data written to address 173 provides data d7 to d0 of the sppat3 setting. the default value is 0. 174 7 to 0 the data written to address 174 provides data d15 to d8 of the sppat3 setting. the default value is 0. 175 7 to 0 the data written to address 175 provides data d23 to d16 of the sppat3 setting. the default value is 0. 176 7 to 0 the data written to address 176 provides data d31 to d24 for a clock of the sppat3 setting. the default value is 0. de?ne sub-sampling pattern shift value 177 2 to 0 de?ne sub-sampling pattern shift value 1 (spshift1). the spshift1 setting has a range from 0 to 7. the default value is 0. 6to4 de?ne sub-sampling pattern shift value 2 (spshift2). the spshift2 setting has a range from 0 to 7. the default value is 0. 178 2 to 0 de?ne sub-sampling pattern shift value 3 (spshift3). the spshift3 setting has a range from 0 to 7. the default value is 0. de?ne pattern length 179 2 to 0 de?ne lsa1 pattern length (ratlsa1). the ratlsa1 setting has a range from 0 to 7. the default value is 7. 180 2 to 0 de?ne lsa2 pattern length (ratlsa2). the ratlsa2 setting has a range from 0 to 7. the default value is 7. 181 2 to 0 de?ne lsa3 pattern length (ratlsa3). the ratlsa3 setting has a range from 0 to 7. the default value is 7. 182 2 to 0 de?ne fsa pattern length (ratfsa). the ratfsa setting has a range from 0 to 7. the default value is 3. 183 2 to 0 de?ne lsb pattern length (ratlsb). the ratlsb setting has a range from 0 to 7. the default value is 7. 184 4 to 0 de?ne fsb pattern length (ratfsb). the ratfsb setting has a range from 0 to 19. the default value is 3. 185 4 to 0 de?ne sp1 pattern length (ratiosp1). the ratiosp1 setting has a range from 0 to 31. the default value is 3. address command bit command description
2001 oct 22 32 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 186 4 to 0 de?ne sp2 pattern length (ratiosp2). the ratiosp2 setting has a range from 0 to 31. the default value is 3. 187 4 to 0 de?ne sp3 pattern length (ratiosp3). the ratiosp3 setting has a range from 0 to 31. the default value is 3. setting polarity for a[1:4] and b[1:4] signals (inva and invb) 188 0 a[1:4] polarity selection. 0 = negative polarity 1 = positive polarity; default state 1 b[1:4] polarity selection. 0 = negative polarity 1 = positive polarity; default state 4 setting the priority of the trig signal during read-out for ff ccd (trgprty). 0 = low priority 1 = high priority; default state setting for dc-to-dc converter 189 (1) 6 control signal of clock signal output for dc-to-dc convertor (clkdc). 0 = enable; default state 1 = disable 5to0 assign the division value of clock generator for dc-to-dc converter (divdc). the divdc setting has a range from 0 to 63. the default value is 3. settings for horizontal pulse pattern generator a ssign the enable signals for hf1 and hf2 pulses 190 (1) 0 de?ne the state during hf1 blanking time (hf1blk). 0 = low state 1 = high state; default state 1 ssc selection (hf1ssc). 0 = unselect 1 = select; default state 2 de?ne the state when ssc is unselected (hf1en). 0 = disable 1 = continuous; default state 4 de?ne the state during hf2 blanking time (hf2blk). 0 = low state 1 = high state, default state 5 ssc selection (hf2ssc). 0 = unselect 1 = select; default state 6 de?ne the state when ssc is unselected (hf2en). 0 = disable 1 = continuous; default state address command bit command description
2001 oct 22 33 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 a ssign the enable signals for hf3 and hf4 pulses 191 (1) 0 de?ne the state during hf3 blanking time (hf3blk). 0 = low state 1 = high state, default state 1 ssc selection (hf3ssc). 0 = unselect 1 = select; default state 2 de?ne the state when ssc is unselected (hf3en). 0 = disable 1 = continuous; default state 4 de?ne the state during hf4 blanking time (hf4blk). 0 = low state 1 = high state, default state 5 ssc selection (hf4ssc). 0 = unselect 1 = select; default state 6 de?ne the state when ssc is unselected (hf4en). 0 = disable 1 = continuous; default state a ssign the enable signals for hf5 and hf6 pulses 192 (1) 0 de?ne the state during hf5 blanking time (hf5blk). 0 = low state 1 = high state, default state 1 ssc selection (hf5ssc). 0 = unselect 1 = select; default state 2 de?ne the state when ssc is unselected (hf5en). 0 = disable 1 = continuous; default state 4 de?ne the state during hf6 blanking time (hf6blk). 0 = low state 1 = high state, default state 5 ssc selection (hf6ssc). 0 = unselect 1 = select; default state 6 de?ne the state when ssc is unselected (hf6en). 0 = disable 1 = continuous; default state address command bit command description
2001 oct 22 34 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 a ssign the enable signals for hf7 and hf8 pulses 193 (1) 0 de?ne the state during hf7 blanking time (hf7blk). 0 = low state 1 = high state, default state 1 ssc selection (hf7ssc). 0 = unselect 1 = select; default state 2 de?ne the state when ssc is unselected (hf7en). 0 = disable 1 = continuous; default state 4 de?ne the state during hf8 blanking time (hf8blk). 0 = low state 1 = high state, default state 5 ssc selection (hf8ssc). 0 = unselect 1 = select; default state 6 de?ne the state when ssc is unselected (hf8en). 0 = disable 1 = continuous; default state a ssign the enable signals for hf9 pulse 194 (1) 0 de?ne the state during hf9 blanking time (hf9blk). 0 = low state 1 = high state, default state 1 ssc selection (hf9ssc). 0 = unselect 1 = select; default state 2 de?ne the state when ssc is unselected (hf9en). 0 = disable 1 = continuous; default state 4 stop hf signals in idle state (hfstop). 0 = disable; default state 1 = enable address command bit command description
2001 oct 22 35 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 test control signals setting (tstsel) 195 (1) 0 tstsel. 0 = normal 1 = test; default state register selection for ccd transfer data setting in shot or preview mode (regsel) 200 (1)(2) 0 regsel. 0 = data sent to register 1 (shot mode); default state 1 = data sent to register 2 (preview mode) high speed pulse control d ata setting for hf1 201 (1) 2 to 0 delay data d2 to d0; default value = 0 202 (1) 7 to 0 pattern data d7 to d0; default value = 0 203 (1) 7 to 0 pattern data d15 to d8; default value = 0 204 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf2 205 (1) 2 to 0 delay data d2 to d0; default value = 0 206 (1) 7 to 0 pattern data d7 to d0; default value = 0 207 (1) 7 to 0 pattern data d15 to d8; default value = 0 208 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf3 209 (1) 2 to 0 delay data d2 to d0; default value = 0 210 (1) 7 to 0 pattern data d7 to d0; default value = 0 211 (1) 7 to 0 pattern data d15 to d8; default value = 0 212 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf4 213 (1) 2 to 0 delay data d2 to d0; default value = 0 214 (1) 7 to 0 pattern data d7 to d0; default value = 0 215 (1) 7 to 0 pattern data d15 to d8; default value = 0 216 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf5 217 (1) 2 to 0 delay data d2 to d0; default value = 0 218 (1) 7 to 0 pattern data d7 to d0; default value = 0 219 (1) 7 to 0 pattern data d15 to d8; default value = 0 220 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf6 221 (1) 2 to 0 delay data d2 to d0; default value = 0 222 (1) 7 to 0 pattern data d7 to d0; default value = 0 223 (1) 7 to 0 pattern data d15 to d8; default value = 0 224 (1) 7 to 0 pattern data d23 to d16; default value = 0 address command bit command description
2001 oct 22 36 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 notes 1. the data sent to these addresses is used in both the shot and preview modes. 2. address 200 for register selection should be assigned first in order to specify the operating settings. 12 timing diagrams for specifying timing diagrams it is necessary to have a pixel-map available. the timing diagrams are dependent upon pixel count and line count. timing diagrams and timing software files are available on request; contact your nearest philips semiconductors sales office. please refer to application note of the saa8103. d ata setting for hf7 225 (1) 2 to 0 delay data d2 to d0; default value = 0 226 (1) 7 to 0 pattern data d7 to d0; default value = 0 227 (1) 7 to 0 pattern data d15 to d8; default value = 0 228 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf8 229 (1) 2 to 0 delay data d2 to d0; default value = 0 230 (1) 7 to 0 pattern data d7 to d0; default value = 0 231 (1) 7 to 0 pattern data d15 to d8; default value = 0 232 (1) 7 to 0 pattern data d23 to d16; default value = 0 d ata setting for hf9 233 (1) 2 to 0 delay data d2 to d0; default value = 0 234 (1) 7 to 0 pattern data d7 to d0; default value = 0 235 (1) 7 to 0 pattern data d15 to d8; default value = 0 236 (1) 7 to 0 pattern data d23 to d16; default value = 0 assign state pattern for frame shift state machine for b pulses (lutfsb) 240 3 to 0 state 8; default value = 0 7 to 4 state 9; default value = 0 241 3 to 0 state 10; default value = 0 7 to 4 state 11; default value = 0 242 3 to 0 state 12; default value = 0 7 to 4 state 13; default value = 0 243 3 to 0 state 14; default value = 0 7 to 4 state 15; default value = 0 244 3 to 0 state 16; default value = 0 7 to 4 state 17; default value = 0 245 3 to 0 state 18; default value = 0 7 to 4 state 19; default value = 0 assign state pattern for a pulses in idle state (lutidle) 246 (1) 3 to 0 lutidle; default value = 0 address command bit command description
2001 oct 22 37 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 13 limiting values in accordance with the absolute maximum rating system (iec 60134) 14 thermal characteristics 15 dc characteristics v dddx = 3.3 v; t amb =25 c symbol parameter min. max. unit v dddx digital supply voltages: v ddd1 , v ddd2 , v ddd3 , v ddd4 and v dd(osc) - 0.5 +5.0 v v ddax analog supply voltages: v dda(buf1) , v dda(buf2) , v dda(buf3) , v dda(dll1) and v dda(dll2) - 0.5 +5.0 v t stg storage temperature range - 40 +125 c t amb operating ambient temperature range - 20 +70 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 67 k/w symbol parameter conditions min. typ. max. unit v dddx digital supply voltage 3.0 3.3 3.6 v i dddx digital supply current f clk = 25 mhz 30 40 50 ma v dda(dllx) analog supply voltage 3.0 3.3 3.6 v i dda(dllx) analog supply current f clk =25mhz 579ma v dd(bufx) outputs supply voltage 3.0 3.3 3.6 v i dd(bufx) outputs supply current f clk =25mhz 468ma v dd(osc) oscillator supply voltage 3.0 3.3 3.6 v i dd(osc) oscillator supply current f clk = 25 mhz 0.20 0.35 0.50 ma data and control inputs v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.3 - v dd v i il low-level input current v il =v ssd --- 1ma i ih high-level input current v ih =v ddd -- 1ma t su(di) data input set-up time 4 -- ns t h(di) data input hold time 4 -- ns data and control output v ol low-level output voltage 0 - 0.5 v v oh high-level output voltage 2.3 - v dd v i ol low-level output current 4 -- ma i oh high-level output current --- 4ma t d(do) data output delay time c l =15pf - 210ns
2001 oct 22 38 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 i 2 c-bus signals: sda_snda and scl_sncl v il low-level input voltage 0 - 0.8 v v ih high-level input voltage 2.3 - v dd v i i input current v i = low or high -- 10 ma v ol sda output voltage i o =3ma -- 0.4 v i o output current during acknowledge 3 -- ma crystal oscillator; see fig.16 f clk clock frequency c l =15pf 6 - 28 mhz t r(clk) clock rising time f clk =25mhz - 2.5 10 ns t f(clk) clock falling time f clk =25mhz - 2.5 10 ns t cy(clk) duty cycle at oscillation f clk = 25 mhz 40 50 60 % hf pulse timing; see fig.15 t r(hf) hf rising time c l = 15 pf; f clk = 25 mhz; t r(clk) =t f(clk) =1ns - 310ns t f(hf) hf falling time c l = 15 pf; f clk = 25 mhz; t r(clk) =t f(clk) =1ns - 310ns t d(hf) delay time from clk to hf rising hf pulse parameter 0f0f0fh; f clk = 25 mhz -- 15 ns t w(hf) pulse width of hf hf pulse parameter 0f0f0fh; f clk = 25 mhz 5 -- ns reset condition; see fig.17 t w(rst) reset pulse width 400 --m s interface timing for front-end ics; see fig.18 t f(sclk) fall time of sclk - 3.5 10 ns t r(sclk) rise time of sclk - 3.5 10 ns t d(sdata) data output delay time of sdata f clk = 25 mhz 36 -- ns t h(sdata) data output hold time of sdata f clk = 25 mhz 36 -- ns t d(sen) data output delay time of sen f clk = 25 mhz 36 -- ns t h(sen) data output hold time of sen f clk = 25 mhz 36 -- ns f sclk clk frequency -- 5 mhz t w(sclk) pulse width of sclk - 50 - % symbol parameter conditions min. typ. max. unit
2001 oct 22 39 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 handbook, full pagewidth fce849 t d(do) t su(di) t h(di) data input (hd, vd) clk 50% data output tdscl or clkdc 50% 20% 80% input timing output timing fig.14 input and output timing. handbook, full pagewidth fce850 t r(hf) t f(hf) t w(hf) t d(hf) t f(clk) t r(clk) 10% hfn 90% 10% 90% 50% 50% 10% clk 90% 90% 10% 50% fig.15 hfn signal output timing (n = 1 to 9).
2001 oct 22 40 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 handbook, full pagewidth fce851 t cy(clk) t f(clk) t r(clk) clk 10% 90% 90% 50% 10% 50% 50% fig.16 crystal oscillator output timing. handbook, full pagewidth fce852 reset input 50% 50% t w(rst) fig.17 reset timing. handbook, full pagewidth fce853 t d(sen) t d(sdata) t h(sdata) t h(sen) 50% sdata sclk sen 50% 10% 90% 10% 90% 50% 50% fig.18 interface timing for front-end ics.
2001 oct 22 41 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 16 application information fce864 handbook, full pagewidth 0.1 m f 3.3 v analog power supply 2 3.3 v analog power supply 1 3.3 v digital power supply saa8103 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 a4 b3 a1 b4 hf8 v ssa(buf1) v ssd3 a2 vtlvl v ssd2 tg v ssa(buf2) hf7 v dda(buf2) hf6 hf2 hf5 hf4 v ssa(buf3) hf3 clkdc cr b1 v dda(buf1) a3 v dda(buf3) test2 (1) hf1 b2 v ddd3 hf9 lockout xout sda_snda scl_sncl v ssd4 v ddd4 stb2 xin v dda(dll2) v dd(osc) v ss(osc) v dda(dll1) v ssa(dll1) stb1 v ssa(dll2) sis snen test1 (1) tdscl encds2 trg vd tdsda endrv reset intego clp1 encds1 hd clp2 v ddd2 v ddd1 v ssd1 0.1 m f 0.1 m f 0.1 m f 15 pf 25 mhz (2) 15 pf 0.1 m f 0.1 m f 0.1 m f h-driver 74act04 h-driver 74act04 0.1 m f 0.1 m f 0.1 m f to v-driver from i 2 c-bus/ snert interfaces to v-driver and front-end ics to ccd and front-end ics to front-end ics to system controller sw sw sw fig.19 ppgft application diagram. (1) these pins should be connected to the ground line. (2) daishinku crystal oscillator.
2001 oct 22 42 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 17 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.60 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1.0 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 99-12-27 00-01-19 d (1) (1) (1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e q e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
2001 oct 22 43 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2001 oct 22 44 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, hbga, lfbga, sqfp, tfbga not suitable suitable hbcc, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2001 oct 22 45 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 19 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. data sheet status (1) product status (2) definitions objective data development this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. preliminary data quali?cation this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. product data production this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. changes will be communicated according to the customer product/process change noti?cation (cpcn) procedure snw-sq-650a. 20 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2001 oct 22 46 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 22 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2001 oct 22 47 philips semiconductors objective speci?cation pulse pattern generator for frame transfer ccd (ppgft) saa8103 notes
? koninklijke philips electronics n.v. 2001 sca73 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753504/01/pp 48 date of release: 2001 oct 22 document order number: 9397 750 08514

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