differential clock buffer/drive r cy28351-400 rev 1.0, november 28, 2006 page 1 of 7 2200 laurelwood road, santa clara, ca 95054 tel:(4 08) 855-0555 fax:(408) 855-05 50 www.spectralinear.com features ? supports 333-mhz and 400-mhz ddr sdram ? 60 ? 273-mhz operating frequency ? phase-locked loop (pll) clock distribution for double data rate synchronous dram applications ? distributes one clock input to ten differential outputs ? external feedback pin (fbin) is used to synchronize the outputs to the clock input ? conforms to the ddri specification ?spread aware ? for electromagnetic interference (emi) reduction ? 48-pin ssop package description this pll clock buffer is designed for 2.6v dd and 2.6av dd operation and differential outputs levels. this device is a zero delay buff er that distributes a clock input (clkin) to ten differential pa irs of clock outputs (yt[0:9], yc[0:9]) and one feedback clock output (fbout). the clock outputs are individually controlled by the serial inputs sclk and sdata. the two-line serial bus can set each output clock pair (yt[0:9], yc[0:9]) to the hi-z state. when av dd is grounded, the pll is turned off and bypassed for the test purposes. the pll in this device uses the input clock (clkin) and the feedback clock (fbin) to provide high-performance, low-skew, low-jitter output differential clocks. block diagram pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vss yc0 yt0 vddq yt1 yc1 vss vss yc2 yt2 vdd sclk clkin nc vddi avdd avss vss yc3 yt3 vddq yt4 yc4 vss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vss yc5 yt5 vddq yt6 yc6 vss vss yc7 yt7 vddq sdata nc fbin vddq fbout nc vss yc8 yt8 vddq yt9 yc9 vss cy28351-400 yt0 yc0 yt1 yc1 yt2 yc2 yt3 yc3 yt4 yc4 yt5 yc5 yt6 yc6 yt7 yc7 yt8 yc8 yt9 yc9 fbout serial interface logic pll fbin clkin sdata sclk avdd 10
cy28351-400 rev 1.0, november 28, 2006 page 2 of 7 zero delay buffer when used as a zero delay buffer, the cy28351-400 will likely be in a nested clock tree application. for these applications the cy28351-400 offers a clock input as a pll reference. the cy28351-400 then can lock onto the reference and translate with near zero delay to low skew outputs. for normal operation, the external feedback input, fbin, is connected to the feedback output, fbout. by connecting the feedback output to the feedback input the propagation delay through the device is eliminated. the pll wo rks to align the output edge with the input reference edge thus producing a near zero delay. the reference frequency affects the static phase offset of the pll and thus the relative delay between the inputs and outputs. when v dda is strapped low, the pll is turned off and bypassed for test purposes. pin description [1] pin number pin name i/o pin descrip tion electrical characteristics 13 clkin i clock input . input 35 fbin i feedback clock input . connect to fbout for accessing the pll. input 3, 5, 10, 20, 22 46, 44, 39, 29, 27 yt(0:9) o clock outputs . differential outputs 2, 6, 9, 19, 23 47, 43, 40, 30, 26 yc(0:9) o clock outputs . 33 fbout o feedback clock output . connect to fbin for normal operation. a bypass delay capacitor at this output will control input reference/output clocks phase relationships. output 12 sclk i serial clock input . clocks data at sdata into the internal register. data input for the two-line serial bus 37 sdata i/o serial data input . input data is clocked to the internal register to enable/disable individual outputs. this provides flexibility in power management. data input and output for the two-line serial bus 11 vdd 2.6v power supply for logic .2.6v nominal 4, 21, 28, 34, 38, 45 vddq 2.6v power supply for output clock buffers .2.6v nominal 16 avdd 2.6v power supply for pll .2.6v nominal 15 vddi 2.6v power supply for two-line serial interface .2.6v nominal 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 vss common ground . 0.0v ground 17 avss ? analog ground . 0.0v analog ground 14, 32,36 nc not connected . function table input outputs pll v dda clkin yt(0:9) [2] yc(0:9) [2] fbout gnd l l h l bypassed/off gnd h h l h bypassed/off 2.5v l l h l on 2.5v h h l h on 2.5v < 20 mhz hi-z hi-z hi-z off notes: 1. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (< 0.2?). if t hese bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. each output pair can be three-stated via the two-line serial interface.
cy28351-400 rev 1.0, november 28, 2006 page 3 of 7 power management the individual output enabl e/disable control of the cy28351-400 allows the user to implement unique power management schemes into the design. outputs are three-stated when disabled through the two-line interface as individual bits are set low in byte0 and byte1 registers. the feedback output (fbout) cannot be disabled via two line serial bus. the enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial ?runt? clocks. serial control registers following the acknowledge of the address byte, two additional bytes must be sent: ? command code byte ? byte count byte. byte0: output register 1 (1 = enable, 0 = disable) bit @pup pin# description 713, 2yt0, yc0 615, 6yt1, yc1 5110, 9yt2, yc2 4 1 20, 19 yt3, yc3 3 1 22, 23 yt4, yc4 2 1 46, 47 yt5, yc5 1 1 44, 43 yt6, yc6 0 1 39, 40 yt7, yc7 byte1: output register 2 (1 = enable, 0 = disable) bit @pup pin# description 7 1 29, 30 yt8, yc8 6 1 27, 26 yt9, yc9 50?reserved 40?reserved 30?reserved 20?reserved 10?reserved 00?reserved byte2: test register 3 bit @pup pin# description 7 1 ? 0 = pll leakage test, 1 = disable test 6 1 ? reserved 5 1 ? reserved 4 1 ? reserved 3 1 ? reserved 2 1 ? reserved 1 1 ? reserved 0 1 ? reserved
cy28351-400 rev 1.0, november 28, 2006 page 4 of 7 maximum operating conditions [3] input voltage relative to v ss :...............................v ss ? 0.3v input voltage relative to v ddq or av dd : ............. v dd + 0.3v storage temperature: ................................. ?65 c to +150 c operating temperature:................................ ?40 c to +85 c maximum power supply: ................................................ 3.5v this device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. for proper operation, v in and v out should be constrained to the range: v ss < (v in or v out ) < v dd . unused inputs must always be tied to an appropriate logic voltage level (either v ss or v dd ). dc electrical specifications [4] parameter description condition min. typ. max. unit all v dd?s supply voltage operating 2.5 ? 2.7 v v il input low voltage sdata , sclk ? ? 1.0 v v ih input high voltage sdata , sclk 2.2 ? ? v v il input voltage low clkin, fbin ? ? 0.3v ddq v v ih input voltage high clkin, fbin 0.6v ddq ??v v id differential input voltage clk, fbin 0.36 ? v ddq + 0.6 v i in input current v in = 0v or v in = v ddq , clkt, fbin ?10 ? 10 a v ol output low voltage v ddq = 2.375v, i ol = 12 ma ? ? 0.6 v v oh output high voltage v ddq = 2.375v, i oh = ?12 ma 1.7 ? ? v v out output voltage swing [5] 1.1 v ddq ? 0.4 v v oc output crossing voltage [6] (v ddq /2) ? 0.15 v ddq /2 (v ddq /2) + 0.15 v i oz high-impedance output current v o = gnd or v o = v ddq ?10 ? 10 a i ddq dynamic supply current [7] all v ddq and v ddi , f o = 273mhz ? 235 300 ma id stat static supply current ? ? 1 ma i dd pll supply current a vdd only ?912ma c in input pin capacitance ? 4 6 pf ac electrical specifications [8,9] parameter description condition min. typ. max. unit f clk operating clock frequency v dd , a vdd , v ddq = 2.5v to 2.7v 60 ? 273 mhz t dc input clock duty cycle 40 ? 60 % t lock maximum pll lock time ? ? 100 s t r t f output clocks slew rate 20% to 80% of v od 1 ?3v/ns t ccj cycle to cycle jitter [11] f > 66 mhz ?75 ? 75 ps tjit(h-per) half-period jitter [11] f > 66 mhz ?75 75 ps t plh low-to-high propagation delay, clkin to yt 1.5 3.5 6 ns t phl high-to-low propagation dela y, clkin to yt 1.5 3.5 6 ns t skew any output to any output skew [10] ??100ps t phase phase error [10] ?150 ? 150 ps t phasej phase error jitter f > 66 mhz ?50 ? 50 ps notes: 3. multiple supplies: the voltage on any input or i/o pin cannot exceed the power pin during power-up. power supply sequencing is not required. 4. unused inputs must be held high or low to prevent them from floating. 5. for load conditions, see figure 7 . 6. the value off voc is expected to be |vtr + vcp|/2. in case of each clock directly terminated by a 120 resistor. see figure 7 . 7. all outputs switching loaded with 16 pf in 60 environment. see figure 7 . 8. parameters are guaranteed by design and char acterization. not 100% tested in production 9. pll is capable of meeting the specified parameters while supporting ssc synthesizers with modulation frequency between 30 khz and 33.3 khz with a down spread of ?0.5%. 10. all differential input and output terminals are terminated with 120 /16 pf, as shown in figure 7 . 11. period jitter and half-perio d jitter specifications are separ ate specifications that must be met independently of each other .
cy28351-400 rev 1.0, november 28, 2006 page 5 of 7 parameter measurement information t ( ? ) n = n=n t ( ? ) n (n is large number of samples) 1 t ( ? ) n t ( ? ) n+1 clkin fbin 1.25v 1.25v 1.25v 1.25v figure 1. static phase offset t d( ? ) t d( ? ) t ( ? ) t ( ? ) t d( ? ) t d( ? ) clkin fbin 1.25v 1.25v figure 2. dynamic phase offset yt[0:9], fbout tsk(o) yc[0:9] yt[0:9], fbout yc[0:9] figure 3. output skew t c(n) 1 f(o) t jit(hper) = t c(n) - 1 fo yt[0:9], fbout yc[0:9] yt[0:9], fbout yc[0:9] figure 4. period jitter
cy28351-400 rev 1.0, november 28, 2006 page 6 of 7 1 f(o) t (hper_n+1) t (hper_n) t jit(hper) = t hper(n) - 1 2x fo yt[0:9], fbout yc[0:9] figure 5. hal f-period jitter t j it(cc) = t c(n) -t c(n+1) yt[0:9], fbout yc[0: 9] t c(n) t c(n) figure 6. cycle-to-cycle jitter clkt t pcb t pcb clkc 110 measurement point 16 pf measurement point 16 pf clkin fbin fbout 50 50 figure 7. differential signal using direct termination resistor
rev 1.0, november 28, 2006 page 7 of 7 cy28351-400 while sli has reviewed all information herein for accuracy and re liability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it inte nded for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear in c., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions ordering information part number package type product flow cy28351oc?400 48-pin ssop commercial, 0 to 70 c cy28351oc?400t 48-pin ssop?tape and reel commercial, 0 to 70 c cy28351oi?400 48-pin ssop industrial, ?40 to 85 c cy28351oi?400t 48-pin ssop?tape and reel industrial, ?40 to 85 c 48-lead shrunk small outline package o48 51-85061-*c
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